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2N1544

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Description 
 
 

2N1544 More Information

Pack: 03+/04+
D/C: TO3P

Description

BYTE WRITE OPERATION: The master initiates the byte write operation by issuing a start condition, followed by the device address byte 1010 (A2) (A1) (A0) 0, followed by 2 memory address bytes, fol- lowed by one data byte, followed by an acknowledge, then a stop condition. After each byte transfer, the Turbo IC 24C64 acknowledges the successful data transmission by pulling the SDA bus low. The stop condition starts the internal EEPROM write cycle, and all inputs are disabled until the completion of the write cycle. If the WP pin is high (1) and the memory address is within the upper quadrant (1800-1FFFH) of memory, then the stop condition does not start the inter- nal write cycle and the Turbo IC 24C64 is immediately ready for the next command.
 2N1544 PDF Download

2N1544 PDF

File Size:272384 KB

Applications

  Built-in watch dog timer   Low current consumption130µA TYP.   Low operating threshold voltageVCC=0.8V   Watch dog stop function (RCT terminal)   Long clock monitoring time   TPR (POWER ON) : TWD (clock monitoring)=1 : 1 6. Fewer outer components
 

Features

Carrier Detect (CMOS Output). Active low. A logic low indicates that an FSK signal is present. A time hysteresis is provided to allow for momentary signal discontinuity. The demodulated FSK data is ignored by the 2N1544 until carrier detect has been activated.

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2N1544 Suppliers

Part Number Mfg Pack D/C Qty Description Inquiry
2N1544 04+ 04+ 139 Nornal Stock
2N1544 TO3P TO3P 03+/04+ 4000
2N100 1350
2N100 CAN 3200
2N100 n/a n/a 17
2N100 1000 1000 CAN3
2N100 06+ 06+ 3880
2N1000 04+ 04+ 1000
2N1000 99+ 99+ 2687
2N1000 99+ 99+ CAN 2687
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