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| An integrated phase lock loop multiplies the incoming ADC sampling clock by a factor of 12. This 12x clock is used in the process of serializing the data output from each channel. The 12x clock is also used to generate a 1x and a 6x clock, both of which are transmitted as LVDS clock outputs. The 6x clock is denoted by the differential pair LCLKP and LCLKN, while the 1x clock is denoted by ADCLKP and ADCLKN. The word output of each ADC channel can be transmitted either as MSB |
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| FB (Pin 1) (74VHCT574AN): The voltage on this pin is compared to the internal reference voltage (1.205V) by the error comparator to keep the output in regulation. An external resistor divider is required between VOUT and FB to pro- gram the output voltage. |
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