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| The B3370V(LM337) and B3370V(LM337) are 9,437,184-bit Syn- chronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System. It is organized as 256K(512K) words of 36(18) bits and inte- grates address and control registers, a 2-bit burst address counter and added some new functions for high perfor- mance cache RAM applications; GW, BW, LBO, ZZ. Write cycles are internally self-timed and synchronous. Full bus-width write is done by GW, and each byte write is performed by the combination of WEx and BW when GW is high. And with CS1 high, ADSP is blocked to control signals. Burst cycle can be initiated with either the address status processor(ADSP) or address status cache controller(ADSC) inputs. Subsequent burst addresses are generated inter- nally in the system¢s burst sequence and are controlled by the burst address advance(ADV) input. LBO pin is DC operated and determines burst sequence(lin- ear or interleaved). ZZ pin controls Power Down State and reduces Stand-by current regardless of CLK. The B3370V(LM337) and B3370V(LM337) are fabricated using SAMSUNG¢s high performance CMOS technology and is available in a 100pin TQFP and Multiple power and ground pins are utilized to minimize ground bounce. |
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| NOTES (a) For a device surface mounted on 25mm x 25mm x 1.6mm FR4 PCB with high coverage of single sided 1oz copper, in still air conditions. (b) For a device surface mounted on 50mm x 50mm x 1.6mm FR4 PCB with high coverage of single sided 1oz copper, in still air conditions. |
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