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FMP2FU More Information


The DS1388 I2C real-time clock (RTC), supervisor, and EEPROM is a multifunction device that provides a clock/calendar, programmable watchdog timer, power- supply monitor with reset, and 512 bytes of EEPROM. The clock provides hundredths of seconds, seconds, minutes, and hours, and operates in 24-hour or 12-hour format with an AM/PM indicator. The calendar provides day, date, month, and year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. A watchdog timer provides a reset for an unre- sponsive microprocessor. It is programmable in 10ms intervals from 0.01 to 99.99 seconds. A temperature- compensated voltage reference and comparator circuit monitors the status of VCC. If a primary power failure is detected, the device automatically switches to the backup supply and drives the reset output to the active state. The backup supply maintains time and date operation in the absence of VCC. When VCC returns to nominal levels, the reset is held low for a period to allow the power supply and processor to stabilize. The device also has a pushbutton reset controller, which debounces a reset input signal. The device is accessed through an I2C serial interface.
 FMP2FU PDF Download


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1 For normal continuous operation. A higher Tj is allowed as an overload condition but at the threshold Tj(TO) the over temperature trip operates   to protect the switch. 2 Reverse battery voltage is allowed only with external resistors to ensure that the input and status currents do not exceed the limiting values.   The internal ground resistor limits the reverse battery ground current. The connected loads must limit the reverse load currents. Power   is dissipated and the Tj rating must be observed. 3 To limit currents during reverse battery and transient overvoltages (positive or negative).


Either 256 refresh cycles or read/write cycles on 212 consecutive row addresses beginning with address 0 have to be executed within an 16 ms interval to maintain the data in the memory arrays. A refresh cycle is determined by the mode control bits, see Addressing and Mode Control. In the refresh mode, the row and column addresses are ignored.

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FMP2FU Suppliers

Part Number Mfg Pack D/C Qty Description Inquiry
FMP016P104 dc99 dc99 fct 3000
FMP1 22500
FMP1 2040
FMP1 00+ 00+ SOT153 96000
FMP1 SOT-5 5100 original,in stock"
FMP1 07+/08+ 07+/08+ SOT-153 10000 Our New Arrivals,please contact chongxonexports@hotmail.com for quotations
FMP1 30000 original &in STK
FMP1 3200 3200
FMP1 00;99 00;99 21000
FMP1 08+ 08+ SOT-153 20800
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