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GBY228 More Information



Sensor core and IFP registers are grouped into two separate address spaces, as shown in Figure 2. The internal registers can be accessed via the two-wire serial interface. Select- ing the desired address space can be accomplished by programming register R1 which remains present in both register sets.
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only when the reference frequency divided by this ratio is within the DCXO capture range. If the frequency is out of range, a flag will be set on the FAIL#/SAFE pin notifying the system that the selected reference is not valid. If the reference moves in range, then the flag will be cleared, indicating to the system that the selected reference is valid.


  The GBY228 is designed to interface directly to the PCI bus and operate as a 64-bit DMA bus master. This function is accomplished through a PCI bus interface unit (PBIU) containing an onboard DMA controller. The PBIU generates and samples PCI control signals, generates host memory addresses, and facilitates the transfer of data between host memory and the onboard frame buffer. It also allows the host to access the GBY228 internal registers and communicate with the onboard RISC processor.   The GBY228 supports the minimum power management capabilities specified in revision 1.1 of the PCI Bus Power Management Interface Specification, which defines power states D0-D3, where D0 provides maximum power consumption and D3 provides minimal power consumption. The D3 power state is entered by either software (D3 hot) or by physically removing power (D3 cold). Hot and cold refer to the presence or absence of VCC, respectively.   The GBY228 supports power states D0, D3 hot, and D3 cold.   The GBY228 onboard DMA controller consists of five independent DMA channels that initiate transactions on the PCI bus and transfer data between the host memory and frame buffer. The command DMA channel is used mainly by the RISC processor for small transfers. The two data DMA channels, one to transmit and one to receive, transfer data between the FC-AL and the PCI bus. The auto-DMA request channel fetches commands from host memory over the PCI bus. The auto-DMA response channel posts status information to host memory.   The PBIU internally arbitrates between the five DMA channels and alternately services them. Each DMA channel has a set of DMA registers that are programmed for transfers by the RISC processor.

Related Models

Parr number/PDF Mfg Pack D/C Descrpion Parr number/PDF Mfg Pack D/C Descrpion
 GBY228 DIODE Sensor core and IFP registers  GBY228 DIODE Sensor core and IFP registers
 GBY228 DIODE Sensor core and IFP registers  GBY228 DIODE Sensor core and IFP registers
 GBY228 DIODE Sensor core and IFP registers  GBY228 DIODE Sensor core and IFP registers

GBY228 Suppliers

Part Number Mfg Pack D/C Qty Description Inquiry
GBY228 DIODE 100000
GBY201209T-070Y-N 2008+ 2008+ 130000
GBY201209T-070Y-S 2008+ 2008+ 170000
GBY201209T-090Y-N 2008+ 2008+ 140000
GBY201209T-090Y-S 2008+ 2008+ 180000
GBY201209T-110Y-N 2008+ 2008+ 150000
GBY201209T-110Y-S 2008+ 2008+ 190000
GBY201209T-170Y-N 2008+ 2008+ 160000
GBY201209T-170Y-S 2008+ 2008+ 200000
GBY201209T-300Y-N 2008+ 2008+ 170000
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