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GT6312 More Information

D/C: 07+


Memory management is handled using a unique MMU (Memory Management Unit) architecture and a 32-bit wide data path. This I/O mapped architecture can sustain back-to-back frame transmission and reception for superior data throughput and optimal performance. It also dynamically allocates buffer memory in an efficient buffer utilization scheme, reducing software tasks and relieving the host CPU from performing these housekeeping functions. The total memory size is 128 Kbytes (external), equivalent to a total chip storage (transmit and receive) of 64 outstanding packets.
 GT6312 PDF Download

GT6312 PDF

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An external inhibit port is provided to control con- verter operation. The converters operation is inhib- ited when this pin is pulled low. It is intended to be driven by an open collector logic device. The pin may be left open for normal operation and has a nominal open circuit voltage of 10.5V with respect to the input return (pin 2).


Loop-Filter Pin for PLL Analog Ground Pin Power-Down pin When L, the GT6312 is powered-down and reset. Soft Mute Pin De-emphasis Filter Control Pin #0 De-emphasis Filter Control Pin #1 L/R Clock Pin for Input Audio Serial Data Clock Pin for Input Audio Serial Data Input Pin Input Data Format pin #0 Input Data Format pin #1 Input Data Format pin #2 Clock Mode Select Pin #0 Clock Mode Select Pin #1 Clock Mode Select Pin #2 Output Data Format pin #0 Output Data Format pin #1 Audio Serial Data Output Pin Audio Serial Data Clock Pin for Output L/R Clock Pin for Output Master Clock Pin for Output Input Buffer Power Supply Pin, 3.3V or 5V Digital Ground Pin Power Supply Pin, 3.3V

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GT6312 Suppliers

Part Number Mfg Pack D/C Qty Description Inquiry
GT6312 05+ 05+ SOP 2000
GT6312 original stock original stock SOP20 220
GT6312 02+ 02+ 150
GT6312 04+ 04+ SOP20 540
GT6312 SOP20 SOP20 220
GT6312 07+ 07+ 5,000 Our New Arrivals,please contact chongxonexports@hotmail.com for quotations
GT6312 05+ 05+ TQFP100 2123
GT6081A 5580
GT6081A 5580 http://www.silicon-ic.com
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