Welcome to Seekchip.com    HOME
   Current position: Home > Shortcut to H > HP2 Series > HP2225


You can fill in the blank to send your urgent purchasing info,so that the suppliers will get to you soon. Note: * are required!
*  Part Number *  Quantity
*  Business Location *  Email

HP2225 More Information

Pack: DIP8


NOTES 1Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V. 2See Figure 2. 3These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the VOL or VOH limits. 4SCLK active edge is falling edge of SCLK. 5These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then   extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means the times quoted in the timing characteristics are the true bus relin-   quish times of the part and as such are independent of external bus loading capacitances.
 HP2225 PDF Download

HP2225 PDF

File Size:90734 KB


The base timer is an 8-bit counter with a 1MHz clock source. The base timer can be enabled/disabled by the CPU. After a reset, the base timer is disabled and cleared. The base timer can be preset by writing BT7 - BT0 to the BT register at any time. When enabled, the base timer starts counting from the preset value. When the value reaches FFH, it generates a timer interrupt only if the timer interrupt is enabled. When it reaches the maximum value of FFH, the base timer will wrap around and begin counting at 00H. The timer interval can be programmed from 1 - 256 µsec. The base timer can be enabled by writing a '0' to ' ENBT ' in the TCON (Timer Control) register. The ENBT is a level trigger.


Addressing Overview After the HP2225 (as receiver) acknowledges the device address, the master can place the memory address on the bus for a write operation. The address requires two bytes. The first is the MSB. Since the device uses only 13 address bits, the value of the upper three bits are dont care. Following the MSB is the LSB with the remaining eight address bits. The address value is latched internally. Each access causes the latched address value to be incremented automatically. The current address is the value that is held in the latch -- either a newly written value or the address following the last access. The current address will be held for as long as power remains or until a new value is written. Reads always use the current address. A random read address can be loaded by beginning a write operation as explained below.

Related Models

Parr number/PDF Mfg Pack D/C Descrpion Parr number/PDF Mfg Pack D/C Descrpion
 HP20 N/A 05+ The MAX104 is supplied in a  HP2201 HP DIP 02+ The Hitachi HN58C1001 is a el
 HP2202 HEWLETT DIP8 Low-Line Logic Output. Early  HP2202 HEWLETT DIP8 Low-Line Logic Output. Early
 HP200 HP DIP8 99+   CAUTION: These device  HP201 HP SO8

HP2225 Suppliers

Part Number Mfg Pack D/C Qty Description Inquiry
HP2225 n/a n/a DIP8 58 new&unused in stock
HP2225 07+ 07+ DIP8 495 STOCK
HP2225 686
HP2225 50 http://www.silicon-ic.com
HP2225 440
HP2225 100
HP2225 500 500 06+
HP2225 DIP8 5000
HP2225 DIP8 673 STRC Verified
HP2225 DIP8 1202
Quick search: 0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z ALL
About Seekchip- Services - Comments - Contact us - Links - Map

© 2008 China Electronics Market,License 浙ICP备10014259号-9