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JRC2068D

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Description 
 
 

JRC2068D More Information

Mfg: JRC
Pack: SOP11

Description

256K x 36 Synchronous Bank-Switchable Dual-ported SRAM Architecture C 64 independent 4K x 36 banks C 9 megabits of memory on chip Bank access controlled via bank address pins High-speed data access C Commercial: 3.4ns(200MHz)/3.6ns (166MHz)/4.2ns   (133MHz) (max.) C Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.) Selectable Pipelined or Flow-Through output mode Counter enable and repeat features Dual chip enables allow for depth expansion without additional logic Full synchronous operation on both ports C 5ns cycle time, 200MHz operation (14Gbps bandwidth) C Fast 3.4ns clock to data out
 JRC2068D PDF Download

JRC2068D PDF

File Size:509746 KB

Applications

 − Single Ended  − Differential Differential Nonlinearity: 0.45 LSB Signal-to-Noise: 60 dB Typ f(IN) at 4.8 MHz Spurious Free Dynamic Range: 72 dB Adjustable Internal Voltage Reference On-Chip Voltage Reference Generator Unsigned Binary Data Output Out-of-Range Indicator Power-Down Mode
 

Features

The JRC2068D is a high precision, high throughput analog front end. True 16-bit p-p resolution is achievable with a total conversion time of 500 µs (2 kHz channel switching), making it ideally suitable for high resolution multiplexing applications.

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JRC2068D Suppliers

Part Number Mfg Pack D/C Qty Description Inquiry
JRC2068D 92 92 DIP 344
JRC2068D SOP- 8 1335
JRC2068D 5000
JRC2068D 1150
JRC2068D SOP11 1525
JRC2068D SOP11 1525
JRC2068D DIP8 3
JRC2068D 04+ 04+ NJM 6500
JRC 4558D 06+ 06+ 5000
JRC0026 1995 1995 SOP3.9mm 1730
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