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NFS50-7608 More Information


  The Micron® Imaging NFS50-7608 VGA-based CMOS active-pixel sensor has a 1/2-inch optical format and delivers superb resolution at a turbocharged 200 fps, making it the perfect solution for machine vision assembly lines, airbag deployment, golf swing analysis, and special effects in movies. The freeze-frame shutter allows the signal charges of all pixels to be integrated in parallelall pixels start integrating simultaneously and stop integrating simultaneously. The charges are then sampled into pixel analog memories (one mem- ory per pixel) and consequently, row by row, are digi- tized and read out-of-chip. The sensor works in master, snapshot, or slave mode. In master mode it generates the readout timing on-chip. In snapshot mode it accepts an external trigger and then generates the readout timing. In slave mode the sensor accepts external readout timing. The integration time is pro- grammed through the two-wire serial interface (mas- ter or snapshot mode) or controlled via externally- generated control signals (slave mode).   The scanning mode can be progressive or inter- laced. There is also an option to scan just a window of interest by choosing start row and column and stop row and column. The user can control the frame rate and row rate through the use of vertical and horizontal blanking as well as the master clock frequency.   The readout of the data out of the chip can be done simultaneously with integration and ADC operation due to the two-cell SRAM which allows data from the previously converted row to be shifted into the output memory for readout.   The sensors ADCs contain special self-calibrating circuitry that allow the sensor to reduce its own col- umn-wise fixed pattern noise. The calibration coeffi- cients can be read from, and written to, the sensor.
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Configuration of a single-ended input has been facilitated by biasing nDIF_REF0 and nDEF_REF1 to Vcc/2, with 50kΩ to Vcc and 50kΩ to ground. The input clock structure, and how it is used with either LVCMOS/LVTTL inputs or a DC- coupled LVPECL clock, is shown in Figure 4.


The STR73xF family is available in 3 packages. The TQFP144 and LFBGA144 versions have the full set of all features. The 100-pin version has fewer timers, I/Os and ADC channels. Refer to the Device Summary on Page 1 for a comparison of the I/Os available on each package.

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NFS50-7608 Suppliers

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NFS-100A-0110 5000
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NFS-10A-0100 5000
NFS-10A-0110 5000
NFS-16A-0100 5000
NFS-16A-0110 5000
NFS-20A-0100 5000
NFS-20A-0110 5000
NFS-20A-0110 A 5000
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