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PAL006

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Description 
 
 

PAL006 More Information

Mfg: PIONEER

Description

Virtex FPGAs are SRAM-based, and are customized by loading configuration data into internal memory cells. In some modes, the FPGA reads its own configuration data from an external PROM (master serial mode). Otherwise, the configuration data is written into the FPGA (Select- MAP™, slave serial, and JTAG modes).
 PAL006 PDF Download

PAL006 PDF

File Size:62439 KB

Applications

This pin normally functions as a three-state input that controls the two LSBs of the Serial Bus Address. When this pin is tied to VCC the two LSBs are 01. When tied to Ground, the two LSBs are 10. If this pin is not connected, the two LSBs are 00. This pin also functions as an output during NAND Tree tests (board-level connectivity testing). To ensure proper NAND tree function, this pin should not be tied directly to VCC or Ground. Instead, a series 5 kΩ resistor should be used to allow the test output function to work. Refer to SECTION 11 on NAND Tree testing.
 

Features

(PAL006 EV kit: VCC = +2.7V to +3.0V, RF_GAIN = VIH, 0V VTX_GC +2.0V, 0V VRX_AGC +2.0V, RBIAS = 12kΩ, no input sig- nals at RF and baseband inputs, RF I/O terminated into 50Ω though a 2:1 balun, receiver baseband outputs are open, transmitter baseband inputs biased at +1.2V, registers set to default power-up settings, TA = -40C to +85C, unless otherwise noted. Typical values are for VCC = +2.7V, TA = +25C, unless otherwise noted.) (Note 1)

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Part Number Mfg Pack D/C Qty Description Inquiry
PAL006 07+ 07+ ZIP 495 STOCK
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PAL.16L8BVC 1621
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PAL001A 00 00 SQL-15 925
PAL001A 0 0 SOP-16 925 Available,Ask Eric
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