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PVC75A-16

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Description 
 
 

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Description

† Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and  functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not  implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.   2. The package thermal impedance is calculated in accordance with JESD 51.
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PVC75A-16 PDF

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Applications

The MAX1108/MAX1109 low-power, 8-bit, dual-channel, analog-to-digital converters (ADCs) feature an internal track/hold (T/H) voltage reference, clock, and serial inter- face. The MAX1108 is specified from +2.7V to +3.6V and consumes only 105µA. The MAX1109 is specified from +4.5V to +5.5V and consumes only 130µA. The analog inputs are software configurable, allowing unipolar/bipolar and single-ended/differential operation; battery monitor- ing capability is also included. The full-scale analog input range is determined by the internal reference of +2.048V (MAX1108) or +4.096V (MAX1109), or by an externally applied reference rang- ing from 1V to VDD. The MAX1108/MAX1109 also feature a software power-down mode that reduces power con- sumption to 0.5µA when the device is not in use. The 4-wire serial interface directly connects to SPI™, QSPI™, and MICROWIRE™ devices without external logic. Conversions up to 50ksps are performed using either the internal clock or an external serial-interface clock. The MAX1108 and MAX1109 are available in a 10-pin µMAX package with a footprint that is just 20% of an 8-pin plastic DIP.
 

Features

See Distribution of Differential Output Offset (Worst-Case Conditions) in the Typical Operating Characteristics. Characterized with a 675Mbps 1-0 pattern. Measurements are taken over an input signal range of 16dB. Deterministic jitter is defined as the arithmetic sum of PWD (pulse-width distortion) and PDJ (pattern-dependent jitter). Deterministic jitter is the difference of total jitter and random jitter, with system jitter calibrated out. It is measured with a 27 - 1PRBS, and 80CIDs with DC-coupled outputs. Typical input resistance of SC pin is 40kΩ. AGC loop time constant is measured with a 20dB change in the input and VSC held constant. With an external capacitor CCG of 0.022µF connected between CG+ and CG-, a typical AGC loop time constant of 760µs is achieved. SD deassert time depends on the AGC loop time constant set by CCG. SD accuracy is defined as the part-to-part variation of the SD threshold at a fixed RTH value. See Distribution of SD Hysteresis (Worst-Case Conditions) in the Typical Operating Characteristics. Measurements are taken over an input signal range of 20dB.

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PVC75A-16 Suppliers

Part Number Mfg Pack D/C Qty Description Inquiry
PVC75A-16 02+ 02+ 300 NEW&ORIGINAL
PVC75A-16 N/A N/A N/A 100
PVC105-8 n/a 450
PVC110-16 MODULE 30
PVC110-16 可控硅 30
PVC110-16 200
PVC110-16 17
PVC110-16 MODULE MODULE 55
PVC110-16 1750
PVC110-16 500 STOCK
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