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RSN312H24

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Description 
 
 

RSN312H24 More Information

Mfg: SANYO

Description

This SOC VGA CMOS image sensor features DigitalClarityMicrons breakthrough, low-noise CMOS imaging technology that achieves CCD image quality (based on signal- to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost and integration advantages of CMOS.
 RSN312H24 PDF Download

RSN312H24 PDF

File Size:592183 KB

Applications

DESCRIPTION Input reference frequency, 5V tolerant input Buffered clock output, Bank A Buffered clock output, Bank A Power Supply Ground Buffered clock output, Bank B Buffered clock output, Bank B Function select input, bit 2 Function select input, bit 1 Buffered clock output, Bank B Buffered clock output, Bank B Buffered clock output, Bank A Buffered clock output, Bank A Buffered clock output, internal feedback
 

Features

In sequential addressing mode, the RSN312H24 functions like a FIFO register. The timing between write-reset and read-reset operations determines the delay or length of the FIFO. Data may be read out as many times as desired after it has been written into the storage array of the memory. Minimum delay between writing and reading is 160 write cycles; maximum delay is one full field plus one block or 245 800 words.

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RSN312H24 Suppliers

Part Number Mfg Pack D/C Qty Description Inquiry
RSN312H24 917
RSN312H24 20
RSN 1/2W 10 J TB 50 new in stock
RSN2003 TO-92 3340 Owen Chen:Tel:0086-10-62101298-603 or 0086-013439884772 Email:owencwl@163.com
RSN2003 TO-92 3340
RSN2003 TO-92 3340 QQ:360383622
RSN307 50
RSN307M42-P DIP DIP 01+ 120
RSN307M44 模块 2
RSN307M44 50
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