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S16C45C More Information

Pack: TO-220
D/C: 04+


The highest count of the various modes is shown in the Extended Counter Range column. Control inputs Kb and Kc can be used to initiate and lock the counter in the master preset state. In this condition the flip-flops in the counter are preset in accordance with the jam inputs and the counter remains in that state as long as Kb and Kc both remain low. The counter begins to count down from the preset state when a counting mode other than the master preset mode is selected.
 S16C45C PDF Download


File Size:67102 KB


Note 11: Maximum power dissipation in the device (PDMAX) occurs at an output power level significantly below full output power. PDMAX can be calculated using Equation 1 shown in the Application Information section. It may also be obtained from the power dissipation graphs.


The S16C45C high speed PARALLEL-IN/SERIAL-OUT SHIFT REGISTER utilizes advanced silicon-gate CMOS technology. It has the low power consumption and high noise immunity of standard CMOS integrated circuits, along with the ability to drive 10 LS-TTL loads. This 8-bit serial shift register shifts data from QA to QH when clocked. Parallel inputs to each stage are enabled by a low level at the SHIFT/LOAD input. Also included is a gated CLOCK input and a complementary output from the eighth bit.

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S16C45C Suppliers

Part Number Mfg Pack D/C Qty Description Inquiry
S16C45C 02+ 02+ TO-220 25000
S16C45C TO- TO- 6000
S16C45C TO- TO- 05无铅 5800
S16C45C TO- TO- 05+ 5800
S16C45C TO- 4760 Delivery
S16C45C 02+ 02+ TO-220 6,500 original parts in stock
S16C45C 04+ 04+ TO-220 TO-220
S16C45C 08+ 08+ TO-220-3 169 .!
S160 00+ 00+ 2200
S160 05+ 05+ SSOP10 50000
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