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V58C2256164SAT5

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Description 
 
 

V58C2256164SAT5 More Information

Description

Description The CE pin is used for interfacing with the CPU. Should be held high to allow access to the CPU. Incorporates a pull-down resistor. Should be held low or open when the CPU is powered off. Allows a maximum input voltage of 5.5v regardless of supply voltage. The SCLK pin is used to input clock pulses synchronizing the input and output of data to and from the SI and SO pins. Allows a maximum input voltage of 5.5v regardless of supply voltage. The SI pin is used to input data intended for writing in synchronization with the SCLK pin. CMOS input. Allows a maximum input voltage of 5.5v regardless of supply voltage. The SO pin is used to output data intended for reading in synchronization with the SCLK pin. CMOS output.  The /INTR pin is used to output alarm interrupt (Alarm_W) and alarm  interrupt (Alarm_D) and output periodic interrupt signals to the CPU signals.  Disabled at power-on from 0V. N-channel open drain output. Allows a  maximum pull-up voltage of 5.5v regardless of supply voltage.  The 32KOUT pin is used to output 32.768-kHz clock pulses. Enabled at  power-on from 0 volts. Nch. open drain output. The Rx5C348A is designed  to disable 32-kHz clock output in response to a command from the host  computer and the Rx5C348B is designed to keep 32-kHz output enabled.  The OSCIN and OSCOUT pins are used to connect the 32.768-kHz crystal  oscillator (with all other oscillation circuit components built into the  Rx5C348A/B). The VDD pin is connected to the power supply. The VSS pin is grounded.
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Applications

5V 10% SUPPLY VOLTAGE COUNTERS FOR SECONDS, MINUTES, HOURS, DAY, DATE, MONTH, YEARS, AND CENTURY YEAR 2000 COMPLIANT SOFTWARE CLOCK CALIBRATION AUTOMATIC POWER-FAIL DETECT AND SWITCH CIRCUITRY I2C BUS COMPATIBLE 56 BYTES OF GENERAL PURPOSE RAM ULTRA-LOW BATTERY SUPPLY CURRENT OF 450nA LOW OPERATING CURRENT OF 300µA OPERATING TEMPERATURE OF C40 to 85C AUTOMATIC LEAP YEAR COMPENSATION SPECIAL SOFTWARE PROGRAMMABLE OUTPUT PACKAGING OPTIONS INCLUDE: C 28-lead SOIC and SNAPHAT® TOP (to be   ordered separately) C SO8
 

Features

PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Partial Reset, the existing mode (IDT or FWFT), programming method (serial or parallel), and programmable flag settings are all retained. RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to LOW (OR to HIGH in FWFT mode) temporarily and does not disturb the write pointer, programming method, existing timing mode or programmable flag settings. RT is useful to reread data from the first physical location of the FIFO. During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset, this pin functions as a serial input for loading offset registers When enabled by WEN, the rising edge of WCLK writes data into the FIFO and offsets into the programmable registers for parallel programming, and when enabled by SEN, the rising edge of WCLK writes one bit of data into the programmable register for serial programming. WEN enables WCLK for writing data into the FIFO memory and offset registers.

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V58C2256164SAT5 Suppliers

Part Number Mfg Pack D/C Qty Description Inquiry
V58C2256164SAT5 317
V58C2256164SAT5 04+ 04+ SSOP 608
V58C2256164SAT5 N/A N/A 04+ 200
V58C2256164SAT5 SSOP 612
V58C2256164SAT5 613 613
V580ME13 2006 2006 MINI-16 418
V580ME13 MINI-16 MINI-16 2006 423
V585ME06 242 new in stock
V585ME12 0 0 1115 IN stock
V585ME48-LF-TR 52 new in stock
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