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XR567

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Description 
 
 

XR567 More Information

Description

The XR567A has two types of power connections in addi- tion to the LI pin. They are the Logic VCC (VCC) and the Quiet VCC (QVCC). There are two logic VCC pins on the XR567 that provide the supply voltage for the logic and control cir- cuitry. Multiple power pins reduce the effects of package in- ductance and thereby minimize switching noise. As these pins are common to the V CC bus internal to the device, a voltage delta should never exist between these pins and the voltage difference between VCC and QV CC should never ex- ceed 0.5V because of ESD circuitry. Additionally, the ESD circuitry between the VCC pins and all other pins except for BTL I/Os and LI pins requires that any voltage on these pins should not exceed the voltage on VCC + 0.5V.
 XR567 PDF Download

XR567 PDF

File Size:257995 KB

Applications

5 ns pin-to-pin logic delays System frequency up to 178 MHz 72 macrocells with 1,600 usable gates Available in small footprint packages - 44-pin PLCC (34 user I/O pins) - 44-pin VQFP (34 user I/O pins) - 48-pin CSP (38 user I/O pins) - 64-pin VQFP (52 user I/O pins) - 100-pin TQFP (72 user I/O pins) Optimized for high-performance 3.3V systems - Low power operation - 5V tolerant I/O pins accept 5 V, 3.3V, and 2.5V   signals - 3.3V or 2.5V output capability - Advanced 0.35 micron feature size CMOS   FastFLASH™ technology Advanced system features - In-system programmable - Superior pin-locking and routability with   FastCONNECT II™ switch matrix - Extra wide 54-input Function Blocks - Up to 90 product-terms per macrocell with   individual product-term allocation - Local clock inversion with three global and one   product-term clocks - Individual output enable per output pin - Input hysteresis on all user and boundary-scan pin   inputs - Bus-hold circuitry on all user pin inputs - Full IEEE Standard 1149.1 boundary-scan (JTAG) Fast concurrent programming Slew rate control on individual outputs Enhanced data security features Excellent quality and reliability - Endurance exceeding 10,000 program/erase   cycles - 20 year data retention - ESD protection exceeding 2,000V Pin-compatible with 5V-core XC9572 device in the 44-pin PLCC package and the 100-pin TQFP package
 

Features

The M54/74HC4017 is a high speed CMOS DE- CADE COUNTER/DIVIDER fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. The M54/74HC4017 is a 5-stage Johnson counter with 10 decoded outputs. Each of the decoded out- puts is normally low and sequentially goes high on the low to high transition of the clock input. Each out- put stays high for one clock period of the 10 clock period cycle. The CARRY output goes low to high after OUTPUT 10 goes low, and can be used in con- junction with the CLOCK ENABLE to cascade sev- eral stages.

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XR567 Suppliers

Part Number Mfg Pack D/C Qty Description Inquiry
XR501261-001 . 140 call me any time
XR501261-001 140 140 .
XR501261-001 140
XR501261-001 2005+ 2005+ DIP 2500
XR501269-002 . 200 call me any time
XR501269-002 DIP DIP 138
XR501269-002 200 200 .
XR501269-002 200
XR501269-002 2005+ 2005+ DIP 12000
XR501-8CJ XR 2000
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