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Boundary scan instructions and associated data registers support a standard methodology for accessing and config- uring Virtex-II devices that complies with IEEE standards 1149.1 - 1993 and 1532. A system mode and a test mode are implemented. In system mode, a Virtex-II device per- forms its intended mission even while executing non-test boundary-scan instructions. In test mode, boundary-scan test instructions control the I/O pins for testing purposes. The Virtex-II Test Access Port (TAP) supports BYPASS, PRELOAD, SAMPLE, IDCODE, and USERCODE non-test instructions. The EXTEST, INTEST, and HIGHZ test instruc- tions are also supported.
n Watchdog fully operational from 2.7 to 5.25 V n Regulated DC voltage monitor, internal voltage   reference n Self recovering watchdog function: reset goes active   after the 1st timeout period, reset goes inactive   again after the 2nd timeout period, repeated active   reset signal until the system recovers n Standard timeout period and power-on reset time   (100 ms), externally programmable from 3 ms to   3 mins if required n Works down to 1.6 V supply voltage n Low voltage alarm prior to reset on power-down n Reset outputs of both polarities n Open drain outputs n Small footprint SO8 and DIP8 packages
High voltage drive to within 1.3 V of supply rails Output short-circuit protection High update rates Fast, 100 Ms/s, 10-bit input data update rate Low static power dissipation: 0.7 W   Includes STBY function Voltage-controlled video reference (brightness) and   full-scale (contrast) output levels INV bit reverses polarity of video signal 3.3 V logic, 9 V to 18 V analog supplies High accuracy voltage outputs Laser trimming eliminates the need for adjustments Flexible logic STSQ/XFR allow parallel 10N60 operation at various   resolutions Fast settling into capacitive loads   30 ns settling time to 0.25% into 150 pF load   Slew rate 460 V/µs Available in 48-lead 7 mm 7 mm LFCSP package
Parr number/PDF Mfg Pack D/C Descrpion
10N02   10N02 10N02 PDF Download MOTOROLA 1. One output at a time for a maximum duration o
10N022   10N022 10N022 PDF Download s Memory mapped I/O s Multilevel Low Voltage De
10N02Z   10N02Z 10N02Z PDF Download MOT SOP8 —— Deadtime High-Current Totem-Pole Dual Output Sta
10N03   10N03 10N03 PDF Download Note 8: CIN, COUT, C1, and C2: Low-ESR Surface-M
10N03L   10N03L 10N03L PDF Download INFIEON TO-263 00+ With a 144 pin package, low power consumption, v
10N03LA   10N03LA 10N03LA PDF Download Notes:  3. Typical specifications are the
10N05   10N05 10N05 PDF Download ON TO-252 98+ - 10, 8, 6 or 4bit up/down counting - Parallel
10N06   10N06 10N06 PDF Download 07+ TO-220 Although the LM2941 offers limiting circuitry fo
10N10   10N10 10N10 PDF Download † Stresses beyond those listed under absol
10N120   10N120 10N120 PDF Download TO-3P The ISL9G2060EG3, ISL9G2060EP3, and ISLPG2060ES3
10N120BN   10N120BN 10N120BN PDF Download HARRIS 05+ The OPA689 is a wideband, voltage feedback op am
10N120BND   10N120BND 10N120BND PDF Download FAIRCHIL TO-3P N/A With reference to Figure 4, assume that VDD is r
10N120BNS   10N120BNS 10N120BNS PDF Download   Typical represents the average reading at
10N20   10N20 10N20 PDF Download FSC TO-220 01+ The 10N20/72 is a device which may be used in p
10N301K   10N301K 10N301K PDF Download The Hynix HY57V641620HG is a 67,108,864-bit CMOS
10N40   10N40 10N40 PDF Download 07+ TO-220 Electrical and Optical Specifications Specificat
10N40E   10N40E 10N40E PDF Download Note 1. Stresses greater than those listed under
10N45   10N45 10N45 PDF Download (AVDD = +4.75V to +5.25V, DVDD = +2.7V to +5.5V,
10N50   10N50 10N50 PDF Download HARRIS TO-220 99+ n 5 Volt Read, Program, and Erase   C Mini
10N50E   10N50E 10N50E PDF Download When VCC is between 0 and 1.2 V, the device is i
10N50E1D   10N50E1D 10N50E1D PDF Download . TO-220 The switching PWM controller drives two N-Channel
10N60   10N60 10N60 PDF Download 原装ST TO-220 10000 Low Output Skew for Clock-Distribution and Clock
10N70   10N70 10N70 PDF Download Note 4: The Absolute Maximum Ratings are those va
10N80   10N80 10N80 PDF Download (1) Stresses beyond those listed under absolute
10N90   10N90 10N90 PDF Download   2.2.1 Specifications, standards, and hand
10NF   10NF 10NF PDF Download This is an internally modified SOIC−8 pack
10NF1KV   10NF1KV 10NF1KV PDF Download
10NF250V   10NF250V 10NF250V PDF Download Supply voltage for the LNA, bias circuits, and c
10NF3KV   10NF3KV 10NF3KV PDF Download
10NF500V   10NF500V 10NF500V PDF Download • Optimized for Quasi-Resonant Converter (
10NF63V   10NF63V 10NF63V PDF Download TIMING CONTROL FUNCTION The Timing Control func
10NH125A   10NH125A 10NH125A PDF Download 256 Megabit (256M) 0.17µm process technolo
10NH-20   10NH-20 10NH-20 PDF Download   The MC10/100EP05 is a 2−input differ
10NK250VDC   10NK250VDC 10NK250VDC PDF Download The two-wire bus is defined as a Serial Data lin
10NK250VDC/B32529C3333K(5MM)   10NK250VDC/B32529C3333K(5MM) 10NK250VDC/B32529C3333K(5MM) PDF Download FEATURES Single Chip Low Power UHF Transmitter
10NK25V   10NK25V 10NK25V PDF Download Hynix HYMD232646A(L)8J-J series is unbuffered 184
10NRD4KJST   10NRD4KJST 10NRD4KJST PDF Download Continuous Drain Current, VGS @ 10V (Silicon lim
10NXK3250V   10NXK3250V 10NXK3250V PDF Download Notes: 1. The nominal thermal resistance of a d
1(P)9193131169   1(P)9193131169 1(P)9193131169 PDF Download n 5 Volt Read, Program, and Erase   C Mini
1.0000MHZNTH030C   1.0000MHZNTH030C 1.0000MHZNTH030C PDF Download Capacitance measurements shall be made by means
1.000M   1.000M 1.000M PDF Download RF input pin. This pin is NOT internally DC bloc
1.000MHZ   1.000MHZ 1.000MHZ PDF Download KDS SMD 2005 ♦ 72dB ACLR at fOUT = 61.44MHz (Single-Carr
1.006-.321   1.006-.321 1.006-.321 PDF Download 1) The amplitude of the signal depends on the ob
1.008.279   1.008.279 1.008.279 PDF Download functional operation of the device at these or a
1.00A125VAC   1.00A125VAC 1.00A125VAC PDF Download † NOTICE: Stresses above those listed unde
1.00E11   1.00E11 1.00E11 PDF Download The STR73xF family is available in 3 packages. T
1.00E114   1.00E114 1.00E114 PDF Download Bidirectional Data I/O Lines. As inputs, they fe
1.00E12   1.00E12 1.00E12 PDF Download Most everything applies to driving the P-Channel
1.00MM8X1P180S   1.00MM8X1P180S 1.00MM8X1P180S PDF Download The ZZ input pin is an asynchronous input. Assert
1.00MM9X1P180S   1.00MM9X1P180S 1.00MM9X1P180S PDF Download The SN74CB3T16212 is a high-speed TTL-compatible
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