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Boundary scan instructions and associated data registers support a standard methodology for accessing and config- uring Virtex-II devices that complies with IEEE standards 1149.1 - 1993 and 1532. A system mode and a test mode are implemented. In system mode, a Virtex-II device per- forms its intended mission even while executing non-test boundary-scan instructions. In test mode, boundary-scan test instructions control the I/O pins for testing purposes. The Virtex-II Test Access Port (TAP) supports BYPASS, PRELOAD, SAMPLE, IDCODE, and USERCODE non-test instructions. The EXTEST, INTEST, and HIGHZ test instruc- tions are also supported.
n Watchdog fully operational from 2.7 to 5.25 V n Regulated DC voltage monitor, internal voltage   reference n Self recovering watchdog function: reset goes active   after the 1st timeout period, reset goes inactive   again after the 2nd timeout period, repeated active   reset signal until the system recovers n Standard timeout period and power-on reset time   (100 ms), externally programmable from 3 ms to   3 mins if required n Works down to 1.6 V supply voltage n Low voltage alarm prior to reset on power-down n Reset outputs of both polarities n Open drain outputs n Small footprint SO8 and DIP8 packages
High voltage drive to within 1.3 V of supply rails Output short-circuit protection High update rates Fast, 100 Ms/s, 10-bit input data update rate Low static power dissipation: 0.7 W   Includes STBY function Voltage-controlled video reference (brightness) and   full-scale (contrast) output levels INV bit reverses polarity of video signal 3.3 V logic, 9 V to 18 V analog supplies High accuracy voltage outputs Laser trimming eliminates the need for adjustments Flexible logic STSQ/XFR allow parallel 10N60 operation at various   resolutions Fast settling into capacitive loads   30 ns settling time to 0.25% into 150 pF load   Slew rate 460 V/µs Available in 48-lead 7 mm 7 mm LFCSP package