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Notes: 2. The Fmin values are based on a set of 16 noise figure measurements made at 16 different impedances using an ATN NP5 test system. From these   measurements Fmin is calculated. Refer to the noise parameter measurement section for more information. 3. Measurements taken above and below 2 GHz was made using a double stub tuner at the input tuned for low noise and a double stub tuner at the   output tuned for maximum OIP3. Circuit losses have been de-embedded from actual measurements.
When 16/68# pin is at logic 1 for Intel bus interface, this output becomes channel B interrupt output. The output state is defined by the user and through the software set- ting of MCR[3]. INTB is set to the active mode and OP2B# output to a logic 0 when MCR[3] is set to a logic 1. INTB is set to the three state mode and OP2B# to a logic 1 when MCR[3] is set to a logic 0. See MCR[3]. When 16/68# pin is at logic 0 for Motorola bus interface, this output is not used and will stay at logic zero level. Leave this output unconnected.
The A030300001 is a Flash memory device designed for use in PC and notebook BIOS applications. The device complies with version 1.1 of Intels LPC Interface Spec- ification, providing support for both FWH and LPC memory read and write cycles. The device can also automatically detect the memory cycle type to allow the A030300001 to be used as a FWH with Intel chipsets or as an LPC Flash with non-Intel chipsets.