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Collision Output. Balanced differential line driver outputs from the collision detect circuitry. The 10 MHz signal from the internal oscillator is transferred to these outputs in the event of collision, excessive transmission (jabber), or during CD Heartbeat condition. These outputs are open emitters; pulldown resistors to VEE are required. When operating into a 78Ω transmission line, these resistors should be 510Ω. In Cheapernet applications, where the 78Ω drop cable is not used, higher resistor values (up to 1.5k) may be used to save power.
  PCI hot-plug and CompactPCI™ hot-swap support   +12V, +5V, +3.3V, and C12V power supply control   Circuit breaker function to protect system   Programmable slew rate control for all supplies   Foldback current-limiting   +5V and +3.3V programmable current-limit thresholds   Undervoltage and overcurrent diagnostic outputs   Deglitch filters on diagnostic fault outputs   Integrated +12V and C12V MOSFET switches   Integrated high-side drivers for 3.3V and 5V external   switches • Precharge supply for CompatPCI™ I/O termination
  Smooth out traffic to uplink port   Ingress Rate Control   - Back pressure   - Flow Control   - WRED (Weighted Random Early Discard) • Egress Rate Control • Down to 16 kbps Rate Control granularity Per queue traffic shaper on uplink port Packet Filtering and Port Security • Static address filtering for source and/or destination MAC • Static MAC address not subject to aging • Secure mode freezes MAC address learning (each port may independently use this mode) • Supports port authentication (IEEE 802.1x) QoS Support • Supports IEEE 802.1p/Q Quality of Service with 2 transmission priority queues (4 for uplink port), with   strict priority and/or WFQ service disciplines • Provides 2 levels of dropping precedence with WRED mechanism • User controls the WRED thresholds. • Buffer management: per class and per port buffer reservations • Port-based priority: VLAN priority in a tagged frame can be overwritten by the priority of Port VLAN ID Supports per-system option to enable flow control for best effort frames even on QoS enabled ports Classification based on: • Port based priority • VLAN Priority field in VLAN tagged frame • DS/TOS field in IP packet • UDP/TCP logical ports: 8 hard-wired and 8 programmable ports, including one programmable range The precedence of the above classifications is programmable Supports IEEE 802.3ad link aggregation • Up to 8 trunk groups, with up to 8 ports per group • Supports load sharing among trunk ports based on:   - Source port   - Source and/or destination MAC address Supports module hot swap on all ports MIB Statistics counters for all ports Full Duplex Ethernet IEEE 802.3x Flow Control Backpressure flow control for Half Duplex ports Hardware auto-negotiation through MII management interface (MDIO) for Ethernet ports Built-in reset logic triggered by system malfunction Built-In Self Test for internal SRAM IEEE-1149.1 (JTAG) test port
Parr number/PDF Mfg Pack D/C Descrpion
B071080002   B071080002 B071080002 PDF Download PHI PQFP44 07+ Each intersection point predicts the voltage of
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B07MC332633   B07MC332633 B07MC332633 PDF Download frb frb dc92+ 3V to 3.6V operating voltage 48MHz to 160MHz out
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B07TG   B07TG B07TG PDF Download COILCRAFT 08+ f. A row of components must be centered between
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B.H.S-26(2.54MM)   B.H.S-26(2.54MM) B.H.S-26(2.54MM) PDF Download Program Verify Command Following byte program,
B/S/B8348   B/S/B8348 B/S/B8348 PDF Download   The ST-BUS architecture can be used both
B/T/BM6485.1   B/T/BM6485.1 B/T/BM6485.1 PDF Download 300mV max Priority management system prevents p
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B00018HA   B00018HA B00018HA PDF Download Infineon MQFP144 99+ Three status indicators on the keyboard-Num Lock,
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