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The UCC5631A is used in multi-mode active termination applications, where single ended (SE) and low voltage differential (LVD) devices might coexist. The UCC5631A has both SE and LVD termination networks integrated into a single monolithic component. The correct termina- tion network is automatically determined by the SCSI bus "DIFSENS" signal.
P1 is a 4-bit input port, P2 and P3 are two 4-bit I/O ports. Any bit of P2 and P3 can be programmed as either input or output port individually. Any valid data transition (H L or L H) of P1, P2 and P3 can reactivate the chip when the chip is in power-down mode.
This device consists of a PIN photo- diode and a transimpedance amplifier assembled in a TO-46 package. It is designed for short-distance ATM up to 155 Mbps. The preamplifiers lin- earity and absence of automatic gain control makes it ideal also for analog applications and applications with bursty signals. Its double-lens optical system is designed for single-mode fiber as well as for multimode fiber with core diameter up to 62.5µm.
Parr number/PDF Mfg Pack D/C Descrpion
BJ3085   BJ3085 BJ3085 PDF Download Common Features • BJ3085T, BJ3085T, and
BJ3157F-2C   BJ3157F-2C BJ3157F-2C PDF Download † The TPS75x01 is programmable using an ex
BJ3450P   BJ3450P BJ3450P PDF Download The R/B output indicates the status of the device
BJ3450S   BJ3450S BJ3450S PDF Download The 12-bit ADCs provide excellent undersampling
BJ378GK   BJ378GK BJ378GK PDF Download
BJ378GKFUTABA   BJ378GKFUTABA BJ378GKFUTABA PDF Download The high-side driver is designed to drive low rD
BJ379-9   BJ379-9 BJ379-9 PDF Download LATCHED ADDRESS BUS: Low-order bits of the syste
BJ399   BJ399 BJ399 PDF Download serial interface that uses a bi-directional data
BJ3FT   BJ3FT BJ3FT PDF Download   The 50C/W for the D2PAK package assumes th
B.H.S-26(2.54MM)   B.H.S-26(2.54MM) B.H.S-26(2.54MM) PDF Download Program Verify Command Following byte program,
B/S/B8348   B/S/B8348 B/S/B8348 PDF Download   The ST-BUS architecture can be used both
B/T/BM6485.1   B/T/BM6485.1 B/T/BM6485.1 PDF Download 300mV max Priority management system prevents p
B000102   B000102 B000102 PDF Download The device is compatible with the JEDEC single-
B00017   B00017 B00017 PDF Download infineon QFP 03+/04+   These N-Channel power MOSFETs   ar
B00017HA   B00017HA B00017HA PDF Download Infineon MQFP144 03+ The MAX2205 has high-input impedance for use with
B00018   B00018 B00018 PDF Download INFINEON 04+ TQFP2020-144 cycle signals between 3MHz and 15 MHz as well as
B00018HA   B00018HA B00018HA PDF Download Infineon MQFP144 99+ Three status indicators on the keyboard-Num Lock,
B00019   B00019 B00019 PDF Download INFINEON 01+ QFP144 B ild / Fig. 7 W1C - E inpha sen -We ch selweg s
B00019HA   B00019HA B00019HA PDF Download Infineon MQFP144 99+ current is out of regulation, the LED_rtn voltag
B0006A201   B0006A201 B0006A201 PDF Download sie sie dc94 Product term sharing is the process of using the
B001   B001 B001 PDF Download 16-bit multi-function timer supporting   PW
B00117CA   B00117CA B00117CA PDF Download Stresses above those listed as absolute maximum
B00119   B00119 B00119 PDF Download infineon QFP 03+/04+ † Measured on typical two-sided PWB with p
B00119CA   B00119CA B00119CA PDF Download Infineon MQFP144 03+ In addition to the programmable 1024-bits of mem
B0019   B0019 B0019 PDF Download INFINEON 2008 Notes: 1. Caution: The SYSCLK frequency, PLL_CFG
B002   B002 B002 PDF Download SOT-89 02+ o Integrated 16-Bit DAC and 32-Channel SHA with
B002/75C   B002/75C B002/75C PDF Download ST TSSOP14 03+ Current sense pin of the LDO. Overcurrent protect
B0026M1   B0026M1 B0026M1 PDF Download SONY O7+ Hynix HYMD232G726B(L)8-M/K/H/L series incorporate
B0031338   B0031338 B0031338 PDF Download Infineon 2003 TQFP Input Voltage Noise Non-Inverting Input Curren
B003138   B003138 B003138 PDF Download  Beneficial comments (recommendations, addit
B003838   B003838 B003838 PDF Download The following circuit shows a charged monitor for
B00489   B00489 B00489 PDF Download   The SY88713V generates a PECL SD output.
B005   B005 B005 PDF Download ST TSSOP Note 6: In the application the HS node is clamped
B0057100   B0057100 B0057100 PDF Download The Am79C987 Hardware Implemented Management In
B006/9341   B006/9341 B006/9341 PDF Download ST TSSOP14 03+   The SY88713V generates a PECL SD output.
B008   B008 B008 PDF Download ST TSOP
B00909   B00909 B00909 PDF Download ¥ PC/104 standard expansion module ¥ Co
B01043   B01043 B01043 PDF Download AT49BV/LV001NT pin 1 for the DIP and PLCC packag
B010550   B010550 B010550 PDF Download BOSCH 模块 模块 The DS1481 also supports overdrive communication
B01056   B01056 B01056 PDF Download The UCC381 family of low dropout linear (LDO) re
B01-05CP(A)   B01-05CP(A) B01-05CP(A) PDF Download teristics and internal reliability and qualifica
B01065   B01065 B01065 PDF Download PARAMETER Collector-emitter voltage peak value
B01066   B01066 B01066 PDF Download Model WS81. The WS81 donut shaped 100 ohm RTD e
B01069   B01069 B01069 PDF Download
B01075   B01075 B01075 PDF Download A computers RS232 transmit signal can be directl
B010767   B010767 B010767 PDF Download BOSCH 模块 模块 • 0.23 µm Process Technology •
B010L8302   B010L8302 B010L8302 PDF Download This N-Channel MOSFET has been designed specific
B01107   B01107 B01107 PDF Download The LT®4256-3 is a high voltage Hot Swap cont
B01108   B01108 B01108 PDF Download Differential output for the synthesizer. LVPECL
B01109   B01109 B01109 PDF Download General Notes: 1. Units in the JPM-A series of Q
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