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STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions TA = 25C, VDD = VM = 5.0 V, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Synchronous Output Enable. When HIGH, it stops clock outputs (except 2Q0 and 2Q1) in a LOW state (for PE = H) - 2Q0 and 2Q1 may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and sOE is HIGH, the nF[1:0] pins act as output disable controls for individual banks when nF[1:0] = LL. Set sOE LOW for normal operation (has internal pull-down).
The DG403DJ incorporates a 16C550A compatible UART and one Multi-Mode parallel port with ChiProtect circuitry plus EPP and ECP support. The DG403DJ does not require any external filter components, is easy to use and offers lower system cost and reduced board area.