The AIC111 IC design specification serves to provide product development teams with a guideline for how the AIC111 IC is specified and programmable options that are available. The document outlines a top-level block description of the IC along with system specifications and functions. Individual block descriptions and target specifications are also outlined.
Unless otherwise stated, VCC=18V, RSET=15k to ground, CT=1.5nF to ground, PKLMT=1V, ENA=7.5V, ELECTRICAL VRMS=1.5V, IAC=100µA, ISENSE=0V, CA Out=3.5V, VA Out=5V, VSENSE=7.5V, no load on SS, CA Out, CHARACTERISTICS VA Out, REF, GT Drv, C55oC<TA<125oC for the UC1854, C40oC<TA<85oC for the UC2854, and
Note 1: Power dissipation is 500 mW when mounted as recommended. Derate at 4.0 mW/C for operation above 25 C. Gen Note: Exceeding the Absolute Maximum Ratings may damage the device. Gen Note: Parameters with min. or max. values are 100% tested at TA = 25 C. Gen Note: Ripple rejection is @ 60 dB when f = 400 Hz, CL = 10 µF, CN = 0.1 µF, input noise = 100 mVrms, VIN = VOUT(TYP) + 1.5 V and IOUT = 30 mA. Gen Note: Output noise is 0.13 ~ 0.23 µV/ Hz at 1 kHz when CN = 0.1 µF.
Unless otherwise stated, VCC=18V, RSET=15k to ground, CT=1.5nF to ground, PKLMT=1V, ENA=7.5V, ELECTRICAL VRMS=1.5V, IAC=100µA, ISENSE=0V, CA Out=3.5V, VA Out=5V, VSENSE=7.5V, no load on SS, CA Out, CHARACTERISTICS VA Out, REF, GT Drv, C55oC<TA<125oC for the UC1854, C40oC<TA<85oC for the UC2854, and
Note 1: Power dissipation is 500 mW when mounted as recommended. Derate at 4.0 mW/C for operation above 25 C. Gen Note: Exceeding the Absolute Maximum Ratings may damage the device. Gen Note: Parameters with min. or max. values are 100% tested at TA = 25 C. Gen Note: Ripple rejection is @ 60 dB when f = 400 Hz, CL = 10 µF, CN = 0.1 µF, input noise = 100 mVrms, VIN = VOUT(TYP) + 1.5 V and IOUT = 30 mA. Gen Note: Output noise is 0.13 ~ 0.23 µV/ Hz at 1 kHz when CN = 0.1 µF.
| Parr number/PDF | Mfg | Pack | D/C | Descrpion |
F730 F730  |
The RUN/SS pin provides soft-start and optional t | |||
| F7301 F7301 |
N/A | N/A | N/A | Input bus select / I2C clock input. The operatio |
| F7303 F7303 |
97 | In addition to the high-speed converter and vers | ||
| F7304 F7304 |
N/A | N/A | N/A | CAUTION: These devices are sensitive to e |
| F7305 F7305 |
IR | O7+ | • 1500 Watts for 10/1000 µs with rep | |
| F7306 F7306 |
IR | SOP-8 | 05+ | Pin Description Address. The 15 address lines s |
| F7307 F7307 |
IR | SOP-8 | 05+ | Power supply voltage VDD = 2.3 V~3.6 V O |
| F7309 F7309 |
IR | SOP-8 | 05+ | 5. CPD is defined as the value of the internal e |
| F731018GJU F731018GJU |
BGA | Notes: ΠRepetitive rating; pulse width li | ||
| F7311 F7311 |
IR | These enhancement-mode (normally-off) transistor | ||
| F731136/AX F731136/AX |
TI | QFP- | ERASE/PROGRAM STATUS BIT: The device offers a sta | |
| F731136B/AX F731136B/AX |
TI | QFP- | A burst write access to an active row is initiat | |
| F731136B/P F731136B/P |
NQRTEL | QFP- | Interpoints HUMMER™ Hold-Up Module Series | |
| F731136C1/A F731136C1/A |
TI | QFP- | High and low band filters are included to shape t | |
| F731136D1/A F731136D1/A |
TI | QFP- | Pin Description Motor Supply Voltage Control Lo | |
| F731136E/AX F731136E/AX |
TI | QFP- | The internal circuit is composed of 2 stages in | |
| F73127APAG F73127APAG |
General purpose pin 4 General purpose pin 3 R | |||
| F7313 F7313 |
IR | SOP-8 | 05+ | The M54/74HC4020/HC4040 are high speed CMOS 14/ |
| F7314 F7314 |
IR | SOP-8 | 05+ | slave devices in the I 2C protocol with all memo |
| F731486GJU F731486GJU |
99 | n Higher gain to match LM126X CMOS preamplifiers | ||
| F731497AGHU F731497AGHU |
FUJITSU | BGA | 07+ | One or more of the following United State |
| F7314Q F7314Q |
IR | SOP-8 | 05+ | ter File, which includes the control and status |
| F731532APGE F731532APGE |
The LVT574 and LVTH574 consist of eight edge-tri | |||
| F731541PGF F731541PGF |
TI | QFP | 07+ | MSL1 = unlimited floor life at <30C / 85% Rela |
| F731567A/P F731567A/P |
HP | O7+ | The period required by the retransmit ope | |
| F731567AGDF F731567AGDF |
TI | BGA | 07+ | Isolated Hermetic Package, JEDEC TO-257AA Outlin |
| F731587DGHZR F731587DGHZR |
DESCRIPTION Using the latest high voltage techn | |||
| F731589DPGE F731589DPGE |
TI | 07+ | Bidirectional 8-bit input/output port. Each bit | |
| F731590/AX F731590/AX |
• Robust High Voltage Termination • A | |||
| F731590/P F731590/P |
Other features include an active-low, power-OK ou | |||
| F731590A F731590A |
An optional feedback resistor can be placed betwe | |||
| F731590A/P F731590A/P |
CISCO | BGA | N/A | • TTL-Compatible 5-Bit Digital Output Volt |
| F731590AGJM F731590AGJM |
TI | BGA | 03+ | • Ampelanwendung • Hinterleuchtung |
| F731590AGPG F731590AGPG |
CISCOSYSTEMS | BGA | BGA | Organized as 4,194,304 words by 16 bits Single p |
| F731590DGNP F731590DGNP |
TEXAS | BGA | BGA | All of the bytes in the chip must be verified to |
| F731590EGNP F731590EGNP |
CISCO SYSTEMS | 98+ | BGA | The configuration EEPROM RESET/OE and CE pins co |
| F7316 F7316 |
IR | SOP-8 | 05+ | This deadtime should allow for the turn o |
| F731648APGE F731648APGE |
CHIPS | 2007 | ||
| F731651AGGUR F731651AGGUR |
TI | 07+ | Fig. 5A represents an additional pull down resis | |
| F731651GGU F731651GGU |
TI | 07+ | CAUTION: These devices are sensitive to e | |
| F731651GGUR F731651GGUR |
TI | 07+ | ||
| F731652A F731652A |
The processor also integrates four complete data | |||
| F731653GGW F731653GGW |
TEXASINS | BGA | Full compliance with the USB Specification v1.1 | |
| F731672/P F731672/P |
BGA | FUJ | 00+ | During steady-state operation for a typical swit |
| F731675GFN F731675GFN |
TEXAS INS | BGA | PLL1, CLKA, and CLKB each have multiple registers | |
| F731678APGE F731678APGE |
TI | QFP/144 | 01+ | Product of input modulation: f = 44MHz, Df = 214 |
| F73168APGE F73168APGE |
100% production tested. 100% production tested a | |||
| F731690ADDT F731690ADDT |
TI | also be used independent of the HALT or IDLE mod | ||
| F7317 F7317 |
N/A | N/A | N/A | The C6701 includes a large bank of on-chip memor |
| F731723CGGURE F731723CGGURE |
The MAX5236/MAX5237 precision, dual, voltage-out- | |||
| F731727APAG F731727APAG |
TI | QFP/64 | 01+ | Two-Wire I²C Serial Interface Supports 400 |
| F731727APAG-0119 F731727APAG-0119 |
TI | 01+ | • Fast Page Mode Access Cycle • TTL | |
| F731727PAG F731727PAG |
TI | QFP/64 | 01+ | This document is a general product description an |
| F731739G/P F731739G/P |
TI | BGA | 02+ | The CIP 3250A is a new CMOS IC that contains on |
| F731742BPTR F731742BPTR |
TI | 00+ | erase operation completion. Ready/Busy pin (RY | |
| F731745 F731745 |
The Fairchild RM3182A line driver is the compani | |||
| F731745/AX F731745/AX |
ships. Data for left and right channel output is | |||
| F731745A/P F731745A/P |
below). In this mode, data is transmitted on the | |||
| F731745AGGZ F731745AGGZ |
CiscoSystems | O7+ | ||
| F731745AGGZ-980C F731745AGGZ-980C |
5. This product is not designed to be radiation | |||
| F731745AGNP F731745AGNP |
N/A | BGA | The FETKY™ family of Co-Pack HEXFET® Po | |
| F731791CPBK F731791CPBK |
TI | The TTL level LOOP pin is used to perform loop-b | ||
| F731791CPBKTEB F731791CPBKTEB |
5. Turn-Off Energy Loss (EOFF) is defined as the | |||
| F731791CPBK-TEB F731791CPBK-TEB |
TI | TQFP1414 | 0149+ | If the 3-wire port is used, the master provides o |
| F731807AGLM F731807AGLM |
TI | BGA | 07+ | |
| F731815AQHQ F731815AQHQ |
BGA | • True dual-ported memory cells that allow | ||
| F731816/AX F731816/AX |
The F731816/AX executes a read cycle whenever WE | |||
| F731816/P F731816/P |
Designed for PCN and PCS base station appl | |||
| F731821APGE F731821APGE |
TI | QFP | When LE is LOW the latches store the information | |
| F731823/P(SBM1210) F731823/P(SBM1210) |
DESCRIPTION The M48Z35/Y ZEROPOWER® RAM is | |||
| F731828EGGVR F731828EGGVR |
TI | Serial Data present at the input is trans | ||
| F731828FGGVR F731828FGGVR |
TI/ERICSSON | BGA | 06+ | The differential inputs provide a full scale sel |
| F731849PGE F731849PGE |
7. The CH1817 DAA as is meets or exceeds the &nb | |||
| F731856BGHM F731856BGHM |
CiscoSystems | O7+ | The SONIC (Figure 1-1 ) consists of an encoder de | |
| F731856BGNP F731856BGNP |
CISCO SYSTEMS | 98+ | BGA | NOTES 1Sample tested during initial release and |
| F731861AGHF F731861AGHF |
BGA | BGA | Actually the extremly high input impedance is i | |
| F731861AGLM F731861AGLM |
N/A | BGA | On power-up, the DS1804 will load the value of EE | |
| F731864A/P F731864A/P |
TI | BGA | 02+ | Programmable versions of the PT6700 and PT6720 s |
| F731874AGHH F731874AGHH |
01 | The current consumption of the VCAs will be dire | ||
| F731874GHH F731874GHH |
TI | BGA | 06+ | Parameter Supply Voltages Positive Suppl |
| F731886BPZ F731886BPZ |
00 | 64K8-bit organization Fast read access time: 70n | ||
| F731891PDV F731891PDV |
CISCO | QFP | 00+ | the performance for a wide range of applications |
| F7319 F7319 |
N/A | N/A | N/A | The CP3SP33 connectivity processor combines high |
| F731957AGKP F731957AGKP |
CRSCO | BGA | 00+ | Notes 1. Device is considered as a two terminal |
| F731957BGKP F731957BGKP |
CISCO | BGA | 0636+ | Ruotare il selettore su OC . Quando lalimentazi |
| F731993APGE F731993APGE |
TI | 07+ | AVDD Operating CurrentIAVDDVAVDD = 20V20&mi | |
| F7321 F7321 |
IR | SOP-8 | 05+ | DRVOUT: (gate drive) The output drive for the boo |
| F7321B F7321B |
PHI | 03+ | SSOP-5.2-20P | Electrically isolated: DBC base plate 3500 VRMS |
| F7322 F7322 |
IOR | O7+ | READY/BUSY: Indicates status of the internal WSM. | |
| F7324 F7324 |
IR | SOP-8 | 05+ | Description The 14.22 mm (0.56 inch) LED dual d |
| F7325 F7325 |
||||
| F7326 F7326 |
N/A | N/A | N/A | Input or Output Voltage (DC or Transient) (Refere |
| F7328 F7328 |
IR | O7+ | OSC1, OSC2 are connected to an RC network | |
| F7331 F7331 |
IR | SO-8 | 04+ | The design is based on an ARM7® microprocess |
| F7335D1 F7335D1 |
IOR | SOP | 07+ | The Header word is a 4 bit Manchester cod |
| F7338 F7338 |
IR | SOP-8 | 05+ | • High speed CMOS logic hex non-inverting |
| F7341 F7341 |
IOR | Maskable Interrupts on all I/O pins 8-bi | ||
| F7341Q F7341Q |
IR | SOP-8 | 05+ | 2 channel 8-bit timer/counter operation (indepen |
| F7342 F7342 |
IR | SOP-8 | 05+ | Protect Register Enable (PREN) The PREN instruct |
| F7343 F7343 |
N/A | N/A | N/A | Notes: 1. Dimensions A and B are datums and T i |
| F7353 F7353 |
IR | O7+ | Over recommended operating free-air temperature | |
| F7357 F7357 |
(4) The products and product specifications desc | |||
| F7358D F7358D |
SE: 1 W to 7.5 W; BTL: 2 W to 15 W operation pos | |||
| F7379 F7379 |
IR | SOP-8 | 04+ | Sector Erase and Bulk Erase The Page Program (P |
| F7380X F7380X |
The sequence of the burst counter is determined b | |||
| F7389 F7389 |
N/A | N/A | N/A | • Three video anti-aliasing or reconstruct |
| F73SP F73SP |
Please be aware that an important notice |
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