| Parr number/PDF | Mfg | Pack | D/C | Descrpion |
| GS301A GS301A |
N/A | QFP80 | 07+ | The MAX4763/MAX4765 include a comparator that can |
| GS3036H GS3036H |
N/A | CAN3 | N/A | DESCRIPTION The device is a power supply contro |
| GS3037H GS3037H |
N/A | CAN3 | N/A | † Stresses beyond those listed under absol |
| GS3040H GS3040H |
N/A | CAN3 | N/A | Figure 3 shows the proper connection of the VRE3 |
| GS305BS2-1 GS305BS2-1 |
GOIDSTAR | Two Pulse Width Modulator modules, each with six | ||
| GS31001500J-LF GS31001500J-LF |
The LM77 is a digital temperature sensor and the | |||
| GS31003301J GS31003301J |
This is a complete series of 1 Watt Zener | |||
| GS31003833F GS31003833F |
Current Transfer Ratio (CTR)1000 4000 Collector | |||
| GS3112-03 GS3112-03 |
Stresses beyond those listed under "Absolute | |||
| GS311203F GS311203F |
ABSOLUTE MAXIMUM RATINGS Absolute maximum ratin | |||
| GS3112-03-F GS3112-03-F |
0013 | 3. Similar Quadraphase Demodulators are available | ||
| GS3137 GS3137 |
IC | SOP | The IC provides 12 key inputs (KEY1~KEY12). Of | |
| GS313708F GS313708F |
12-Bit DAC with Serial Digital Input Interface N | |||
| GS3137-08-F GS3137-08-F |
0003 | DESCRIPTION Using the latest high voltage techn | ||
| GS313708T GS313708T |
The MAX101 ECL-compatible, 500Msps, 8-bit analog- | |||
| GS3137-08T GS3137-08T |
GLOBE | TSSOP | 05+ | 180-240V AC single-phase input, 50/60 Hz Single |
| GS3137-08-T GS3137-08-T |
GLOBESPANS | 1. Stresses above those listed under the Absolut | ||
| GS3137-08TA GS3137-08TA |
N/A | N/A | 2006+ | |
| GS3137-08-TA GS3137-08-TA |
GLOBESPAN | SSOP28 | 0723+ | NOTES: 1Full Scale Range (FSR) is 10V for unipo |
| GS3137-08-TAZ GS3137-08-TAZ |
GLOBESPAN | TSSOP28 | 0721+ | ActiveThe device operates at full speed using the |
| GS3137-08TAZTR GS3137-08TAZTR |
is provided by an active LOW Chip Enable (CE), a | |||
| GS3137-8-T GS3137-8-T |
N/A | SSOP | N/A | A word-width-select option is provided on |
| GS3180-01 GS3180-01 |
The PSoC™ family consists of many Mixed-Si | |||
| GS3180-01-A GS3180-01-A |
GLOBE | QFP | QFP | The Data ALU registers can be read or written ov |
| GS32 GS32 |
FAI | SMD0805 | Wide supply voltage range from 1.65 V to 5.5 V | |
| GS322522-1R2K GS322522-1R2K |
PANASONIC | 3225-1R2K | n Pop & click circuitry eliminates noise dur | |
| GS322522-2R2K GS322522-2R2K |
N/A | 3225 | Memory encompasses 16 KB of Flash for program st | |
| GS322522-4R7K GS322522-4R7K |
N/A | 3225 | The capacitance (Ciss) is read from the capacita | |
| GS322522R-100J GS322522R-100J |
KOA | 3225-100J | 05+ | This is the master clock input pin. The c |
| GS3232-203 GS3232-203 |
44 | GLOBESPA | Encoder input and decoder output filters are inc | |
| GS3232203001D GS3232203001D |
NOTES: 1. The Phase Voltage is capable of | |||
| GS3232-203-001D GS3232-203-001D |
GS | TQFP | 05+ | In the EDO page mode, read (data out) and |
| GS3232-203-001D-DB GS3232-203-001D-DB |
The bq2083−V1P2 SBS-compliant gas gauge IC | |||
| GS32437TT GS32437TT |
This mode allows high speed download with bitrate | |||
| GS324S GS324S |
GS | 00+ | SOP-14 | Note 1 : The maximum junction temperature rating |
| GS3253Q GS3253Q |
Calibrated directly in Kelvin Line | |||
| GS3316C-150M GS3316C-150M |
N/A | Hardware Reset, active Low. Provides a hardware m | ||
| GS3316C-470M GS3316C-470M |
The transition from VIH to VID must be slower t | |||
| GS3316F-221M GS3316F-221M |
YAGEO | • In-Circuit Serial Programming (ICSP͐ | ||
| GS3316F-4R7 GS3316F-4R7 |
N/A | The Sensitivity of the test fixture Figure 12 is | ||
| GS3316P-6R8M GS3316P-6R8M |
N/A | Up to eight devices (two for the MSOP package) m | ||
| GS3318M GS3318M |
NS | SOP-8 | 05+ | Note 4: Limits are 100% production tested at 25 |
| GS33AB GS33AB |
NA | 02+ | When this input pin transitions from LOW to HIGH, | |
| GS34063P GS34063P |
IC | DIP | 0028+ | The ISL6115 has an integrated charge pump allowin |
| GS34063S GS34063S |
GS | 05+ | Totally Synchronous Operation All Outputs Buffer | |
| GS34063SF GS34063SF |
♦ Four Regulators in One Package ♦ | |||
| GS345821 GS345821 |
After a successful ATR, the Protocol and Paramet | |||
| GS345-HYB2100 GS345-HYB2100 |
SOSHIN | • Flame retardant encapsulant (UL 94V-0). | ||
| GS34X2245Q3 GS34X2245Q3 |
IDT | SOP-80 | 04+ | VBST (Pin 2): Boosted Switch Supply. This boosted |
| GS34X245Q3 GS34X245Q3 |
IDT | SOP-80 | 04+ | Indirect addressing options provide addressing f |
| GS3524AF GS3524AF |
01 | Like all of the UltraLogic™ FLASH370i devic | ||
| GS3526N GS3526N |
TERMINATION (VTT) HCLKI Termination &nb | |||
| GS35AC GS35AC |
BGA | 02+ | The parts (D) and (E) of figure 3 relate to the | |
| GS36129(24.5535MHZ) GS36129(24.5535MHZ) |
Four- ('390), Eight- ('388A), or Sixteen- ('386) | |||
| GS3710-271-001D GS3710-271-001D |
The transmission codes of the HT6221/6222 consist | |||
| GS3720-274-001R GS3720-274-001R |
One 64 x 8 (512-bit) Configuration Zone | |||
| GS3720-474 GS3720-474 |
GLOBESPA | QFP | This document is a general product description an | |
| GS3720-474-001 GS3720-474-001 |
These receivers adopt the all-in-view positionin | |||
| GS3720-474-001M GS3720-474-001M |
GSI | QFP | QFP | The integrated receiver is intended to be used a |
| GS3720-474-001R GS3720-474-001R |
GLOBESPA | BGA | 01+ | The NJU26108 audio interface provides industry st |
| GS3720-474-001R11 GS3720-474-001R11 |
For wireless LAN applications, the device meets t | |||
| GS3720-674-001R GS3720-674-001R |
CONEXANT | 06-07+ | The format conversion produced in the demultiple | |
| GS3750-474-001R GS3750-474-001R |
BGA | 0609+ | complement of the page address indicated by the | |
| GS3750-474-001RA2 GS3750-474-001RA2 |
GLOBESPAN | BGA | 03+ | The DS26502 is a building-integrated timing- sup |
| GS3750-474-001R-A2 GS3750-474-001R-A2 |
Single 5V operation Low power | |||
| GS3750-474-001RAZ GS3750-474-001RAZ |
CONEXANT | 06-07+ | The XPLA3 architecture follows a simple timing m | |
| GS3760-401-002AA-A2 GS3760-401-002AA-A2 |
The 12-bit ADCs provide excellent undersampling | |||
| GS3770-174 GS3770-174 |
LUCENT | TQFP1010-64 | 00+ | The EC000 core offers sixteen 32-bit registers a |
| GS3770174001H GS3770174001H |
An output enable (OE) pin is provided to three-s | |||
| GS3770-174-001H GS3770-174-001H |
GS | TQFP | 05+ | 7. Series resistance of the resonator (ceramic re |
| GS3770-174-001-H GS3770-174-001-H |
Copyright © 2003 SigmaTel, Inc. All rights r | |||
| GS3771-174 GS3771-174 |
ZILOG | QFP | 00+ | The basic unit of logic on the ispLSI 2032V devi |
| GS3771-174-001 GS3771-174-001 |
Ideal for battery operated applications; the MIC5 | |||
| GS3771-174-001A GS3771-174-001A |
CAUTION: These devices are sensitive to e | |||
| GS3771-174-001H GS3771-174-001H |
LG | QFP-M64P | 6+ | Note 6: Load and line regulation are measured at |
| GS3771-174-001HA GS3771-174-001HA |
QFP-M64P | 6+ | ||
| GS3771-174-00H GS3771-174-00H |
The M54/74HC4017 is a high speed CMOS DE- CADE | |||
| GS3771-HA001 GS3771-HA001 |
External gain-setting capability A | |||
| GS3780-170012 GS3780-170012 |
05-07+ | Note 7: All limits guaranteed at room temperature | ||
| GS3780-174 GS3780-174 |
GLOBESPA | QFP | The Low Power SDRAM provides for programmable opt | |
| GS3780-174-0012 GS3780-174-0012 |
GlobeSpan | TQFP | 04+ | |
| GS3780-174-0012D GS3780-174-0012D |
GLOBESPA | TQFP | 0343/16+ | Note 4 WS (tWAIT) c (number of preprogrammed wait |
| GS3780-174-0017 GS3780-174-0017 |
The power factor controller section consists of t | |||
| GS3780174001Z GS3780174001Z |
globe | globe | dc0402 | Referring to the block diagram, the current moni |
| GS3780-174-001Z GS3780-174-001Z |
T | QFP-M64P | QFP | Sector/Block Erase Operation The Sector/Block E |
| GS3780-174-001ZD GS3780-174-001ZD |
GS | TQFP | 05+ | • Asynchronous loading of control paramete |
| GS3800-808-001 GS3800-808-001 |
CONEXANT | 0525+ | BGA | PARAMETER Serial Clock Frequency Bus Fr |
| GS3800-808-001AA GS3800-808-001AA |
GS | BGA | 05+ | In message mode the CPU writes data to the Connec |
| GS3800-808-001AAB1 GS3800-808-001AAB1 |
MOT | BGA | BGA | The PCF8813 is a low power CMOS LCD controller d |
| GS3800-808-001AA-B1 GS3800-808-001AA-B1 |
The device features fully programmable R and N c | |||
| GS3800-808-001AABI GS3800-808-001AABI |
Entering SIMD mode also has an effect on the way | |||
| GS3800-808-011AA GS3800-808-011AA |
BGA | The Sidac is a silicon bilateral voltage trigger | ||
| GS3800-808-011AAZ GS3800-808-011AAZ |
CONEXANT | 08+ | ||
| GS3800Q GS3800Q |
Max. UnitsConditions CCCVVGE = 0V, IC = 500&micr | |||
| GS3800S GS3800S |
GSI | ISOLATION PARAMETERS Rated Voltage, Continuous | ||
| GS3820-826-001CC GS3820-826-001CC |
CONEXANT | 06-07+ | Permanent device damage may occur if Absolute Max | |
| GS3820-850-001CC GS3820-850-001CC |
GLOBESPA | BGA | 04+ | The AD581 is easy to use in virtually all precis |
| GS3842BDR14 GS3842BDR14 |
SGS | SMD | 99+ | NOTE: 1. 10K series circuits are designed to me |
| GS3845A GS3845A |
99+ | DIP | No products described or contained herein | |
| GS386 GS386 |
N/A | SOP8 | N/A | Notes: (1) See SOA curves or consult factory for |
| GS38A30801 GS38A30801 |
MOTOROLA | PLCC | 00+ | Room = 25C, Full = as determined by the operatin |
| GS38AC30801 GS38AC30801 |
MOTOROLA | PLCC | (2) Storage The LEDs should be stored at | |
| GS38AC30801FN GS38AC30801FN |
On receipt of PWM signal start instruction | |||
| GS38BC374PM01R2 GS38BC374PM01R2 |
RC32300 32-bit Microprocessor C Enh | |||
| GS38JC300 GS38JC300 |
MOTOROLA | PLCC | 00+ | • Multiplexed Inputs: 1, 2, 6 or 8 channels |
| GS38LC321PG06 GS38LC321PG06 |
mot | mot | dc96 | Schottky Barrier Diode Characteristics Stripped |
| GS3G GS3G |
GULF | SMB | 2007 | Floating bootstrap supply pin for the upper gate |
| GS3T02200J GS3T02200J |
The LTC6900 operates with a single 2.7V to 5.5V p |
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