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This family is a 16M bit dynamic RAM organized 2,097,152 x 8-bit configuration with Fast Page mode CMOS DRAMs. Fast Page mode is a kind of page mode which is useful for the read operation. The circuit and process design allow this device to achieve high performance and low power dissipation. Optional features are access time(60, 70 or 80ns) and refresh cycle(2K ref. or 4K ref.) and power consumption (Normal or Low power with self refresh). Hyundais advanced circuit design and process technology allow this device to achieve high bandwidth, low power consumption and high reliability.
Round Control. When this control is HIGH, a one is added to the Most Significant Bit (MSB) of the LSP. This position is dependent on the FA control; FA = HIGH indicates RND adds to the 2-15 bit (P15), and FA = LOW indicates RND adds to the 2-16 bit (P14).
The DB package and the DF package are only available left-end taped and reeled (indicated by the LE suffix on the device type; e.g., H100IDBLE). The DAP package is only available taped and reeled (indicated by the R suffix on the device type; e.g., H100IDAPR).