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Upon power-up, the FIFO must be reset with a Reset (RS) cycle. This causes the FIFO to enter the Empty condition signified by EF being LOW. All data outputs (Q0C8) go LOW tRSF after the rising edge of RS. In order for the FIFO to reset to its default state, the user must not read or write while RS is LOW. All flags are guaranteed to be valid tRSF after RS is taken LOW.
The HEF40106B is available in the 10-pin MSOP package, making the entire converter occupy less than 0.15 in2 of PCB area with components on one side only. The 10-pin MSOP package is specified for operation over the full -40C to +85C temperature range.
The HEF40106B provides four output clocks: SSCLK1a, SSCLK1b, SSCLK2, and REFOUT. SSCLK1a/b and SSCLK2 are modulated clocks and REFOUT is a buffered copy of the reference clock or oscillator. The HEF40106B frequency and spread % ranges are selected by programming S0, S1, S2, and S3 digital inputs. S0 and S1 use three (3) logic states including High (H), Low (L), and Middle (M) to select one of nine available frequency and spread % ranges. Refer to Figure 2 for details on programming three level inputs S0 and
Parr number/PDF Mfg Pack D/C Descrpion
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HEF4000BD   HEF4000BD HEF4000BD PDF Download PHILIPS . 90+
HEF4000BP   HEF4000BP HEF4000BP PDF Download 84 Ratiometricity   Ratiometricity simply mea
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HEF4001BT(PB)   HEF4001BT(PB) HEF4001BT(PB) PDF Download All voltages are referenced to VSS. Operating VI
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