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These modes are entered by placing a high voltage VPP on pin 19, with pins 18 and 20 set to VILP. In this state, pin 21 becomes a latch signal, allowing the upper 5 address bits to be latched into an onboard register, pin 22 becomes an active LOW program (PGM) signal and pin 23 becomes an active LOW verify (VFY) signal. Pins 22 and 23 should never be active LOW at the same time. The PROGRAM mode exists when PGM is LOW, and VFY is HIGH. The verify mode exists when the reverse is true, PGM HIGH and VFY LOW and the program inhibit mode is entered with both PGM and VFY HIGH. Program inhibit is specifically provided to allow data to be placed on and removed from the data pins without conflict
The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal operation, it is recommended that the TESTM terminal be connected to VDD through a 1-kΩ resistor, and SE be tied to ground through a 1-kΩ resistor, while SM is connected directly to ground.
CURRENT SOURCES, IREF1 AND IREF2 Zero-Code Output Level, Each Coarse DAC, 256 Steps   Adjustment Range(7)   Step Size Fine DAC, 256 Steps   Adjustment Range(7)   Step Size Linearity   Coarse   Fine   vs Temperature Matching   vs Temperature Compliance Voltage, Positive(5) Output Impedance Current Noise