1. Typical characteristics are at TA = 25oC.2. Fmax = 1/tRC. 3. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 4.IccsB1_Max. is 3uA / 10uA at Vcc=3V / 5V and TA=70oC.5. Icc_Max. is 30mA(@3V) / 62mA(@5V) under 55ns operation.
These active LOW inputs allow individual bytes to be written when a WRITE cycle is active and must meet the setup and hold times around the rising edge of CLK. BYTE WRITEs need to be asserted on the same cycle as the address. BWs are associated with addresses and apply to subsequent data. BWa# controls DQa, DQPa pins; BWb# controls DQb, DQPb pins; BWc# controls DQc, DQPc pins; BWd# controls DQd, DQPd pins.
Reduced harmonic content of input currents corresponding to standards Rectifier generates maximum DC power with a given AC fuse Wide input voltage range No external isolation Easy to mount with two screws Suitable for wave soldering High temperature and power cycling capability
These active LOW inputs allow individual bytes to be written when a WRITE cycle is active and must meet the setup and hold times around the rising edge of CLK. BYTE WRITEs need to be asserted on the same cycle as the address. BWs are associated with addresses and apply to subsequent data. BWa# controls DQa, DQPa pins; BWb# controls DQb, DQPb pins; BWc# controls DQc, DQPc pins; BWd# controls DQd, DQPd pins.
Reduced harmonic content of input currents corresponding to standards Rectifier generates maximum DC power with a given AC fuse Wide input voltage range No external isolation Easy to mount with two screws Suitable for wave soldering High temperature and power cycling capability
| Parr number/PDF | Mfg | Pack | D/C | Descrpion |
M5500-16MHZ M5500-16MHZ  |
MF | 5 | 1. Corrected the errataJan. 10, 2005 2. Revised | |
| M5500-24MHZ M5500-24MHZ |
MF | 5 | Notes: (1) Measured with baluns on the input and | |
| M5501 M5501 |
ALI | QFP | 04+ | No Option and Option 300 contain 50 units (HCPL-7 |
| M5501A0 M5501A0 |
ALI | 02+ | TQFP-L208P | These devices are fully programmable; that is, t |
| M5501A0EP M5501A0EP |
ALI | 02+ | TQFP-L208P | Chip selection input with pull-high resistor. Whe |
| M5501A1 M5501A1 |
ALI | 04+ | QFP-L208P | The Texas Instruments TFP401 and TFP401A are TI |
| M5501AOHS29 M5501AOHS29 |
ALI | QFP-L208P | 07+ | The bq2083−V1P2 supports the Smart Battery |
| M5501AOHS30 M5501AOHS30 |
ALI | QFP-L208P | 07+ | When the output load exceeds the current-limit t |
| M5501AOT M5501AOT |
ALI | QFP-L208P | 07+ | Load Regulation Parasitic line resistance can d |
| M5501N M5501N |
ALI | 03+ | QFP | The Philips SA56004X is an SMBus compatible, 11- |
| M5502 M5502 |
OKI | DIP- | 07+/08+ | † Stresses beyond those listed under absol |
| M5503 M5503 |
ALI | 00+ | TQFP-M100P | FIN and OSC IN input level Max. operating freque |
| M5505 M5505 |
SUMMARY DESCRIPTION The M29F800A is an 8 Mbit ( | |||
| M5505-A1D M5505-A1D |
ALI | QFP | 05+ | The ISL6118 is a fully independent dual channel o |
| M5505AOB M5505AOB |
ALI | 04+ | TQFP-L220P | 1 Undervoltage sensors causes each channel to swi |
| M5508A-G M5508A-G |
Infineon | 07+ | While numerous ATE systems are available and are | |
| M5509 M5509 |
This product has been designed to meet the extrem | |||
| M550A M550A |
The S5K433CA and S5K433LA are highly inte | |||
| M551 M551 |
When the enable input is high, all four analog | |||
| M5512 M5512 |
98 | Specially providing EL driver functions Non-tra | ||
| M551216010HC12HI M551216010HC12HI |
The LNA has a 2.4dB typical noise figure and a -1 | |||
| M55121607HC M55121607HC |
amd | amd | dc96 | The initial set-up sequence programs the two bli |
| M55144250210 M55144250210 |
In the 10-bit mode the 8b/10b Codec is disabled, | |||
| M5515 M5515 |
MITSUBISHI | ZIP | 00+ | Hynix HYMD232G726(L)8M-K/H/L series incorporates |
| M55165FP M55165FP |
0 | 0 | Memories C 1K, 2K or 4K bytes Program memory (O | |
| M55181/1-03RTV M55181/1-03RTV |
The MPC942 is a single supply device. The | |||
| M55181/1-04 M55181/1-04 |
Stanford Microdevices M55181/1-04 is a high perf | |||
| M55181/2-01 M55181/2-01 |
Active Connection to Remote Node Power-Down Feat | |||
| M5522 M5522 |
OKI | See the functional block diagram and Figure 1 fo | ||
| M55281A510FLT M55281A510FLT |
SOWB | SOP-7.2-16P | 07+ | • 90%+ Efficiency • Internal Short-C |
| M553 M553 |
COMPRESSED GCI MODE In GCI compressed mod | |||
| M5530 M5530 |
VCC and GND are the supply voltage pins for the | |||
| M55302/128-CN1E M55302/128-CN1E |
AMP | Please be aware that an important notice | ||
| M55302/57A30X M55302/57A30X |
Two serial outputs (QS1 and QS2) are available | |||
| M55302/61B10 M55302/61B10 |
Pin 8 is the drive control input. This pi | |||
| M5530213201 M5530213201 |
NOTES: 1. Stresses greater than those listed un | |||
| M55302241500779 M55302241500779 |
||||
| M5530256A44 M5530256A44 |
DESCRIPTION The LD1086 is a LOW DROP Voltage Re | |||
| M5530259B90X M5530259B90X |
Figure 4 shows the sensor output signal r | |||
| M55310/08-B04A M55310/08-B04A |
2 | The Preliminary Information presented herein rep | ||
| M55310/09B01A M55310/09B01A |
NOTES: 1. Timings referenced as in AC Test Condi | |||
| M55310/09-B01A-1M84320 M55310/09-B01A-1M84320 |
Q-TECH | 06+ | 500 | PCI Controller Compatible with PCI 2.1 specific |
| M55310/09-B01A-6M M55310/09-B01A-6M |
N/A | STI | 04+ | CBR refresh is performed by bringing CAS low ear |
| M55310/16-B01A M55310/16-B01A |
(LX)high-frequency | Applications include transducer amplifiers, dc a | ||
| M55310/16-B21A M55310/16-B21A |
(LX)high-frequency | The CM3513 also prevents backdrive current flowi | ||
| M55310/16-B21A-4M00000 M55310/16-B21A-4M00000 |
Q-TECH | 06+ | 500 | DISABLE - Is the connection for disabling all 4 o |
| M55310/16-B21A-4M608000 M55310/16-B21A-4M608000 |
Q-TECH | 06+ | 500 | The delay in this mode is dependent only on the c |
| M55310/16-B24A M55310/16-B24A |
CAN | 0340 | s High-speed: 35, 70 ns s Ultra low DC operating | |
| M55310/16-B31A M55310/16-B31A |
Q-TECH | 晶振14 | 34 | • 1024 refresh cycles, 16 ms refresh inter |
| M55310/16-B34A M55310/16-B34A |
晶振14 | 3.3 Reference and Clock An internal bandgap circ | ||
| M55310/16-B34A10.000MHZ M55310/16-B34A10.000MHZ |
The device features extremely low consumption (7 | |||
| M55310/16-B34A12.990MHZ M55310/16-B34A12.990MHZ |
(1) Stresses above these ratings may cause perma | |||
| M55310/16-B34A-12M0000 M55310/16-B34A-12M0000 |
NA | 30 | • Implements CCITT recommendations V.14 and | |
| M55310/16-B34B12.987MHZ M55310/16-B34B12.987MHZ |
The integrated receiver is intended to be used a | |||
| M55310/16-B41A M55310/16-B41A |
晶振14 | ABSOLUTE MAXIMUM RATINGS (per diode)) IFRMSRMS F | ||
| M55310/16-B41A-32M00000 M55310/16-B41A-32M00000 |
Q-TECH | 06+ | 500 | Nonvolatile memory maintains wiper settings 64- |
| M55310/16-B44A M55310/16-B44A |
晶振14 | N-channel enhancement mode logic level field-e | ||
| M55310/16-B44A40.000MHZ M55310/16-B44A40.000MHZ |
Bridge or stereo configuration. Few External c | |||
| M55310/16-B44A41.439MHZ M55310/16-B44A41.439MHZ |
The melting temperature of solder is highe | |||
| M55310/16-B44B44.000MHZ M55310/16-B44B44.000MHZ |
Available either in sensitive (TS8) or standard | |||
| M55310/17-B11A M55310/17-B11A |
(LX)high-frequency | Typical data are for initial design estim | ||
| M55310/17-B21A M55310/17-B21A |
晶振14 | This family is a 16M bit dynamic RAM organized 2, | ||
| M55310/18-B42A M55310/18-B42A |
(LX)high-frequency | The TPS6021x charge pumps provide a regulated 3. | ||
| M55310/19-B01A M55310/19-B01A |
LCC晶振 | 9021+ | Flash Memory Plus SRAM Reduces Memory Board Sp | |
| M55310/19-B11A M55310/19-B11A |
The M55310/19-B11A is a 3-channel DC/DC converter | |||
| M55310/19-B12B M55310/19-B12B |
The architecture of the current feedback opamp co | |||
| M55310/19-B21A M55310/19-B21A |
Covering the power range from below 25 wa | |||
| M55310/26-B23A-1.8432MHZ M55310/26-B23A-1.8432MHZ |
Q-TECH | 06+ | 500 | The ZR78L Series show performance characteristic |
| M55310/26-B32A-20M00000 M55310/26-B32A-20M00000 |
Q-TECH | 06+ | 500 | Notes: 1. Repetitive Rating : Pulse width limite |
| M55310/26-B33A-9.8304MHZ M55310/26-B33A-9.8304MHZ |
Q-TECH | 06+ | 500 | The EL2244 and EL2444 also feature an extremely |
| M55310/26-B36A M55310/26-B36A |
(LX)high-frequency | UART channel A Transmit Data or infrared encoder | ||
| M55310/26-B36A-10M00000 M55310/26-B36A-10M00000 |
Q-TECH | 06+ | 500 | The AFV461 EMI filter will reduce the input line |
| M55310/26-B36A-16M00000 M55310/26-B36A-16M00000 |
Q-TECH | 06+ | 500 | WRITE ENABLE ( W ) A write cycle is initi |
| M55310/26-B42A-31M00000 M55310/26-B42A-31M00000 |
Q-TECH | 06+ | 500 | All of the bytes in the chip must be verified to |
| M55310/26-B53A-40M00000 M55310/26-B53A-40M00000 |
Q-TECH | 06+ | 500 | This center tap Schottky rectifier has been opti |
| M55310/26-B53B-40MHZ M55310/26-B53B-40MHZ |
Q-TECH | 06+ | 500 | When V CC is out of tolerance, the circuit write |
| M5531009B01A M5531009B01A |
dc90 | NOTES: (1) Stresses above these ratings may caus | ||
| M5531009B05A4.000MHZ M5531009B05A4.000MHZ |
Selections for 5.0 to 170 volts standoff voltages | |||
| M5531009B11A M5531009B11A |
oszilatek | oszilatek | dc96 | NOTES: 1. Stresses greater than those listed und |
| M5531016B14A100KHZ M5531016B14A100KHZ |
Alternate Function RXD (serial input por | |||
| M55310-16B21A500K0000 M55310-16B21A500K0000 |
AM26LS32A Devices Meet or Exceed the Requirement | |||
| M5531016B31A M5531016B31A |
I2C interface select / I2C RESET (active low, as | |||
| M5531016B31A10MHZ M5531016B31A10MHZ |
o 12-Bit Resolution, 1/2LSB Linearity o Single | |||
| M5531016B44A M5531016B44A |
sti | sti | dc91 | systems where system integrity must be ensured o |
| M5531016B44A2400MHZ M5531016B44A2400MHZ |
NOTES: 1. For conditions shown as Min. or Max., | |||
| M5531016B44A264MHZ M5531016B44A264MHZ |
APPLICATION NOTES POWER CONSIDERATIONS & | |||
| M55339/04-00030 M55339/04-00030 |
International Rectifier Radiation Hardened MOSFE | |||
| M55339/08-0064 M55339/08-0064 |
AMP | 398 | The MPX5500 series piezoresistive transdu | |
| M55339/20-00201 M55339/20-00201 |
where N is the number of cells, RB1 is connected | |||
| M553392200636 M553392200636 |
n Variable power management n Packaged in 6-le | |||
| M55342K02B10E0R M55342K02B10E0R |
The LinCMOS process is a linear polysilicon-gate | |||
| M55342K02B20E0R M55342K02B20E0R |
The 153CMQ isolated, center tap Schottky rectifi | |||
| M55342K02B4E99SWB M55342K02B4E99SWB |
DL | 06+/07+ | RSDS INTERFACE WITH SKEW CONTROL This functional | |
| M55342K03B100ER M55342K03B100ER |
Note 1 Specification is at TA e 25 C Actual value | |||
| M55342K03B100GS M55342K03B100GS |
Notes: 1. For Max. or Min. conditions, use appr | |||
| M55342K03B10E0R M55342K03B10E0R |
CardBus while retaining the 16-bit PC Card speci | |||
| M55342K03B150DR M55342K03B150DR |
External Access enable: EA must be externally he | |||
| M55342K03B150ER M55342K03B150ER |
Test mode select. One of four terminals required | |||
| M55342K03B1E00RS2 M55342K03B1E00RS2 |
DL | 06+/07+ | The maximum allowable power dissipation is a func | |
| M55342K03B1F00R M55342K03B1F00R |
Note 3 The maximum absolute allowable voltage whi | |||
| M55342K03B20E0R M55342K03B20E0R |
In addition to having higher performance than f | |||
| M55342K03B221DR M55342K03B221DR |
VFB (Pin 7): Error Amplifier Inverting Input. The | |||
| M55342K03B24E3R M55342K03B24E3R |
It is based on optical navigation technology w | |||
| M55342K03B2E00R M55342K03B2E00R |
A read cycle is initiated by the falling edge of | |||
| M55342K03B2E21R M55342K03B2E21R |
||||
| M55342K03B301DR M55342K03B301DR |
Figure 1 shows the connections for simple ripple | |||
| M55342K03B301ER M55342K03B301ER |
• FR60Lite CPU • 32-bit RISC, | |||
| M55342K03B30E1R M55342K03B30E1R |
||||
| M55342K03B499DR M55342K03B499DR |
Oscillation Equations for the Dual Inverter Osci | |||
| M55342K03B4E02R M55342K03B4E02R |
• N channel FET switches with no parasitic | |||
| M55342K03B51D1R M55342K03B51D1R |
• AC97 Rev 2.2 compatible stereo codec &nb | |||
| M55342K03B51E1R M55342K03B51E1R |
Multi-channel selector Lch input Input selector | |||
| M55342K03B562DR M55342K03B562DR |
Note 1: Relative accuracy is the deviation of the | |||
| M55342K03B56E2R M55342K03B56E2R |
The DSTINIm400 is a fully assembled and tested c | |||
| M55342K03B5E11R M55342K03B5E11R |
The CM3002 family of regulators is fully protect | |||
| M55342K03B6E81R M55342K03B6E81R |
Modulus control output for controlling an extern | |||
| M55342K03B8E06R M55342K03B8E06R |
High Data Integrity Applications Data storage a | |||
| M55342K04B100DR M55342K04B100DR |
FEATURES Operates over entire Li+ Battery range | |||
| M55342K04B100GR M55342K04B100GR |
s ESD protection of one automotive LIN bus line | |||
| M55342K04B10E0R M55342K04B10E0R |
The PI74FCT827/828T and the PI74FCT2827/2828T ar | |||
| M55342K04B10H0R M55342K04B10H0R |
The output pulse of the oscillator is used as a | |||
| M55342K04B121ER M55342K04B121ER |
Over temperature shutdown Over current shutdow | |||
| M55342K04B15E4R M55342K04B15E4R |
• Single element, current limiting fuses p | |||
| M55342K04B18E2R M55342K04B18E2R |
Information at the D inputis transferred to the | |||
| M55342K04B1E00R M55342K04B1E00R |
In an M68300 family component, the major functio | |||
| M55342K04B1H00R M55342K04B1H00R |
C High-performance 32-bit RISC Architectu | |||
| M55342K04B22E1R M55342K04B22E1R |
On receipt of PWM signal start instruction | |||
| M55342K04B26E1R M55342K04B26E1R |
Notes: 1. The luminous intensity is measured on | |||
| M55342K04B330GR M55342K04B330GR |
The SOA curve should be interpreted as an absolu | |||
| M55342K04B33E2R M55342K04B33E2R |
† Stresses beyond those listed under absol | |||
| M55342K04B3E32R M55342K04B3E32R |
FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS | |||
| M55342K04B3E57R M55342K04B3E57R |
Data on the Qs output is transferred to a second | |||
| M55342K04B3E83R M55342K04B3E83R |
PTFM type has been developed for protecting powe | |||
| M55342K04B46E4R M55342K04B46E4R |
The Versatile Timer Unit (VTU) module contains f | |||
| M55342K04B4E42R M55342K04B4E42R |
The LED and RXD outputs are controlled by the | |||
| M55342K04B4E64R M55342K04B4E64R |
Power Up and Down Requirements. There are no re | |||
| M55342K04B5E90R M55342K04B5E90R |
The internal gating of chip-enable (CE) signals | |||
| M55342K04B71E5R M55342K04B71E5R |
The M55342K04B71E5R/M55342K04B71E5R8/M55342K04B71 | |||
| M55342K04B75D0R M55342K04B75D0R |
† NOTICE: Stresses above those listed unde | |||
| M55342K04B7E50R M55342K04B7E50R |
Signal data can be provided in binary or 2s comp | |||
| M55342K04B7E68R M55342K04B7E68R |
The device powers on in the read mode. Command | |||
| M55342K04B8E66R M55342K04B8E66R |
Note 5: Maximum ambient temperature (TA-MAX) is d | |||
| M55342K04B91G0R M55342K04B91G0R |
© 1997 MX•COM Inc.www.mxcom.com Tele: | |||
| M55342K04B9E53R M55342K04B9E53R |
• Dual Analog Comparator module with: &nb | |||
| M55342K05B12E4R M55342K05B12E4R |
Case: JEDEC TO-247AD molded plastic body Termina | |||
| M55342K05B220GR M55342K05B220GR |
To allow for dc coupling to ADCs, its unique out | |||
| M55342K05B33G0R M55342K05B33G0R |
Life Support Policy: HY-LINE does not authorize t | |||
| M55342K06B100DR M55342K06B100DR |
The SST49LF080A flash memory device is manufactu | |||
| M55342K06B100ER M55342K06B100ER |
RFT6100 Device Features • Reduction in com | |||
| M55342K06B100ES M55342K06B100ES |
The #WP pin provides inadvertent write protection | |||
| M55342K06B10D0R M55342K06B10D0R |
The DVR EN*, DATA, and VTT EN pins are digital in | |||
| M55342K06B10D0S M55342K06B10D0S |
Since this issue does not affect operation if th | |||
| M55342K06B10E0R M55342K06B10E0R |
The Intel 80C186XL is a Modular Core re-implemen | |||
| M55342K06B10E0RWB M55342K06B10E0RWB |
DL | 06+/07+ | The MLX90247DSG sensor IC is integrated togethe | |
| M55342K06B110DR M55342K06B110DR |
As the HFBR-5710L is inserted, first contact i | |||
| M55342K06B120AR M55342K06B120AR |
BENEFITS EMI symmetrical (I/O) low-pass filter | |||
| M55342K06B121DR M55342K06B121DR |
Voltages (typically 1% of its specified value) | |||
| M55342K06B121ER M55342K06B121ER |
256K x 4 advanced high-speed CMOS static RAM JED | |||
| M55342K06B121ES M55342K06B121ES |
The current source provides a closely reg | |||
| M55342K06B12E1R M55342K06B12E1R |
q INDUSTRIAL PROCESS CONTROL Transducer I | |||
| M55342K06B12E1S M55342K06B12E1S |
There is a small temperature drift of the compar | |||
| M55342K06B130DS M55342K06B130DS |
The device is designed to comply with all JEDEC | |||
| M55342K06B13E7S M55342K06B13E7S |
where N is the number of cells, R2 is connected t | |||
| M55342K06B140DR M55342K06B140DR |
This document is a general product description an | |||
| M55342K06B14E0R M55342K06B14E0R |
sensor and thermistor can be used independent o | |||
| M55342K06B150ER M55342K06B150ER |
Layout Consideration The output capacitors must | |||
| M55342K06B15E0R M55342K06B15E0R |
AC CHARACTERISTICS PARAMETER DQM to input data | |||
| M55342K06B162ES M55342K06B162ES |
VGD: The VGD pin which is coarsely regulated arou | |||
| M55342K06B16E2R M55342K06B16E2R |
† Stresses beyond those listed under absol | |||
| M55342K06B16E2S M55342K06B16E2S |
In case the HT9142 is battery powered, when the p | |||
| M55342K06B16E9R M55342K06B16E9R |
microprocessor. When the voltage on VSENSE rises | |||
| M55342K06B17E4R M55342K06B17E4R |
These devices are mounted on an JEDEC low-k boar | |||
| M55342K06B17E8R M55342K06B17E8R |
This is the output terminal for the LPF input an | |||
| M55342K06B182DR M55342K06B182DR |
ENCV Variable clock enable (TTL compatible input) | |||
| M55342K06B18E2R M55342K06B18E2R |
Available in the Texas Instruments NanoStarɽ | |||
| M55342K06B19E1R M55342K06B19E1R |
The LTC3722-1/LTC3722-2 feature adjustable synchr | |||
| M55342K06B1E00R M55342K06B1E00R |
Note 1: Dropout voltage is defined as VIN - VOUT, | |||
| M55342K06B1E00RWB M55342K06B1E00RWB |
DL | 06+/07+ | HR700 Series DC/DC converters are designed to pr | |
| M55342K06B1E00S M55342K06B1E00S |
Configured by Loading Binary File - Unlimited | |||
| M55342K06B1E10R M55342K06B1E10R |
NOTES: 1. pin #9 = pin #17(internally connected) | |||
| M55342K06B1E15S M55342K06B1E15S |
Forward-Current Transfer Ratio IC = 1.0 A | |||
| M55342K06B1E21R M55342K06B1E21R |
The AV34063 is a monolithic control circu | |||
| M55342K06B1E30R M55342K06B1E30R |
handles the microprocessor control signals CS, | |||
| M55342K06B1E47R M55342K06B1E47R |
3. Initializes function parameters. The paramete | |||
| M55342K06B1E50R M55342K06B1E50R |
(1) Pulsed: Pulse duration = 300 µs, duty | |||
| M55342K06B1E78R M55342K06B1E78R |
Output of 1394b driver block. These twisted-pair | |||
| M55342K06B1E82R M55342K06B1E82R |
Main CLK(Hz)Under 3.58M14.3M Opera | |||
| M55342K06B1F00R M55342K06B1F00R |
The 56800 core is based on a Harvard-style archi | |||
| M55342K06B1H60R M55342K06B1H60R |
Spread spectrum may be enabled through I2C progra | |||
| M55342K06B1T00R M55342K06B1T00R |
† Stresses beyond those listed under absol | |||
| M55342K06B200DR M55342K06B200DR |
NOTE 1: The HDQ engine of the bq2019 interests a | |||
| M55342K06B200ES M55342K06B200ES |
The EB-2100x is an all-digital amplifier evaluat | |||
| M55342K06B205DR M55342K06B205DR |
The MAX6673 has a push-pull output. The rise and | |||
| M55342K06B20E0R M55342K06B20E0R |
The 3 series of decoders provide various com- b | |||
| M55342K06B20E0S M55342K06B20E0S |
Data out is the same polarity as data in. The ou | |||
| M55342K06B21E0R M55342K06B21E0R |
The M55342K06B21E0R series of FET-input op amps | |||
| M55342K06B226DR M55342K06B226DR |
2. Short-circuits from the output to VCC can cau | |||
| M55342K06B22D1R M55342K06B22D1R |
ADJ: In the adjustable version, the user programs | |||
| M55342K06B22E1R M55342K06B22E1R |
The NetPHY™ 4LP device operates on a 3.3 V | |||
| M55342K06B23E2R M55342K06B23E2R |
Operates from a single +5V supply Maintains ne | |||
| M55342K06B243DR M55342K06B243DR |
||||
| M55342K06B243DS M55342K06B243DS |
REACTIVE LOADSAC SIGNALS Figure 6 shows the rela | |||
| M55342K06B249DR M55342K06B249DR |
C Support of ReachDSLTM with digital com- | |||
| M55342K06B267DR M55342K06B267DR |
served When the S input is LOW a CP HIGH-LOW tra | |||
| M55342K06B27E4S M55342K06B27E4S |
Buffer Operating Frequency: 8 MHz to 200 MHz Lo | |||
| M55342K06B29E4R M55342K06B29E4R |
A single transistor Collpits crystal osci | |||
| M55342K06B2E00R M55342K06B2E00R |
Notes: 1. Repetitive Rating : Pulse width limite | |||
| M55342K06B2E21R M55342K06B2E21R |
This new IRK serie of MAGN-A-paks modules uses h | |||
| M55342K06B2E21S M55342K06B2E21S |
n RSDS™ (Reduced Swing Differential Signal | |||
| M55342K06B2E43R M55342K06B2E43R |
The CS8920A is available in a thin 144-pin TQFP | |||
| M55342K06B2E49S M55342K06B2E49S |
The M55342K06B2E49S drives a high-side P-channel | |||
| M55342K06B2E74S M55342K06B2E74S |
All voltages are referenced to V SS = 0 V (groun | |||
| M55342K06B301DS M55342K06B301DS |
The M55342K06B301DSA5/B5 is a 32K ROM version of | |||
| M55342K06B324DR M55342K06B324DR |
The Erase Suspend/Erase Resume feature allows th | |||
| M55342K06B33E2R M55342K06B33E2R |
When used as a decimating post-filter with a doub | |||
| M55342K06B392ES M55342K06B392ES |
The PACSZ1284 provides a complete parallel port | |||
| M55342K06B39E2R M55342K06B39E2R |
Features • High sensitivity (+4dB compared | |||
| M55342K06B3E01R M55342K06B3E01R |
The BCT8244A scan test devices with octal buffe | |||
| M55342K06B3E01S M55342K06B3E01S |
M55342K06B3E01SM M55342K06B3E01SC Decade Counter | |||
| M55342K06B3E32R M55342K06B3E32R |
Offset adjusting for the ADS-119 is normally acc | |||
| M55342K06B3E92R M55342K06B3E92R |
Offered in 256Mx8bit or 128Mx16bit, the K9F2GXXU0 | |||
| M55342K06B402DR M55342K06B402DR |
Note 1: Absolute Maximum Ratings are those values | |||
| M55342K06B422DR M55342K06B422DR |
7.3.1 ILMI Embedded software provides an ILMI 4 | |||
| M55342K06B43E2R M55342K06B43E2R |
Note: 1. For DIP package: Soldering temperature | |||
| M55342K06B46E4R M55342K06B46E4R |
VCC to GND PGND to GND FB to GND SHDN to GND | |||
| M55342K06B470GR M55342K06B470GR |
This input is used to control the motion of the | |||
| M55342K06B475DR M55342K06B475DR |
/EOP /End of Process (Input, active Low). To term | |||
| M55342K06B47E5R M55342K06B47E5R |
Since front polarizer is easily damaged, pay atte | |||
| M55342K06B47H0R M55342K06B47H0R |
No heatsinks required! 77% efficie | |||
| M55342K06B499DR M55342K06B499DR |
VID0-VID4 (DAC Digital Input Code Control) Pins 1 | |||
| M55342K06B49D9R M55342K06B49D9R |
The FCT841T high-performance interface is design | |||
| M55342K06B49E9S M55342K06B49E9S |
The Hynix HYM71V16M635B(L)T6 Series are Du | |||
| M55342K06B4E32R M55342K06B4E32R |
Operating from a wide-input voltage range of 7 V | |||
| M55342K06B4E75R M55342K06B4E75R |
Lead temperature 1,6 mm (1/16 inch) from case fo | |||
| M55342K06B4E75S M55342K06B4E75S |
The XR16L27521 (2752) is a low voltage dual uni | |||
| M55342K06B51E1R M55342K06B51E1R |
Device programming occurs by executing the progra | |||
| M55342K06B51G0R M55342K06B51G0R |
Differential output transmit. DOUT_TXP and DOUT_ | |||
| M55342K06B52D3R M55342K06B52D3R |
• Up to 10 MIPS operation: - DC - | |||
| M55342K06B549DR M55342K06B549DR |
This pin normally functions as a three-state inp | |||
| M55342K06B56D2R M55342K06B56D2R |
Pulse triggering occurs at a particular voltage | |||
| M55342K06B56E2R M55342K06B56E2R |
The trigger condition for the time stage is dete | |||
| M55342K06B5E11P M55342K06B5E11P |
The device is optimized for use in many indus- | |||
| M55342K06B5E11R M55342K06B5E11R |
HT1623 make it suitable for multiple LCD applicat | |||
| M55342K06B5E23R M55342K06B5E23R |
product term timing. For optimization of logic, | |||
| M55342K06B5E23S M55342K06B5E23S |
Notes: 1. Measurements made on a fixed tuned pr | |||
| M55342K06B5E62R M55342K06B5E62R |
This block reads/writes configuration data from | |||
| M55342K06B604DR M55342K06B604DR |
64K x 16 advanced high-speed CMOS Static RAM Equ | |||
| M55342K06B60E4R M55342K06B60E4R |
Ci is required when regulator is located an appr | |||
| M55342K06B63E4R M55342K06B63E4R |
Note 5: The output pins RST and RST have an inter | |||
| M55342K06B681DR M55342K06B681DR |
Information furnished by Analog Devices is belie | |||
| M55342K06B68D1R M55342K06B68D1R |
5 ns pin-to-pin logic delays System frequency | |||
| M55342K06B698DR M55342K06B698DR |
Note: (1) This parameter is tested initially an | |||
| M55342K06B69E8R M55342K06B69E8R |
C High-performance 32-bit RISC Architectu | |||
| M55342K06B6E04R M55342K06B6E04R |
The Hitachi HM62V8100I Series is 8-Mbit static R | |||
| M55342K06B6E04S M55342K06B6E04S |
These octal bus transceivers are designed for a | |||
| M55342K06B6E19R M55342K06B6E19R |
The S5T8554B/7B are single-chip PCM encoders and | |||
| M55342K06B6E98R M55342K06B6E98R |
DESCRIPTION The EMIF02-MIC02 is a highly integr | |||
| M55342K06B750DR M55342K06B750DR |
INDUCTOR SELECTION Selecting the appropr | |||
| M55342K06B75D0R M55342K06B75D0R |
Skyworks CX65105 Evaluation Board is used to test | |||
| M55342K06B7E15R M55342K06B7E15R |
Hynix HYMD232726A(L)8-M/K/H/L series incorporates | |||
| M55342K06B7E50R M55342K06B7E50R |
pull-down circuit is built into the Si91871 to c | |||
| M55342K06B7E50S M55342K06B7E50S |
The 8 'X' lines can be directly connected to th | |||
| M55342K06B806DR M55342K06B806DR |
Copyright © 2002 Integrated Silicon Solutio | |||
| M55342K06B825DR M55342K06B825DR |
Maximum DC Blocking Voltage Maximum Average Fo | |||
| M55342K06B82D5R M55342K06B82D5R |
The Hynix HYM71V16M635AT6 Series are Dual | |||
| M55342K06B90E9R M55342K06B90E9R |
This is the supply voltage for the regulator con | |||
| M55342K06B90E9RS28 M55342K06B90E9RS28 |
An external capacitor connected to this pin sets | |||
| M55342K06B9E09S M55342K06B9E09S |
NOTES: 1. See Test Conditions under TEST CIRCUI | |||
| M55342K08B10D0R M55342K08B10D0R |
o dcOutput Duty Cycle48 NOTE 1: Defined as ske | |||
| M55342K08B121DR M55342K08B121DR |
The values for the equation are found in | |||
| M55342K08B1E00R M55342K08B1E00R |
CAUTION ESD (electrostatic discharge) sensitive | |||
| M55342K08B301DR M55342K08B301DR |
||||
| M55342K08B49D9R M55342K08B49D9R |
The 82C37A is an enhanced version of the industr | |||
| M55342K09B100DR M55342K09B100DR |
NOTES: A. CL includes probe and test-fixture cap | |||
| M55342K09B12D1R M55342K09B12D1R |
for an overvoltage condition on unselected chann | |||
| M55342K09B182DR M55342K09B182DR |
For the case where Register 2 is set to xxxx11xx, | |||
| M55342M06R4K30M M55342M06R4K30M |
printer ports BUSY and SELECT OUT signals (pins | |||
| M5535 M5535 |
N/A | OKI | 04+ | The Si9160 Controller for RF Power Amplifier Boo |
| M5537 M5537 |
OKI | QFP | 04+ | The K6R4004C1D is a 4,194,304-bit high-speed Stat |
| M5537A1-C M5537A1-C |
96 | To ensure good thermal conductivity, the backsid | ||
| M5537A1-D M5537A1-D |
ALI | QFP | 97+ | The on-board RISC processor enables the I |
| M5538 M5538 |
OKI | DIP14 | 95+ | between the two supply inputs is + 8.0 volts whi |
| M554522P M554522P |
100 | 天龙伟业 | 靳先生 | Fairchild's LS series product of Insulated Gate B |
| M5547 M5547 |
OKI | SIP | Low Voltage Operation (+2.7 to +5 V) Low On-Res | |
| M5547A1 M5547A1 |
ALI | 97 | Data Inputs/Outputs: Inputs array data during pr | |
| M5547-A1DA M5547-A1DA |
Ali | QFP | 1998 | The maximum graphics resolution supported is 12 |
| M554977P M554977P |
N/A | DIP | 07+ | NOTES: 1. See Test Conditions under TEST CIRCUI |
| M5549A1 M5549A1 |
N/A | N/A | N/A | Similar To Industry Standard LT1033 Approved To |
| M5549-A1 M5549-A1 |
MTT | Differential or single-ended clock input signal. | ||
| M554V24616-10TK M554V24616-10TK |
The sealed modules offer a metal baseplate for i | |||
| M55501 M55501 |
DIP | The device features simultaneous read/write op- | ||
| M5559B M5559B |
98+ | SOP-8 | HIGH SPEED: tPD = 0.3ns (TYP.) at VCC = 3.0V t | |
| M5559RS M5559RS |
98 | Unless otherwise specified, the typical specifica | ||
| M555CN M555CN |
Stresses beyond those listed under Absolute Maxi | |||
| M555N M555N |
MIT | Min Typ Max Min Typ Max UnitsTest Conditions 32 | ||
| M555TM2 M555TM2 |
K | DIP-14 | Low profile package (half pitch) AC Isolation | |
| M5562 M5562 |
OKI | DIP | 06+ | The ISSI IS41C82052 and IS41LV82052 are 2,097,15 |
| M5565-01 M5565-01 |
These three terminal negative regulators are sup | |||
| M5567 M5567 |
N/A | OKI | 04+ | Maximum gain setpoint for all phase setpoints V |
| M55730 M55730 |
The user assumes all responsibility and liabilit | |||
| M55746SP M55746SP |
MIT | DIP-12 | 98+ | With 1mA load With 1mA load With 20pF maximum |
| M5576 M5576 |
94 | The F157A is a high-speed quad 2-Input multiplex | ||
| M5577 M5577 |
TRI-STATE is a registered trademark of National | |||
| M557704L M557704L |
MITSUBISHI | N/A | N/A | The device can be used as a three-terminal poten |
| M55D10R0FT52 M55D10R0FT52 |
SUBCARRIER: The output of the encoder stage (Man | |||
| M55FW M55FW |
SOP | The SOA curves combine the effect of thes | ||
| M55HT M55HT |
Single chip teletext IC Analog CVB | |||
| M55RF M55RF |
0 | International Rectifier's 300V series are the sta |
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