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Power down control. When PD is LOW, the inputs are disabled and internal switching is stopped. OMODE selects whether the outputs are gated LOW/HIGH or tri-stated. When OMODE is HIGH, PE determines the level at which the outputs stop. When PE is LOW/ HIGH, the nQ and QFB are stopped in a HIGH/LOW state, while the nQ and QFB are stopped in a LOW/HIGH state. When OMODE is LOW, the outputs are tri-stated. Set PD HIGH for normal operation. PLL lock indication signal. HIGH indicates lock. LOW indicates that the PLL is not locked and outputs may not be synchronized to the inputs. The output will be 2.5V LVTTL. Output disable control. Determines the outputs' disable state. Used in conjunction with nsOE and PD. (See Output Enable/Disable and Powerdown tables.)
The MC3001P is a highly efficient multiphase synchronous buck switching regulator controller optimized for converting a 12 V main supply into the core supply voltage required by high per- formance Intel processors. It uses an internal 6-bit DAC to read a voltage identification (VID) code directly from the processor, which is used to set the output voltage between 0.8375 V and 1.6 V, and uses a multimode PWM architecture to drive the logic level outputs at a programmable switching frequency that can be optimized for VR size and efficiency. The phase relationship of the output signals can be programmed to provide 2-, 3-, or 4-phase operation, allowing for the construction of up to four comple- mentary buck switching stages.
This data sheet applies to all versions of the MC3001P and MC3001P products including MC3001PA, MC3001PB, MC3001PA, and MC3001PB. As a result of product changes, Revision 4 parts are labeled MC3001PB and MC3001PB. Revision 3 parts are labeled MC3001PA and MC3001PA. The differences in these product revisions are described in the MC3001P/975 Specification Update.