Current position: Home > Shortcut to M > MVA Series

In burst mode the A/D converter does repeated conversions at the rate selected by the CLKS field in the ADCR, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1-bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit.
  SDRAM Controller  C 2 memory banks, non-interleaved, 512 MB total  C 32-bit wide data path  C Supports 4-bit, 8-bit, and 16-bit wide SDRAM chips  C SODIMM support  C Stays on page between transfers  C Automatic refresh generation Peripheral Device Controller  C 26-bit address bus  C 32-bit data bus with variable width support of 8-,16-, or 32-bits  C 8-bit boot ROM support  C 6 banks available, up to 64MB per bank  C Supports Flash ROM, PROM, SRAM, dual-port memory, and   peripheral devices  C Supports external wait-state generation, Intel or Motorola style  C Write protect capability  C Direct control of optional external data transceivers System Integrity  C Programmable system watchdog timer resets system on time-   out  C Programmable bus transaction times memory and peripheral   transactions and generates a warm reset on time-out DMA  C 16 DMA channels  C Services on-chip and external peripherals  C Supports memory-to-memory, memory-to-I/O, and I/O-to-I/O   transfers  C Supports flexible descriptor based operation and chaining via   linked lists of records (scatter / gather capability)  C Supports unaligned transfers  C Supports burst transfers
  C Caches are physically addressed, implement a least recently used (LRU)   replacement algorithm, and are lockable on a cache block basis. Instruction and data caches are two-way, set-associative, physically addressed,   LRU replacement, and lockable on-line granularity. MMUs with 32-entry TLB, fully associative instruction, and data TLBs MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16   virtual address spaces and 16 protection groups Advanced on-chip-emulation debug mode Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits) 32 address lines Operates at up to 80 MHz Memory controller (eight banks) Contains complete dynamic RAM (DRAM) controller Each bank can be a chip select or RAS to support a DRAM bank Up to 15 wait states programmable per memory bank Glueless interface to DRAM, SIMMS, SRAM, EPROM, Flash EPROM, and   other memory devices. DRAM controller programmable to support most size and speed memory   interfaces Four CAS lines, four WE lines, one OE line Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory) Variable block sizes (32 Kbyte to 256 Mbyte) Selectable write protection On-chip bus arbitration logic General-purpose timers Four 16-bit timers or two 32-bit timers Gate mode can enable/disable counting Interrupt can be masked on reference match and event capture System integration unit (SIU) Bus monitor Software watchdog Periodic interrupt timer (PIT) Low-power stop mode Clock synthesizer