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High-speed video signal switching/routing HDTV-quality video signal routing Audio signal switching/routing Data acquisition ATE systems Telecomm routing Switch between multiple video sources Token Ring transceivers High-speed networking
The IEEE 1284 specification requires both termination and EMI filtering on a total of 17 lines. Basic filtering is provided through the presence of a capacitor on all sig- nal lines. The filter capacitor is the junction capacitance of an ESD diode. The typical capacitance at a reverse voltage of 2.5V is 150pF. This diode capacitance is somewhat voltage dependent. See Figure 1.
The HMJ2 is a high dynamic range, GaAs FET mixer. This active FET mixer realizes a typical third order intercept point of +37 dBm at an LO drive level of +17 dBm. The HMJ2 comes in a low cost, J-lead package. Typical applica- tions include frequency up/down conversion, modulation and demodulation for receivers and transmitters used in PCS systems.

Parr number/PDF	Mfg	Pack	D/C	Descrpion

NJU062 NJU062	JRC	SOP8	07+	Unlike other devices, the error amplifier in the
NJU072BV NJU072BV	JRC	96	SSOP-8	The ZREF25 design provides a stable voltage wit
NJU072M NJU072M	JRC		02+	Driving Cables and Capacitive Loads When driving
NJU1101F-TE1 NJU1101F-TE1	JRC	SOT23-6	04+	NOTES: 1. For conditions shown as Max. or Min.,
NJU1102L NJU1102L	JRC	STK	2005+	3.3V 10% Output Transmit Power Supply. Bypass wit
NJU1147 NJU1147				The main gate drive output (OUT1) is controlled
NJU1151 NJU1151				This series of 500 W Transient Voltage Suppressor
NJU1510 NJU1510				NanoStar and NanoFree Packages L
NJU1510(NJM1510) NJU1510(NJM1510)	JRC		35000	A unity gain, differential amplifier is provided
NJU1515A(NJM1515A) NJU1515A(NJM1515A)	JRC		3000	*Stresses above those listed under Absolute Maxim
NJU200 NJU200				Normally the signal source for the LM1881 is ass
NJU201 NJU201	JRC	DIP/16		4. Setting possible during non-induction
NJU201A NJU201A	★★★		96	A power ready/undervoltage lockout function outp
NJU201AD NJU201AD	NJR	DIP	04+	The instruction and data caches operate independ
NJU201AD-ZZZB NJU201AD-ZZZB	JRC		0809+	MAX 7000A devices provide programmable speed/pow
NJU201AM NJU201AM	NJR	SOP-16	90+	The M37273MFH-XXXSP is single-chip microcomputer
NJU201AM(T1) NJU201AM(T1)	JRC	SOP16	1997	HT1623 is a peripheral device specially designed
NJU201AM(TE2) NJU201AM(TE2)	JRC	SOP-16	1996
NJU201AM-T1 NJU201AM-T1	JRC	SOP-8	2005+	Stresses above those listed under Absolute Maxim
NJU201AM-TE2 NJU201AM-TE2	JRC	03	SOP16	The HCPL-7850/7851 is an isolation amplifier t
NJU2068M NJU2068M	JRC		95+	A Hysteresis with 30% PWM duty cycle (when THRES
NJU211 NJU211	JRC	SOP	03/+04+	Operating voltage: 2.4V~5.0V Low standby current
NJU211D NJU211D	NJR	DIP	05+	Supply Voltage Hall Input Voltage Range Output
NJU211D04 NJU211D04				Notes: 1.The luminous intensity Iv is measured
NJU211D-ZZZB NJU211D-ZZZB	JRC		06+	The sensor consists of a precision linear Hall IC
NJU211M NJU211M	NJR		02+	433-MHz, 868-MHz, and 915-MHz Industrial, Scient
NJU211M-TE2 NJU211M-TE2	JRC		06/07+	In a multiple supply, fault tolerant, redundant
NJU2150D NJU2150D				The power circuit and layout within the m
NJU2175L NJU2175L	JRC	56PIN-PDIP	07+
NJU2211D NJU2211D				The NL27WZU04 is a high performance dual
NJU2233BD NJU2233BD	JRC	8PIN-PDIP	07+	Digital ground. Ground pin for the internal CMOS
NJU2234M NJU2234M	JRC		07+
NJU2240M NJU2240M	JRC			The coarse and fine mixers can be combined to sp
NJU2246M NJU2246M	JRC	STK	2005+	The Customer Demonstration Board provides the ROC
NJU2285M NJU2285M				Moving the data from two groups of registers to
NJU2403M NJU2403M	JRC	STK	2005+	Both the differential data (DIN, DINQ) and clock
NJU2406F-TE1 NJU2406F-TE1	JRC	SOT23/5	2002	HIGH SPEED: tPD=4.4ns (TYP.) at VCC = 3.3V 5V
NJU25301F NJU25301F	AD	QFP	01+	Like most micropower circuits the LM34 has a lim
NJU25301FC5 NJU25301FC5	JRC		06/07+	The AD8152s fully differential signal path reduc
NJU2530F NJU2530F	na	na	05+	The ICU receives interrupt requests from interna
NJU2596 NJU2596	JRC	01+		Reset: A low on this pin resets the microcontroll
NJU26016F NJU26016F				The accuracy of the DAC/reference combination is
NJU26101 NJU26101			1780	JEDEC compatible LVTTL level inputs and outputs
NJU26101F NJU26101F				RESET/RESETRESET: RESET OUTPUTSRESET (RESET CAT1
NJU26102 NJU26102			1780
NJU26103 NJU26103	JRC		07+	The CD54AC574/3A and CD54ACT574/3A are octal D-t
NJU26103F NJU26103F			02	VDE = Differential Error Voltage = Common-
NJU26106 NJU26106				The Burst Write command is initiated by applying
NJU26106F NJU26106F	JRC	QFP/32	02+	• External interrupt circuit (8 channels)
NJU26108F NJU26108F	JRC		2005	HPCTM family core features 16-bit data bu
NJU26150F NJU26150F	JRC	QFP	05+	PCI compatible BusCfriendly architecture includi
NJU26501 NJU26501
NJU26901 NJU26901				Multi-function Input One (1): If Mode = L (m68
NJU26901E2 NJU26901E2	JRC		07+PB	also has an automatic power-down feature that sig
NJU26901E2-TE1 NJU26901E2-TE1	JRC	SOP-8	0410-025S	The RC5033 is a synchronous mode DC-DC controlle
NJU26902 NJU26902				Each channel consists of a TTL/CMOS-compa
NJU26902VM1(TE2) NJU26902VM1(TE2)	JRC		0411	The bqHYBRID™ series are highly integrated
NJU2768M-TE1 NJU2768M-TE1	JRC	91+	SOP/8	The amplifier family has an output that swings wi
NJU-2903V NJU-2903V	JRC	SOT	05+	device ranging from 4 to 12 wide, with an averag
NJU2904 NJU2904	JRC	SOP8	07+	The CD54AC112/3A and CD54ACT112/3A are dual J-K
NJU3102L000 NJU3102L000	JRC		08+	This parameter has to be as low as possible in
NJU3151D NJU3151D		DIP16	00+	Notes: 1. Standard packing: Carton (Tube): 40 pc
NJU3152 NJU3152				Configuration of a single-ended input has been
NJU3152L NJU3152L		SOP20	99	A buffered output-enable (OE) input can be used
NJU3404 NJU3404	JRC	STK	2005+	Power Integrations may make changes to its produc
NJU3404A NJU3404A	202	JRC	O4	‡ Stresses beyond those listed under absol
NJU3421A NJU3421A				The HYM72V32756B(L)T8 Series are 32Mx72bits Synch
NJU3421AC NJU3421AC	JRC	DIP		∙ 2,097,152-word 8-bit configuration &#
NJU3421AF NJU3421AF	JRC	467	01+	When the BLANKING input is high, the out
NJU3421AL NJU3421AL	JRC	DIP	00+	CASE: Void-free transfer molded thermosetting ep
NJU3423AF NJU3423AF	JRC	STK	2005+	Additional features also include temperature com
NJU3426 NJU3426				On Board 24Mhz Crystal Driver Circuit Can be clo
NJU3426FP1 NJU3426FP1	JRC		2005	When used alone, the CLP30-200B1 acts at the in
NJU3430 NJU3430				An active-high input enables the Host mode. Data
NJU3430F NJU3430F	JRC	STK	2005+	The bq2000 is a programmable, monolithic IC for
NJU3430FG1-02 NJU3430FG1-02	JRC	QFP	2002	NOTES: 1. See Test Conditions under TEST CIRCUI
NJU3430FG1-0204 NJU3430FG1-0204				1A Output Current Capability Input Operating V
NJU3430S NJU3430S				RFT6120 Device Features • CDMA2000 1X Mobi
NJU3430SF NJU3430SF	JRC	STK	2005+	Note: There is no external connection for voltag
NJU3503 NJU3503	JRC	STK	2005+	Each channel has a mask bit associated with it wh
NJU3503LA00 NJU3503LA00	JRC		08+	time exhibits drift characteristics of the best
NJU3517E2 NJU3517E2	JRC	08+		Optimized for 2.5V LVTTL Guaranteed Low Skew <
NJU3551 NJU3551	JRC	SOP	07+	The CLC031A has a unique Built-In Self-Test (BIS
NJU3552 NJU3552		SOP	00+	This document is a general product description an
NJU35521 NJU35521		DIP	99	The S2/SUSPEND input can be configured to shut do
NJU3553L NJU3553L	JRC	STK	2005+
NJU3555F NJU3555F	JRC	STK	2005+	The Versatile Timer Unit (VTU) module contains f
NJU3555L NJU3555L	JRC	STK	2005+	The ADS7886 is a 12-bit, 1-MSPS analog-to-digita
NJU3602 NJU3602		SOP	97	KEY FEATURES 350 MHz High Performance Blackfin
NJU3711 NJU3711	JRC			These voltage regulators are monolithic integrate
NJU3711D NJU3711D	NJR	DIP-14	90+	output transistor, as a result the output voltage
NJU3711M NJU3711M	JRC	SOP	00+	The following are trademarks of Skyworks Solution
NJU3711M(T1) NJU3711M(T1)	JRC	SOP	1999	Each of the 6 high-side and 6 low-side drivers i
NJU3711M(TE1) NJU3711M(TE1)	JRC	08+		• Interfaces directly to a single-scan pan
NJU3711M(TE2) NJU3711M(TE2)				QA[0-2], Qx[0-2] are active. Deassertion of OE c
NJU3711MTE1 NJU3711MTE1				1. Intersil Pb-free products employ special Pb-fr
NJU3711M-TE1 NJU3711M-TE1	JRC	DMP14		ADDRESS DATA BUS: These lines constitute the tim
NJU3711M-TE2 NJU3711M-TE2	JRC	SOP-14	2004	Other operating features include an on/off inhib
NJU3712 NJU3712	JRC		04+	This family is a 16M bit dynamic RAM organized 4,
NJU3712A NJU3712A				The MB90590/590G series with two FULL-CAN*1 inte
NJU3712D NJU3712D	NJR		06/07+	contains an Erase Suspend feature. This feature
NJU3712M NJU3712M	NJR	SOP	2002	6. a) Reference point of the RJL is the drain le
NJU3712M(TE2) NJU3712M(TE2)	JRC	SOP	05+	or Powered-Down Low and Flat ON-State Resistance
NJU3712M-TE1 NJU3712M-TE1	SMD	JRC	05+	The device offers fast page access times of 25,
NJU3713 NJU3713	JRC	SMD	SMD	Note 1: Dropout voltage is defined as VIN - VOUT,
NJU3713A NJU3713A	JRC			The 8th bit of the control register is the write
NJU3713D NJU3713D	JRC	DIP	N/A	When the ECU experiences a loss of ground condit
NJU3713G NJU3713G	JRC			All typical values are at VCC = 5 V. On product
NJU3713G(TE1) NJU3713G(TE1)	JRC		5.2mm-8p	One or more in-system programmable PROMs can be
NJU3713GTE1 NJU3713GTE1				The high speed charge pump consists of a switcha
NJU3713G-TE1 NJU3713G-TE1	JRC	SOP	9712	The PCA9544A provides four interrupt inputs (one
NJU3713G-TE2 NJU3713G-TE2	JRC	SOP/18	01+	Output Drive Capability: 10 LSTTL Loads Outputs
NJU3714 NJU3714	JRC			• Four Crystal modes: - LP, XT, HS
NJU3714D NJU3714D			98	Notes: 1. Propagation Delays and Enable/Disable
NJU3714G NJU3714G	JRC	06+		This is a stress rating only and functional opera
NJU3714G-TE2 NJU3714G-TE2	JRC	SOT-223		The FAN2502/03 allows the user to utilize a wide
NJU3714M NJU3714M				The EM128C08 is an integrated memory device cont
NJU3715 NJU3715	JRC	SOP	03/+04+	NOTES 1Oversampling disabled. Static DAC perform
NJU3715A NJU3715A				Speed Is Enhanced Two Ways Delays in LCA-based
NJU3715AM NJU3715AM	JRC	DMP24		Except for pin-to-pin input and output parameter
NJU3715G NJU3715G	NJR	SOP22		CAUTION: THIS IS AN ESD SENSITIVE DEVICE The fol
NJU3715G-TE1 NJU3715G-TE1	JRC	SOP	2001	The power good (PG) function serves as a reset f
NJU3715G-TE2 NJU3715G-TE2	JRC	SOP22	00+	The HC4059 are high-speed silicon-gate devices t
NJU3715L NJU3715L	JRC	DIP		Single supply: 1.8 V to 5.5 V Two-wire serial
NJU3715M NJU3715M	JRC	SMD		The device is organized as a 10-bit switch with
NJU3716 NJU3716	JRC		0027	Please read the General Operating Consider
NJU3716A NJU3716A				The A0 to A6 inputs are used to specify which by
NJU3716L NJU3716L	NJR
NJU3716M NJU3716M	NJR		00+	The brushless DC fans found in many types of eq
NJU3716M(T2) NJU3716M(T2)	JRC	SOP-24	1996	BLOCK WRITE protection for top 1/8, top 1/4, top
NJU3716M(TE2) NJU3716M(TE2)				A simple method of calculating the values of actu
NJU3716M-T2 NJU3716M-T2	JRC	N/A	2002	Frame sequence, constant throughput delay
NJU3716M-TE2 NJU3716M-TE2	SMD	JRC	03+	2 inputs selectable for fan speed or voltage mon
NJU3716M-TE2-ZZZB NJU3716M-TE2-ZZZB	JRC		06+	The automatic mode select/change feature switche
NJU3717D NJU3717D				Features 1) Built-in bias resistors enabl
NJU3718 NJU3718	JRC	SO28	P5019C	The NJU3718 adds a second level hiccup mode cur
NJU3718A NJU3718A				Sequential reads are initiated by either a curren
NJU3718G NJU3718G	NJR		06/07+	Drain-Source Voltage Gate-to-Source Volta
NJU3718G-TE1 NJU3718G-TE1	JRC		97	Once the FIFO is full (indicated by FSTAT1 and F
NJU3718G-TE2 NJU3718G-TE2	JRC		00	Main CLK(Hz)Under 3.58M7.16M10.74M14.3M &
NJU3718L NJU3718L	NJR	DIP/28	98+	Only few external Components required Input Und
NJU3718M-TE2 NJU3718M-TE2	JRC		03+	MASK-ROM PIN-OUT COMPATIBLE SUPPLY VOLTAGE C V
NJU3719 NJU3719				Table 3.1 - LAN91C100FD Pin Requirements Table 5
NJU37192L NJU37192L	JRC	2007		NOTES: 1. These power consumption characteristic
NJU3719L NJU3719L	JRC	DIP	00+	Maximum ratings are those values beyond wh
NJU3770AD3 NJU3770AD3				As described under "Current Limiting,"
NJU3912E2 NJU3912E2		SOP	00+	The QS32X2245 provides a set of 16 high-s
NJU39610 NJU39610		DIP
NJU39610D2 NJU39610D2	NJR			• Low forward voltage VF and good wave detec
NJU39610D205 NJU39610D205				In this circuit the hot side of the line
NJU39610D2-ZZZB NJU39610D2-ZZZB	JRC		0809+	Data written to the DS1267 over the 3-wire serial
NJU39610D2-ZZZD NJU39610D2-ZZZD	NJRC			5. Applies to each output; each output has indep
NJU39610FM NJU39610FM	JRC		PLCC28	The auto identify mode allows the reading out of
NJU39610FM2 NJU39610FM2	NJR	2008		- Highly Reliable CMOS EEPROM Technology - 10 Ye
NJU39610FM205 NJU39610FM205				An on-board temperature sensor protects the modu
NJU39610FM2-ZZZB NJU39610FM2-ZZZB	JRC		0809+	When enabled by WEN, the rising edge of WCLK wri
NJU39612 NJU39612				The LX1910 does not require a minimum loa
NJU39612E2 NJU39612E2	JRC	SOP	06+	The negative output voltage of the Power Trends
NJU39612E204 NJU39612E204				The ADG3232 is a level translator 2-1 mux design
NJU39612E2-TE2 NJU39612E2-TE2	JRC		2000	The SY10EP89V is a differential fanout ga
NJU39612E2ZZB NJU39612E2ZZB				The Erase Suspend/Erase Resume feature allows th
NJU39612E2-ZZZ NJU39612E2-ZZZ				Each channel includes a variable gain amplifier,
NJU39612E2-ZZZB NJU39612E2-ZZZB	JRC		0809+	An internal Dummy Ringer is permanently connected
NJU4001 NJU4001				HY57V161610D is offering fully synchronous operat
NJU4001B NJU4001B	JRC			(25-MHz through 165-MHz Pixel Rates) Universal G
NJU4001BD NJU4001BD	JRC	DIP14	93+	*The maximum junction temperature rating of the
NJU4001BM NJU4001BM				The FAN4174 is designed on a CMOS process and pro
NJU4001M NJU4001M	JRC	STK	2005+	The application circuit examples are only to exp
NJU4001MCD4001 NJU4001MCD4001				MAX 7000A devices provide programmable speed/pow
NJU4011B NJU4011B	JRC	08+		Power for the circuit is from a 12V suppl
NJU4011BD NJU4011BD			97	• Low-power consumption (Standby) Mode &nb
NJU4011BM NJU4011BM				The HYS 64V8301 is an industry standard 168-pin
NJU4011BM(T1) NJU4011BM(T1)	JRC	00+	SOP	Ideally, the relative size of measurement error
NJU4011BP NJU4011BP	JRC	DIP	1	Configuration Programs For Field Programmable Gat
NJU4013 NJU4013				The LM393 series are dual independent pre
NJU4013B NJU4013B	JRC	SMD		• 2.1 MHz Clock Rate • Low power C
NJU4013BD NJU4013BD			01	Motorola reserves the right to make changes with
NJU4013BM NJU4013BM	JRC		92	CNY17-1/2/3 are also available in white package
NJU4013BMCD4013 NJU4013BMCD4013				The D-channel is primarily intended to carry sig
NJU4019BD NJU4019BD	JRC	STK	2005+	Notes: 1. For Max. or Min. conditions, use appr
NJU4020B NJU4020B	JRC		2001	TAOperating free-air temperature−5512
NJU4030 NJU4030				The DSP56800 core is based on a Harvard-style ar
NJU4030BD NJU4030BD	N/A	N/A	06+	The LT®3433 is a 200kHz fixed-frequency curre
NJU4040B NJU4040B				The MAX3873 is implemented in Maxims second-gener
NJU4040BM NJU4040BM	JRC	STK	2005+	The device is enabled when EN is set from logic
NJU4040BM-T1 NJU4040BM-T1				The front end also includes a 12-channel input m
NJU4050BD NJU4050BD	JRC	STK	2005+	Test Condition: 1.0KHz / 1V. Electrical specif
NJU4051 NJU4051				Gain Drift is a measure of the change in the ful
NJU4051B NJU4051B	JRC	SOP16		7.5 ATM Encapsulation and spanning-tree RFC 1483
NJU4051BD NJU4051BD	NJR	96+	DIP/16	Case: JEDEC TO-247AD molded plastic body Termina
NJU4051BM NJU4051BM	NJR		02+	† All typical values are at VCC = 2.5 V, T
NJU4051BM(T1) NJU4051BM(T1)				Gain error and gain temperature coefficien
NJU4051BM-T1 NJU4051BM-T1	JRC	N/A	2002	Overcurrent detection pin Monitors equivalent lo
NJU4051BM-TE1 NJU4051BM-TE1	JRC	DMP16		The COP8TAB9/TAC9 Flash microcontrollers are hig
NJU4051BM-TE2 NJU4051BM-TE2	JRC		06/07+	To provide long life and to insure soft-s
NJU4051BV NJU4051BV	JRC	99+	TSSOP	NOTES: 1. These power consumption characteristic
NJU4051BV(TE1) NJU4051BV(TE1)	JRC	03+	SOP	C-BUS is MX-COMs proprietary standard for the tra
NJU4051BV-TE1 NJU4051BV-TE1	JRC	SSOP16		The OPA688 is a wideband, unity gain stable volt
NJU4051V-TE1 NJU4051V-TE1	JRC	N/A	2003	Low ON-State Resistance (10 Ω) Control Inp
NJU4052 NJU4052	JRC	SMD	1997	The power dissipation of the SC-74 is a f
NJU4052B NJU4052B	JRC
NJU4052BA NJU4052BA	JRC	SOP	07+	The Infineon single mode ATM transceiver is a si
NJU4052BD NJU4052BD	NJR	DIP-16		The Timing and Watchdog Module (TWM) contains a
NJU4052BM NJU4052BM	NJR	SMD	1997	READ: The AT49BV16X4(T) is accessed like an EPROM
NJU4052BM(TE1) NJU4052BM(TE1)	JRC		2004	• 18V to 36V Input Voltage Range •
NJU4052BMA NJU4052BMA	JRC		01+	If the NJU4052BMA is in a nonvolatile write cycl
NJU4052BM-T1 NJU4052BM-T1	JRC	SOP16	92	The address sequence is completed when the numbe
NJU4052BM-TE1 NJU4052BM-TE1	JRC	04+	SOP/16	5V TOLERANT INPUTS HIGH SPEED: tPD = 5.9ns (MA
NJU4052BM-TE1-ZZZB NJU4052BM-TE1-ZZZB	JRC		06+	Timer counter 0 : 8-bit 1 (square-wave/8-
NJU4052BV NJU4052BV	JRC	SSOP	N/A	The NJU4052BV is a fully static CMOS 8051 compat
NJU4052BV(TE1) NJU4052BV(TE1)	JRC	SSOP	1999	The ÉlanSC300 microcontrollers true stati
NJU4052BV-(TE1) NJU4052BV-(TE1)	JRC		01	MAX 3000A devices are supported by Altera develo
NJU4052BV(TE2) NJU4052BV(TE2)	JRC	TSSOP	2000	Floating bootstrap supply pin for the upper gate
NJU4052BV-TE1 NJU4052BV-TE1	JRC	SOP16
NJU4052BV-TE2 NJU4052BV-TE2	JRC	00+	14850	Within each logic block there are 16 macrocells.
NJU4052BV-TEI NJU4052BV-TEI				Selects Burst Order. When tied to GND selects lin
NJU4052D NJU4052D	JRC	SOP28		(1) Signal Output The OUT1/1X and OUT2/2X
NJU4053 NJU4053	JRC		03+	The IDT7200/7201/7202 are dual-port memor
NJU4053/2257 NJU4053/2257				1.1 Program Memory Organization The TLC154/155 h
NJU4053B NJU4053B	JRC	SOP16
NJU4053BD NJU4053BD	NJR	DIP	1996	BUFFER READ: Data can be read from either one of
NJU4053BM NJU4053BM	NJR	SMD	9110	The S2/SUSPEND input can be configured to shut do
NJU4053BM(T2) NJU4053BM(T2)			03	Note 7: This parameter is guaranteed by design bu
NJU4053BM(TE1) NJU4053BM(TE1)	JRC	00+	SOP	NOTES 1Stresses above those listed under Absolut
NJU4053BM(TE2) NJU4053BM(TE2)				The FAN2500/01 is designed to supply 100mA at th
NJU4053BM-TE1 NJU4053BM-TE1	JRC		06/07+
NJU4053BM-TF2 NJU4053BM-TF2				This calculation was derived from laboratory meas
NJU4053BV NJU4053BV			97
NJU4053BV(TE1) NJU4053BV(TE1)	JRC	02+	TSSOP	1. The output optical power is compliant with IEC
NJU4053BV-TE1 NJU4053BV-TE1	JRC	SSOP16		This datasheet contains new product information.
NJU4053D NJU4053D	JRC		06/07+	3. Turn-Off Energy Loss (EOFF) is defined as the
NJU4053V NJU4053V	JRC	99+	SSOP	Suggestion: (1) Choose a small enough value pull
NJU4053V-TE1 NJU4053V-TE1	JRC	N/A	2003	Low I/O capacitance at 7pF typical In-system E
NJU4054 NJU4054		00+	SSOP	Transmit Error Active high. When an error happen
NJU4058BV NJU4058BV	JRC	SOP	0410	By combining a conventional thin-film R-2R ladde
NJU4066B NJU4066B	JRC	SMD	1991	RXD_14[0]CRSDV_14TXEN_14TXD_14[0]TXD_14[1]RXD_13[
NJU4066BD NJU4066BD	NJR		97	The 128-bit instruction line, which can contain
NJU4066BM NJU4066BM	NJR	SOP/14	99+	The MAX5026 constant-frequency, pulse-width modul
NJU4066BM(T1) NJU4066BM(T1)				• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
NJU4066BM(T2) NJU4066BM(T2)	JRC	SOP-14	00+	If the user wants to program the board with a fi
NJU4066BM(TE2) NJU4066BM(TE2)	JRC	SOP	2000	temperature variations. Simply tying the biasing
NJU4066BM(TEL) NJU4066BM(TEL)	JRC	SOP-14	1996	The CENTRAL SEMICONDUCTOR CMDZ2L4 Series Silicon
NJU4066BM-T2 NJU4066BM-T2				C Squelch on receive and collision pairs
NJU4066BM-TE1 NJU4066BM-TE1	JRC	DMP14		to be transmitted to the sensor diaphragm. The g
NJU4066BM-TE2 NJU4066BM-TE2	JRC	SOP/14	00+	Voltage, current, and temperature measurements ar
NJU4066BU NJU4066BU			95	1) CPD is defined as the value of the ICs intern
NJU4066BV NJU4066BV	JRC		98	4.4 Conformance inspection. Conformance in
NJU4066BV(TE1-R) NJU4066BV(TE1-R)				The ZL30414 is an analog phase-locked loop (APLL)
NJU4066BV-TE1 NJU4066BV-TE1	JRC	SSOP14		regard to the supply voltage. This device can be
NJU4066DV NJU4066DV	JRC	org packing	96+	Each circuit offers a choice of open-collector o
NJU4066M NJU4066M	JRC	SOP 14PIN		The variance in output pulse width from device t
NJU4066V-1 NJU4066V-1				Fourth Generation HEXFETs from International Rect
NJU4069UB NJU4069UB	MIT	SOP14M	2007+	-15 VOUT - is a regulated -15 volt output availab
NJU4069UBD NJU4069UBD	JRC	1992	DIP	In the normal mode, these devices are 18-bit uni
NJU4093B NJU4093B	JRC			The pre-emphasis is used to compensate for long
NJU4093BD NJU4093BD	JRC	DIP14P	96+	Because of these RF frequencies, it is necessary
NJU4093BM NJU4093BM			96	Temperature sensor ICs such as the MAX6672/ MAX6
NJU431U NJU431U				The integrated receiver is intended to be used a
NJU431U-TE1 NJU431U-TE1	JRC	SOT-89	06+	1. Test conditions unless otherwise noted: 25&or
NJU4538B NJU4538B				TEMPERATURE COMPENSATION Figure 2 shows
NJU4538BD NJU4538BD	JRC	DIP-16	9111	The Z86LXX architecture is based on Zilog's 8-bi
NJU4538BM NJU4538BM	JRC	SMD	1991	• Compliant with Intel® CK 408 rev 1.1
NJU4538BM-(T1) NJU4538BM-(T1)	JRC	05+	SOP	The device offers a highly integrated solution fo
NJU4558 NJU4558		SOP8	97/98	Available in the Texas Instruments NanoStarɽ
NJU4565M NJU4565M				NOTES 1All voltages are measured with respect to
NJU4565M(TE1) NJU4565M(TE1)	JRC	SOP8	0404+	Hynix HYMD232646B(L)8J-J series incorporates SPD(
NJU-4565V NJU-4565V	JRC			The MultiMediaCard is a universal low cost data s
NJU4580 NJU4580	54	JRC	O2	As a committed partner to the community and the
NJU501CA NJU501CA	JRC		03+	LCD BIAS Output Voltage Range FB Threshold Volt
NJU501D-CA NJU501D-CA	JRC		03+	Four selectable Receive and Transmit FIFO interr
NJU501EF NJU501EF	JRC		95	Dissipation Factor: The dissipation factor, dete
NJU501M-CC NJU501M-CC	JRC		9303	Conversion Time: CNV Rising Edge to Data Availab
NJU501M-EC NJU501M-EC	JRC	04+		• One chip ATM User Network Interface for
NJU501M-EE NJU501M-EE	JRC	STK	2005+	• Third Generation Field-Programmable Gate
NJU501MEF NJU501MEF
NJU501M-EF NJU501M-EF	JRC		95	Motorola reserves the right to make changes with
NJU501M-EF(T1) NJU501M-EF(T1)	N/A	N/A	N/A	Low Loss Replacement for PowerPathTM ORing Diode
NJU501M-LB NJU501M-LB				Parameter Total Gate Charge (turn-on) Ga
NJU5504D-JR NJU5504D-JR	JRC	STK	2005+	The AD7524M is capable of performing 2-quadrant
NJU555 NJU555				will vary with supply voltage, switching frequenc
NJU5601V NJU5601V	JRC		97+	The W83877TF supports one PC-compatible printer p
NJU6043F1 NJU6043F1	JRC	SOT-163	04+	Total Endurance, ICSP, In-Circuit Serial Program
NJU6048 NJU6048				• Constant current and voltage charging &
NJU6048F-TE1 NJU6048F-TE1	NJR			When a sync pulse is detected on channel A (CVBS)
NJU6048F-TE1-ZZZB NJU6048F-TE1-ZZZB	JRC		06+
NJU6050 NJU6050				The L5970AD is a step down monolithic power swi
NJU6050F-TE1 NJU6050F-TE1				The basic unit of logic on the ispLSI 2128VE dev
NJU6050F-TE1-ZZZB NJU6050F-TE1-ZZZB	JRC		06+	Stresses beyond those listed under absolute maxi
NJU6050F-TE2 NJU6050F-TE2				For proper compare operation the expander inputs
NJU6051 NJU6051				The AV9155 is a low cost frequency generator desi
NJU6051KM1-TE1-ZZZB NJU6051KM1-TE1-ZZZB	JRC		06+	TAOperating free-air temperatureC55125C4085
NJU6051V-TE1-ZZZB NJU6051V-TE1-ZZZB	JRC		06+	The intended application of these devices and si
NJU6052 NJU6052				BRIDGE CONFIGURATION EXPLANATION As shown in Fi
NJU6052KN1-TE1-ZZZB NJU6052KN1-TE1-ZZZB	JRC		06+	The various buffers within the BUFxx703 are care
NJU6052V-TE1-ZZZB NJU6052V-TE1-ZZZB	JRC		06+	Optional Asynchronous JTAG reset. Can be used to
NJU6053 NJU6053				The NLAS4501 is an analog switch manufact
NJU6053KP4-TE1-ZZZB NJU6053KP4-TE1-ZZZB	JRC		06+	The device integrates preamps for stereo differen
NJU6060 NJU6060				All the 80C186XL integrated peripherals are con-
NJU6060V NJU6060V	JRC	SOP/DIP	08+	The MAX4364/MAX4365 are bridged audio power ampl
NJU6060VTE1 NJU6060VTE1				The AC/ACT374 is a high-speed, low-power octal D
NJU6060V-TE1 NJU6060V-TE1
NJU6060V-TE1-ZZZB NJU6060V-TE1-ZZZB	NJRC			The 3.3-volt device is fully accessible and data
NJU6101 NJU6101	JRC	STK	2005+	hardware write protects selected sectors. The s
NJU6105 NJU6105	JRC			Flexible 3-Wire Serial Digital Audio Input and &
NJU6105A NJU6105A	JRC	STK	2005+	This is a four-state pin. DF/DCS = VA, output
NJU6248H04 NJU6248H04	JRC	BARE CHIP	01+	The EM39LV040 provides Chip-Erase feature, which
NJU6301FM NJU6301FM			92	CAUTION: These devices are sensitive to e
NJU6318A NJU6318A				Single amplifiers are offered in SOT-23 packages
NJU6318AE NJU6318AE	JRC	SOP-8	03+	s ESD protection of one automotive LIN bus line
NJU6318P NJU6318P				tpZLEnable time, high-impedance-to-low-leve
NJU6318PE NJU6318PE	JRC	99+	1780	By substituting the attenuated values of Vd and
NJU6318XC NJU6318XC	JRC		06/07+	SET (Pin 3): Frequency-Setting Resistor Input. Th
NJU6318XE NJU6318XE	JRC		06/07+	The output data consists of 128 bits of analog d
NJU6319A NJU6319A				The TLE 6363 G is a multifunctional power supply
NJU6319AE NJU6319AE	JRC	SMD	01+	The IDT71V2576/78 are high-speed SRAMs or
NJU6319AE(TE1) NJU6319AE(TE1)	JRC		03+	(1) MTTF calculator available at http://www.moto
NJU6319AE-TE1 NJU6319AE-TE1	JRC	01+	SOP/8	(2) The technical information described in this
NJU6319AE-TE2 NJU6319AE-TE2	JRC		06/07+	Input Voltage Range: 8V to 75V Valle
NJU6319BETE2 NJU6319BETE2				Thereareadditionalprovisionsfor demonstrating DD
NJU6320AC NJU6320AC	JRC	91		Notes: 1. The dominant wavelength, ëD , is
NJU6320AE NJU6320AE	JRC		5.2mm	The VHC125 contains four independent non-inverti
NJU6320EC NJU6320EC	JRC	96		The NJU6320EC, NJU6320EC, NJU6320EC, NJU6320EC, a
NJU6320EE NJU6320EE	JRC	96	SOP-8	The Fairchild Power Switch(FPS) product family i
NJU6320EE(TE1) NJU6320EE(TE1)	JRC	08+		Test Condition: 1.0KHz / 1V. Electrical specif
NJU6320EE(TE2) NJU6320EE(TE2)	JRC	01+	SOP/8	MIC1 or Line1 Analog Input (Left Minus or Multifu
NJU6320FE NJU6320FE	JRC		98+	convenient upgrade from and/or compatibility to
NJU6320FE(TE2) NJU6320FE(TE2)	JRC	00+	SOP/8	Honeywells enhanced SOI RICMOS™ IV (Radiat
NJU6320GC NJU6320GC	JRC	96		This example program is a function written in ge
NJU6320HE(TE1) NJU6320HE(TE1)	JRC	2007		The S8S3122X16 is 4,194,304 bits synchrono
NJU6320HE(TE2) NJU6320HE(TE2)	JRC	00+	SOP/8	The interrupt controller organizes hardware inte
NJU6321 NJU6321	JRC	06+	500	The TFDU6108 is an infrared transceiver module
NJU6321A NJU6321A				Partial Reset also sets the Read and Write point
NJU6321AE NJU6321AE	JRC		00+	1.1 Scope. This specification covers the
NJU6321AE(TE1) NJU6321AE(TE1)	JRC	SOP8	04+	There are four sources of power consumption in C
NJU6321AE-TE1 NJU6321AE-TE1	JRC	SOP/8P3.9mm	00+	The information provided herein is believed to be
NJU6321AE-TE1-ZZZB NJU6321AE-TE1-ZZZB	NJRC			For operation below 0C, the external capacitors
NJU6321AE-TE2 NJU6321AE-TE2	JRC	01+	SOP/8	Sample Mode Offset Error - S/H1 Gain Error - S/H
NJU6321P NJU6321P				The ADSP-BF535 Blackfin processor is a highly in
NJU6321PE NJU6321PE	JRC	SOP-8	01+	Due to pin limitations the intermediate carries
NJU6321PE(TE1) NJU6321PE(TE1)	JRC	04+	SOP
NJU6321PE-TE1 NJU6321PE-TE1	JRC	二脚铁帽		Output of 1394b driver block. These twisted-pair
NJU6321PE-ZZZB NJU6321PE-ZZZB				switch and a second IMP8980D for communication w
NJU6322 NJU6322	JRC			The T8xC51SND1 provides all necessary features f
NJU6322CC NJU6322CC				The VRE3041 is recommended for use as a referenc
NJU6322K NJU6322K				Hynix HYMD264G726(L)4M-K/H/L series is Low Profil
NJU6322KE NJU6322KE	JRC	2008		Stresses beyond those listed under Absolute Maxim
NJU6322KE(TE1) NJU6322KE(TE1)	JRC	SOP/8	00+	The signal bandwidth of a transimpedance amplifi
NJU6322KE(TE2) NJU6322KE(TE2)	JRC		95	Pixel select C Selects between one or two pixels
NJU6322KE-TE1 NJU6322KE-TE1	JRC	97+	SOP/8	XC9500XV CPLDs are also 1.8V I/O compatible. The
NJU6322L NJU6322L				The device can readily control keys over graphic
NJU6322LE NJU6322LE	jrc	jrc	dc90	No license is granted, implied or otherwise, und
NJU6322M NJU6322M				Note: 1. Except for the rating "Operating T
NJU6322M-1 NJU6322M-1	JRC			The 512K EPROM and OTP PROM are programmed using
NJU6322ME(TE1) NJU6322ME(TE1)	JRC	SOP-8	2002+	This series of fixed-voltage integrated-circuit
NJU6322N NJU6322N				Two data address generators (DAGs) provide addre
NJU6322NC NJU6322NC	jrc	jrc	dc90	The MMA3200 series of dual axis (X and Y)
NJU6322NE NJU6322NE	jrc	jrc	dc90	Centuries in BCD Format C bq4802Y: 5-V Op
NJU6322NE(TE1) NJU6322NE(TE1)	JRC	SOP8	04+	4.3 Screening (JANS, JANTX, and JANTXV le
NJU6322P NJU6322P				The read transaction shows a request packet at c
NJU6322PE NJU6322PE	JRC	SMD-8	9831+	The NJU6322PE is a member of the HPCTM family of
NJU6322PE(TE1) NJU6322PE(TE1)	JRC	07+		Supply current falls to less than 1µA in sh
NJU6323 NJU6323				3. Die Attach a. Eutectic Eutectic die attach c
NJU6323E NJU6323E				Stresses beyond those listed under "absolut
NJU6323E(TE1) NJU6323E(TE1)				4.4 Conformance inspection. Conformance in
NJU6323E-TE1 NJU6323E-TE1	JRC	SOP8	04+	The ispLSI 5000VE Family ranges from 128 macroce
NJU6324FC NJU6324FC	JRC	93		The software Block Erase mode is initiated by iss
NJU6324GE(TE2) NJU6324GE(TE2)	JRC	07+		In no event shall ELAN Microelectronics be made
NJU6324L NJU6324L				A short program illustrating the initialization a
NJU6324LE NJU6324LE				Drain-Source Voltage Gate-to-Source Voltage C
NJU6324M NJU6324M	JRC	STK	2005+	Every byte put on the SDATA line must be 8-bits l
NJU6324MC NJU6324MC	JRC	93		This chip, when properly assembled, display char
NJU6331HC NJU6331HC				Maximum ratings are those values beyond which de
NJU6331HE NJU6331HE	JRC		5.2mm	Notes: 1. For Max. or Min. conditions, use appro
NJU6331HE(TE1) NJU6331HE(TE1)	JRC	SOIC-8	07+/08+	The STTH5R06, which is using ST Turbo 2 600V te
NJU6331HETE2 NJU6331HETE2				The ADC works in fully differential mode from th
NJU6331QC NJU6331QC	jrc	jrc	dc90	To correct for this type of error, we can indivi
NJU6331QE NJU6331QE	JRC	STK	2005+	The SM561 uses a Cypress proprietary phase-locke
NJU6331QE(TE1) NJU6331QE(TE1)	JRC	SOIC-8	07+/08+	New B6HF bipolar technology, 25GHz fT Small out
NJU6332QE NJU6332QE	JRC	SOP/8	99+	NOTE: Device will meet the specifications after
NJU6333A NJU6333A				Maximum ratings are those values beyond which de
NJU6333AE NJU6333AE	JRC		06/07+	The product information and the selection guides
NJU6333AE(TE2) NJU6333AE(TE2)				The melting temperature of solder is highe
NJU6333AE-TE2 NJU6333AE-TE2	SMD	JRC	03+	Expansion header J7 is provided to monitor or ap
NJU6333H NJU6333H				The HS-800/810 Series of quartz crystal oscillat
NJU6333HC NJU6333HC	JRC		93+
NJU6333Q NJU6333Q				Data must be set up for a duration of tSD before
NJU6333QE NJU6333QE	JRC	SOP	00+	A buffered output-enable (OE) input can be used
NJU6333XC NJU6333XC	JRC		06/07+	Efficiency at 3-A Continuous Output Current Uses
NJU6333XE NJU6333XE	JRC		06/07+	With the boost feature the small signal s
NJU6342 NJU6342
NJU6342E NJU6342E	JRC		06/07+	Sleep Mode. Control input SLEEP is used to minim
NJU6342H NJU6342H				DC bus capacitor filter with NTC inrush
NJU6342HE NJU6342HE	JRC		06/07+	Reading from the device is accomplished by takin
NJU6350 NJU6350				Notes: 7. Typical performance plots are based on
NJU6350R NJU6350R	JRC	00+	TSSOP	NOTES: 1. Skew parameters are guaranteed across
NJU6355 NJU6355				READ CYCLE TRCRead Cycle Time TAAAddress
NJU6355E NJU6355E	99+	JRC	2500	The AS4C1M16F5 features high speed page mode ope
NJU6355ED NJU6355ED	JRC		06/07+	Test 2 Pin(Internal pull-down pin) Receiver Inp
NJU6355EM NJU6355EM	JRC		06/07+	The crystal oscillators should be fundame
NJU6355EMTE1 NJU6355EMTE1	jrc	jrc	dc00	MPC8xx core that incorporates memory management
NJU6355EM-TE1 NJU6355EM-TE1	JRC		06/07+	The RHL package is available taped and reeled on
NJU6355EM-TE1-ZZZB NJU6355EM-TE1-ZZZB				tors output sets the trip voltage. Therefore, the
NJU6356ED NJU6356ED				The Sigma Delta Modulator is a 3rd order (second
NJU6356EM NJU6356EM	JRC	SOIC8	04+.04	s Programmable MAC Interface supports most &nbs
NJU6356EM-TE2 NJU6356EM-TE2	JRC	SOP8	02+	The Electrical and Switching Characteristics of
NJU6358V NJU6358V	JRC	TSSOP14	04+	Push-Pull CMOS Output Drives Capacitive Loads Wi
NJU6358V24 NJU6358V24				VDM = 67% VDRM(max);20 Tj = 125 ˚C; expone
NJU6361AC NJU6361AC	JRC		06/07+	Note 2: The algebraic convention, where the most
NJU6361AE NJU6361AE	JRC		06/07+	The P8xC557E8 contains a volatile 2048 bytes rea
NJU6366 NJU6366				Built-in superimpose function Built-in Y-C mix c
NJU6366A NJU6366A				The ADS800 employs digital error correction to p
NJU6366AF NJU6366AF	JRC	SOT23-6	2002	2. Memory Address Expansion The VP-1000A's inter
NJU6366AF1 NJU6366AF1	JRC		06/07+	Functions To provide memory addresses. During s
NJU6366B NJU6366B				HY57V281620E(L)T(P) is offering fully synchronous
NJU6366BF1-TE1-ZZZB NJU6366BF1-TE1-ZZZB	JRC		06+	• 64-bit password security • One arr
NJU6366D NJU6366D				C High-performance 32-bit RISC Architectu
NJU6366DF1-TE1 NJU6366DF1-TE1	NEC	2001	SOT-6	The CP3SP33 contains a CR16CPlus CPU core. This
NJU6368 NJU6368				The NJU6368 SX is an intelligent high-performance
NJU6368B NJU6368B				The CY7B9950 features split power supply buses f
NJU6368D NJU6368D				Each port has independent control pins: Chip Ena
NJU6368P NJU6368P				Note A: All data listed in the above graphs, exc
NJU6373A NJU6373A				Available parts are detailed in the ordering inf
NJU6373AE(TE1) NJU6373AE(TE1)	JRC	08+		Asynchronous output enable. OE must be low to rea
NJU6373B NJU6373B				The high-current pass element provides a
NJU6373BE(TE1) NJU6373BE(TE1)	JRC	SOP	2002	The V 6108 is a CMOS integrated circuit that dri
NJU6373C NJU6373C				Special handling is required for Flash Memory pro
NJU6373CE(TE1) NJU6373CE(TE1)	JRC	SOP	2003	MOSI is the serial data input to the ISD5008 de-
NJU6373G NJU6373G	JRC	08+		cause large currents to flow which can result in
NJU6373GE NJU6373GE				Composite type with an N-Channel Sillicon
NJU6373H NJU6373H				Within each processing element is a set of compu
NJU6373HC NJU6373HC	JRC	98
NJU6373HE NJU6373HE	JRC		97+	BVDSSDrain-to-Source Breakdown Voltage-100 W
NJU6373HE(TE2) NJU6373HE(TE2)	JRC	01+	SOP/8	The LMP7711 is a low noise, low offset, CMOS inp
NJU6373J NJU6373J				Note 8: This specification is provided only to in
NJU6373JETE1 NJU6373JETE1	N/A	N/A	04+
NJU6373Q NJU6373Q				All functions of this device are fully controlla
NJU6373QE NJU6373QE	JRC	95	3000	MEMORY ARRAY ORGANIZATION The 1 MByte Flash mem
NJU6373QE(TE1) NJU6373QE(TE1)	JRC	05+		0.75dB per step/32step AGC Control Interface Au
NJU6373QE-TE2 NJU6373QE-TE2	JRC		06/07+	QEB125 single output DC/DC converters provide up
NJU6374AE(TE2) NJU6374AE(TE2)	JRC	00+	SOP/8	Reference Acknowledgement (REF_ACK) Output The R
NJU6374HC NJU6374HC	JRC	98		The 5B45 and 5B46 are single-channel isolated fr
NJU6374HE(TE1) NJU6374HE(TE1)	JRC	08+		Figure 1 shows the equivalent circuit for the OT
NJU6374Q NJU6374Q				Retires as many as three instructions per clock
NJU6374QE NJU6374QE	JRC	95	3000	Output skew with respect to the REF input
NJU6374QE(TE1) NJU6374QE(TE1)	JRC	08+		• 13 I/O pins with individual direction co
NJU6376 NJU6376				MOUT: (multiplier output and current amplifier in
NJU6376AF1 NJU6376AF1	JRC			The MAX1108/MAX1109 low-power, 8-bit, dual-channe
NJU6378D NJU6378D				the full-scale output current. The differential
NJU6378DF1-TE1-ZZZB NJU6378DF1-TE1-ZZZB	JRC		06+	Note: 6. Full Device AC operation require
NJU6391C NJU6391C				1) CPD is defined as the value of the ICs intern
NJU6391CE NJU6391CE	JRC		03+	Similar To Industry Standard LT1033 Approved To
NJU6391CE-TE2 NJU6391CE-TE2	JRC	SOP/8	00+	The ASH transceivers unique feature set is made p
NJU6391PE(TE1) NJU6391PE(TE1)				a. Absolute maximum continuous ratings are those
NJU6401B NJU6401B	JRC	07+		TACHYON Architecture Tachyon TL continues with
NJU6401BD NJU6401BD	JRC	SMT-76		Each frame of non-interlaced video is vertically
NJU6401BM NJU6401BM	N/A	N/A	N/A	- Compliant to USB specifications - Dual indepen
NJU6401D NJU6401D	JRC	DIP	06+
NJU6402B NJU6402B	JRC	00-04		A; P1, B; P2, C; P4, D; P3 All o
NJU6402BD NJU6402BD	JRC	DIP	97+	The data will be transmitted in the silent period
NJU6402BM NJU6402BM				There are three ways of displaying the field seq
NJU6402BM(TE1) NJU6402BM(TE1)				The READ instruction is the only instruction tha
NJU6402BMTE1 NJU6402BMTE1				The bq2050H determines battery capacity by moni-
NJU6406 NJU6406				To protect against load faults, the regulators i
NJU6406B NJU6406B				Figure 1 shows a typical bq2060-based battery pac
NJU6406BC-02 NJU6406BC-02				output selectable). On-chip RAM performs bufferi
NJU6406BC-08 NJU6406BC-08	NJRC		07/08+	When the HSP3824 is conﬁgured to generate
NJU6406BC-A3 NJU6406BC-A3	JRC	WAFER/MODEL	9508-524T	The following specifications apply for AGND = DG
NJU6406BF NJU6406BF	JRC	STK	2005+	The MAX3873A successfully meets the quali
NJU6406BH01P-A8 NJU6406BH01P-A8	JRC		06/07+	The Flash program memory supports both parallel
NJU6406CF NJU6406CF	JRC	STK	2005+	The Simtek STK12C68 is a fast static RAM with a
NJU6407C NJU6407C				1. Test conditions: T = 25º C, Supply Volta
NJU6407CF NJU6407CF		JRC	500	The AWL9224 is manufactured using advanced InGaP
NJU6407CFA1 NJU6407CFA1			95	The block diagram on page 1 shows the relationsh
NJU6407CFAI NJU6407CFAI	JRC	2008		Purchase of I2C components from Maxim Integ
NJU6408B NJU6408B				qOne-side printed circuit board is recommended.
NJU6408BF NJU6408BF	JRC	QFP80		The line impedance presented by the Line Driver c
NJU6408BFC1 NJU6408BFC1	JRC	QFP	9909	An on-chip oscillator eliminates the need for an
NJU6408BFC1-00 NJU6408BFC1-00	JRC	2008		Offset Drift is a measure of the actual change i
NJU6408BFC1-01 NJU6408BFC1-01				A sense FET monitors the current supplied to the
NJU6408BFC1-01A NJU6408BFC1-01A	JRC	QFP	9909	The ISD1000A ChipCorder Series devices are desig
NJU6408BFC1-07 NJU6408BFC1-07	JRC	QFP/80	97+	Operating voltage: fSYS=4MHz: 3.3V~5.5V fSYS=8M
NJU6408BFCI NJU6408BFCI		08+		When the PAR/SER pin is high the chip is in paral
NJU6408BFG1-02 NJU6408BFG1-02	JRC		06/07+	Stability The AP1187 requires the use of an outp
NJU6413A NJU6413A				The SiP5630 senses the operational state of the
NJU6413AD NJU6413AD	JRC			The CY7C1350G is a synchronous-pipelined Burst SR
NJU6413AM NJU6413AM				This document describes how to design a platform
NJU6415 NJU6415				Mode switch The DC voltage on the CTL pin can b
NJU6415C NJU6415C	JRC		06/07+	• Floating High Side Driver with boot-strap
NJU6415F NJU6415F	JRC	QFP100		Each of the LMH6628's closely matched channels p
NJU6416 NJU6416				The NCP1050 through NCP1055 are monolithic
NJU6416C NJU6416C	JRC		06/07+
NJU6416F NJU6416F				Power Control (SO-14 only) Maximum Logic 0 Min
NJU6416FC1 NJU6416FC1	NJR			Only the destination of the lower-order byte in t
NJU6416FC1-ZZZB NJU6416FC1-ZZZB	JRC		06+	Track: This is an analog control input that enab
NJU6417BF NJU6417BF				FLEX 8000 devices contain an optimized microproc
NJU6417C NJU6417C				Number of channels : 8 Resolution : set 10-bit
NJU6417CC NJU6417CC	JRC		06/07+	2.2 Specifications, standards, and handbo
NJU6417CF NJU6417CF	JRC			The sequence of the burst counter is determined b
NJU6417CF(JRC) NJU6417CF(JRC)				The RESET pin is asserted whenever VCC falls bel
NJU6417CFC1-A NJU6417CFC1-A				Stresses above those listed under Absolute Maxim
NJU6417CFC1-ZZZB NJU6417CFC1-ZZZB	JRC		06+	n Drive up to 4, 6, 8 or 10 white LEDs for Dual
NJU6417CFC2 NJU6417CFC2				The Inhibit pin is an open-collector/drain activ
NJU6417F NJU6417F	JRC		01+	Reader Response: Conexant strives to produce qual
NJU6420B NJU6420B				Level adjust for video signals Video faders and
NJU6420BF NJU6420BF	JRC	QFP100		Positive input voltage for the regulator. The in
NJU6420BFC1-03 NJU6420BFC1-03	JRC	06+		Notes: 1. ZZZZ or ZZZ denotes the assigne
NJU6420BFC2-03 NJU6420BFC2-03	JRC	QFP		After a program or erase cycle has been com- pl
NJU6420BFCI-03 NJU6420BFCI-03		97	QFP	!Features 1) Built-in bias resistors enable the
NJU6420F NJU6420F	JRC	2008		Secured Silicon Sector: Extra 256 Byte sector &
NJU6423B NJU6423B				HY57V658020B is offering fully synchronous operat
NJU6423BF NJU6423BF	1500	JRC	97+	A programmable interval timer generates periodic
NJU6423BF02 NJU6423BF02				RXCLK is the clock output bit clock. This clock
NJU6423BFC1-02 NJU6423BFC1-02	JRC	97		The nominal value of the RF choke L1 is 100 nH.
NJU6423BFC1-03 NJU6423BFC1-03				The design of the DM562P is optimized for desktop
NJU6423BLF NJU6423BLF				Carrier Detect. This input controls the recovery
NJU6423BLFC1-02 NJU6423BLFC1-02				• System Integration Module (SIM07), Incor
NJU6423F02 NJU6423F02				Current sensing is done in this case by a
NJU6424 NJU6424				Maximum ratings are those values beyond which de
NJU6424F NJU6424F	JRC	STK	2005+	REFIN Input Capacitance REFIN Inpu
NJU6425 NJU6425	N/A	N/A	N/A	The wide operating supply range and high accuracy
NJU6425FC2-02A NJU6425FC2-02A	JRC	QFP	1994	The data of Figure 13 is based on TJ(pk)
NJU6426BF NJU6426BF	JRC	STK	2005+	SET - RESET CAPABILITY STATIC FLIP-FLOP OPERAT
NJU6426C-02 NJU6426C-02	JRC	DICE		† Notice: Stresses above those listed under
NJU6426F NJU6426F	JRC	2007		The Hynix HYM71V16M655B(L)T6 Series are Du
NJU6426FC1-ZZZB NJU6426FC1-ZZZB	JRC		06+	Port 1 is an 8 bit bi-directional I/O port with
NJU6428 NJU6428				The ispLSI 3448 is a High-Density Programmable L
NJU6428BF NJU6428BF	JRC		03+	NOTES: 1. For conditions shown as Max. or Min.,
NJU6428CH04 NJU6428CH04	JRC	07+		This new series of digital transistors is
NJU6428CH04-A1 NJU6428CH04-A1				NOTES: 1. A17 is a NC for IDT70V3399. 2. VDD, O
NJU6428H04 NJU6428H04	JRC	07+		Outputs from the GLBs drive the Global Routing P
NJU6428LF NJU6428LF	JRC	STK	2005+	Competition among network providers enables the m
NJU6428LFA2 NJU6428LFA2	JRC	98		The MAX1512 is a programmable VCOM-adjustment so
NJU6428LFG1 NJU6428LFG1				Stresses beyond those listed under Absolute Maxim
NJU6428LFG1-02 NJU6428LFG1-02	JRC		00	A family of products offers 3-line, 2-line, and
NJU6428LFG1-A2 NJU6428LFG1-A2
NJU6428LH04-A1 NJU6428LH04-A1				NJU6428LH04-A1o reduce the value of ROUNJU
NJU6429 NJU6429				Tiny SOT−353 and SOT−553 Packages Ex
NJU6429CF NJU6429CF	JRC		03+	4-channel Pulse Width Modulator (PWM) generator
NJU6432B NJU6432B	TOS	STK	01#	Parameter Collector-base breakdown volt
NJU6432BF NJU6432BF	JRC	QFP		The DS1543 is in the write mode whenever WE and
NJU6432BFB2 NJU6432BFB2	JRC		98	Ultra-low power consumption, quiet, pump
NJU6432BFD1 NJU6432BFD1				The maximum output is set to VMAX, the mi
NJU6432BFDI NJU6432BFDI	JRC	QFP-64	98+	Built on the Vishay Siliconix proprietary high v
NJU6432BFG1 NJU6432BFG1	JRC		0809+
NJU6433B NJU6433B
NJU6433BF NJU6433BF	JRC	05+	TQFP	> 90% Maximum Efficiency Low Quiescent Supply
NJU6433BFG1-ZZZB NJU6433BFG1-ZZZB	JRC			The four high order bits deﬁne the instru
NJU6433F NJU6433F	JRC	QFP	QFP	Total Power Supply and Zener Current Output Cu
NJU6433FB2 NJU6433FB2	JRC		0809+	† Typical values are at VCC = 5 V, TA = 25
NJU6433FD1 NJU6433FD1	JRC		0809+	A Retriggerable one-shot multivibrator has an ou
NJU6433FG1 NJU6433FG1	JRC	QFP	2005	Housed in SOIC−8 or PDIP−8 pac
NJU6433FG1-ZZZB NJU6433FG1-ZZZB	JRC		0809+	The two single-ended charge-pump power stages op
NJU6435 NJU6435	JRC	STK	2005+	operation, the AGB3302 is ideal for wireless in
NJU6435BF NJU6435BF				Writing to the device is accomplished by taking
NJU6435DF NJU6435DF				• 3V to 40V Input Voltage Operation •
NJU6435EF NJU6435EF	JRC	2008		When a valid DTMF signal burst is present, ESt or
NJU6435EFB2 NJU6435EFB2	JRC	SOP		Each output buffer has a fixed gain of +6dB and c
NJU6435EFG1 NJU6435EFG1				NOTES: (1) For detailed drawing and dimension ta
NJU6435EFG1-ZZZB NJU6435EFG1-ZZZB	JRC		0809+	Maximum power dissipation at indicated ambient te
NJU6435FF NJU6435FF	JRC	93	QFP	− Inputs capable of generating interrupts
NJU6435FFG1 NJU6435FFG1	JRC		0809+	256-byte SecSi™ (Secured Silicon) Sector
NJU6436 NJU6436				The TMAX register is programmed using a standard
NJU6436F NJU6436F	JRC	00+	1450	The HT815D0 has a built-in RC oscillator which
NJU6436FG1 NJU6436FG1	JRC		2004	The large Cs capacitor creates a virtual ground
NJU6437 NJU6437				Notes: 2. The voltage on any input or I/O
NJU6437CH-E-CT2 NJU6437CH-E-CT2	JRC		06/07+	The HY62LF16406D is a high speed, super lo
NJU6438 NJU6438				n Single-cell 0.9V to 2.5V battery operation n
NJU6438CH NJU6438CH	JRC		0809+	Note: Agilent Technologies encoders are not r
NJU6439 NJU6439				1.2.3 Device class designator. The device
NJU6439CL NJU6439CL	JRC		0809+	Note 8: The converter is in external SCK mode of
NJU6445 NJU6445				Copyright © 2002 Integrated Silicon Solutio
NJU6445F NJU6445F	JRC	STK	2005+	The Am29F032B is a 32 Mbit, 5.0 volt-only Flash
NJU6450A NJU6450A				The main purpose of this bipolar transistor is b
NJU6450AC NJU6450AC	JRC		0809+	Proven in substantial volumes, this devic
NJU6450AF NJU6450AF
NJU6450AFC1 NJU6450AFC1	JRC		0809+	Common I O for reduced pin count Four operation
NJU6450AFG NJU6450AFG				(2) JC data values stated are derived from MIL-S
NJU6450AFG1 NJU6450AFG1	JRC	2008		(4) The products and product specifications desc
NJU6450AFJRCA5016C NJU6450AFJRCA5016C				Palladium plating is used on the terminal pins. A
NJU6450AFV NJU6450AFV				A bidirectional data strobe (DQS) is transmitted
NJU6451A NJU6451A				DEVICE POWER SUPPLY: The VCC pin is used to suppl
NJU6451AC NJU6451AC	JRC	裸片	00+	The case (mounting flange) is electrically
NJU6451AF NJU6451AF				The CMX866 can be made to perform a variety of lo
NJU6451AFC1 NJU6451AFC1	JRC		1	output to provide state-of-the-art step- down s
NJU6452A NJU6452A	JRC		0809+	The ADS5423 is a 14 bit 80 MSPS analog-to-digita
NJU6452AF NJU6452AF	JRC	QFP	1999	†Purchase of I2C components from Maxim Inte
NJU6466C-02 NJU6466C-02				In addition to the Voltage Identification, there
NJU6467 NJU6467				The two single-ended charge-pump power stages op
NJU6467F NJU6467F	JRC			• Low-power, high-speed CMOS EPROM/
NJU6468 NJU6468				DETAILED FEATURES High Definition Programmable
NJU6468F NJU6468F	JRC			DAC08 applications include 8-bit, 1 µs A/D
NJU6468F(JRC) NJU6468F(JRC)				The temperature of the H7422 outer case rises du
NJU6468FC-00A NJU6468FC-00A				The initial setup sequence programs the two blin
NJU6468FC1-00 NJU6468FC1-00	JRC		06+	Note 3: The linearity error is calculated by the
NJU6468FC1-B3 NJU6468FC1-B3	JRC		QFP	If VSB is below either of the two EDV thresholds,
NJU6468FC1-B4 NJU6468FC1-B4		04+		NOTES: 1. Dimensions are in inches. Metric
NJU6468FC1-B5 NJU6468FC1-B5		04+		ware reset to ensure that no spurious alteration
NJU6468FG NJU6468FG	JRC		04+	When the device is operating as a timing master,
NJU6469 NJU6469				For best performance, controlled impedance trans
NJU6469AF NJU6469AF	JRC	STK	2005+	Parameter Bias Offset Voltage(MODP) Bias offset
NJU6469LE NJU6469LE	JRC			Pin-compatible with AD9054 High conversion rat
NJU6469LF NJU6469LF				• Fully supports PowerPC™ 60x bus pr
NJU6469LFG1-02 NJU6469LFG1-02	JRC	QFP	2000	LCD BIAS Output Voltage Range FB Threshold Volt
NJU6469LP NJU6469LP	JRC	STK	2005+	cause large currents to flow which can result in
NJU6469NF NJU6469NF	JRC	TQFP	07+	The high-bandwidth digital content protection sy
NJU6469NFG1-A2 NJU6469NFG1-A2	JRC	TQFP-100P	07+	Maximum ratings are those values beyond which de
NJU6470 NJU6470				The µPA1853 is a switching device wh
NJU6470F NJU6470F		QFP	98	To support PCMCIA-compatible word-wide access d
NJU6533 NJU6533				†For information on tape and reel specific
NJU6533KQ1-TE4 NJU6533KQ1-TE4	JRC	05+	QFN	Throughout this data sheet, references are made
NJU6535 NJU6535				SNR = 90 dB in 150 kHz bandwidth (to Nyquist &n
NJU6535F NJU6535F	JRC	QFP64		NJU6535F is a single chip ISO/IEC 11172-3
NJU6535FG1 NJU6535FG1	JRC		0809+	pins 1 & 5 connected See application schemat
NJU6535FH1 NJU6535FH1	JRC		0809+	To improve total system throughput and reduce pa
NJU6539 NJU6539				Notes: The gain for the unmatched device in 50
NJU6570F NJU6570F	JRC	STK	2005+	Enhanced PCI South Bridge for Desktop, Mobile an
NJU6575A NJU6575A	JRC	QFN	05+	The output capacitor must meet the requirements
NJU6575AH04 NJU6575AH04				Overcurrent detection pin Monitors equivalent lo
NJU6580 NJU6580	JRC		0809+	The NJU6580 is a 2-digit BCD to 7-segment decode
NJU6580H01 NJU6580H01	JRC		0809+	The LTC6900 operates with a single 2.7V to 5.5V p
NJU6600F NJU6600F	JRC	STK	2005+	A programmable signal-detect level set pi
NJU6623A NJU6623A				• This catalog has only typical specificat
NJU6623AF NJU6623AF	JRC	QFP
NJU6623F NJU6623F	JRC	STK	2005+	AL, BL, CL - Are the logic level inputs for contr
NJU6624A NJU6624A				This method fails if a user applies RESET during
NJU6624AF NJU6624AF	JRC			3. In case that these products are proved to hav
NJU6624AFG1-02 NJU6624AFG1-02	JRC	TQFP	2000	The device provides a JEDEC-approved optional sof
NJU6624AGF1-02 NJU6624AGF1-02	JRC	QFP	05+	5. CPD is defined as the value of the internal e
NJU6624B NJU6624B				Please read Application Note 1 "Gener
NJU6624BF NJU6624BF	JRC	STK	2005+	The HYM72V64C756T4P -Series are high spee
NJU6624C NJU6624C				The HA-5004 current feedback ampliﬁer is
NJU6624CF NJU6624CF		TQFP100	99	Low Loss Replacement for ORing Diode in Multiple
NJU6678V NJU6678V				Control Register A password protected read or w
NJU6678VBCL-G-CT2 NJU6678VBCL-G-CT2	JRC	TCP	2	Note 4: For a power supply of 5V r10% the worst-
NJU6679 NJU6679				Power mode: Normal, Slow, Idle, Stop mode and SL
NJU6679ACJ-G-CT2 NJU6679ACJ-G-CT2	JRC		0809+
NJU6701 NJU6701		PLCC32	03/+04+	A short program illustrating the initialization a
NJU6833F NJU6833F				EPIC™ (Enhanced-Performance Implanted CMOS
NJU6912 NJU6912	JRC	SOP	07+	NOTES 1Input bias current is specified for two d
NJU6915AF NJU6915AF			QFP-80	The byte pointer bit must be toggled to the corr
NJU6918D NJU6918D	JRC	STK	2005+	The DS1543 is a full-function real-time clock/ca
NJU7001 NJU7001	NJRC			If Military/Aerospace specified devices are requi
NJU7001D NJU7001D	JRC		0809+	 Common output structure for standard and
NJU7001M NJU7001M	JRC	SMD/8	94/90	The bq4802Y/bq4802LY provides direct connections
NJU7001M(TE1) NJU7001M(TE1)	JRC	SOP	1998	Time t6, represents a transition between light a
NJU7001M-TE1-ZZZB NJU7001M-TE1-ZZZB	JRC		0809+	1.1 Scope. This specification covers the
NJU7001V NJU7001V	JRC		04+	The HPR2XX Series uses advanced circuit design a
NJU7001V(TE1) NJU7001V(TE1)	JRC	SSOP	2004	The LTC®1051/LTC1053 are high performance, lo
NJU7001V-TE1 NJU7001V-TE1	JRC		02+	‡ Stresses beyond those listed under absol
NJU7001V-TE2 NJU7001V-TE2	JRC			CMOS imager sensor CMOS imager sensor 2:
NJU7002 NJU7002	JRC		07+	The W536XXXP, a member of ViewTalkTM family, is a
NJU7002D NJU7002D	JRC		0809+	2.1 General. The documents listed in this
NJU7002D05 NJU7002D05
NJU7002M NJU7002M	JRC	2000	SOP	The MSM514262 supports three types of operation :
NJU7002M(T1) NJU7002M(T1)	JRC		9607	Stresses above those listed under Absolute Maxim
NJU7002M(TE1) NJU7002M(TE1)	JRC	SOP	04/99	Added -7 Bining product. - In Orde
NJU7002M(TE2) NJU7002M(TE2)	JRC	SOP-8	02+	TMIN = −40C, TMAX = +85C. Typical values a
NJU7002MTE1 NJU7002MTE1				The Sirenza Microdevices qualification process co
NJU7002M-TE1 NJU7002M-TE1	JRC	N/A	03+	The 1.8 Volt Intel Wireless Flash Memory with 3
NJU7002M-TE1-ZZZB NJU7002M-TE1-ZZZB	JRC		0809+	The TC554161AFT is a 4,194,304-bit static
NJU7004 NJU7004	JRC	SMD	SMD	Port 3 pins P3.0 to P3.5, P3.7 are seven bi-dire
NJU7004D NJU7004D	JRC	DIP-14	2003+	The MAX5026 constant-frequency, pulse-width modul
NJU7004M NJU7004M	JRC		03+	To Diode Anode. Connected to remote discrete di
NJU7004M(7E1) NJU7004M(7E1)	JRC	96/97	5500
NJU7004M(TE1) NJU7004M(TE1)	JRC	07+		The AT91X40 Series features a direct connection
NJU7004M-TE1 NJU7004M-TE1		SOP	08+	The EM785840 series are 8-bit RISC type m
NJU7004V NJU7004V	JRC	STK	2005+
NJU7004V(TE1) NJU7004V(TE1)				Outputs of the analog signal ground voltage. SGT
NJU7004V-TE1 NJU7004V-TE1	JRC		0809+	Description These displays have a 32.9 mm (1.3
NJU7006 NJU7006	JRC		07+	Lead Temperature (soldering, 10s)+260C (1) Stre
NJU7006F NJU7006F				in the modem is the best in its class. With a lo
NJU7006F-TE1 NJU7006F-TE1	JRC		07+	The TLV2252 and TLV2254 are dual and quadruple
NJU7006F-TE1-ZZZB NJU7006F-TE1-ZZZB	JRC		0809+	• 2nd generation HOTLink® technology &
NJU7007 NJU7007	JRC		07+	Channel monitor Simultaneous output update via
NJU7007F3-TE1 NJU7007F3-TE1				In the test mode, the normal operation of the SC
NJU7007F3-TE1-ZZZB NJU7007F3-TE1-ZZZB	JRC		0809+
NJU7008 NJU7008	JRC		07+	The ESR of the required capacitor must be less t
NJU7008F2-TE1 NJU7008F2-TE1	N/A			For more information on the PWP package,
NJU7008F3 NJU7008F3	JRC	SOT-353		In the MEI scheme, all MEI compatible CPEs must
NJU7008F3-TE1 NJU7008F3-TE1	JRC		0809+	State-of-the-Art BiCMOS Design Significantly Red
NJU701 NJU701
NJU7011 NJU7011	JRC		07+	Freescale Semiconductor reserves the right to ma
NJU7011F NJU7011F				The HYM72V64636B(L)T8 Series are 64Mx64bits Synch
NJU7011F(TE1) NJU7011F(TE1)	JRC		2005PB	Wide gain bandwidth: 1.3MHz Large voltage gain:
NJU7011F-TE1 NJU7011F-TE1	JRC	SOT153-A42B	04+	• 1.8V/2.5V +0.1V/-0.1V Power Supply. R
NJU7011F-TE2 NJU7011F-TE2	JRC		99+	I/O2 bit toggling. Please see status bit table f
NJU7011V-TE2 NJU7011V-TE2	JRC			(6) When designing your equipment, comply with t
NJU7012 NJU7012	JRC		07+	2. TVS devices are normally selected according t
NJU7012F NJU7012F	JRC	SOT-153	05+
NJU7012F/A872 NJU7012F/A872	JRC			This series of hermetically packaged products fe
NJU7012FTE1 NJU7012FTE1				Bias voltage generator Ground connection, Connec
NJU7012F-TE1 NJU7012F-TE1	JRC	SOT25	6+	Low Power Consumption Industry Standard Size In
NJU7012F-TE1-ZZZB NJU7012F-TE1-ZZZB	JRC		0809+	Temperature :stg max Test duration : 1000h Tem
NJU7012F-TE2 NJU7012F-TE2	JRC	SOT23-5P/REEL	04+	devastating effect is that, in the smaller cryst
NJU7012F-TEI NJU7012F-TEI	JRC			Figure 2 shows the typical Insertion Loss graphs
NJU7013 NJU7013	JRC		07+	The chip is built around an ARM946ES RISC proces
NJU7013F NJU7013F	JRC	SOT-153	05+	† Stresses beyond those listed under absol
NJU7014 NJU7014	JRC		07+	The PD# signal is used to bring all clocks to a
NJU7014D NJU7014D				Note : 1. * : These pins are not used in this mo
NJU7014M NJU7014M
NJU7014M-TE1-ZZZB NJU7014M-TE1-ZZZB	JRC		0809+	Data input from Serial Bus Ring Indicator, activ
NJU7014R NJU7014R	JRC			Designed for PCN and PCS base station appl
NJU7014R(TE1) NJU7014R(TE1)	JRC	04+	MSOP	The 1N5333-5388B JEDEC registered series of axial
NJU7014RB1 NJU7014RB1	JRC	TSOP-8	03+	Parameter VDD to GND VOUTA, VOUTB, VBZ to GND
NJU7014RB1(TE1) NJU7014RB1(TE1)	JRC		SOP	It is important that the logic used to tu
NJU7014RB1-(TE1) NJU7014RB1-(TE1)				The Microwire interface allows several devices t
NJU7014R-TE2 NJU7014R-TE2	JRC		01/P4	The W83877TF provides two high-speed serial commu
NJU7015 NJU7015	JRC		07+	The Asynchronous mode is used for communication
NJU7015D NJU7015D				1.00(31.75mm) PCB Height One Row of SDRAMs on SO
NJU7015M NJU7015M	JRC		0809+	VSS for PLL Analog Register Pin for VCO Gain VD
NJU7015R NJU7015R	JRC		0809+	The 32 registered macrocells in the GLB are driv
NJU7015R(TE2) NJU7015R(TE2)	JRC	TSSOP-8	2005	An overrun character is placed in the HT82K628A b
NJU7015R-TE1 NJU7015R-TE1	JRC	04+	SOP	Notes: 1. Unless noted otherwise, all specificat
NJU7015R-TE1-ZZZB NJU7015R-TE1-ZZZB	JRC		0809+	Hynix HYMD232646(L)8-K/H/L series is unbuffered 1
NJU7015V NJU7015V				1. Torque rating applies with use of compression
NJU7015V(TE1) NJU7015V(TE1)				C Caches are physically addressed, implem
NJU7016 NJU7016	JRC		07+	This noise blanker integrated circuit con
NJU7016D NJU7016D				Absolute Maximum Ratings indicate limits beyond
NJU7016M NJU7016M	JRC		00+	The MSM518221's function is simple, and similar t
NJU7016M(TE1) NJU7016M(TE1)				• Pout>18W, çT>20% @ VDD=12.5
NJU7016R NJU7016R	JRC	SMD	2000	STATIC ELECTRICAL CHARACTERISTICS Characteristic
NJU7016R(TE1) NJU7016R(TE1)	JRC		0809+	The FM25L16 provides substantial benefits to use
NJU7016V NJU7016V				The LVT16543 and LVTH16543 16-bit transceivers
NJU7016V(TE1) NJU7016V(TE1)	JRC	TSSOP	2004	NOTE: EP circuits are designed to meet the DC sp
NJU7016V-TE1 NJU7016V-TE1	JRC		00+	selectable genuine 10-bit A/D converter with 8
NJU7016V-TE1-ZZZB NJU7016V-TE1-ZZZB	JRC		0809+	14-bit resolution with no missing codes Through
NJU7017 NJU7017	JRC		07+	During the SELF REFRESH operation, the row addre
NJU7017F-TE1 NJU7017F-TE1	JRC		0809+	Ro mismatch between A & B Change in \|Vod\| b
NJU7017F-TE1/ NJU7017F-TE1/				The DS1642 is a 2K x 8 nonvolatile static RAM and
NJU7018 NJU7018	JRC		07+	Both 8-pin DIP and SOIC packages are available i
NJU70180R NJU70180R	JRC	SOP	01+	Command Buffer - The command buffer stores up to
NJU7018M NJU7018M	JRC		01	Floppy Disk Available on Parallel Port Pins Enha
NJU7018M(TE1) NJU7018M(TE1)				Note 11: Two on-chip diodes are tied to each anal
NJU7018R NJU7018R	JRC		03+	NOTES: 1. Dimensions are in inches.
NJU7018R(TE1) NJU7018R(TE1)	JRC	SSOP	2003	The VHC164 is an advanced high-speed CMOS device
NJU7018R-TE1 NJU7018R-TE1	JRC		02	If more than one binary input bit is high, the r
NJU7018V(TE1) NJU7018V(TE1)	JRC	02+	MSOP	For example, S/H1 should not be commanded into t
NJU7018V-TE1 NJU7018V-TE1	JRC	TSSOP	06+	The control register sets the mode and signal di
NJU7019 NJU7019	JRC		07+	1. Ultra-low current consumption 2. Low operatin
NJU7021 NJU7021	JRC		07+	The VSP2272 device is a complete mixed-signal p
NJU7021D NJU7021D	JRC		0809+	The output voltage transient comparators provide
NJU7021M NJU7021M	JRC	STK	2005+	DESIGN CHANGES: ProTek reserves the right to dis
NJU7021M-TE1 NJU7021M-TE1	JRC		0809+	The information provided herein is believed to b
NJU7021V NJU7021V				Call Progress Monitor and Group Listening - Adju
NJU7021V-TE1 NJU7021V-TE1	JRC		0809+	Automatically Wakes Up, Measures Temperature and
NJU7022 NJU7022	JRC		07+	The Am29F032B is a 32 Mbit, 5.0 volt-only Flash
NJU7022D NJU7022D	JRC		0809+	1. Reset Consideration The Reset pin should neve
NJU7022M NJU7022M	JRC		97	The layout of Figure 6 shows two 0.1µF dec
NJU7022M(TE1) NJU7022M(TE1)				LP PACKAGE: Thermal Resistance-Junction
NJU7022M(TE2) NJU7022M(TE2)				8-bit A/D Converter (ADC) with 8 channels Fully
NJU7022M(TE3) NJU7022M(TE3)	JRC	SOP-8	2000+/	The sequence of the burst counter is determined b
NJU7022M-T1 NJU7022M-T1	JRC		08+	This IC was developed as an interface IC for vide
NJU7022M-TE1 NJU7022M-TE1	JRC		0809+	In EDO page mode read cycle, the data-out is hel
NJU7024 NJU7024	JRC	SMD	SMD	An attenuator from the CONOUT (control output) to
NJU7024D NJU7024D	NJRC			Designed to enable the engineer to program
NJU7024M NJU7024M	JRC		97+	The Fairchild Semiconductors RMLA3565C is a sing
NJU7024M(T2) NJU7024M(T2)	JRC	05+	SOP	Celeritek reserves the right to make changes wit
NJU7024V NJU7024V	JRC		03+	PCI Controller Compatible with PCI 2.1 specific
NJU7024V(TE2) NJU7024V(TE2)				Information For further information on technolog
NJU7031 NJU7031	JRC		0809+	The ICS950703 is part of a whole new line of ICS
NJU7031D NJU7031D	JRC		0809+	MBF2 is set LOW by a LOW-to-HIGH transition of CL
NJU7031M NJU7031M				Note 5: For IOS, the use of high-speed test appar
NJU7031M(TE1) NJU7031M(TE1)	JRC		94+	Description 7.6 mm Common Anode Right Ha
NJU7031M-TE1 NJU7031M-TE1	JRC		0809+	Hynix HYMD132645A(L)8-K/H/L series is unbuffered
NJU7031V NJU7031V				Fast transient response Input voltage range: VI
NJU-7031V NJU-7031V	JRC			The ISL84521/ISL84522/ISL84523 are quad single-p
NJU7031V(TE1) NJU7031V(TE1)	JRC	TSSOP-8	2004	The SN74AUP1G57 features configurable multiple f
NJU7031V-TE1 NJU7031V-TE1	JRC		0809+	Intended compliance for future Revision 2.2 6
NJU7032 NJU7032	JRC		07+	BVDSSDrain-to-Source Breakdown Voltage-100 W
NJU7032D NJU7032D	JRC		0809+	INTERFACE COMMUNICATION: The IC pin determines wh
NJU7032FB NJU7032FB				5 VDC Stanby:70mA, Transmit:<80mA A linear
NJU7032M NJU7032M	JRC	SMD	1995	The OPA688 is a wideband, unity gain stable volt
NJU7032M(ICL762.TLC272.LMC662) NJU7032M(ICL762.TLC272.LMC662)				The device is available with an access time of 5
NJU7032M(T1) NJU7032M(T1)				The STTH2R06 is using ST Turbo 2 600V planar Pt
NJU7032M(TE1) NJU7032M(TE1)	JRC	07+
NJU7032M(TE3) NJU7032M(TE3)	JRC	N/A	00+	Novel current mode design Virtual gr
NJU7032M-T1 NJU7032M-T1	JRC	SOP36		In addition, the ADSP-TS202S processor supports
NJU7032M-TE1 NJU7032M-TE1	JRC		0809+	Amplifier A4 is an astable multivibrator generati
NJU7032M-TE2 NJU7032M-TE2	JRC		0809+	Blocks A and B typically have an open loop voltag
NJU7032MTE3 NJU7032MTE3				The Hitachi HN27C101AG/HN27C301AG is a 1-Mbit ul
NJU7032MX NJU7032MX				It is recommended that tantalum capacitors have
NJU7032X NJU7032X	JRC		96+	This Infineon module family are industry standar
NJU7034 NJU7034	JRC	SMD	SMD	Function Q Baseband Input Filter Pins. Connect
NJU7034D NJU7034D	JRC		0809+	FEATURES High breakdown voltage (BVCEO 5
NJU7034M NJU7034M	JRC		0809+	board, minimum creepage and clearance requiremen
NJU7034M(T1) NJU7034M(T1)	JRC	01+	SOP
NJU7034M-TE1 NJU7034M-TE1	JRC	02+	SOP/14
NJU7034V NJU7034V	JRC		03+	The XC7336 has a multibit security system that c
NJU7034V(TE1) NJU7034V(TE1)	JRC	SSOP	0510+	transmission line with other RS-232 devices whi
NJU7034V-TE1 NJU7034V-TE1	JRC	SSOP14		Receive Clock Tri-statable. The falling edge of t
NJU7034V-TE1-ZZZB NJU7034V-TE1-ZZZB	JRC		0809+	Notes: 1. Dominant Wavelength, ëd, is deriv
NJU7040 NJU7040				Schottky barrier diodes are having large-r
NJU7040F NJU7040F	JRC			The CAN driver IC B10011S is a low-speed, high-l
NJU7042 NJU7042	JRC		07+	Turn-On Time: The converter typically produces a
NJU7042F NJU7042F	JRC	5	SOT23-5	The LOOP feature can also be used in application
NJU7042F-TE1 NJU7042F-TE1	JRC	SOT23-5	0202+	Three-channel DMA controller 512-byte data DMA F
NJU7043 NJU7043	JRC		07+	The AD5379 contains 40, 14-bit DACs in one CSPBG
NJU7043D NJU7043D	JRC		0809+	DATEL offers two standard heat sinks that can be
NJU7043M NJU7043M	JRC		0809+	Besides replacing fixed regulators, the LM117 is
NJU7043M(TE1) NJU7043M(TE1)	JRC	SOP	2003	The set/reset line (SR) is an asynchronous activ
NJU7043M-TE1 NJU7043M-TE1	JRC	SMD-8	03+	The state machine watches for transitions on RO.
NJU7043RB1 NJU7043RB1				The MAX1540/MAX1541 dual pulse-width modulation
NJU7043RB1-TE1 NJU7043RB1-TE1	JRC		0809+	Note 4: For a power supply of 5V r10% the worst
NJU7043V-TE1 NJU7043V-TE1	JRC		0809+	The TOSHIBA products listed in this docume
NJU7051 NJU7051	JRC		07+	Margin Down: When this input is asserted to GND,
NJU7051D NJU7051D				TransceiversClowering overall system interoperab
NJU7051M NJU7051M				The NJU7051M is a multi band RF mixer oscillator
NJU7052 NJU7052	JRC		07+	The MPX5050 pressure sensor is available
NJU7052M NJU7052M	JRC		0809+	Pins 3 & 7 connected See application schemat
NJU7052M-TE1 NJU7052M-TE1	JRC	SOP		The Design Browser allows users to select and im
NJU7054 NJU7054	JRC	SOP	00+	NOTES: • Use a 0.1 µF capacitor on V
NJU7054D NJU7054D				Positive And Negative Regulators In One Package
NJU7054M NJU7054M	JRC	SOP	95.96+	Synchronous Clock Enable Input. When CEN is sampl
NJU7054M-TE1 NJU7054M-TE1	JRC	SOP-14	N/A	Notes : 1. In-Band EI 115.2 kb/s and FIR_SEL
NJU7061 NJU7061	JRC		07+	NOTES: (1) Stresses above these ratings may caus
NJU7061D NJU7061D				The HYM75V32M636(L)T6 Series are 32Mx64bits Synch
NJU7062 NJU7062	JRC		07+	The 89CNQ...A center tap Schottky rectifier modul
NJU7062D NJU7062D				These edge-triggered multivibrators feature outp
NJU7062M NJU7062M				SCLK is the clock for the SD serial bus.The data
NJU7062M(TE1) NJU7062M(TE1)	JRC		2000	The interrupt request output is an open drain, a
NJU7062M-TE1 NJU7062M-TE1	JRC	SOP/8	99+	Contents in this document are subject to change w
NJU7064 NJU7064	JRC		07+	n Deserializes one to six Bus LVDS input serial
NJU7064D NJU7064D	JRC		0809+	<Common> • Operating Temperature :
NJU7064M NJU7064M	JRC		03+	- Address Input - Data Input/Outputs - Inter
NJU7064V NJU7064V	JRC	TSSOP-14	03+	The MAX3873A is implemented in Maxim's second-gen
NJU7064V(TE1) NJU7064V(TE1)	JRC	TSSOP14	05+	The power MOSFET outputs of these devices are si
NJU7071 NJU7071	JRC		07+	The SC5388 is a 2-channel digital preset
NJU7071D NJU7071D	JRC		0809+	400 x 300 pixels resolution 8um x 8um square pix
NJU7072 NJU7072	JRC		07+	The I/O expanders eight quasi bidirectional data
NJU7072D NJU7072D				Various performance features exist between the t
NJU7072M NJU7072M				1. High-performance CPU The ML66525 fami
NJU7074 NJU7074	JRC		07+	1. When UB and LB are in select mode (low), I/O 0
NJU7074D NJU7074D				−I2S, Left, Right Justified or DSP −
NJU7074M NJU7074M				The MLX90247DSG sensor IC is integrated togethe
NJU7074M(TE1) NJU7074M(TE1)				Enhanced Parallel Port (EPP) Compatible - EPP
NJU7081 NJU7081				The DS1258W executes a read cycle whenever WE (Wr
NJU7081R NJU7081R	JRC		05/06+	UL recognition2500 Vrms for 1 minute per U
NJU7081R-TE1 NJU7081R-TE1	JRC	03+	MSOP/8	These octal buffers and line drivers are designe
NJU-7081V NJU-7081V	JRC			Buffer addressing is referenced in the datasheet
NJU7081V-TE1 NJU7081V-TE1	JRC	98+	SSOP-8/TO.23	Data of C1 , C2 and C3 code bit become 1
NJU7082B NJU7082B				On-chip ROM is available in a PROM (ZTAT™
NJU7082BM NJU7082BM	JRC		06/07+
NJU7082BM(TE1) NJU7082BM(TE1)				NOTE: 1. Stresses greater than those listed und
NJU7082BM(TE2) NJU7082BM(TE2)				This signal is asserted to indicate either 0 or
NJU7082BM-TE1 NJU7082BM-TE1	JRC		0809+	3. Hitachi makes every attempt to ensure that it
NJU7082BM-TE1-ZZZB NJU7082BM-TE1-ZZZB	JRC		06+	NOTES: 1. The device may be operated outside rec
NJU7082BU NJU7082BU	JRC	N/A	N/A	Differential inputs Near zero pop & click 1
NJU7082BV NJU7082BV	JRC	05+	TSSOP	The C0 input controls the pinout configuration o
NJU7082BV(TE1) NJU7082BV(TE1)				An HR700 Series converter in still air (other th
NJU7082BV-TE1 NJU7082BV-TE1	JRC		0809+	Note 9: This parameter is guaranteed by design bu
NJU7082BV-TE2 NJU7082BV-TE2	JRC	TSSOP	00+	The TPS6021x charge pumps provide a regulated 3.
NJU7091A NJU7091A				Stresses beyond those listed under absolute maxi
NJU7091AFTE1 NJU7091AFTE1				The interconnect structure (GRP) is very similar
NJU7091AF-TE1 NJU7091AF-TE1				Fabricated in high-density CMOS with 5V-tolerant
NJU7091AF-TE1/A282 NJU7091AF-TE1/A282	JRC			Parameter VDD to GND VA, VB, VW to GND PU, PD,
NJU7091AF-TE1-ZZZB NJU7091AF-TE1-ZZZB	JRC		0809+	† Stresses beyond those listed under absol
NJU7092A NJU7092A				Supports LVCMOS Switching Levels on the Control
NJU7092AF-TE1 NJU7092AF-TE1	JRC	SOT25	00+	A fast, high precision differential input stage
NJU7092F-TE1 NJU7092F-TE1				Oscillator Master Clock (CMOS Output). For cryst
NJU7093 NJU7093	JRC	SOP	98+	The 1.8 Volt Intel® Wireless Flash Memory (w
NJU7093A NJU7093A				The NJU7093AA is a three-stage UHF amplifier mod
NJU7093AF NJU7093AF	JRC	153		Clocking is accomplished by a low-to-high transi
NJU7093AF/AA22 NJU7093AF/AA22				Notes: 1. The algebraic convention, where most
NJU7093AF-TE1 NJU7093AF-TE1	JRC	SOT363	2003	The A1425 ac-coupled Hall-effect sensor is a mon
NJU7093F NJU7093F	JRC	SOT-8	C919	MATERIAL: Units are encapsulated in a low
NJU7093F/ NJU7093F/
NJU7093F/L805 NJU7093F/L805	JRC
NJU7093F-TE1 NJU7093F-TE1	JRC	2004	SOT23-5	These octal bus transceivers are designed for as
NJU7094 NJU7094	JRC		07+	+3 Volt single power supply Low power CMOS desig
NJU7094D NJU7094D				Note 3: When the input voltage at any pin exceeds
NJU7094M NJU7094M
NJU7094R NJU7094R	JRC	39845	SSOP-8	cleared immediately, and remains cleared. If the
NJU7094R(TE1) NJU7094R(TE1)	JRC	SSOP-8	02/01	The ADC122S051 is a low-power, two-channel CMOS
NJU7094RB1-TE1 NJU7094RB1-TE1	JRC	07+	SOP-8	Hynix HYMD232M646(L)8-K/H/L series is unbuffered
NJU7094R-TE1 NJU7094R-TE1				Output skew with respect to the REF input
NJU7094V-TE1 NJU7094V-TE1				Output Enable, asynchronous input, active LOW. C
NJU7095 NJU7095	JRC		07+	FEATURES • Normally Open, Single Pole Sing
NJU7095D NJU7095D				Serializer/Deserializer Independent Channel Oper
NJU7095M NJU7095M				At turn-on, the external gate capacitor of the N-
NJU7095RB1-TE1 NJU7095RB1-TE1				Note 3: Internal thermal shutdown circuitry prote
NJU7095R-TE1 NJU7095R-TE1				A CommandUser Interface (CUI) serves as the inte
NJU7095V-TE1 NJU7095V-TE1				Out (pin 7) This is the main timing chain
NJU7096 NJU7096	JRC		07+	Command Structure There are six commands called
NJU7096D NJU7096D				The TC54 Series are CMOS voltage detector
NJU7096M NJU7096M				The ADC08D1500 is a dual, low power, high perfor
NJU7096RB1-TE1 NJU7096RB1-TE1				DRAM Interface • 2-bank individual contro
NJU7096R-TE1 NJU7096R-TE1				Bay Linear products are not authorized for and s
NJU7096V-TE2 NJU7096V-TE2				Base Stations: Single/Multicarrier UMTS, CDMA, GS
NJU7102A NJU7102A				Measurement includes the recommended inter
NJU7102AD NJU7102AD	JRC		0809+	Interrupt Controller C Interrupt control module
NJU7102AM NJU7102AM	JRC		03+	involves the following phases : PHASE 0:
NJU7102AM-TE1 NJU7102AM-TE1	JRC		0809+	The temperature is measured by a diffused
NJU7104A NJU7104A				Collector-to-Emitter Voltage Continuous Collec
NJU7104AD NJU7104AD				Note : Permanent device damage may occur if ABSOL
NJU7104AM NJU7104AM	JRC	SOP14L	1995+	The M59PW064 is a 64Mbit (4Mbx16), Mask- ROM pi
NJU7104AN NJU7104AN				The BG-LEDs are packed in cardboard boxes after p
NJU7104D NJU7104D	JRC	DIP	06+	The 5 and 12 volt output models provide full pow
NJU7106BD NJU7106BD	INTERSIL		04+	The HC4066 and CD74HCT4066 contain four independ
NJU7108 NJU7108				The XP152A01D8MR is a P-Channel Power MOS FET wi
NJU7108F2-TE1 NJU7108F2-TE1	JRC		03+	The KM4110 offers superior dynamic performance
NJU7108F3 NJU7108F3	JRC	SOT-353	05+	Enhanced N channel FET with no inherent diode to
NJU7108F3-TE1 NJU7108F3-TE1	JRC	SOT-135	08+	C Rapidly access Flash memory with BDMA for &nb
NJU7108F3-TE1-ZZZB NJU7108F3-TE1-ZZZB	JRC		0809+	The IC41C1665 and the IC41LV1665 have two CAS co
NJU7112A NJU7112A				Updated part listing on first page and in Table
NJU7112AM NJU7112AM	JRC		95	3. Multiple-Message Playback, Sequential Control
NJU7112AM-TE1-ZZZB NJU7112AM-TE1-ZZZB	JRC		0809+
NJU7114 NJU7114	JRC	SOP	03/+04+	The 74LVC(H)32244A is a high-performance, low-po
NJU7114A NJU7114A	JRC			All 32 bits of the MPC555 data bus are available
NJU7114AD NJU7114AD	JRC	DIP	2001	The PWR_DWN# signal is an asynchronous, active-lo
NJU7114AM NJU7114AM	JRC		03+
NJU7114AM-TE1 NJU7114AM-TE1	JRC	99+	SOP/14	• Four Crystal modes, up to 40 MHz •
NJU7116 NJU7116				NOTES: 1. Stresses beyond those listed under ab
NJU7116F NJU7116F	JRC	SOT-153	05+	The Hyundai HYM72V32736AT8 Series are Dual
NJU7116F-TE1 NJU7116F-TE1	JRC		05+	(a) For a dual device surface mounted on 8 sq cm
NJU7116F-TE1-ZZZB NJU7116F-TE1-ZZZB	JRC		0809+	Offered in 128Mx8bit the K9F1G08X0A is 1G bit wit
NJU7116F-TE2 NJU7116F-TE2	JRC	07+/08+		DESCRIPTION The IS66_ series are
NJU7116F-TE2-ZZZB NJU7116F-TE2-ZZZB	JRC		0809+	SUMMARY DESCRIPTION The M29W400B is a 4 Mbit (5
NJU7118 NJU7118				DESCRIPTION The RA07N3340M is a 7.5-watt
NJU7118F2 NJU7118F2				The selection of the reference crystal frequency
NJU7118F3 NJU7118F3				Under and over temperature alert thresholds can
NJU7118F3-TE1 NJU7118F3-TE1	JRC	2004	SOT-5	1. H = HIGH voltage level L = LOW voltag
NJU7141 NJU7141	JRC	SOP	04+	The oscillator uses an external, low-cost 32.768
NJU7141F-TE1 NJU7141F-TE1	JRC	SOT363	2003	The CMPIN pin drives two data slicers, which conv
NJU7200 NJU7200				NOTES: 1. WE is high in read Cycle. 2. Device i
NJU7200L33 NJU7200L33				- Output voltage: 3.3V, 5V, 12V and adjustable &
NJU7200L33-T3 NJU7200L33-T3	JRC		03+	NOTES 1Stresses above those listed under Absolut
NJU7200L55 NJU7200L55				A: The value of R JA is measured with the device
NJU7200U15-TE1 NJU7200U15-TE1	JRC		00+	• Instruction set designed for high level
NJU7200U21-TE1 NJU7200U21-TE1	JRC		00+	MAX6323_UT__-T -40C to +125C 6 SOT23-6 Pus
NJU7200U25-TE1 NJU7200U25-TE1	JRC		00+	After the CMX866 has been successfully powered up
NJU7200U25-TE1/25H NJU7200U25-TE1/25H	JRC			These devices contain up to 22 inputs and 10 out
NJU7200U26-TE1 NJU7200U26-TE1	JRC		00+	PRELIMINARY INFORMATION describes products that a
NJU7200U27-TE1 NJU7200U27-TE1	JRC		00+
NJU7200U29-TE1 NJU7200U29-TE1	JRC		00+	The NJU7200U29-TE1 is a triple inverter from Fai
NJU7200U30 NJU7200U30				FUNCTION The M63800FP has seven circuits, which
NJU7200U30-TE1 NJU7200U30-TE1	JRC		00+	Note 2: The Absolute Maximum Ratings are those va
NJU7200U32-TE1 NJU7200U32-TE1	JRC		00+	True remote load sensing it is not possible to p
NJU7200U33 NJU7200U33	JRC	SOT-89	05+	There are two alternatives to set the boot block.
NJU7200U33TE1 NJU7200U33TE1	jrc	jrc	dc01	Notes: 6. Test conditions assume signal t
NJU7200U33-TE1 NJU7200U33-TE1	JRC	SOT-89	05+	The MAX196/MAX198 multirange, 12-bit data-acquisi
NJU7200U35 NJU7200U35	JRC	SOT-89	05+	Gate-to-Source Forward Leakage Gate-to-Source
NJU7200U35-TE1 NJU7200U35-TE1	JRC		00+	With performance of up to 900 million floating-p
NJU7200U40 NJU7200U40	JRC	SOT-89	04+	The ADM666A contains on-chip circuitry for low p
NJU7200U40-TE1 NJU7200U40-TE1	JRC		00+	Protection is guaranteed in terms of short-circu
NJU7200U40-TE2 NJU7200U40-TE2	JRC	SOT-89	04+	The HYM72V64C756T8 Series are gold plated socket
NJU7200U45-TE1 NJU7200U45-TE1	JRC		00+	CMOS Technology Low Power Consumption 4-Bit or
NJU7200U48-TE1 NJU7200U48-TE1	JRC		00+	*Stresses above those listed under Absolute Maxi
NJU7200U50-TE1 NJU7200U50-TE1	JRC		00+	The Am79C987 Hardware Implemented Management In
NJU7200U50-TE1-ZZZB NJU7200U50-TE1-ZZZB	JRC		0809+	Fully Compliant with Ultra3 SCSI Provides Multim
NJU7200U52-TE1 NJU7200U52-TE1	JRC	SOT-89	06+	(1) Stresses beyond those listed under absolute
NJU7200UXX-TE1-ZZZB NJU7200UXX-TE1-ZZZB	JRC		0809+	ISO256 is a precision three-port isolation opera
NJU7201 NJU7201				The NCP1575 is a low voltage buck control
NJU7201L12 NJU7201L12	jrc	jrc	dc90	Chip Select: Enables or disables all inputs excep
NJU7201L2-32 NJU7201L2-32				The RC32355 includes a configurable ATM S
NJU7201L30 NJU7201L30	JRC		袋TO-92	− Dynamic Range: 113 dB −
NJU7201L32 NJU7201L32				* High performance CMOS technology. * Rhythm win
NJU7201L32T3 NJU7201L32T3				The IRU1050 is a low dropout three-terminal adjus
NJU7201L40 NJU7201L40	JRC		排TO-92	Specifications are production tested at TA =25C.
NJU7201L45 NJU7201L45	JRC		排TO-92	STATIC ELECTRICAL CHARACTERISTICS Characteristic
NJU7201L50 NJU7201L50	JRC		05+	A token-passing protocol provides predictable res
NJU7201L50-T1 NJU7201L50-T1	JRC	TO92	01+	C1 is the transfer capacitor and C2 stores energy
NJU7201L55 NJU7201L55	JRC	TO-92		The HY51V(S)16163HG/HGL is the new generation dyn
NJU7201LXX-ZZZD NJU7201LXX-ZZZD				MIC1 or Line1 Analog Input (Left Minus or Multifu
NJU7201U12 NJU7201U12	JRC	SOT223		The circuit diagram used in the temperature disp
NJU7201U12-TE1 NJU7201U12-TE1	JRC		00+	POWER-ON INITIALIZATION When power is first app
NJU7201U12-TE1-ZZZB NJU7201U12-TE1-ZZZB	JRC		0809+	The IRSF3021 Lamp and DC motor driver is a fully
NJU7201U15 NJU7201U15	JRC	SOT-89	05+
NJU7201U15-TE1 NJU7201U15-TE1	JRC		00+	The DDX-2100 surface mount package includes an e
NJU7201U15-TE1/15A NJU7201U15-TE1/15A				Wide Operating Voltage Range of 2 V to 6 V Outpu
NJU7201U15-TE1-ZZZB NJU7201U15-TE1-ZZZB	JRC		0809+	Hynix HYMD564646(L)8-K/H/L series is designed for
NJU7201U25 NJU7201U25	JRC	SOT-89	05+	The standard MBM29DL16XTE/BE offer access times
NJU7201U25-TE1 NJU7201U25-TE1	JRC		00+	The GF9102A is a linear phase FIR digital filter
NJU7201U25-TE1-ZZZB NJU7201U25-TE1-ZZZB	JRC		0809+	• HiPerFETTM technology - low RDSon
NJU7201U27 NJU7201U27	JRC		99+	The MAU100 series has limitation of maxim
NJU7201U27-TE1 NJU7201U27-TE1	JRC		00+	SMBJ5V0(C)A SMBJ6V0(C)A SMBJ6V5(C)A SMBJ7V0(C)
NJU7201U30 NJU7201U30	JRC		0809+	The wide input voltage range of 20V down to as l
NJU7201U30TE1 NJU7201U30TE1				10-bit ADC -1LSB INL; No Missing Codes -Progra
NJU7201U30-TE1 NJU7201U30-TE1	JRC	SOT	07+	FEATURES • Four 8-Bit DACS Differ
NJU7201U30-TE104 NJU7201U30-TE104	JRC		06/07+	With a dual supply voltage (e.g., 15V) the exter
NJU7201U30-TE1-ZZZB NJU7201U30-TE1-ZZZB	JRC		0809+	1 A critical component is a component used in a l
NJU7201U32 NJU7201U32	JRC	SOT-89	05+	The standard device offers access times of 70, 9
NJU7201U32-TE1 NJU7201U32-TE1	JRC	04+	SOP
NJU7201U32-TE1(32A) NJU7201U32-TE1(32A)				Two data pointers 3.3-volt operation Sma
NJU7201U35 NJU7201U35	NJRC		07/08++	IF input frequency at IFInP, IFInM is 130 MHz. I
NJU7201U35(TE1) NJU7201U35(TE1)				• Inductance range: 1.5-680nH (E-12 Series)
NJU7201U35-TE1 NJU7201U35-TE1	JRC		00+	† Stresses beyond those listed under absol
NJU7201U35-TE1-ZZZB NJU7201U35-TE1-ZZZB	JRC		0809+
NJU7201U40 NJU7201U40	JRC	SOT-89	05+	This advanced power MOSFET is designed, tested,
NJU7201U40-TE1 NJU7201U40-TE1	JRC	SOT89-40A		IL5 through IL0 are available on the TP3070. IL
NJU7201U45-TE1 NJU7201U45-TE1	JRC		00+	• 3V input produces approx. 5V unregulated
NJU7201U50 NJU7201U50	JRC			DATEL offers two standard heat sinks that can be
NJU7201U50(TE1) NJU7201U50(TE1)				The Data Input/Output mask places the DQ buffers
NJU7201U50TE1 NJU7201U50TE1				Note 1: Absolute Maximum Ratings indicate limits
NJU7201U50-TE1 NJU7201U50-TE1	JRC	SOT-89		For improved FM performance, an integrated IF fi
NJU7201U50-TE1/50A NJU7201U50-TE1/50A	JRC	SOT-89		Voltage as Low as 2.7 V Replaces Mechanical Ther
NJU7201U50-TE104 NJU7201U50-TE104	JRC		06/07+	Notes: 1) Current CEPT/ETSI regulations: CEPT RE
NJU7201U50-TE1-ZZZB NJU7201U50-TE1-ZZZB	JRC		0809+	2. A variety of power saving modes Attach
NJU7201U52 NJU7201U52	JRC	SOT-89	05+	Cathode Voltage Continuous Cathode Current Po
NJU7201U52-TE1 NJU7201U52-TE1				6. Maximum package power dissipation limits must
NJU7201U55-TE1 NJU7201U55-TE1	JRC	04+	SOT89	These surface mount Transient Voltage Suppressors
NJU7201UXX-TE1-ZZZB NJU7201UXX-TE1-ZZZB	JRC		0809+	The ADSP-21365/6 includes an on-chip instruction
NJU7202 NJU7202	JRC	TO-92		Complete Development Tools ❐ Free
NJU7202L33 NJU7202L33	NJRC		04+	These display devices are designed to provide
NJU7202U30-TE1 NJU7202U30-TE1	JRC		00+	The CS4344 family is based on a fourth order mult
NJU7202U33 NJU7202U33	JRC	SOT-89	04+	and PCN system , receive path Usable passband:
NJU7202U33-TE1 NJU7202U33-TE1	JRC	SOT-89		An on-chip Peripheral Data Controller (PDC) tran
NJU7202U33-TEI NJU7202U33-TEI				These dual P-Channel logic level enhancement mode
NJU7202U50/50B NJU7202U50/50B	JRC			The LS323 contains eight edge-triggered D-type f
NJU7202U50-TE1 NJU7202U50-TE1				Received Data Output, push-pull CMOS driver
NJU7202UXX-TE1-ZZZB NJU7202UXX-TE1-ZZZB	JRC		0809+	The HSDL-1100 contains a high speed, high effi
NJU7211 NJU7211				• 0.17 µm Process Technology •
NJU7211L30 NJU7211L30				The ENDEC (Encoder Decoder) unit is the interfac
NJU7211L50 NJU7211L50				If any input pin (S1, S0, DATA, or CLK) i
NJU7211U20 NJU7211U20	JRC	SOT-89	05+	NOTES 1Oversampling disabled. Static DAC perform
NJU7211U20-TE1 NJU7211U20-TE1	JRC	SOT89	0309+	Note 2: The algebraic convention, where the most
NJU7211U20-TEI NJU7211U20-TEI	JRC			An example of this situation is a power op amp c
NJU7211U30 NJU7211U30	JRC	SOT-89	05+	5. Luminance system After generating the
NJU7211U30-TE1 NJU7211U30-TE1	JRC		1650	The operation mode of the M5M51016B series are d
NJU7211U30-TE1/30C NJU7211U30-TE1/30C	JRC	SOT-89		• 64-bit Password Security • One Arr
NJU7211U40 NJU7211U40	JRC		1450	Very low power operation - typ 3.0mW Single cel
NJU7211U40-TE1 NJU7211U40-TE1	JRC/99+	N/A	99	Normally, the B port operates at GTLP signal lev
NJU7211U50 NJU7211U50	JRC	SOT-89		The error signal from the optocoupler is fed int
NJU7211U50-TE1 NJU7211U50-TE1	JRC		08+
NJU7211U50-TE1-ZZZB NJU7211U50-TE1-ZZZB	JRC		0809+	Fast, high-density Field-Programmable Gate Array
NJU7211UXX-TE1-ZZZB NJU7211UXX-TE1-ZZZB	JRC		0809+	* All specs and applications shown above subject
NJU7221U12-TE1 NJU7221U12-TE1	JRC		00+	The CY7C1350G is a 3.3V, 128K x 36 synchronous-pi
NJU7221U15-TE1 NJU7221U15-TE1	JRC		00+	CLKDs output originates from the cross point swit
NJU7221U19-TE1 NJU7221U19-TE1	JRC		00+	I , Q = 1 Vp-p implies that themagnitude of the
NJU7221U20-TE1 NJU7221U20-TE1	JRC		00+	This device contains circuitry to protect the in
NJU7221U25-TE1 NJU7221U25-TE1	JRC		00+	The DDX-2000 converts serial I2S digital audio s
NJU7221U27-TE1 NJU7221U27-TE1	JRC		00+	The IRU1117-18 is a low dropout three-terminal fi
NJU7221U30-TE1 NJU7221U30-TE1	JRC		00+	Maximum ratings are those values beyond which de
NJU7221U32 NJU7221U32	JRC	SOT-89		The crystal oscillators should be fundame
NJU7221U32-TE1 NJU7221U32-TE1	JRC		00+	Stresses above those listed under Absolute Maxim
NJU7221U35TE1 NJU7221U35TE1	jrc	jrc	dc94	+15 VOUT- is a regulated +15 volt output availabl
NJU7221U35-TE1 NJU7221U35-TE1	JRC		00+	If the external master has initiated a register
NJU7221U40-TE1 NJU7221U40-TE1	JRC		00+	Stresses beyond those listed under absolute maxi
NJU7221U50-TE1 NJU7221U50-TE1	JRC		00+	In addition to the standard output configuration
NJU7221U55-TE1 NJU7221U55-TE1	JRC	SOT	0	NOTE: The parameters listed in Table 3 are contr
NJU7221U55-TE2 NJU7221U55-TE2				If the part is attached in a reflow oven, the tem
NJU7221U5F-TE1 NJU7221U5F-TE1				Single amplifiers are offered in SOT-23 packages
NJU7221UXX-TE1-ZZZB NJU7221UXX-TE1-ZZZB	JRC		0809+	Most modules operate from clocks derived from Ma
NJU7222 NJU7222				† TI380C3x devices can be used with TI380P
NJU7222L50 NJU7222L50				GS 702 replaces most of the original transmitter
NJU7222U30 NJU7222U30				POWER-ON INITIALIZATION When power is first app
NJU7222U30-TE1 NJU7222U30-TE1	JRC		00+	Muting all channel drivers can be obtained using
NJU7222U30-TE1-ZZZB NJU7222U30-TE1-ZZZB	JRC		0809+	A 1% resistor must be connected directly between
NJU7222U33 NJU7222U33	JRC	SOT-89	05+	Application areas include transducer amplifiers,
NJU7222U33-TE1 NJU7222U33-TE1	JRC		00+	CAUTION: These devices are sensitive to electros
NJU7222U33-TE1-ZZZB NJU7222U33-TE1-ZZZB	JRC		0809+	ROW/COLUMN ADDRESS SELECT: In the A/A Mux interfa
NJU7222U50 NJU7222U50	JRC	SOT-89	05+	The NJU7222U50TF is made to fully comply with Mic
NJU7222U50TE1 NJU7222U50TE1	jrc	jrc	dc0309	The A64 device has six communication interfaces:
NJU7222U50-TE1 NJU7222U50-TE1	JRC	SOT-89		UV (Pin 3): Analog Undervoltage Input. When UV is
NJU7222U50-TE1-ZZZB NJU7222U50-TE1-ZZZB	JRC		0809+	Note 1: Specifications are production tested at T
NJU7222UXX-TE1-ZZZB NJU7222UXX-TE1-ZZZB	JRC		0809+	The internal data word address counter maintains
NJU7222V50 NJU7222V50	JRC		99	The CDC7005 is a high-performance, low-phase noi
NJU7223 NJU7223				The output stages consist of an low RDS ON Power-
NJU7223DL NJU7223DL	JRC		05	TRB Transmitter or receiver select. A logic low
NJU7223DL1 NJU7223DL1				SecSi™ (Secured Silicon) Sector region &n
NJU7223DL1-18 NJU7223DL1-18	JRC	02+	TO252	The PC87108 is a serial communications device wi
NJU7223DL1-18-TE1 NJU7223DL1-18-TE1	JRC		00+	The output and reset of the integrators is contr
NJU7223DL1-19-TE1 NJU7223DL1-19-TE1	JRC		00+	18 keys can be connected by key input K1~
NJU7223DL1-25 NJU7223DL1-25	JRC	SOT-252	06+NOPB	FEATURES Low Cost, 3.3 V-CMOS, Mixed Signal, Fr
NJU7223DL1-25(TE1) NJU7223DL1-25(TE1)	JRC	TO252-3	0606+	1.3A, 0.18Ω, internal power switch VIN op
NJU7223DL1-25-TE1 NJU7223DL1-25-TE1	JRC	TO252-3	05+	Notes: 1. Repetitive Rating : Pulse width limite
NJU7223DL1-33 NJU7223DL1-33	JRC	TO252	01+	25 mV (or less) For normal line resistances data
NJU7223DL1-33(TE1) NJU7223DL1-33(TE1)	JRC	TO252-3	0606+	µ PD780308 with enhanced display function
NJU7223DL1-33-TE1 NJU7223DL1-33-TE1	JRC		00+	The UC62LV2008 is a high performance, ver
NJU7223DL1-33-TE1-Z NJU7223DL1-33-TE1-Z	JRC		06+	Refer to Figure 20 for performance into a
NJU7223DL1-50 NJU7223DL1-50	JRC	SOT252	04+	NOTES: 1. Skew measured between all outputs und
NJU7223DL1-50-TE1 NJU7223DL1-50-TE1	JRC		00+	The SDA 9251 is a triple port 868 352 bit dynami
NJU7223DL1-XX-TE1-Z NJU7223DL1-XX-TE1-Z	JRC	08+		The output of these devices (pin 3) switc
NJU7223F18 NJU7223F18				Conditions Measured from input terminals to out
NJU7223F25 NJU7223F25		TO-220		designed to protect the gate from any remaining
NJU7223F-3.3 NJU7223F-3.3	JRC		0301	The LX8385/85A/85B series devices are pin
NJU7223F33 NJU7223F33	JRC		05+	The ADS1258 is a 16-channel (multiplexed), low-
NJU7223F50 NJU7223F50	JRC	TO220F		The DMS-EB-AC/DC board includes provision
NJU7223F50-ZZZB NJU7223F50-ZZZB	J RC		0809+	Features ❏ InGaP HBT Technology ❏
NJU7223FXX NJU7223FXX				At 333 MHz (3.0 ns) core instruction rate, the A
NJU7223FXX-ZZZB NJU7223FXX-ZZZB	JRC		06+
NJU7231 NJU7231				The MT3x7xB is a family of high performance DTMF
NJU7231F12-TE1 NJU7231F12-TE1	NJR (VA)			NOTES: 1. For conditions shown as Max. or Min.,
NJU7231F28-TE1 NJU7231F28-TE1	NJR (VA)			One or more of the following United States patent
NJU7231F52-TE1 NJU7231F52-TE1	NJR (VA)			Notes: 1. For max. or min. conditions, use appr
NJU7231FXX-TE1-ZZZB NJU7231FXX-TE1-ZZZB	JRC		06+	Note: Definition of I/O column pneumonic on pin d
NJU7231L12 NJU7231L12				Applying a LOW to the INIT input causes an immed
NJU7231L28 NJU7231L28				When the PC is turned off, the hardware clock run
NJU7231L52 NJU7231L52				Peripheral Features D 34 I/O Pins D Additional
NJU7231LXX NJU7231LXX				READ: The AT28C010-12DK is accessed like a Static
NJU7231U12-TE1 NJU7231U12-TE1	NJR (VA)			Charge current can be set by an external resisto
NJU7231U18-TE1 NJU7231U18-TE1	NJR			Supply Voltage Hall Input Voltage Range Output
NJU7231U30-TE1 NJU7231U30-TE1	NJR (VA)			PRODUCT PREVIEW information concerns products in
NJU7231U33-TE1 NJU7231U33-TE1				The IA186ES/188ES is a form, fit, and function r
NJU7231U50-TE1 NJU7231U50-TE1	NJR (VA)			Currents smaller than 100pA will result in incre
NJU7231UXX-TE1-ZZZB NJU7231UXX-TE1-ZZZB	JRC		06+	Notes: 1. Specifications measured with one outp
NJU7241 NJU7241	JRC	SOT-153		Information furnished by Analog Devices is believ
NJU7241F18-TE1 NJU7241F18-TE1	NJR (VA)			Operation of this device beyond any one of these
NJU7241F25-TE2 NJU7241F25-TE2	SONY		4000	The Sidac is a silicon bilateral voltage trigger
NJU7241F28-TE1 NJU7241F28-TE1	NJR (VA)			HITAG(1) is the name of one of the universal and
NJU7241F31 NJU7241F31	JRC	SOT-153	06+	Support for 12 independent ports. Low power co
NJU7241F31-TE2 NJU7241F31-TE2	JRC	SOT23-5	01+	Note 5 Pins G6 and RESET are designed with a high
NJU7241F40-TE1 NJU7241F40-TE1	NJR (VA)			Strap:see Note 4 Notes: 1. DQ-to-I/O wi
NJU7241F50 NJU7241F50	JRC	SOT-153	05+	C. These materials are solely intended for a cus
NJU7241F50-TE1 NJU7241F50-TE1	NJR (VA)	0106+	4000	The Am29PDL640G is a 64 Mbit, 3.0 volt-only Page
NJU7241FXX-TE1-ZZZB NJU7241FXX-TE1-ZZZB	JRC		06+	One or more of the following United States patent
NJU7250 NJU7250				FlexCAN (CAN Version 2.0 B-compliant) module wit
NJU7250F25-TE1 NJU7250F25-TE1	NJR (VA)			• The information in this document is curre
NJU7250FXX-TE1-ZZZB NJU7250FXX-TE1-ZZZB	JRC		06+	Cr ystal input, has inter nal load cap (33pF) an
NJU7261U30-TE1 NJU7261U30-TE1	NJR (VA)	SOT	99	Permanent device damage may occur if ABSOLUTE MA
NJU7261U30-TE1（30Z.902) NJU7261U30-TE1（30Z.902)				The primary application of this device is to pro
NJU7261U30-TE1(30ZS.902) NJU7261U30-TE1(30ZS.902)				➀ Typical at TA = +25C under nominal line
NJU7261U33-TE1 NJU7261U33-TE1	NJR (VA)	SOT89-5	06+	Mode switch The DC voltage on the CTL pin can b
NJU7261U50TE1 NJU7261U50TE1				Hynix HYMD264646(L)8-K/H/L series is designed for
NJU7261U50-TE1 NJU7261U50-TE1	NJR (VA)	JRC	05+	= Essential Part Number = Standard Device = T
NJU7262B NJU7262B	JRC		99+	† Stresses beyond those listed under absol
NJU7285CV(TE1) NJU7285CV(TE1)	JRC			Burst mode operation Auto & se
NJU7301 NJU7301	JRC	DIP	1995	The internal circuit is composed of 3 stages in
NJU7301D NJU7301D	NJR	DIP	05+	The HSDL-2300 is a new generation 3.3 V power
NJU7301M NJU7301M	NJR	SOP16	99+	• 2GHz gain-bandwidth product • Gai
NJU7304D NJU7304D	JRC	DIP	06+	pin signalised an interrupt (logic 0). However, i
NJU7305 NJU7305	JRC	2007		† Stresses beyond those listed under absol
NJU7305AL NJU7305AL	JRC	DIP-28	01+	RST Pin The RST pin is normally driven h
NJU7305L NJU7305L				Driving Transmission Lines The NJU7305L
NJU7305M NJU7305M	JRC	04+		For reasons of interference protection and surge
NJU7305M(T1) NJU7305M(T1)				Apply a positive voltage (1.3 V VPWUP VPOS ) to
NJU7306 NJU7306				Notes; (1) Repetitive Rating: Pulse Width Limit
NJU7306L NJU7306L				1 ms instruction cycle time Fourteen multi-sourc
NJU7307 NJU7307				The OPA680 represents a major step forward in un
NJU7307F NJU7307F		QFP	97	Preliminary product information describes produc
NJU7307L NJU7307L	JRC	2007		Resistor Terminal A1 Wiper Terminal W1 Resistor
NJU7311 NJU7311	JRC		07+	10 years minimum data retention in the absence
NJU7311A NJU7311A	JRC		97	Electrical characteristics apply over the full o
NJU7311A2 NJU7311A2				The Power Saving (PS) module implements the Idle
NJU7311AL NJU7311AL	JRC	DIP	DIP	These electrically erasable programmable memo-
NJU7311AL/L NJU7311AL/L				The MAX4649 successfully meets the qualit
NJU7311AL-ZZZB NJU7311AL-ZZZB	JRC		06+	PGND (Bump D3): Power ground pin. Connect directl
NJU7311AM NJU7311AM	NJR	SOP	03+	† Stresses beyond those listed under absol
NJU7311AM(T1) NJU7311AM(T1)	JRC	SOP30	2005	Notes: 1. See test circuit and waveforms. 2. Th
NJU7311AM(TE2) NJU7311AM(TE2)				The CSPEMI306A is a six channel low-pass filter
NJU7311AM-T1 NJU7311AM-T1	JRC	SMD	98+	Available in the Texas Instruments NanoStar͐
NJU7311L NJU7311L	JRC	97+	DIP/28	Frame sequence, constant throughput delay
NJU7312 NJU7312	JRC			SDLVL and deasserts low otherwise. SD can be fed
NJU7312A NJU7312A	N/A	N/A	N/A	The DS1386 is in the write mode whenever the WE (
NJU7312AL NJU7312AL	JRC	DIP	DIP	Signal Processing Technologies, Inc. reserves th
NJU7312AL/L NJU7312AL/L				Notes: 1. Pulsed measurement, pulse width 350 &
NJU7312AL-ZZZB NJU7312AL-ZZZB	JRC		06+	The block diagram (Figure 1) shows the parasite-p
NJU7312AM NJU7312AM	NJR	SOP30	1997	These N-Channel power MOSFETs ar
NJU7312AM(TE2) NJU7312AM(TE2)				The 38B7 group is the 8-bit microcomputer based
NJU7312L NJU7312L	JRC	DIP	DIP	NOTES: 1. WE is high for read Cycle. 2. Device
NJU7312M NJU7312M	JRC	SMD	SMD	The NC7SZ08 is a single 2-Input AND Gate from Fa
NJU7313 NJU7313	JRC		07+	(7) Standby Control Function By setting
NJU7313A NJU7313A	JRC	SMD	SMD	Crossover Lockout The charge pump contains two
NJU7313AC NJU7313AC	JRC	SOP	01+	Whenever connected to a dedicated antenna for the
NJU7313AL NJU7313AL	JRC	DIP	DIP
NJU7313AL/L NJU7313AL/L				The NJU7313AL/L/NJU7313AL/L are available in PDIP
NJU7313AL-ZZZB NJU7313AL-ZZZB	JRC		06+	Parameter VDD to GND VOUTA, VOUTB, VBZ to GND
NJU7313AM NJU7313AM	NJR	SOP	00+	First of all, the voltage difference need only b
NJU7313AM(T1) NJU7313AM(T1)				Ultra Low RDS(on) Higher Efficiency Extending Ba
NJU7313AM(T2) NJU7313AM(T2)	JRC	SOP	2000	A temperature-dependent current limitation in th
NJU7313AM(TE2) NJU7313AM(TE2)	JRC	SOP	2006	A 3-state C-BUS serial data output to the µ
NJU7313AM-T1 NJU7313AM-T1	JRC	SOP/30	01+	The NJU7313AM-T1 is a rail-to-rail high resolutio
NJU7313AM-TE2-ZZZB NJU7313AM-TE2-ZZZB				The external voltage supply is connected to this
NJU7313AN-(T2) NJU7313AN-(T2)	JRC			Undervoltage Lockout Adjust (Input): With this p
NJU7313G NJU7313G	JRC	STK	2005+
NJU7313L NJU7313L	JRC	DIP	DIP	The Allegro ACS750 family of current sensors prov
NJU7313M NJU7313M	JRC	SMD	SMD	DESCRIPTION Designed for monitors and high perf
NJU7314 NJU7314	JRC			STORAGE • Condition : 5C~35C,R.H.60% •
NJU7325 NJU7325	JRC	N/A	05+	The waveform of the maximum DC applied voltage is
NJU7325R-TE1 NJU7325R-TE1	NJR (VA)		08+	PIN DESCRIPTION This pin provides shutdow
NJU7326 NJU7326				The 56F802 controller includes 8K words (16-bit)
NJU7326R NJU7326R	N/A	N/A	06+	Notes: 1. In-Band El 115.2 kb/s. 2. Logic Low
NJU7326R-TE1-ZZZB NJU7326R-TE1-ZZZB	JRC		0809+	Suggestion: (1) Choose a small enough value pull
NJU7329ABR2-TE1 NJU7329ABR2-TE1				The number formed by the full offset least signi
NJU7329ARB2 NJU7329ARB2	JRC	05+	SMD	Switching Frequency On/Off Standby (Pin 3) &nbs
NJU7329ARB2-TE1 NJU7329ARB2-TE1	JRC		06/07+	The ACT16470 are 16-bit registered transceivers
NJU7329RB2(TE1) NJU7329RB2(TE1)	JRC	SSOP	2003	• Bidirectional data strobe(DQS) • D
NJU7333R NJU7333R				The IDT71016 is a 1,048,576-bit high-spee
NJU7333R(TE1) NJU7333R(TE1)				The HYNIX HY27(U/S)F(08/16)1G2M series is a 128Mx
NJU7333R-TE1 NJU7333R-TE1				1-Phase, Full-Wave, Linear DC Motor Driver Buil
NJU7344R(TE1) NJU7344R(TE1)	JRC		05+	The HT6026 is a CMOS LSI encoder designed for r
NJU7370 NJU7370				Flash Media Controller Complete System Solutio
NJU7370F NJU7370F	JRC	QFP	,0034	† All characteristics are measured with ze
NJU7370FB2 NJU7370FB2	JRC		06/07+	It must also be noted that in (noninverting) gai
NJU74HC00M NJU74HC00M	JRC	SOIC-14	07+/08+	1) Can select center frequency and Q value of Ba
NJU74HC02M NJU74HC02M	JRC			The LX1744 is a compact high efficiency
NJU74HC04M NJU74HC04M	JRC	96+	SOP-	S2 is a general-purpose input that can be program
NJU74HC08M NJU74HC08M	JRC	SOP	1992
NJU74HC123M NJU74HC123M	JRC	SOP	06+	This MOSFET is an enhancement-mode silicon-gate
NJU74HC139M NJU74HC139M				VID0-VID4 (DAC Digital Input Code Control) Pins 1
NJU74HC14M NJU74HC14M	JRC			The VSP5000 device is a complete application spe
NJU74HC20D NJU74HC20D	JRC		97	low insertion loss, 0.8 dB typ. excellent isol
NJU74HC238D NJU74HC238D				When idle advanced power management features all
NJU74HC32M NJU74HC32M	JRC		96	NOTE: 1. AVSS (reference ground) must be connec
NJU74HC4066M NJU74HC4066M				Random-Lock Synchronization: The deserializer can
NJU74HC58M-T1 NJU74HC58M-T1	JRC	SOP8现货		While the AD8021 is internally short-circuit pro
NJU74HCU04D NJU74HCU04D				• C40C to +85C operation • 16 to 40
NJU74HCU7204M NJU74HCU7204M	JRC	SMD/8	99	The LH1526 relay is two SPST normally open swit
NJU74HCU7204M(TE3) NJU74HCU7204M(TE3)				asynchronous communications. The 73K322L is desi
NJU7503F NJU7503F	JRC		94 新	The Fairchild Switch FSTU3125 provides four high
NJU7505 NJU7505				The OP4008B will tune from 0 to 5 volts as shown
NJU7505AD NJU7505AD	JRC		0809+	Stresses beyond those listed under absolute maxim
NJU7505AD01 NJU7505AD01				There are two limitations on the power ha
NJU7505AD-ZZZB NJU7505AD-ZZZB	JRC		06+	The FM local oscillator consists of a transistor
NJU7505AM NJU7505AM	JRC		02+	Synchronous Address Advance. ADV is an active LOW
NJU7507 NJU7507				• On-chip mixed signal processing •
NJU7507AD NJU7507AD	JRC	03+	DIP8	additional logic Full synchronous operation on b
NJU7507AD-ZZZB NJU7507AD-ZZZB	JRC		06+	The GC5018s receive input data interface accepts
NJU7507AM NJU7507AM	JRC		04	Hardware data protection measures include a low
NJU7507AM-TE1-ZZZB NJU7507AM-TE1-ZZZB	JRC		06+	• IXYS advanced low gate charge pr
NJU7508D NJU7508D	JRC	DIP	97	Notes: 1. Insulation characteristics are guarant
NJU7600M NJU7600M				VCC is the main 5V supply, which can be disabled
NJU7600RB1-TE1 NJU7600RB1-TE1	NJR (VA)			Enhanced N channel FET with no inherent diode to
NJU7602RB1-TE1-ZZZZB NJU7602RB1-TE1-ZZZZB				The NJU7602RB1-TE1-ZZZZBA center tap Schottky rec
NJU7608D NJU7608D	JRC	DIP	97	The following are trademarks of Skyworks Solution
NJU7631M NJU7631M				Notes: 1. The luminous intensity, I v, is measu
NJU7660 NJU7660	JRC	SOP	05+	Notes: 1. Repetitive Rating : Pulse width limite
NJU7660D NJU7660D	N/A	N/A	N/A	RFMs amplifier-sequenced hybrid (ASH) transceiver
NJU7660D05 NJU7660D05				The W536XXXP, a member of ViewTalkTM family, is a
NJU7660D-ZZZB NJU7660D-ZZZB	JRC		06+	DESCRIPTION The 74AC257 is an advanced high-spe
NJU7660M NJU7660M	JRC	SOP	99+	MATERIAL: A) PACKAGE BODY & COVER : WHITE A
NJU7660M(LF) NJU7660M(LF)
NJU7660M(TE1) NJU7660M(TE1)		Jack(Available)		The IDT7133/7143 are high-speed 2K x 16 D
NJU7660M(TE3) NJU7660M(TE3)	JRC		03+	Stresses beyond those listed under absolute maxi
NJU7660M-T1 NJU7660M-T1				Typical active current 400 mA Typical standby cur
NJU7660M-TE1 NJU7660M-TE1	JRC	DMP8	07+
NJU7660M-TE1-ZZZB NJU7660M-TE1-ZZZB	JRC		0809+	For optimal DSP program execution, programmers m
NJU7660MX NJU7660MX				The device provides ultrastable +4.096V output w
NJU7660V NJU7660V	NJU	TSSOP8	01+	The byte pointer bit must be toggled to the corr
NJU7660V(TE1) NJU7660V(TE1)	JRC	SSOP	2002	Intel and Pentium are registered trademarks of In
NJU7660V(TE2) NJU7660V(TE2)	JRC	01＋	MSOP	• 6A Output Current • Input Voltage
NJU7660V-(TE2) NJU7660V-(TE2)	JRC	99	2850	Notes a. The algebraic convention whereby the m
NJU7662 NJU7662	JRC	STK	2005+	The MPC860 Quad Integrated Communications Contro
NJU7662D NJU7662D	JRC		2003	Capacitance measurements shall be made by means
NJU7662M NJU7662M	JRC	2008		tional ACX300 Series products (2.0 type to 3.5
NJU7662M(LF) NJU7662M(LF)				D0 - D4 (DAC Digital Input Control Codes): These
NJU7662M(TE1) NJU7662M(TE1)				The HT74XX series is a set of three-terminal hi
NJU7662M(TE2) NJU7662M(TE2)	JRC	SOP-8P	0311+	external components Burst operation under seco
NJU7662M(TE3) NJU7662M(TE3)				The XR16C854/854D1 (854) is an enhanced quad Un
NJU7662M-TE1 NJU7662M-TE1				The DSP56F801 incorporates an 8 input, 12-bit An
NJU7662M-TE1-ZZZB NJU7662M-TE1-ZZZB	JRC		06+	Temperature coefficients Silicon resistors are v
NJU7663R NJU7663R	JRC	SOP8	99+	The DLYBLK input can be used to halt address gen
NJU7664 NJU7664				• High-speed access time: 55, 70, 100 ns
NJU7664R NJU7664R				To retain data, 1,024 refresh cycles are require
NJU7665AF-TE1 NJU7665AF-TE1	NJR (VA)			Signal input data is clocked into 8-stage FIFOs
NJU7665CF NJU7665CF	JRC		06+	The ISL6208 features 4A typical sinking current f
NJU7665CF-TE1 NJU7665CF-TE1	JRC		06/07+	Typical specifications represent average
NJU7670 NJU7670				The DDX-2100 Power Device is a dual channel H-Br
NJU7670M NJU7670M	NJR	00+	SOP/14	• IEEE 802.3u D5 repeater and management c
NJU7670M-TE1 NJU7670M-TE1	JRC	08+		16-Bit Monotonic Over Temperature Relative Accur
NJU7670M-TE1-ZZZB NJU7670M-TE1-ZZZB	NJRC			programming the ADC into the desired mode. The
NJU7670V-TE1 NJU7670V-TE1	NJR		00+	In the normal mode, these devices are 18-bit uni
NJU7700 NJU7700				NOTES: (1) Long-Term Input Offset Voltage Stabil
NJU7700F21-TE1 NJU7700F21-TE1				Chip Select (Pin 23) Chip Select Input.
NJU7700F21-TE1-ZZZB NJU7700F21-TE1-ZZZB				tional (HCPL-900J/-090J), two channels in one di
NJU7700F25-TE1 NJU7700F25-TE1				The Simultaneous Read/Write architecture provides
NJU7700F27-TE1 NJU7700F27-TE1				Often, an SOA curve provides information showing
NJU7700F28-TE1 NJU7700F28-TE1	JRC		00+	The HPC46400E is an upgraded HPC16400 Features h
NJU7700F33-TE1-ZZZB NJU7700F33-TE1-ZZZB	JRC		0809+	C 512 Kbytes on-chip flash memory single &
NJU7700FXX-TE1 NJU7700FXX-TE1	JRC		06/07+	† For execution of these commands on cycle
NJU7701 NJU7701				† Stresses beyond those listed under absol
NJU7701155 NJU7701155				The TA78DLAS series consists of positive fixed o
NJU7701F06-TE1 NJU7701F06-TE1				All terminations can be disconnected from the bu
NJU7701F28-TE1 NJU7701F28-TE1				Up to 97% Efficiency 2MHz PWM Switching 800mA G
NJU7701F44-TE1 NJU7701F44-TE1				The direct connects allow immediate connections
NJU7701FXX-TE1 NJU7701FXX-TE1	JRC		06/07+
NJU7702F27(TE1) NJU7702F27(TE1)				*This is a stress rating only and functional ope
NJU7704 NJU7704				4. This specification represents the current flo
NJU7704F27A(TE1) NJU7704F27A(TE1)	JRC	05+	SOT343
NJU7705 NJU7705
NJU7705F22A NJU7705F22A	JRC			Chip Select : Enables or disables all inputs exc
NJU7706 NJU7706
NJU7741 NJU7741				Widebus  Family A-Port Outputs Have Equi
NJU7741FXX-TE1-ZZZB NJU7741FXX-TE1-ZZZB	JRC		06+	Leading edge blanking is also applied to the cur
NJU7744 NJU7744				The Atmel architecture was developed to provide
NJU7744FXX-TE1-ZZZB NJU7744FXX-TE1-ZZZB	JRC		06+	Samsung Electronics' microcontroller business ha
NJU7747 NJU7747				Please be aware that an important notice
NJU7747F4-XX-TE1-ZZ NJU7747F4-XX-TE1-ZZ	JRC		06+	*Stresses above those listed under Absolute Maxi
NJU7748 NJU7748				Pin-compatible upgrade of TMC2242B User-selectab
NJU7748F4-XX-TE1-ZZ NJU7748F4-XX-TE1-ZZ	JRC		06+	A serial communications interface (SCI) is integ
NJU7751 NJU7751				Single Down/Up Count Control Line Look-Ahead Cir
NJU7751F32 NJU7751F32				Ring provides half of the two-wire connection to
NJU7751FXX-TE1-ZZZB NJU7751FXX-TE1-ZZZB	JRC		06+	trigger/retrigger input (nA1) , an overriding ac
NJU7754 NJU7754				RECEIVER DC CHARACTERISTICS High Level Output V
NJU7754FXX-TE1-ZZZB NJU7754FXX-TE1-ZZZB	JRC		06+	Bild / Fig. 8 W3 C - Dr eiphasen -We chselwegsch
NJU7757 NJU7757				The SY89833L is a 3.3V, high-speed 2GHz d
NJU7757F4-XX-TE1-ZZ NJU7757F4-XX-TE1-ZZ	JRC		06+	• 1500 Watts for 10/1000 µs with rep
NJU7758 NJU7758				The signal response slew rate of the converter d
NJU7758F4-XX-TE1-ZZ NJU7758F4-XX-TE1-ZZ	JRC		06+	Conexant products are not intended for use in me
NJU7771 NJU7771				The NJU7771 is a 64-position, one-time programma
NJU7771F03-TE1 NJU7771F03-TE1	NJR
NJU7771F05-TE1 NJU7771F05-TE1	NJR (VA)			The Media Access Control function, provided by t
NJU7771FXX-TE1-ZZZB NJU7771FXX-TE1-ZZZB	JRC		06+	Full duplex UART Three 16-bit timers each with t
NJU7772 NJU7772
NJU7772F03-TE1 NJU7772F03-TE1	NJR (VA)	04+	SOP	such as a gaussian, or a rectangular pulse then
NJU7772F15-TE1 NJU7772F15-TE1				1. VCC and GND This IC has two VCC termin
NJU7772F25-TE1 NJU7772F25-TE1	JRC	04+	SOP	Absolute Maximum Ratings (Ta = 25C, Vss = 0V) &#
NJU7772F28-TE1 NJU7772F28-TE1	JRC	04+	SOP	SUPPLY VOLTAGE C VDD = 1.65V to 2.2V Core Power
NJU7772FXX-TE1-ZZZB NJU7772FXX-TE1-ZZZB	JRC		06+	• SAW (Surface Acoustic Wave) IF fil
NJU7773 NJU7773				For a general estimate of ICC, the following equa
NJU7773F25-TE1 NJU7773F25-TE1	NJR			When fewer vertical clock lines are connected, t
NJU7773F33-TE1 NJU7773F33-TE1	NJR			SelfCTest The sensor provides a selfCtes
NJU7773FXX-TE1-ZZZB NJU7773FXX-TE1-ZZZB	JRC		06+	This three terminal positive regulator is suppli
NJU7774 NJU7774				2) LOCKPRE is changed to PRE. - Texts, Ta
NJU7774F03-TE1 NJU7774F03-TE1	NJR			400 MSPS Internal Clock Speed Integrated 14-bit
NJU7774F15-TE1 NJU7774F15-TE1	NJR (VA)			The traditional PC motherboard uses a chip-set
NJU7774F28-TE1 NJU7774F28-TE1	NJR (VA)			Three-phase bipolar drive Direct PWM drive (cont
NJU7774FXX-TE1-ZZZB NJU7774FXX-TE1-ZZZB	JRC		06+
NJU7775 NJU7775				5. Output clip detection function (pin(1))
NJU7775F05-TE1 NJU7775F05-TE1	NJR (VA)			The MK1491-06 is a low cost, low jitter, high p
NJU7775F33-TE1 NJU7775F33-TE1	NJR			The HY29DS16x can be programmed and erased in-s
NJU7775FXX-TE1-ZZZB NJU7775FXX-TE1-ZZZB	JRC		06+	Reset: A low on this pin resets the microcontroll
NJU7776 NJU7776				The new generation CoolSET™-F3 provides Ac
NJU7776F25-TE1 NJU7776F25-TE1	NJR			NOTES: A. Vres is the minimum input voltage for
NJU7776F33-TE1 NJU7776F33-TE1	NJR			The user can program the frequency of the output
NJU7776FXX-TE1-ZZZB NJU7776FXX-TE1-ZZZB	JRC		06+	A typical multipoint application is shown in the
NJU7780 NJU7780				• Designed expressly for Switch-Mode Power
NJU7780U1-04-TE1-ZZ NJU7780U1-04-TE1-ZZ				the CY7C261 automatically powers down into a low-
NJU7780U1-33-TE2-ZZ NJU7780U1-33-TE2-ZZ				• 1024 Resistor Taps C 10-Bit Resolution &
NJU7780U1-XX-TE1-ZZ NJU7780U1-XX-TE1-ZZ	JRC		06+	On the subsequent clock rise the data lines are a
NJU7781 NJU7781				The CMX866 shares internal register addresses and
NJU7781U1-XX-TE1-ZZ NJU7781U1-XX-TE1-ZZ	JRC		06+	This output configuration enables a simple match
NJU7806 NJU7806	JRC	STK	2005+	No products described or contained herein are in
NJU78L08A NJU78L08A				Piezo Speaker Driving Analog Audio Signal Input,
NJU7920M NJU7920M	JRC	SOIC-8	07+/08+	NOTES: 1. Designators in TYPE: P: power supply a
NJU8001 NJU8001	JRC	SOP	03/+04+	FEATURES Bidirectional crowbar protection Vo
NJU80010 NJU80010	JRC	SOP
NJU8001D NJU8001D	JRC			Noise shaping mode selection. This pin selests b
NJU8001M NJU8001M				The audio processor that has been address
NJU8101 NJU8101				Data of C1 , C2 and C3 code bit become 1
NJU8101M NJU8101M	JRC	SOP8		common mode range is that of the CA3080 differen
NJU8101MK NJU8101MK	JRC	SOP8现货		Sensitivity is defined as the average signal lev
NJU8711 NJU8711				DESCRIPTION The M74HC166 is an high speed CMOS
NJU8711V(TE2) NJU8711V(TE2)	JRC	TSSOP-10P	2002	The NJU8711V(TE2)E demodulates the QPSK (quadrat
NJU8711V-TE2 NJU8711V-TE2				The information contained herein is presented on
NJU8713 NJU8713	JRC			The chip requires a single, even-parity bit to b
NJU8713V NJU8713V	JRC	SOP	2004
NJU8713V(TE1) NJU8713V(TE1)				• Diode noise level of this series is appro
NJU8713V(TE2) NJU8713V(TE2)	JRC	04+	SOP-14	Ground pin. This pin provides a ground for the c
NJU8713V-TE1 NJU8713V-TE1				Motorola reserves the right to make changes with
NJU8721V-TE1 NJU8721V-TE1				For output voltages less than 10 V, the minimum
NJU8725 NJU8725				Connect a resistor from this pin to the drain of
NJU8725V-TE1 NJU8725V-TE1	JRC		06/07+	A separate power supply pin, VLOGIC, allows the b
NJU8752 NJU8752				2 MHz (typ.) PWM Switching Frequency &nbs
NJU8752B NJU8752B				2-cell 1.5V to 3.6V battery operation &nb
NJU8752BV-TE1-ZZZB NJU8752BV-TE1-ZZZB	JRC		06+	The RC4700 ALU consists of the integer ad
NJU8752KM1-TE4-ZZZB NJU8752KM1-TE4-ZZZB	JRC		06+	This method fails if a user applies RESET during
NJU8752V NJU8752V	NJRC		07/08++	Hardware data protection measures include a low
NJU8752V-TE1 NJU8752V-TE1	JRC	08+		The CMPIN pin drives data slicer DS1, which conve
NJU8752V-TE1-ZZZB NJU8752V-TE1-ZZZB	JRC		0809+	The LIS2L02AL has a full scale of 2g and it is
NJU8754 NJU8754				comprising R7 R8 R9 R10 and R26 The output of thi
NJU8754KM1-TE4-ZZZB NJU8754KM1-TE4-ZZZB	JRC		06+	Hynix HYMD264M726A(L)8-J/M/K/H/L series is unbuff
NJU8754V-TE1-ZZZB NJU8754V-TE1-ZZZB	JRC		06+	Two temperature ranges are available for
NJU8754V-TE2 NJU8754V-TE2				PRODUCT PREVIEW information concerns products in
NJU8755 NJU8755				The transmitter consists of a PLL frequency synt
NJU8755V NJU8755V	JRC	08+		This is an analog control input that enables the
NJU8755V(TE1) NJU8755V(TE1)				Single channel T1/E1/J1 long haul/short haul lin
NJU8755V-TE1 NJU8755V-TE1	JRC	SSOP20	08+	Hynix HYMD212G726A(L)S4-M/K/H/L series is registe
NJU8755V-TE1-ZZZB NJU8755V-TE1-ZZZB	JRC			Notes: 1. See XPLA3 family data sheet (DS012) f
NJU9201BD NJU9201BD	JRC		06/07+	Features • Supports 510H/760H system CCD i
NJU9201BM NJU9201BM	JRC		06/07+	In cases in which absolute stability under all l
NJU9201CC NJU9201CC	JRC		06/07+	Flexible On-Chip Memory ❐ 4K Bytes
NJU9201CD NJU9201CD	N/A	N/A	N/A	The TO-247 package is preferred for commercial-in
NJU9202 NJU9202				The CS8920A requires the minimum number of exte
NJU9202BD NJU9202BD	JRC	DIP	1998	The ABT162244 devices are 16-bit buffers and li
NJU9202BM NJU9202BM	JRC	QFP		Figure 3 shows the timing relationship between da
NJU9203BD NJU9203BD	JRC	DIP-40	01+	The terminator's internal power is dissipated pr
NJU9203BF NJU9203BF				Epoxy die attach is recommended. The top and bot
NJU9203BM NJU9203BM	JRC	SOP-40	2001+	(5-V Input and Output Voltages With 3.3-V VCC)
NJU9204 NJU9204				n Clock recovery from PLL lock to random data pa
NJU9204BD NJU9204BD	JRC			The EM39LV040 provides Chip-Erase feature, which
NJU9204BFB1 NJU9204BFB1	JRC		06/07+	True Dual-Ported memory cells which allow simulta
NJU9204BM NJU9204BM		SOP	05+	The output of this device is generated and filter
NJU9204BM-ZZZB NJU9204BM-ZZZB	JRC		06+	1. Startup includes both the application of a va
NJU9205 NJU9205				The information provided herein is believed to b
NJU9207B NJU9207B				Clock and Data Transitions: The SDA pin is normal
NJU9207BF NJU9207BF				The bq2000 detects the battery chemistry by monit
NJU9207BFC NJU9207BFC	JRC		00+	• DLL aligns DQ and DQS transitions with CK
NJU9207F NJU9207F	JRC	QFP80		To assist in the transceiver evaluation proces
NJU9207FC1 NJU9207FC1	JRC		06/07+	Program Erase Enable input VPEN, program
NJU9208F NJU9208F			2000	hold the output low (Figure 2). This resistor va
NJU9210 NJU9210
NJU9210BD NJU9210BD	JRC			OSCS is a system oscillator I/O pin connected to
NJU9210BFC NJU9210BFC	JRC		06/07+	The ISD1000A Series eliminates the need for dig-
NJU9210FB NJU9210FB				The varistors consist of a disc of low-â c
NJU9210FC NJU9210FC	JRC	QFP	00+	A/D converters are calibrated by positioning the
NJU9210FC1-00 NJU9210FC1-00	JRC		06/07+	The device has the capability to protect the dat
NJU9210FC1C-00 NJU9210FC1C-00	JRC		06/07+	NOTES 1Input bias current is specified for two d
NJU9212 NJU9212				NCS2510 is a 1.0 GHz current feedback mono
NJU9212F NJU9212F				PWM Capability up to 60 kHz with Duty Cycle from
NJU9212FG1 NJU9212FG1	JRC		06/07+	Excellent ac characteristics, such as 20MHz GBW,
NJU9214 NJU9214				Member of LAN9118 Family;optimized for medium- h
NJU9214FG1-00 NJU9214FG1-00	JRC		06/07+	2 MHz (typ.) PWM Switching Frequency Operates
NJU9214FGC1-00 NJU9214FGC1-00	JRC		06/07+	Analog Undervoltage input. When UV is pulled belo
NJU9252D NJU9252D	JRC		04+	This link option selects the source of the CONVS
NJU9252P NJU9252P				Software Data Protection The M28LV16 offers a s
NJU9610D2 NJU9610D2				RST is a device reset pin. When RST is pulsed hi
NJU9701D NJU9701D	JRC	DIP-24		Provides real time clock: − Counts secon
NJU9702 NJU9702		DIP		Comment: Exposing the device to stresses above th
NJU9702D NJU9702D	JRC	2008		Two independent LVDS receiver serial ports for
NJU9702G NJU9702G	JRC	2008		An HDLC transceiver is included on the SNIC for l
NJUM2904M NJUM2904M	JRC		03+	Guaranteed by design and characterization. ESD
NJUW4301M NJUW4301M	JRC	SOP	07+	If parallel loading is selected, both the COEF_WR

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