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HIGH SPEED : tPD = 5.4 ns (MAX.) at VCC = 3V 5V TOLERANT INPUTS POWER DOWN PROTECTION ON INPUTS INPUT VOLTAGE LEVEL: VIL = 0.8V, VIH = 2V at VCC =3V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA=25C LOW NOISE: VOLP = 0.3V (TYP.) at VCC =3.3V SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4 mA (MIN) at VCC =3V BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 16373 IMPROVED LATCH-UP IMMUNITY
† Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and  functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not  implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values except differential voltages are with respect to network ground.   2. Differential voltages are at IN+ with respect to IN C.   3. Short circuits from outputs to VDD can cause excessive heating and eventual device destruction.
Figure 2 shows a typical application circuit for the OBNZ MMIC. The device is internally matched to 50 Ω, and therefore does not require any external matching. The value of the input and output DC blocking capacitors C1 and C2 depends on the operating frequency; see the tables below. Capacitors C1 and C2 are used in conjunction with L1 and C3 to fine tune the input and output impedance. For optimum supply decoupling, a 1 µF capacitor (C5) can be added. The external components should be placed as close as possible to the MMIC. When using via holes, use multiple via holes per pin in order to limit ground path induction. Resistor R1 is a bias resistor providing DC current stability with temperature.
Parr number/PDF Mfg Pack D/C Descrpion
OBNZ   OBNZ OBNZ PDF Download N/A DIP 94+ s GENERAL DESCRIPTION   The NJW1151 is a
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