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This pin is active only when the chip transmits tone dialing signals. Otherwise, it al- ways outputs a low. The pin outputs tone signals to drive the external transmitter amplifier circuit. The load resistor (to VSS) should not be less than 5kW and any DC load connected to VDD is not allowed.
Organization . . . 512K 16 2 Banks 3.3-V Power Supply ( 10% Tolerance) Two Banks for On-Chip Interleaving (Gapless Accesses) High Bandwidth C Up to 83-MHz Data Rates CAS Latency (CL) Programmable to 2 or 3 Cycles From Column-Address Entry Burst Sequence Programmable to Serial or Interleave Burst Length Programmable to 1, 2, 4, 8, or Full Page Chip Select and Clock Enable for Enhanced-System Interfacing Cycle-by-Cycle DQ-Bus Mask Capability With Upper and Lower Byte Control Auto-Refresh and Self-Refresh Capability 4K Refresh (Total for Both Banks) High-Speed, Low-Noise, Low-Voltage TTL (LVTTL) Interface Power-Down Mode Compatible With JEDEC Standards Pipeline Architecture Temperature Ranges:   Operating, 0C to 70C   Storage, C 55C to 150C
  The SC33003LB01 is a driver for a small-to-medium-sized scale dot matrix graphic LCD. It includes the functions of the T9841B (column driver) and the T9842B (row driver). It has an 8-bit interface circuit and can be operated with an 80-Series MPU. It generates all the timing signals for the display with an on-chip oscillator. It receives 8-bit data from an MPU, latches the data to an on-chip RAM, and displays the image on the LCD (the data in the display RAM correspond to the dots on the display). The device has 120 column driver outputs and 64 row driver outputs enabling it to drive a 120-dot by 64-dot LCD. In addition, there are resistors to divide the bias voltage, a power supply op-amp, DC-DC converter (+5 V −5 V) and contrast control circuit, enabling the LCD to be driven by a single power supply. The device can be connected to another SC33003LB01 to drive a 240-dot by 64-dot LCD.