| Parr number/PDF |
Mfg |
Pack |
D/C |
Descrpion |
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STK0010II STK0010II  |
SANYO |
|
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1) CPD is defined as the value of the ICs intern |
STK0025 STK0025  |
SANYO |
|
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Signal Processor (DSP) C SMJ320C62x C 5- |
STK0029 STK0029  |
SANYO |
|
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These lamps are made with an advanced optical |
STK0029N STK0029N  |
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|
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Notes ; Repetitive Rating : Pulse Width Limited |
STK0030 STK0030  |
|
|
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The lamp current is monitored by means of an ext |
STK0035 STK0035  |
SANYO |
|
|
Information furnished by Analog Devices is believ |
STK0039 STK0039  |
SANYO |
ZIP |
03+ |
5V power supply 5V power supply 5V LNA power s |
STK0040 STK0040  |
|
|
|
The ADF4007 is a high frequency divider/PLL synt |
STK0040II STK0040II  |
SANYO |
HYB |
01+ |
Figure 1 shows the proper connection of t |
STK0049 STK0049  |
Darlington |
Hybrid |
|
The HS-0546RH and HS-0547RH are radiation harden |
STK0050 STK0050  |
SANYO |
MODULE |
00+ |
DESCRIPTION Positive power supply for the chip |
STK-0050 STK-0050  |
SANYO |
模块 |
|
Figure 1 shows a typical battery pack application |
STK0050II STK0050II  |
SANYO |
|
|
Notes a. The algebraic convention whereby the m |
STK0050MK2 STK0050MK2  |
|
|
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s Two serial (I2S-bus/Japanese) digital audio in |
STK0055 STK0055  |
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|
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Device programming and erasure are initiated thr |
STK0059 STK0059  |
|
moudle |
|
5) Next, a heat sink with lower SA than the one |
STK0060 STK0060  |
SANYO |
|
|
† Stresses beyond those listed under absol |
STK0060II STK0060II  |
SANYO |
|
|
The STK0060II/2/3/4 family of non-unity gain stab |
STK0060MK2 STK0060MK2  |
|
|
|
The three manuals listed in Table 1 are require |
STK0070 STK0070  |
|
DIP |
05+ |
|
STK0070II STK0070II  |
|
DIP |
05+ |
1. Hitachi neither warrants nor grants licenses |
STK0070MK2 STK0070MK2  |
|
|
|
The DMS-EB-AC/DC board includes provision |
STK0080 STK0080  |
SANYO |
MODULE |
N/A |
Activity LED polarity/operation/blink rate Full |
STK0080A STK0080A  |
|
|
|
H - High-Terminal Potentiometer. This is the high |
STK0080II STK0080II  |
SANYO |
|
|
Sound volume, tone and balance controls for car |
STK0080-II STK0080-II  |
|
|
|
BVDSSDrain-to-Source Breakdown Voltage-100 W |
STK0080MK2 STK0080MK2  |
|
|
|
† Stresses beyond those listed under absol |
STK0100 STK0100  |
|
|
|
Vcc = 2.7V~3.3V, TA = 0C to 70C/ -40C to 85C unle |
STK0100II STK0100II  |
SANYO |
STK |
2004+ |
(i.e. Ground) output voltage. In contrast, an un |
STK0105 STK0105  |
|
DIP |
05+ |
Freescales semiconductor products are classified |
STK011 STK011  |
SANYO |
模块 |
|
Control and safety devices for airplanes, |
STK-011 STK-011  |
SANYO |
模块 |
|
The IC also includes 4 readable input (I1..I4) p |
STK012 STK012  |
SANYO |
|
|
The IRU1261, using a proprietary process, combine |
STK013 STK013  |
SANYO |
|
|
The on-board oscillator supplies the signal for |
STK014 STK014  |
SANYO |
|
652
|
Integrated Adaptive Receive Equalization |
STK015 STK015  |
SANYO |
MODULE |
N/A |
The A-to-B enable (CEAB) input must be low to & |
STK-015 STK-015  |
SANYO |
SIP |
00+ |
The ICC supply current is reduced by applying a |
STK016 STK016  |
SANYO |
|
|
Features/Benefits: •QuadRomTM frequency s |
STK018 STK018  |
SANYO |
|
|
The CPU features two sets of functional units. E |
STK0182 STK0182  |
|
|
|
This is the high impedance input to the FSK volt |
STK020 STK020  |
|
|
|
Low power loss, high efficiency. High surge ca |
STK022 STK022  |
|
|
|
Notes 1. Derate linearly from 25C at a rate of |
STK023 STK023  |
|
|
|
A good compromise for (1) and (2) is to s |
STK024 STK024  |
|
|
|
Figure 1 shows the main screen of typical Maxim R |
STK0241 STK0241  |
SANYO |
|
|
The RC4700 incorporates all system contro |
STK025 STK025  |
SANYO |
|
|
NOTES : 1. In case of 40MHz Frequency, CL1 can b |
STK0260 STK0260  |
|
|
|
Features Serial Input Bus 2.0 MHz |
STK0260F STK0260F  |
AUK |
06+ |
TO-220 |
the latches store information that was present o |
STK027 STK027  |
SANYO |
|
|
The advanced and highly flexible digital output |
STK029 STK029  |
SANYO |
|
|
Note 2. Regulation is measured at constant junct |
STK0292 STK0292  |
|
|
|
The IF section uses a true-synchronous vision IF |
STK030 STK030  |
|
DIP |
05+ |
Klares Miniatur-Kunststoffgehäuse, seitlich |
STK031 STK031  |
|
|
|
The output drivers in the HIP6602B have the capac |
STK032 STK032  |
SANYO |
|
|
The DS90C385A is a pin to pin compatible replace |
STK035 STK035  |
|
SIP |
|
clock stream is corrupted during a transmission. |
STK036 STK036  |
SANYO |
|
04+ |
Power up State Programming At power up in serial |
STK040 STK040  |
SANYO |
|
|
One External Resistor Sets the Frequency 1kHz to |
STK0401 STK0401  |
SANYO |
|
04+ |
This device requires the 3-STATE control input G |
STK041 STK041  |
|
DIP |
05+ |
more than 99% when deselected (CE HIGH or both BL |
STK043 STK043  |
SANYO |
|
|
Acknowledge is a software convention used to pro |
STK0460 STK0460  |
AUK |
TO-220F |
06环保 |
7. Multifunctional PWM The family device |
STK0460F STK0460F  |
AUK |
06+ |
TO-220 |
W0, W1, W2Wipers of the Potentiometers. These pin |
STK0460FN STK0460FN  |
AUK |
TO-220F |
2007 |
Keyboard Events Wake-up on any key Supports p |
STK050 STK050  |
SANYO |
ZIP16 |
N/A |
When handling individual devices (which a |
STK054 STK054  |
SANYO |
|
|
3. Always set IOCC PAGE1 bit 0 = 1 otherwise part |
STK-054 STK-054  |
|
|
|
Portable Instrumentation Automatic Test Equipmen |
STK055 STK055  |
SANYO |
|
03+ |
The information herein is given to describe cert |
STK056 STK056  |
SANYO |
|
|
The Processor Enable bit (bit 6) places e |
STK-056 STK-056  |
|
|
|
PSoC Designer sets up power-on initialization ta |
STK057 STK057  |
SANYO |
|
04+ |
2. MATERIAL: Units are encapsulated in a low the |
STK058 STK058  |
SANYO |
|
|
The MAX1578/MAX1579 provide four regulated output |
STK060 STK060  |
SANYO |
|
04+ |
The HC4049 and HC4050 are fabricated with high-s |
STK067 STK067  |
|
|
|
The information provided herein is believed to b |
STK068 STK068  |
|
|
|
EEPROM is not required for configurations with e |
STK070 STK070  |
SANYO |
MODULE |
04+ |
The Fairchild Switch FST16862 provides 20-bits o |
STK071 STK071  |
SANYO |
|
|
5. The dominant wavelength, ëd, is derived |
STK073 STK073  |
|
|
|
Organization . . . 512K 16 2 Banks 3.3-V Power |
STK075 STK075  |
SANYO |
|
|
Note that the STK075 has no provisions for detect |
STK075G STK075G  |
SANYO |
|
03+ |
Serial data from the demodulator is passed first |
STK0760 STK0760  |
AUK |
TO-220F |
06+ |
T510 capacitor series are suggested over many ot |
STK0765 STK0765  |
ST |
DIP-32 |
06+ |
The Flash program memory supports both parallel |
STK077 STK077  |
|
|
|
DESCRIPTION These dual channel dio |
STK077G STK077G  |
SANYO |
|
|
The principle of operation behind the two DPLLs i |
STK-077G STK-077G  |
SANKEN |
SIP |
99 |
Low profile (5.9mm max. height) SMD type. Unshie |
STK078 STK078  |
|
|
|
The LPS input is considered inactive if it remai |
STK078-105 STK078-105  |
|
DIP |
05+ |
This family is a 16M bit dynamic RAM organized 4, |
STK078G STK078G  |
SANYO |
|
07+ |
(1) Stresses in excess of those listed above may |
STK080 STK080  |
SANYO |
SIP |
|
|
STK080G STK080G  |
SANYO |
|
|
NOTES: 1. Stresses greater than those listed un |
STK082 STK082  |
SANYO |
|
|
The 224 I/O cells are grouped into 14 sets of 16 |
STK082-105 STK082-105  |
|
DIP |
05+ |
These TTL circuits feature dual 1-line-to-4-line |
STK082G STK082G  |
SANYO |
|
|
A (sawtooth) reference signal has to be applied |
STK083 STK083  |
|
DIP |
05+ |
64-Bit SDRAM interface 66 MHz to 100 MHz freq |
STK083G STK083G  |
|
DIP |
05+ |
The LXT974 and LXT975 are four-port PHY Fast Eth |
STK084 STK084  |
SANYO |
|
|
The attack and decay time constant of the AGC is |
STK084G STK084G  |
SANYO |
|
|
Port 1, I/O. Port 1 functions as both an 8-bit, b |
STK085 STK085  |
|
|
|
‡ Stresses beyond those listed under absol |
STK-085 STK-085  |
STK |
|
98+ |
Port 3 Port 3 is an 8-bit bidirectional I O port |
STK0850F STK0850F  |
AUK |
06+ |
TO-220 |
These display devices are designed to provide |
STK086 STK086  |
|
|
|
7 channels of ESD protection designed to meet I |
STK086G STK086G  |
|
DIP |
05+ |
Single-chip CardBus host adapter Supports 2 PC |
STK089 STK089  |
SANYO |
HYB |
N/A |
* If bit 2 of the corresponding Connection High |
STK100/12 STK100/12  |
|
|
|
The STK100/12 uses advanced trench technology to |
STK1000 STK1000  |
|
|
|
The IS93C56-3 is controlled by seven 9-bit instr |
STK101 STK101  |
|
|
|
The IDT octal buffer/line driver is built |
STK1030 STK1030  |
|
Hybrid |
|
The CM2010 connects between a video graphics con |
STK1035 STK1035  |
SANYO |
STK |
2004+ |
There are two limitations on the power ha |
STK1039 STK1039  |
|
Hybrid |
|
UVDLY (Under Voltage Delay) Pin 20 - This is an a |
STK1040 STK1040  |
SANYO |
STK |
2004+ |
Unlike masked or programmable gate arrays, which |
STK1045 STK1045  |
SANYO |
STK |
2004+ |
These devices feature 3-state outputs designed s |
STK1049 STK1049  |
SANYO |
|
04+ |
(Note 1) Derate 0.5mA above 70C. (Note 2) 50% du |
STK1050 STK1050  |
|
|
|
Fully compliant with USB v1.1 specification and |
STK1050A STK1050A  |
SANYO |
STK |
2004+ |
Outputs the extracted generic flow control bits |
STK1050II STK1050II  |
SANYO |
STK |
2004+ |
A: The value of R JA is measured with the device |
STK1050MK2 STK1050MK2  |
|
|
|
NOTES:1. Maximum voltage must be adjusted for po |
STK1059 STK1059  |
SANYO |
STK |
2004+ |
Round Control. When this control is HIGH, a one |
STK1060 STK1060  |
SANYO |
|
-- |
Test conditions unless otherwise noted. 1. T = |
STK1060II STK1060II  |
SAN |
IC |
|
|
STK1060MK2 STK1060MK2  |
|
|
|
This is a diagram of a typical application |
STK1070 STK1070  |
|
ZIP-12P |
|
Please be aware that an important notice |
STK1070A STK1070A  |
|
|
|
The FLEx36 family includes 1M, 2M, 4M and 9M pipe |
STK1070II STK1070II  |
SANYO |
|
2007+ |
• High speed tAA = 12 ns • |
STK1070MK2 STK1070MK2  |
|
|
|
|
STK1077 STK1077  |
|
|
|
Note : 1. * : These pins are not used in this mo |
STK1080 STK1080  |
SANYO |
STK |
2004+ |
Note: These are stress ratings only. Stresses ex |
STK1080II STK1080II  |
SANYO |
STK |
2004+ |
PLL1, CLKA, and CLKB each have multiple registers |
STK10C168-C35 STK10C168-C35  |
SIMTEK |
93+ |
AUCDIP28 |
* On products compliant to MIL-PRF-38535, this p |
STK10C48-P45 STK10C48-P45  |
SIMTEK |
|
DIP |
Radiation Hardened up to 1 x 106 Rads (Si) Sing |
STK10C48-S35I STK10C48-S35I  |
SIMTEK |
SOP |
07+ |
For the AT49BV1614(T), the BYTE pin controls whe |
STK10C48-S45 STK10C48-S45  |
SIMTEK |
|
SOP28 |
1. Current consumption is measured in the measure |
STK10C68 STK10C68  |
|
|
|
Supports PentiumIII, K6, and Socket 7 CP |
STK10C68-45PI STK10C68-45PI  |
STK |
DIP |
|
A page write is initiated the same as byte write, |
STK10C68-5C45M STK10C68-5C45M  |
SIMTEK |
|
CDIP |
Ground. Oscillator input. Oscillator output. A |
STK10C68-C30 STK10C68-C30  |
|
|
|
When VCC is between 0 and 1.5 V, the device is i |
STK10C68-C45 STK10C68-C45  |
STMTEK |
CWDIP28窄金面 |
92+ |
The three transmitter operating modes C transmit |
STK10C68-P3 STK10C68-P3  |
|
|
|
The situation is different in the case of underv |
STK10C68-P35 STK10C68-P35  |
SIMTEK |
DIP-28 |
|
|
STK10C68P45 STK10C68P45  |
|
|
|
Single Supply for Read and Write: 2.7V to 3.6 (BV |
STK10C68-P45 STK10C68-P45  |
SIMTEK |
DIP28 |
2000 |
NOTES 1Temperature range is as follows: B Versio |
STK10C68-S35 STK10C68-S35  |
SIMTEK |
|
SOP28 |
TIA/EIA-644 Standard Operate With a Single 3.3-V |
STK10C68-S45 STK10C68-S45  |
SIMT.. |
SOP |
06+ |
Replaces SN74AS305 Maximum Output Skew of 1 ns |
STK11006 STK11006  |
SK |
|
97 |
Note 5: The maximum allowable power dissipation i |
STK1101 STK1101  |
SK |
SIP |
|
Copyright © 2002 Lattice Semiconductor Corp |
STK11100 STK11100  |
AMS |
BGA0909 |
04+ |
MB90895 series devices are 16-bit micro g |
STK11C48 STK11C48  |
|
|
|
Description Clock input. A[1:2] is the "tru |
STK11C48-P45 STK11C48-P45  |
SIMTEK |
DIP28 |
08+ |
To implement this feature, the tags must be prog |
STK11C68 STK11C68  |
MOT |
CDIP28 |
9124 |
|
STK11C68545 STK11C68545  |
|
|
|
The data written during the Write operation is co |
STK11C68-5K55M STK11C68-5K55M  |
Cypress Semiconductor Corp |
|
CDIP |
Oscillator Section (Note 4) Initial Accuracy V |
STK11C68-C35 STK11C68-C35  |
Cypress Semiconductor Corp |
. |
|
A digital audio receiver (U002) is provided for |
STK11C68-C35I STK11C68-C35I  |
Cypress Semiconductor Corp |
CDIP28 |
9514 |
The PCF85xxC-2 is a family of floating gate Elec |
STK11C68C55M STK11C68C55M  |
Simtek |
SOP |
9124 |
4Mbits (512k x 8 bits) organization FIFO Indepen |
STK11C68P30 STK11C68P30  |
|
|
|
Low Drive Reset. This bidirectional signal is eit |
STK11C68P45 STK11C68P45  |
|
|
|
SANYO assumes no responsibility for equipment fai |
STK11C68-P45 STK11C68-P45  |
SIMTEK |
DIP |
|
Hynix HYMD116725A(L)8-K/H/L series is unbuffered |
STK11C68-S35 STK11C68-S35  |
SIMTEK |
|
SOP28 |
|
STK11C68-S45 STK11C68-S45  |
N/A |
N/A |
N/A |
Transfer can be started from MSB or LSB Support |
STK11C68-SF45 STK11C68-SF45  |
Cypress Semiconductor Corp |
|
07+ |
Two times of receiving check Built-in oscillator |
STK11C68-SF45I STK11C68-SF45I  |
Cypress Semiconductor Corp |
N/A |
2006+ |
Note 2: CPD is defined as the value of the intern |
STK11C88 STK11C88  |
|
|
|
Selects Burst Order. When tied to GND selects lin |
STK11C88-N45 STK11C88-N45  |
STK |
SOP |
|
Applications using CPU generated controls must po |
STK11C88-N45I STK11C88-N45I  |
STMETK |
04+ |
SOP32 |
The Am29DS323D family consists of 32 megabit, 1. |
STK11C88-NF25 STK11C88-NF25  |
Cypress Semiconductor Corp |
N/A |
2006+ |
The LPV511 is a micropower operational amplifier |
STK11C88-NF25I STK11C88-NF25I  |
Cypress Semiconductor Corp |
N/A |
2006+ |
The IS24CXX (IS24C64-2, IS24C64-3, IS24C32-2 and |
STK11C88-NF45 STK11C88-NF45  |
Cypress Semiconductor Corp |
N/A |
2006+ |
• Input Voltage Range: 36 V to 75 V |
STK11C88-NF45I STK11C88-NF45I  |
Cypress Semiconductor Corp |
N/A |
2006+ |
|
STK11C88-P45 STK11C88-P45  |
|
|
|
small signal bandwidth from VREF to output up to |
STK11C88-S45 STK11C88-S45  |
|
|
|
programmable address/data which meet vari- ous |
STK11C88-SF25I STK11C88-SF25I  |
Cypress Semiconductor Corp |
N/A |
2006+ |
The MC14014B and MC14021B 8−bit stat |
STK11C88-SF45 STK11C88-SF45  |
Cypress Semiconductor Corp |
N/A |
2006+ |
Pin Function Supply Input. (VIN1 and VIN2 are i |
STK11C88-SF45I STK11C88-SF45I  |
Cypress Semiconductor Corp |
N/A |
2006+ |
If Military/Aerospace specified devices are requi |
STK11C88-W35 STK11C88-W35  |
|
|
|
4.3 Screening (JANTX AND JANTXV levels only |
STK1210DLQP STK1210DLQP  |
|
|
|
RSL (Pin 4): The slew control resistor sets the m |
STK12712-O STK12712-O  |
KRC |
06+ |
SOT-23 |
Figure 4 illustrates the differential or |
STK12C58-W45 STK12C58-W45  |
|
|
|
Recording level calibration pin. ∗ Cont |
STK12C68 STK12C68  |
|
|
2003 |
The MBRS130TRPbF surface-mount Schottky rectifier |
STK12C68545 STK12C68545  |
|
|
|
Industry's first TotalCMOS™ PLD - both CMO |
STK12C68-545 STK12C68-545  |
|
|
|
Compliance with ANSI X3T10/1142D SCSI Parallel |
STK12C68P45 STK12C68P45  |
SIMTEK |
DIP |
98+ |
• Fully asynchronous operation • Aut |
STK12C68-P45 STK12C68-P45  |
SIMTEK |
DIP |
06+ |
The 78P7200 is a line interface transceiver IC i |
STK12C68-P45I STK12C68-P45I  |
SIMTEK |
PDIP28 |
N/A |
Reset. An active high signal on this pin will put |
STK12C68-P55 STK12C68-P55  |
SIMTEK |
DIP |
07+ |
Margin Up: When this input is asserted to GND, th |
STK12C68-PF25 STK12C68-PF25  |
Cypress Semiconductor Corp |
N/A |
2006+ |
Temperature Sensor Output The temperature |
STK12C68-PF25I STK12C68-PF25I  |
Cypress Semiconductor Corp |
N/A |
2006+ |
Propagation Delay Tempco Prop Delay SkewRising T |
STK12C68-PF45 STK12C68-PF45  |
Cypress Semiconductor Corp |
N/A |
2006+ |
Electrical These devices use a modified 4 x 7 |
STK12C68-PF45I STK12C68-PF45I  |
Cypress Semiconductor Corp |
N/A |
2006+ |
Aside from jitter effects, noise and pulse distor |
STK12C68-S25 STK12C68-S25  |
05/ |
|
120 |
FEATURES • Compliant with ATM, SONET OC-3 |
STK12C68-S25I STK12C68-S25I  |
N/A |
N/A |
N/A |
The only external RF components needed for the tr |
STK12C68-S35 STK12C68-S35  |
04+ |
|
100 |
Low−Power Schottky TTL Load Over the |
STK12C68-S35I STK12C68-S35I  |
|
|
|
The HCPL-7850/7851 is an isolation amplifier t |
STK12C68S45 STK12C68S45  |
simtek |
simtek |
dc00 |
These ChipLEDs come either in two top emitting |
STK12C68-S45 STK12C68-S45  |
SIMTEK |
07+ |
|
• Timer0: 8-bit timer/counter with 8-bit p |
STK12C68S45I STK12C68S45I  |
|
|
|
The CS42416 integrated PLL provides a low-jitter |
STK12C68-S45I STK12C68-S45I  |
|
1242 |
05+ |
The K6F2008U2E families are fabricated by |
STK12C68-SF25 STK12C68-SF25  |
Cypress Semiconductor Corp |
N/A |
2006+ |
If, after the ISL6118 has latched off, and the fa |
STK12C68-SF25I STK12C68-SF25I  |
Cypress Semiconductor Corp |
N/A |
2006+ |
In environments that are particularly noisy it m |
STK12C68-SF45 STK12C68-SF45  |
Cypress Semiconductor Corp |
N/A |
2006+ |
The 74HC/HCT299 contain eight edge-triggered D-t |
STK12C68-SF45I STK12C68-SF45I  |
Cypress Semiconductor Corp |
|
07+ |
The A128 devices have six communication interfac |
STK12C68W45 STK12C68W45  |
SIMTEK |
|
1999 |
Description: The NTE5452 through NTE5458 are sen |
STK12C68-W45 STK12C68-W45  |
SIMTEK H |
|
9801 |
The output power as a function of the supply vol |
STK12C68-W55 STK12C68-W55  |
SIMTEK |
|
00 |
† Stresses beyond those listed under absol |
STK12C68-WF45 STK12C68-WF45  |
Cypress Semiconductor Corp |
|
|
Since G6 and G7 are input only pins any attempt |
STK12C69-S45 STK12C69-S45  |
SINTA |
|
00+ |
Figure 1 shows an application schematic, which d |
STK12C86-S30 STK12C86-S30  |
SIMTEK |
SOIC28 |
|
Hynix HYMD216M726A(L)6-J/M/K/H/L series is design |
STK12C86-S35 STK12C86-S35  |
SIMTEK |
SOIC28 |
|
The Rambus ® RIMMTM module is a gener |
STK12C86-W45 STK12C86-W45  |
|
|
|
G5131-25T11Uf G5131-26T11Uf G5131-27T11Uf G513 |
STK12N05 STK12N05  |
ST |
TO |
|
tr, tf0.11.0ns0.55 to 2.4V AC characterist |
STK12N05L STK12N05L  |
ST |
TO |
|
|
STK12N06 STK12N06  |
ST |
TO |
|
The input stage contains an Automatic Gain Contr |
STK12N06L STK12N06L  |
ST |
TO |
|
|
STK13003 STK13003  |
STM |
07+ |
|
The ZN409CE incorporates a precision dual |
STK14C88- STK14C88-  |
|
|
|
The LTC ®3406B-2 is a high efficiency monolit |
STK14C88-3N35 STK14C88-3N35  |
SIMTEK |
SOP |
06+ |
the latches store information that was present o |
STK14C88-3N35I STK14C88-3N35I  |
SIMTEK |
|
SOP32 |
The CY74FCT16841T and CY74FCT162841T are 20-bit |
STK14C883N45 STK14C883N45  |
SIMTEK |
|
0514 |
The design of the main power inductor in a switc |
STK14C88-3N45 STK14C88-3N45  |
SIMTEK |
|
07+ |
The adjustable version of the FAN2502/03 include |
STK14C88-3N45I STK14C88-3N45I  |
SIMTEK |
|
SOP32 |
• Compact Package • 8 mm (0.31 inch) |
STK14C88-3NF35 STK14C88-3NF35  |
Cypress Semiconductor Corp |
0620+ |
SOP32 |
BiMOS II devices have much higher data-in |
STK14C88-3NF35I STK14C88-3NF35I  |
Cypress Semiconductor Corp |
|
06+ |
3.1 POWER SUPPLY & VOLTAGE REFERENCE The int |
STK14C88-3NF45 STK14C88-3NF45  |
Cypress Semiconductor Corp |
SOP |
0626+ |
NOTES: A. CL includes probe and test-fixture cap |
STK14C88-3NF45I STK14C88-3NF45I  |
Cypress Semiconductor Corp |
|
08+ |
The electrical characteristic data has been deve |
STK14C88-C45I STK14C88-C45I  |
Cypress Semiconductor Corp |
CDIP32 |
|
Each device includes a voltage regulator |
STK14C88-N25 STK14C88-N25  |
CYPRESS |
00+ |
SOP-32 |
All minimum and maximum specifications ar |
STK14C88-N25I STK14C88-N25I  |
SIMTEK |
|
SOP32 |
Pin(40-39)&,Pin(37-36) Pin(1 |
STK14C88N35 STK14C88N35  |
ST |
SOP28 |
04/05+ |
The ADS1258 is a 16-channel (multiplexed), low- |
STK14C88-N35 STK14C88-N35  |
SIMTEK |
SOP |
N/A |
3.3V core power supply 3.3V power supply for CK4 |
STK14C88-N35.N45 STK14C88-N35.N45  |
SIEMENS |
SOP32W |
2007+ |
This publication is issued to provide outline in |
STK14C88-N35E STK14C88-N35E  |
SIMTEK |
|
|
edges of the laminated structure. The entire stru |
STK14C88-N35I STK14C88-N35I  |
SIMTEK |
01+ |
SOP-32 |
The wiper settings are controllable through an I |
STK14C88-N45 STK14C88-N45  |
SIMTEK |
SOP |
N/A |
Both versions can also be used as comparators. D |
STK14C88N-45 STK14C88N-45  |
SIMTEK |
SOP-32 |
|
loaded into the device. After the last bit of th |
STK14C88-N45I STK14C88-N45I  |
SIMTEK |
SOP32 |
04+ |
erly terminated without the STK14C88-N45I, the p |
STK14C88-NF25 STK14C88-NF25  |
Cypress Semiconductor Corp |
|
07+ |
The IC is designed specifically to work with app |
STK14C88-NF25I STK14C88-NF25I  |
Cypress Semiconductor Corp |
DC |
07+ |
Port 0: Port 0 is an open-drain, bi-directional I |
STK14C88-NF35 STK14C88-NF35  |
Cypress Semiconductor Corp |
N/A |
2006+ |
The reference included in the RC5051 is a precis |
STK14C88-NF35I STK14C88-NF35I  |
Cypress Semiconductor Corp |
|
|
Certain applications using semiconductor product |
STK14C88-NF45 STK14C88-NF45  |
Cypress Semiconductor Corp |
N/A |
2006+ |
Theseversatile devices are usefulfor driving a w |
STK14C88-NF45I STK14C88-NF45I  |
Cypress Semiconductor Corp |
|
06+ |
This document is a general product description a |
STK14CA8-N45 STK14CA8-N45  |
|
|
|
A simple sleep mode was incorporated in the modu |
STK14CA8-NF25 STK14CA8-NF25  |
Cypress Semiconductor Corp |
|
|
The XPLA3 architecture follows a simple timing m |
STK14CA8-NF25I STK14CA8-NF25I  |
Cypress Semiconductor Corp |
|
|
Fully differential Low noise 2.25 nV/Hz |
STK14CA8-NF35 STK14CA8-NF35  |
Cypress Semiconductor Corp |
|
|
In the intended application, it is expect |
STK14CA8-NF35I STK14CA8-NF35I  |
Cypress Semiconductor Corp |
|
|
The output signals of the SDA 9188-3X are analog |
STK14CA8-NF45 STK14CA8-NF45  |
Cypress Semiconductor Corp |
|
08+ |
© Cypress Semiconductor Corporation, 2004. T |
STK14CA8-NF-45 STK14CA8-NF-45  |
SIMTEK |
06+ |
TSOP |
Stanford Microdevices STK14CA8-NF-45 is a high p |
STK14CA8-NF45I STK14CA8-NF45I  |
Cypress Semiconductor Corp |
|
|
HN58X24xxSI series are two-wire serial interface |
STK14CA8-RF25 STK14CA8-RF25  |
Cypress Semiconductor Corp |
|
|
1. All high speed inputs and outputs are differe |
STK14CA8-RF25I STK14CA8-RF25I  |
Cypress Semiconductor Corp |
|
|
The STK14CA8-RF25I is an stereo audio power ampl |
STK14CA8-RF35 STK14CA8-RF35  |
Cypress Semiconductor Corp |
|
|
Note 1:Limits is 100% production tested at TA= +2 |
STK14CA8-RF35I STK14CA8-RF35I  |
Cypress Semiconductor Corp |
|
|
Load Mux. RRE = "1" and MSE = "1&q |
STK14CA8-RF45 STK14CA8-RF45  |
Cypress Semiconductor Corp |
|
|
A capacitive load on the regulators output will |
STK14CA8-RF45/TR STK14CA8-RF45/TR  |
SIMTEK |
|
08+ |
The MT3x7xB is a family of high performance DTMF |
STK14CA8-RF45I STK14CA8-RF45I  |
Cypress Semiconductor Corp |
0 |
08+ |
This link option selects the source of the RD in |
STK14CB8-N35 STK14CB8-N35  |
|
|
|
This device contains circuitry to protect the in |
STK14D88-N35 STK14D88-N35  |
|
|
|
The bq2050H Lithium Ion Power Gauge™ IC is |
STK14D88-RF25 STK14D88-RF25  |
Cypress Semiconductor Corp |
|
|
External clock option: The receiver can accept a |
STK14D88-RF45 STK14D88-RF45  |
Cypress Semiconductor Corp |
|
|
Output Voltage Amplitude and Serial Interface Cl |
STK14D88-RF45I STK14D88-RF45I  |
Cypress Semiconductor Corp |
|
|
3.1.1 SPI bus While SSB pin is pulled to "h |
STK14N05 STK14N05  |
ST |
TO |
|
They are fully static parts fabricated using dou |
STK14N06 STK14N06  |
ST |
TO |
|
The STK14N06 is a high-performance digital ampli |
STK14N10 STK14N10  |
ST |
TO |
|
Fujitsu resonators (C1, C3, C4 series) feature o |
STK15C68 STK15C68  |
|
|
|
The 16K-byte boot block can be used to store key |
STK15C68-P45 STK15C68-P45  |
SIMTEK |
DIP |
05+ |
The PCF84C12A, PCF84C22A and PCF84C42A are gene |
STK15C68-S45I STK15C68-S45I  |
|
|
|
Associated with each of the ten OR functions is |
STK15C68-W25I STK15C68-W25I  |
SIMTEK H |
|
01 |
• Ultrafast recovery 2.5 Amp rectifier ser |
STK15C68-W45I STK15C68-W45I  |
SIMTEK |
DIP |
|
Notes: 1. Absolute maximum ratings are limits b |
STK15C88 STK15C88  |
SIMTEK |
|
07/08+ |
BRAKE. When the BRAKE input goes Low the |
STK15C88-N25I STK15C88-N25I  |
|
SOP28 |
05+ |
The NL17SZ07 is a high performance single |
STK15C88-N35 STK15C88-N35  |
|
|
|
The IDT70V7399 is a high-speed 128Kx18 (2 |
STK15C88-N45 STK15C88-N45  |
N/A |
N/A |
N/A |
With reference to Figure 4, assume that VDD is r |
STK15C88-NF25 STK15C88-NF25  |
Cypress Semiconductor Corp |
|
|
Note 7: Min and Max limits are guaranteed by desi |
STK15C88-NF25I STK15C88-NF25I  |
Cypress Semiconductor Corp |
SOP28 |
05+ |
Note: 1. The inductor L2 is recommended to isol |
STK15C88-NF45 STK15C88-NF45  |
Cypress Semiconductor Corp |
|
. |
The product term allocator is a dynamic, configur |
STK15C88-NF45I STK15C88-NF45I  |
Cypress Semiconductor Corp |
SOP28 |
05+ |
The data strobe, associated with one data byte, s |
STK15C88P45 STK15C88P45  |
|
|
|
This document may not, in whole or in part be co |
STK15C88-P45 STK15C88-P45  |
STMTEK |
|
03/04+ |
FEATURE: Output frequency range 50khz ~ 1 |
STK15C88-S45 STK15C88-S45  |
SIMTEK |
SOP |
06+ |
• HiPerFREDTM Epitaxial Diodes - f |
STK15C88-S45I STK15C88-S45I  |
SIMTEK |
06+ |
SSOP-28 |
Electrostatic discharge can cause damage ranging |
STK15C88-SF25 STK15C88-SF25  |
Cypress Semiconductor Corp |
SOP28 |
05+ |
Notes: 1. Except for the rating Operating Tempera |
STK15C88-SF45 STK15C88-SF45  |
Cypress Semiconductor Corp |
|
08+ |
IOH = -12 mA IOL = 12 mA Measure between 0.8 V |
STK15C88-SF45I STK15C88-SF45I  |
Cypress Semiconductor Corp |
|
|
This series of Schottky diode chips are specific |
STK15C88-SF45ITR STK15C88-SF45ITR  |
Cypress Semiconductor Corp |
|
|
With FSK = Low the switch at pin XTO2 is closed, |
STK15C88W STK15C88W  |
|
|
|
(1) All typical values are at TA = +25C. (2) In |
STK15C88-W STK15C88-W  |
|
|
|
If the part is attached in a reflow oven, the tem |
STK15C88-W25 STK15C88-W25  |
SIMTEK |
|
9725 |
Output enable terminal: no matter in what phase M |
STK15C88W45 STK15C88W45  |
SIMTEK |
|
99+ |
Notes: 1. Load and Line Regulation are specifie |
STK15C88-W45 STK15C88-W45  |
SIMTEK |
|
03/04+ |
Chip Enable Out output. This signal is asserted |
STK15C88-WF45I STK15C88-WF45I  |
|
|
|
Flame-resistant Suppress combustion and s |
STK16C68-W45 STK16C68-W45  |
SIMTEK H |
|
01 |
Enhanced N channel FET with no inherent diode to |
STK16C88-3WF45 STK16C88-3WF45  |
SIMTEK |
DIP28 |
|
The HT27LC020 chip family is a low-power, 2048K |
STK16C88-W45 STK16C88-W45  |
SIMTEK |
|
03+ |
The transmitter contains a laser driver circuit |
STK16C88-WF25 STK16C88-WF25  |
Cypress Semiconductor Corp |
|
|
Controller (host) sends a start bit. &nbs |
STK16C88-WF25I STK16C88-WF25I  |
Cypress Semiconductor Corp |
|
|
VBB is an analog input which establishes the thre |
STK16C88-WF45 STK16C88-WF45  |
Cypress Semiconductor Corp |
|
08+ |
The flip-flop is set and reset by ac |
STK16C88-WF45I STK16C88-WF45I  |
Cypress Semiconductor Corp |
|
|
n 5 Volt Read, Program, and Erase C Mini |
STK16CA8-W25 STK16CA8-W25  |
|
|
|
Motherboard (LOM) or Network Interface Ca |
STK16N10L STK16N10L  |
ST |
TO |
|
Gate-to-Source Forward Leakage Gate-to-Source |
STK1791CE STK1791CE  |
|
|
|
Notes: (1) Clip mounting (on case), where lead |
STK17N10 STK17N10  |
ST |
TO |
|
Positive digital supply pin. This pin should be |
STK17T88-RF25I STK17T88-RF25I  |
Cypress Semiconductor Corp |
|
|
Wide data capture range (+/- 1.5 channel |
STK17T88-RF45I STK17T88-RF45I  |
Cypress Semiconductor Corp |
|
|
Dimensions are in inches. Metric equivalents a |
STK17TA8-RF25I STK17TA8-RF25I  |
Cypress Semiconductor Corp |
|
|
Complete Power Management Solution for USB Bus-P |
STK17TA8-RF35I STK17TA8-RF35I  |
SIMTEK |
04+ |
SSOP |
Compatible with Microsoft WinXP, WinME, Win2K SP |
STK17TA8-RF45 STK17TA8-RF45  |
Cypress Semiconductor Corp |
04+ |
SSOP |
Measurements made on production test board. Thi |
STK17TA8-RF45I STK17TA8-RF45I  |
Cypress Semiconductor Corp |
04+ |
SSOP |
Description Output High Current Output |
STK181 STK181  |
|
|
|
resistor segment towards the VH/RH terminal. Si |
STK181B STK181B  |
SANYO |
|
|
1) Worst case package. 2) Max number of output |
STK181C STK181C  |
|
|
|
The MC74HC1G02 is a high−speed CMOS |
STK1828EF STK1828EF  |
|
|
|
Spectrum. The finite Fourier transform (FFT) of |
STK1828SF STK1828SF  |
AUK |
SOT-23 |
|
A bidirectional parallel port that includes &nb |
STK183 STK183  |
|
|
|
micropackage. The HCC/HCF4000B, HCC/HCF4001B, HC |
STK183BC STK183BC  |
|
|
|
The processor features a full set of program cont |
STK183BC-M STK183BC-M  |
|
|
|
|
STK185B STK185B  |
sanyo |
|
|
Specifications to -40C are guaranteed by design a |
STK18N05 STK18N05  |
ST |
TO |
|
TA = 0C to 70C / -40C to 85C (I), unless otherwis |
STK18N06 STK18N06  |
ST |
TO |
|
NOTES: 1. Stresses greater than those listed un |
STK18N06L STK18N06L  |
|
|
|
Indicates to the IA21140AF that access to the bus |
STK190-010 STK190-010  |
SANYO |
ZIP-12P |
|
In a typical application, the Y and C input sign |
STK190-020 STK190-020  |
SANYO |
单列-12 |
C4.D4 |
The TMS320C672x floating-point digital signal pr |
STK190-050 STK190-050  |
STK |
SIP |
SIP |
1 Prior to the onset of overvoltage clamping. For |
STK190-110 STK190-110  |
SANYO |
单列-9 |
3J.C4 |
5.2.2 Framing Functions The ST20196 incorporate |
STK2025 STK2025  |
|
|
|
The AX432 series are three-terminal adjustable re |
STK2025M STK2025M  |
|
|
|
Figure 2 shows a Bergerton diagram for switching |
STK2028 STK2028  |
|
|
|
Motorolas MPXAZ4115A series sensor integr |
STK2028B STK2028B  |
|
|
|
The LCX16373 contains sixteen non-inverting latc |
STK2028MK2 STK2028MK2  |
|
|
|
Controller (host) sends a start bit. &nbs |
STK2029 STK2029  |
SANYO |
HYB |
02+ |
Multiple pulse inputs (repetitive pulse inputs) c |
STK2029M STK2029M  |
|
|
|
The Fairchild Switch FSTU16861 provides 20-Bits |
STK2030 STK2030  |
|
|
|
|
STK2038 STK2038  |
SANYO |
MOUDLE |
N/A |
14-Bit (XRD9814) or 16-Bit (XRD9816) &nb |
STK2038B STK2038B  |
|
|
|
Both circuits have three binary select inputs (A |
STK2038II STK2038II  |
SANYO |
|
652
|
The HC174 and HCT174 are edge triggered flip-flo |
STK2038IV STK2038IV  |
|
|
|
Number of channels : 6 (8/16-bit 6 channels) P |
STK2038MK2 STK2038MK2  |
|
|
|
To keep the RC4700s high-performance pipe |
STK2040 STK2040  |
SANYO |
|
|
This pin is internally connected to the sync dete |
STK2048 STK2048  |
|
|
|
The Ultra37000 devices operate with a 5V supply a |
STK2048II STK2048II  |
|
300 |
|
This is a small PCB that houses the STK2048II sen |
STK2048IV STK2048IV  |
|
|
|
Reader Response: Conexant strives to produce qual |
STK2050 STK2050  |
|
|
|
Note 4: The CMRR with a voltage gain, AV, larger |
STK2068 STK2068  |
SANYO |
HYB |
01+ |
|
STK2068II STK2068II  |
SANYO |
模块 |
|
|
STK20C04-W45 STK20C04-W45  |
SIMTEK |
DIP |
|
The AT84CS001 DMUX is started by the ASYNCRST co |
STK20C04-WF45 STK20C04-WF45  |
SIMTEK |
N/A |
2006+ |
Program Erase Enable input VPEN, program |
STK2100II STK2100II  |
|
|
|
Clock high pulse width Clock low pul |
STK2101 STK2101  |
|
|
|
Electrical characteristics are guaranteed over t |
STK2110 STK2110  |
|
|
|
Hynix HYMD116G725A(L)8-K/H/L series is registered |
STK2110X STK2110X  |
STK |
ZIP-12 |
07+/08+ |
Dimensions InchesMillimeters &nb |
STK2125 STK2125  |
SANYO |
05+/06+ |
|
The 8K EEPROM is capable of a 16-byte page write. |
STK2129 STK2129  |
|
|
|
If you have any marketing or sales questions, ple |
STK2135 STK2135  |
SANYO |
STK |
2004+ |
Widebus Family Designed to Be Used in Vo |
STK2139 STK2139  |
|
|
|
† Stresses beyond those listed under absol |
STK2139M STK2139M  |
SK |
SIP |
|
The CS4344 family members are complete, stereo d |
STK2145 STK2145  |
SANYO |
STK |
2004+ |
Luminance Output A 75 Ω termination resist |
STK2155 STK2155  |
|
|
652
|
(2) The technical information described in this |
STK2230 STK2230  |
SANYO |
|
|
Meets Intels Mobile 133.3MHz Chips |
STK2240 STK2240  |
SANYO |
|
|
Active High Master Reset. When logic HIGH, the i |
STK2250 STK2250  |
SANYO |
|
|
A downstream PLL, contained in a clock buffer IC |
STK2260 STK2260  |
|
Hybrid |
|
This combination of excellent dc performance wit |
STK22C48 STK22C48  |
|
|
|
¶ Time required for the integrated PLL circ |
STK22C48-N25I STK22C48-N25I  |
SIMTEK |
01+ |
SOP |
The device offers complete compatibility with the |
STK22C48-N45 STK22C48-N45  |
STK |
SOP28 |
|
Note 6: The input bias currents are junction leak |
STK22C48-NF25 STK22C48-NF25  |
Cypress Semiconductor Corp |
N/A |
2006+ |
HIGH SPEED: fMAX = 180MHz (TYP.) at VCC = 5V L |
STK22C48-NF25I STK22C48-NF25I  |
Cypress Semiconductor Corp |
N/A |
2006+ |
Fully compatible with 16550 and 16450 devices E |
STK22C48-NF45 STK22C48-NF45  |
Cypress Semiconductor Corp |
N/A |
2006+ |
This is not an extensive capacitor list. |
STK22C48-NF45I STK22C48-NF45I  |
Cypress Semiconductor Corp |
|
08+ |
|
STK22C48-S45 STK22C48-S45  |
|
|
|
The CD54AC161/3A and CD54ACT161/3A are synchrono |
STK22C48-SF25 STK22C48-SF25  |
Cypress Semiconductor Corp |
N/A |
2006+ |
Available in the Texas Instruments NanoStarɽ |
STK22C48-SF25I STK22C48-SF25I  |
Cypress Semiconductor Corp |
N/A |
2006+ |
Test Conditions/Comments Sampling CLKIN/128, 3.5 |
STK22C48-SF45 STK22C48-SF45  |
Cypress Semiconductor Corp |
N/A |
2006+ |
These INFINEON modules are industry standard 144 |
STK22C48-SF45I STK22C48-SF45I  |
Cypress Semiconductor Corp |
N/A |
2006+ |
The LCX16373 contains sixteen D-type latches wit |
STK22C48-W45 STK22C48-W45  |
SIMTEK H |
|
01 |
TX voice (Mic.) inputs, selectable by SW1 availa |
STK22N05 STK22N05  |
ST |
TO |
|
used to reduce the width of the deadband to acce |
STK22N06 STK22N06  |
ST |
TO |
|
The Schottky Power Rectifier employs the |
STK23N05L STK23N05L  |
ST |
TO |
|
• Internal self-timed write cycle • |
STK23N06L STK23N06L  |
ST |
TO |
|
The VSX60 Series are dual output converters with |
STK25C48 STK25C48  |
|
|
|
The MBM29DL16XTE/BE are a 16M-bit, 3.0 V-only Fl |
STK25C48W45 STK25C48W45  |
|
|
|
Count Enable Parallel Input Count Enable Trickle |
STK25C48-W45 STK25C48-W45  |
SIMTEK |
|
03/04+ |
CAUTION ESD (electrostatic discharge) sensitive |
STK290-010 STK290-010  |
|
|
|
the device can work also with dynamic ones). Man |
STK2N50 STK2N50  |
ST |
TO |
|
Reference Clock. This input is the clock frequen |
STK2N52 STK2N52  |
SGS |
|
97 |
Note 3: The maximum power dissipation must be der |
STK2N60 STK2N60  |
|
|
|
Inhibit: The Inhibit pin is an open-collector/dra |
STK2N80 STK2N80  |
ST |
TO |
|
The grounded Co-Planar Wave Guide (G-CPW) PCB in |
STK2N80PL STK2N80PL  |
|
|
|
Time timer and a Watchdog unit. The Real-Time Cl |
STK2NA60 STK2NA60  |
ST |
TO |
|
The 78P2253 is a transceiver IC designed for 139 |
STK2NB80 STK2NB80  |
|
|
|
The HYM72V32C756AT8 H-Series are high spe |
STK300/16E STK300/16E  |
|
|
|
Places the 1-bit bypass register between the TDI |
STK301-020 STK301-020  |
|
ZIP-18 |
|
SDRAM Controller 64-bit data bus. Up to 90MHz |
STK3033C STK3033C  |
SANKEN |
|
02+ |
matching resistors. In CMI mode the transmitter |
STK3041 STK3041  |
SANYO |
|
|
(*) Typical temperature coefficient for all VDD |
STK3041A STK3041A  |
|
|
|
Features International standard packages |
STK3042 STK3042  |
SANYO |
|
|
demodulator goes to an ATSC A/53 coding Forward |
STK3042A STK3042A  |
|
|
|
16 Channels 12-bit (4096 Steps) Grayscale PWM Co |
STK3042II STK3042II  |
SANYO |
|
|
s Unique, patent-pending input termination and V |
STK3042IIA STK3042IIA  |
|
|
|
Supports PIO mode 4, both at 16.6 Mbytes/second |
STK3042III STK3042III  |
SANYO |
HYB |
98+ |
The gate drive ready pin (GDR) is used to indicat |
STK3042MK2 STK3042MK2  |
|
|
|
There are two kinds of logic blocks, the Program |
STK3042MK2A STK3042MK2A  |
SANYO |
|
04+ |
when the CLOCK INHIBIT signal is high. A high R |
STK3042MK3 STK3042MK3  |
SANYO |
DIP |
04/05+ |
The device also features Personal Video Recordin |
STK3044 STK3044  |
SANYO |
SIP-15 |
00+ |
Multi-Input Wake Up (on the 8-bit Port L) Brown |
STK-3044 STK-3044  |
|
|
|
Distributor: Electro-Stock www.electrostock.com |
STK3048 STK3048  |
|
(LX)high-frequency |
|
n Sector Protection C Sectors may be lock |
STK3048A STK3048A  |
SANYO |
HYB |
98+ |
BUFFER TO MAIN MEMORY PAGE PROGRAM WITH BUILT-IN |
STK-3048A STK-3048A  |
|
|
|
Palladium plating is used on the terminal pins. A |
STK3048II STK3048II  |
SANYO |
|
04+ |
R1,R2=15W, 1/2 watt R3,R4=15W, 1 watt L1,L3=1 1 |
STK3050 STK3050  |
|
|
|
FEATURES 40 MSPS Correlated Double Sampler (CDS |
STK3055E STK3055E  |
N/A |
05+ |
TO |
The DS600 is a 0.5C accurate analog-output tempe |
STK3056 STK3056  |
|
|
|
TAOperating free-air temperature−4085 |
STK-3056 STK-3056  |
SK |
|
|
The RC2207 is designed to operate over a power s |
STK3061Y STK3061Y  |
SANYO |
模块 |
|
and Class C (Exceeding 400 V) per Machine |
STK3062 STK3062  |
N/A |
sanyo |
05+ |
KEY FEATURES n 2k bytes or 4k bytes Flash Progr |
STK3062II STK3062II  |
SANYO |
模块 |
|
The MC74HC1G02 is a high−speed CMOS |
STK3062IIA STK3062IIA  |
SANYO |
HYB |
97+ |
Regulates voltage over a broad operating current |
STK3062III STK3062III  |
SANYO |
HYB |
04+ |
The ADCMP565 is an ultrafast voltage comparator |
STK3062IV STK3062IV  |
|
|
|
This center tap Schottky rectifier series has bee |
STK3062MK2 STK3062MK2  |
|
|
|
The second solution can be used if all digits' se |
STK3062MK3 STK3062MK3  |
|
|
|
The ADP3806 is a complete Li-Ion battery-charging |
STK3076 STK3076  |
|
|
|
The sensing element, capable to detect the accel |
STK-3076 STK-3076  |
SK |
|
|
8-bit resolution. ADC gain adjust. 2 GHz full p |
STK3081Y STK3081Y  |
SANYO |
模块 |
|
OSC1, OSC2 are connected to an RC network |
STK3082 STK3082  |
N/A |
sanyo |
05+ |
Notes: 3. The loser of the port arbitrati |
STK3082A STK3082A  |
|
|
|
RTCF: Real Time Clock Fail BitVolatile This bit |
STK3082II STK3082II  |
SANYO |
摸块 |
|
The Technical Support BBS, known as AESOP (Applic |
STK3082IIA STK3082IIA  |
SANYO |
|
02+ |
The STK3082IIA, Tachyon TS, is a second-genera |
STK3082III STK3082III  |
SANYO |
MODULE |
N/A |
The CBTLV16210 operates as a single 20-bi |
STK3082MK2 STK3082MK2  |
|
|
|
CS falling edge to first SCLK falling edge. SCL |
STK3082MK3 STK3082MK3  |
|
|
|
Writing of memory data is performed in ei |
STK3101 STK3101  |
|
|
|
On the MPC859DSL, the SCC (SCC1) is for e |
STK3101Y STK3101Y  |
|
|
07+ |
The IRU3027 controller IC is specifically designe |
STK3102 STK3102  |
SANYO |
|
|
Data Setup Time Data Hold Time Address Set-up |
STK3102II STK3102II  |
SANYO |
|
|
A time delayed reset can be accomplished with th |
STK3102IIA STK3102IIA  |
SANYO |
HYB |
04+ |
Figure 1 shows a simplified schematic of one hal |
STK3102III STK3102III  |
SANYO |
HYB |
|
A last alternative for calibrating your PC clock, |
STK3102-III STK3102-III  |
|
|
|
The Freescale manuals are available on the Frees |
STK3102IV STK3102IV  |
SANYO |
MODULE |
04+ |
The HA-460 Series of quartz crystal oscillators |
STK3102-IV STK3102-IV  |
|
|
|
Sensitivity is defined as the average signal lev |
STK3102MK2 STK3102MK2  |
SANYO |
SIP15 |
03+ |
*Absolute maximum ratings apply at 25C, unless o |
STK3102MK3 STK3102MK3  |
SANYO |
|
-- |
Figure 5 shows the effects of a fast transient on |
STK3106 STK3106  |
SANYO |
MODULE |
N/A |
The combination of narrow nonlinear range and lo |
STK311-120 STK311-120  |
|
|
|
TOUT - This pin is the buffered output of the tem |
STK3120C STK3120C  |
|
|
DIP |
Typical Data is at TA = +25C and VCC = 5 V and is |
STK3122 STK3122  |
SANKEN |
MODULE |
N/A |
The center tap Schottky rectifier module has bee |
STK3122II STK3122II  |
SANYO |
|
|
Surface mount board layout is a critical |
STK3122III STK3122III  |
|
Hybrid |
|
The ST7263 Microcontrollers form a sub family of |
STK315 STK315  |
|
00+ |
1450
|
INPUT Initial Offset Voltage vs Tempera |
STK3152 STK3152  |
SANYO |
|
|
The error amplifier compares a sample of the dc- |
STK3152II STK3152II  |
SANYO |
HYB |
04+ |
Fifth Generation HEXFETs from International Rect |
STK3152III STK3152III  |
SANYO |
HYB |
03+ |
Notes: 1. CX1 must be placed within 0.7 cm of t |
STK3156 STK3156  |
|
|
|
The XC2173 series are high frequency, low power |
STK3240C STK3240C  |
|
|
DIP |
DISP high disables the LED display. DISP tied to |
STK3400A STK3400A  |
|
ZIP-21 |
|
Single channel 5 V, 3.3 V and 2.5 V operation |
STK3400B STK3400B  |
|
|
|
The broadband MMIC amplifier can be directly app |
STK3400BS STK3400BS  |
|
|
|
|
STK3400C STK3400C  |
STK |
SIP |
1995 |
Before a START condition is detected, CS, CLK, a |
STK3400E STK3400E  |
|
|
|
The IR 3310(S) is a Fully Protected 4 terminal hi |
STK3400M STK3400M  |
|
|
|
Calibration Cycle Initiate. A minimum 80 input c |
STK350-000 STK350-000  |
SANSYO |
|
|
The Z86319 is a member of the Z8 family of CMOS |
STK350-010 STK350-010  |
SANYO |
STK |
2004+ |
move one resistor segment towards the VH/RH ter |
STK350-010A STK350-010A  |
SANYO |
模块 |
|
n Variable power management n Packaged in 6-le |
STK350-020 STK350-020  |
SANYO |
STK |
2004+ |
• ARCHITECTURE FEATURES Enhanced P |
STK350-030 STK350-030  |
SANYO |
|
|
Serial Peripheral Interface (SPI) : a ki |
STK350-040 STK350-040  |
SANYO |
STK |
2004+ |
Maximum rating STK350-040he maximum ratings are |
STK350-050 STK350-050  |
SANYO |
STK |
2004+ |
Input-Output Enable, asynchronous input, |
STK350-130 STK350-130  |
SANYO |
|
|
1.1 Scope. This specification covers the |
STK350-130A STK350-130A  |
STK |
07+/08+ |
|
The 24XX128 supports a bidirectional 2-wire bus |
STK350-230 STK350-230  |
SANYO |
|
|
These devices, feature an enhanced automatic po |
STK350-230A STK350-230A  |
SANYO |
|
652
|
Digital Pixel Inputs These pins accept digital p |
STK350-230-E STK350-230-E  |
|
|
|
The MAU400 series has limitation of maxim |
STK350-430 STK350-430  |
SANYO |
HYB |
03+ |
|
STK350-530 STK350-530  |
|
|
|
|
STK365051II-Y STK365051II-Y  |
|
|
|
State-of-the-Art Advanced BiCMOS Technology (ABT |
STK390-010 STK390-010  |
SANYO |
|
01+ |
Note 7: FO = 0V (internal oscillator) or fEOSC = |
STK390-040 STK390-040  |
|
|
|
♦ Adjustable Accurate DPWM Frequency with |
STK390-110 STK390-110  |
SANYO |
SIP |
00+ |
Deviation Limiter In: Input to the on-chip deviat |
STK390-120 STK390-120  |
SANYO |
|
|
Feedback Disable: This input controls the state o |
STK390-910 STK390-910  |
SANKEN |
厚膜 |
|
NOTES 1I/P pin Logic 1 = 5 V, Logic 0 = GND. It |
STK390-910(1DB) STK390-910(1DB)  |
SANYO |
|
02+ |
On-Chip Data RAM 1 Kbyte Critical Variable Stora |
STK391 STK391  |
|
|
|
Figure 3. Input/Output Block. Each IOB includes |
STK391-020 STK391-020  |
SANKEN |
ZIP-15 |
04+ |
• Alert specification forum (ASF 1.0 suppo |
STK391-020-E STK391-020-E  |
|
|
|
Maximum resolution and accuracy may be obtained |
STK391-110 STK391-110  |
SANYO |
SIP |
98+ |
|
STK391-110S STK391-110S  |
STK |
ZIP |
ZIP |
|
STK391-110S(JP) STK391-110S(JP)  |
|
|
|
The STK391-110S(JP) is a surface mountable flip |
STK391-120 STK391-120  |
SANYO |
SIP-10P |
2002 |
The fixed 2.5-V output controller uses an intern |
STK391-220 STK391-220  |
N/A |
SANYO |
04+ |
Any offset and/or gain calibration procedures sh |
STK392/120E STK392/120E  |
|
|
|
Electrical Characteristics (Tc=25) Item |
STK392-010 STK392-010  |
SANYO |
DIP |
06+ |
For packing material that is returned to us uns |
STK392-020 STK392-020  |
SANYO |
MODULE |
02+ |
The MX803A is a full-duplex device for use with |
STK392-020E STK392-020E  |
|
|
|
The TSB41AB3 provides the digital and analog tra |
STK392-020-E STK392-020-E  |
|
|
|
All synchronous inputs pass through input registe |
STK392-030 STK392-030  |
SANYO |
|
|
The current source provides a closely reg |
STK392-040 STK392-040  |
SANYO |
MODULE |
N/A |
The programmable features of the ICS84321 suppor |
STK392-040-E STK392-040-E  |
|
|
|
The sensing element, capable to detect the accel |
STK392-110 STK392-110  |
SANYO |
|
|
The HYM71V631601 H-Series are Dual In-line Memory |
STK392-110-E STK392-110-E  |
|
|
|
5V TOLERANT INPUTS HIGH SPEED: tPD = 4.2ns (MA |
STK392-110T STK392-110T  |
|
|
|
Wake-up Function for a Microcontroller with Pream |
STK392-120 STK392-120  |
|
|
03+ |
L1, L2 = 270 nH. See the Choosing the Correct In |
STK392-120E STK392-120E  |
|
|
|
Note 7: FO = 0V (internal oscillator) or fEOSC = |
STK392-150 STK392-150  |
SANYO |
HYB |
N/A |
The charge flows are absorbed by the touch of a |
STK392-180 STK392-180  |
|
|
03+ |
No part of this manual may be reproduced, copied |
STK392-220 STK392-220  |
SANYO |
|
|
Shunt protection devices clamp voltage peaks at |
STK392-550 STK392-550  |
|
|
|
the ISAnet evaluation adapter card is designed a |
STK392-560 STK392-560  |
SANYO |
SIP |
N/A |
3) This input current only exists when the volta |
STK392-560C STK392-560C  |
SANYO |
HYB |
03+ |
To use the LX1991 at the maximum usable f |
STK392-570 STK392-570  |
SANYO |
MOUDLE |
03+ |
The TLV2262/4 also makes great upgrades to the T |
STK392-570-E STK392-570-E  |
|
|
|
When HIGH, this input is used to advance the inte |
STK392-910 STK392-910  |
SANYO |
|
|
The ILED is the constant current programm |
STK392-910A STK392-910A  |
|
|
|
The 3D7205 five-tap delay line architecture is s |
STK393-110 STK393-110  |
SANYO |
HYB |
03+ |
Shielded cables for SCSI connection external to |
STK393-110-E STK393-110-E  |
|
|
|
1. The ALD1704 CMOS operational amplifier uses a |
STK394-110 STK394-110  |
SANYO |
|
03+ |
NOTES:1. Complete part number includes a suffix |
STK394-160-E STK394-160-E  |
|
|
|
|
STK394-210 STK394-210  |
SANYO |
|
03+ |
Standoff Voltage: Applied Reverse Voltage to assu |
STK394-210E STK394-210E  |
SANYO |
ZSIP18 |
O5 |
The DDU7C relies on a stable power supply to pro |
STK394-210-E STK394-210-E  |
|
|
|
To limit maximum duty cycle, the internal clock |
STK394-220 STK394-220  |
|
|
|
The external bus interface (EBI) provides a glue |
STK394-240 STK394-240  |
SANYO |
模块 |
|
Wide supply voltage range from 1.65 V to 5.5 V |
STK394-250 STK394-250  |
SANYO |
HYB |
03+ |
AT49BV/LV001NT pin 1 for the DIP and PLCC packag |
STK394250A STK394250A  |
|
|
|
Supply Voltage(pin 4) Supply Current(Pin 4) DC |
STK394-250A STK394-250A  |
SANYO |
SIP-18 |
04+ |
in. The FWH could hold multiple certificates, ea |
STK394-250-E STK394-250-E  |
|
|
|
|
STK394-250T STK394-250T  |
|
|
|
TOSHIBA is continually working to improve the qu |
STK394-260 STK394-260  |
|
SANYO |
2005-06 |
For each bridge, the user selects an exte |
STK394-510 STK394-510  |
SANYO |
MODULE |
N/A |
adjusted using two potentiometers. The DC voltag |
STK394-710 STK394-710  |
SANYO |
|
04+ |
No Auxiliary Winding Operation Internal Output S |
STK396-010 STK396-010  |
SANYO |
|
2007+ |
Intended compliance for future Revision 2.2 6 |
STK396-010M STK396-010M  |
|
|
|
• Wide frequency rangeC2.25MHz to 36.0MHz |
STK396-110 STK396-110  |
SANYO |
|
4200
|
prevents time loss as the timekeeping countdown c |
STK396-120 STK396-120  |
|
ZIP-11 |
|
This is a special part of the memory used to save |
STK396-120-E STK396-120-E  |
SANYO |
98+ |
|
Parameter Total Gate Charge (turn-on) G |
STK396-130 STK396-130  |
|
ZIP-11 |
|
These lamps are made with an advanced optical |
STK396-130-E STK396-130-E  |
|
|
|
• Compact Package • 8 mm (0.31 inch) |
STK397-010 STK397-010  |
|
|
|
Game boxes are using more powerful processors to |
STK397-101 STK397-101  |
|
|
|
High-end embedded control applications demand mo |
STK3N50 STK3N50  |
ST |
TO |
|
PLIM: This pin is programmed to set the maximum i |
STK3NA50 STK3NA50  |
ST |
TO |
|
NOTES: 1. tPLH and tPHL are production tested. |
STK400-010 STK400-010  |
SANYO |
|
04+ |
The HYM72V64C756T8 H-Series are high spee |
STK400-020 STK400-020  |
|
|
|
Light has characteristics to move electrons in th |
STK400-030 STK400-030  |
SANYO |
HYB |
97+ |
|
STK400-040 STK400-040  |
SANYO |
|
|
The ispClock5510 and ispClock5520 are in-system- |
STK400-050 STK400-050  |
|
|
|
|
STK400-050A STK400-050A  |
SANYO |
HYB |
03+ |
The TC650/TC651 acquire and convert their juncti |
STK400-060 STK400-060  |
SANYO |
|
04+ |
-1774.50 -1779.30 -1779.30 -1779.30 -1779.30 |
STK400-070 STK400-070  |
SANYO |
STK |
2004+ |
Thus the first step in designing the antenna cir |
STK400-070A STK400-070A  |
SANYO |
STK |
2004+ |
The host system can detect whether a program or |
STK400-090 STK400-090  |
STK |
SIP |
1997 |
They are intended for applications in the RF fr |
STK400-290 STK400-290  |
SANYO |
STK |
2004+ |
The TMS551xx devices offer a split-register-tran |
STK400-300 STK400-300  |
|
|
|
Stresses above these ratings may cause permanent |
STK400-490 STK400-490  |
SK |
STK |
01# |
The TLV2352 has internal electrostatic-discharge |
STK401 STK401  |
|
|
|
4. EMI/RFI Suppression. The capacitor/ i |
STK401-010 STK401-010  |
SANYO |
HYB |
03+ |
• High Blocking Voltage • Epitaxial |
STK401-020 STK401-020  |
|
|
|
©Atmel Corporation 2004. All rights reserved |
STK401-030 STK401-030  |
SANYO |
HYB |
|
HIGH PERFORMANCE • Polynomial complies to |
STK401-031 STK401-031  |
|
|
|
Teccor Electronics reserves the right to make cha |
STK401-040 STK401-040  |
SANYO |
05+/06+ |
|
1) CPD is defined as the value of the ICs intern |
STK401-041 STK401-041  |
SANYO |
HYB |
03+ |
These beam lead diodes are constructed using a m |
STK401-050 STK401-050  |
SANYO |
|
|
Note 6: Limits are 100% production tested at 25 |
STK401-051 STK401-051  |
SANYO |
模块 |
|
The Build-in oscillator circuitry of STK4 |
STK401-060 STK401-060  |
|
|
02+ |
Notes: (1) See SOA curves or consult factory for |
STK401-061 STK401-061  |
SANYO |
|
04+ |
RESET FLAG Proper operation of the RESET circui |
STK401-061S STK401-061S  |
SANYO |
HYB |
03+ |
Vectron International reserves the right to make |
STK401-070 STK401-070  |
SANYO |
|
|
The ripple rejection values are measured with th |
STK401-071 STK401-071  |
SANYO |
HYB |
03+ |
The unique differential input sample-and-hold can |
STK401-080 STK401-080  |
|
|
|
(VDD = +2.7V to +3.6V; unipolar input mode; COM = |
STK401-081 STK401-081  |
|
|
|
tCONV = tCONV(local) + tCONV(remote). Following |
STK401-090 STK401-090  |
SANYO |
|
|
Absolute maximum continuous ratings are those ma |
STK401-100 STK401-100  |
SANYO |
HYB-16 |
06+ |
The STK401-100/STK401-100 quad low-voltage differ |
STK401-110 STK401-110  |
SANYO |
HYB |
02+ |
|
STK401-120 STK401-120  |
SANYO |
SIL-9 |
02+ |
• Low VCE (on) Non Punch Through IGBT Tech |
STK401-130 STK401-130  |
|
|
|
Notes: 1. NC pins are not connected to th |
STK401-140 STK401-140  |
SANYO |
|
-- |
The Rx5C348A/B are CMOS real-time clock ICs conne |
STK401-210 STK401-210  |
SANYO |
|
652
|
Class A operation Internally matched to 50(ohm) |
STK401-220 STK401-220  |
SANYO |
|
04+ |
The SCSI bus DIFSENS signal line is used to iden |
STK401-230 STK401-230  |
SANYO |
HYB |
96+ |
The four Ports (IR, COM, AUX, and General Purpos |
STK401-240 STK401-240  |
SANYO |
HYB |
97+ |
The upper and lower gates are held low until the |
STK401-250 STK401-250  |
SANYO |
|
04+ |
The OPA688 is a wideband, unity gain stable volt |
STK401-260 STK401-260  |
SANYO |
|
652
|
Must be chosen from an inspection lot that has b |
STK401-261 STK401-261  |
|
|
|
(Continued) Instruction system best suit |
STK401-270 STK401-270  |
SANYO |
HYB |
03+ |
Vcc = 5.0V10%, TA = 0C to 70C, unless otherwise s |
STK401-271 STK401-271  |
|
|
|
Although the chip permits all combinations of en |
STK401-280 STK401-280  |
SANYO |
HYB |
01+ |
|
STK401-290 STK401-290  |
SANYO |
HYB |
05+ |
|
STK401-300 STK401-300  |
|
|
|
Transceivers through Standard MII Ports Dual ARM |
STK401-310 STK401-310  |
|
|
|
Even though absolute integral and differential l |
STK401-320 STK401-320  |
SANYO |
HYB |
96+ |
|
STK401-330 STK401-330  |
SanKen |
|
N/A |
Power Diode Module DD200HB series are designed f |
STK401-340 STK401-340  |
SANYO |
HYB |
01+ |
The receive section of the CYP15G0401DXA Quad HO |
STK4015S STK4015S  |
HITACHI |
模块 |
|
The out-of-band receiver in the STK4015S contain |
STK401-680 STK401-680  |
|
|
|
NOTES: 1. All VDD pins must be connected to 3.3V |
STK4017 STK4017  |
sanyo |
|
|
VFB to the output of the error amplifier. Note 4 |
STK4019 STK4019  |
SANYO |
|
|
Internal Memory - Character Generato |
STK402-010 STK402-010  |
SANYO |
HYB |
02+ |
Switch Enable into Heavy Load If a switch is pow |
STK402-020 STK402-020  |
SANYO |
HYB |
05+ |
The LCX74 is a dual D-type flip-flop with Asynch |
STK402-020-E STK402-020-E  |
|
|
|
This device is particularly well suited for port |
STK402-020S STK402-020S  |
SANYO |
STK |
2004+ |
(a full wave circuit has twice these efficiencie |
STK402-030 STK402-030  |
SANYO |
模块 |
|
Chrontels CH7004 digital PC to TV encoder is a s |
STK402-030-E STK402-030-E  |
|
|
|
The receiver offers an exceptionally high level |
STK402-030S STK402-030S  |
SANYO |
模块 |
|
Information furnished is believed to be accurate |
STK402-040 STK402-040  |
SANYO |
模块 |
|
Case: SOT-363, Molded Plastic Case material - |
STK402-040N STK402-040N  |
STM |
DIP-16 |
00+ |
The HT6P20 is a CMOS LSI encoder designed for re- |
STK402-041 STK402-041  |
SANYO |
STK |
2004+ |
This signal is used internally as part of the I |
STK402-050 STK402-050  |
sanyo |
|
|
Each DS1258W device is shipped from Dallas Semico |
STK402-050S STK402-050S  |
SANYO |
模块 |
|
The PLCC-2 SMT LED products with a viewing angle |
STK402-060 STK402-060  |
SANYO |
STK |
2004+ |
The data contained in the data stream can also a |
STK402-070 STK402-070  |
SANYO |
MODULE |
N/A |
Full or Partial Card compliance checking LUN con |
STK402-070H STK402-070H  |
SANYO |
|
n/a |
The STK402-070H is a new generation of monitor &m |
STK402-070N STK402-070N  |
SANYO |
05+/06+ |
|
Motorola reserves the right to make changes with |
STK402-070S STK402-070S  |
SANYO |
HYB |
02+ |
The state of the data line represents valid data |
STK402-070S-E STK402-070S-E  |
|
|
|
Maximum ratings are those values beyond which de |
STK402-071 STK402-071  |
SANYO |
模块 |
|
Upon initial power up, the IC can either isolate |
STK402-071N STK402-071N  |
SANYO |
模块 |
|
NOTES: 1. Stresses greater than those listed und |
STK402-090 STK402-090  |
STK |
SIP |
SIP |
Validation of a token first involves an authenti |
STK402-090A STK402-090A  |
SANYO |
STK |
2004+ |
Data flow in each direction is controlled by the |
STK402-090B STK402-090B  |
SANYO |
STK |
2004+ |
Notes: 1. All byte outputs are active in read c |
STK402-090-E STK402-090-E  |
|
|
|
Input bus select / I2C clock input. The operatio |
STK402-090S STK402-090S  |
SANYO |
|
|
We could accumulate a running total indefinitely |
STK402-090S-E STK402-090S-E  |
|
|
|
Case: SOD-523, Molded Plastic Case material - UL |
STK4020II STK4020II  |
|
|
|
The Flash technology provides fixed Erase and Pro |
STK4021 STK4021  |
SANYO |
|
|
16-Bit Output For Use in Microprocessor-Based Sy |
STK402-100 STK402-100  |
|
|
|
Clock with 1/2 frequency of XTL1 Test pin Chip |
STK402-100E STK402-100E  |
SANYO |
|
2007+ |
The internal configuration of the Xinger® bal |
STK402-100S STK402-100S  |
SANYO |
HYB |
02+ |
Integrated Single-Chip 10/100 Ethernet Switch |
STK402-110 STK402-110  |
SANYO |
HYB |
02+ |
With reference to WG 2 Resolution M33.31 in docu |
STK402-110S STK402-110S  |
|
|
|
Drain-to-Source Breakdown Voltage Gate Th |
STK402-120 STK402-120  |
SANYO |
模块 |
|
Crystal input, Nominally 14.318MHz. Crystal out |
STK402-120(JP) STK402-120(JP)  |
|
|
|
A LOW on this pin initializes the FIFO read and w |
STK402-120C STK402-120C  |
SANYO |
STK |
2004+ |
+15 VOUT- is a regulated +15 volt output availabl |
STK402-120-E STK402-120-E  |
|
|
|
150V Power Schottky rectifier are suited for swi |
STK402-120S STK402-120S  |
SANYO |
|
00 |
The Si3056 is an integrated direct access arrange |
STK402-120Y STK402-120Y  |
|
|
|
*Note: Insert the threshold level suffixes for VC |
STK402-130 STK402-130  |
SANYO |
MODULE |
02+ |
As long as store input is low, data is continuou |
STK402-150 STK402-150  |
SANYO |
|
652
|
Note 3 The HALT mode will stop CKI from oscillati |
STK402-220 STK402-220  |
|
|
|
|
STK402-230 STK402-230  |
SANYO |
ZIP |
N/A |
|
STK402-240 STK402-240  |
SANYO |
|
|
The ISL6118 has integrated current sensing on the |
STK402-240A STK402-240A  |
SANYO |
模块 |
|
The Intersil ISL422XE devices are 2.7V to 5.5V p |
STK402-250 STK402-250  |
|
|
|
Continuous Drain Current, V GS @ 10V Continuous |
STK402-270 STK402-270  |
sanyo |
|
|
Most functions of the FM25L16 either are control |
STK402-270A STK402-270A  |
SANYO |
|
1728
|
• RGB or YCrCb Inputs, Selectable on a &n |
STK4023 STK4023  |
|
|
|
Low Frequency Vibration: Vibration shall consist |
STK402-370 STK402-370  |
SANYO |
MOUDLE |
04+ |
The Link Fault Indicator (LFI) output is a TTL-l |
STK4023II STK4023II  |
SANYO |
模块 |
|
AEC-Q100† Qualified for Automotive Applica |
STK4024 STK4024  |
|
|
|
Adaptive Differential Pulse Code Modulation (ADP |
STK402-408 STK402-408  |
|
|
|
Total Power Supply and Zener Current Output Cu |
STK402-450 STK402-450  |
SANYO |
|
652
|
TI warrants performance of its semiconductor pro |
STK402-480 STK402-480  |
STK |
SIP |
1999 |
Note 1: Absolute Maximum Ratings indicate limits |
STK4024II STK4024II  |
SANYO |
STK |
2004+ |
|
STK4024IIK STK4024IIK  |
|
|
|
C 16-bit Timer with 8-bit Prescaler, and Watchdo |
STK4024MK2 STK4024MK2  |
|
|
|
1. Test conditions: T = 25º C, Supply Volta |
STK4024V STK4024V  |
SANYO |
|
04+ |
Both pre- and post-radiation performance are tes |
STK-4024V STK-4024V  |
SANKEN |
SIP |
99 |
IMPORTANT INFORMATION The LM2462 performance is |
STK4025 STK4025  |
SANYO |
|
|
|
STK402-500 STK402-500  |
|
|
|
The FMS6400 is a dual Y/C 5th order Butterworth |
STK4026 STK4026  |
|
|
|
VREFR− Rch Negative Voltage Reference Out |
STK402-650 STK402-650  |
SANYO |
|
02+ |
1-of-4 bi-directional translating multipl |
STK402-680 STK402-680  |
STK |
SIP |
226 |
NOTES: 1. Stresses greater than those listed un |
STK4026II STK4026II  |
SANYO |
|
|
This document is a general product description an |
STK4026-II STK4026-II  |
SANYO |
STK |
2004+ |
BBE High Pass Filter Output (Ach) |
STK4026MK2 STK4026MK2  |
-- |
|
-- |
Baud-Rate-Generator Input Clock Prescaler Select |
STK4026MK5 STK4026MK5  |
|
|
|
For more details on the ARCNET protocol engine a |
STK4026V STK4026V  |
SANYO |
|
|
For packing material that is returned to us un- |
STK402-700 STK402-700  |
SANYO |
HYB |
04+ |
Figure 6 shows the clock, enable, and dat |
STK4028 STK4028  |
SANYO |
|
04+ |
Cs: The input pin to the overcurrent comparator. |
STK4028II STK4028II  |
|
模块 |
|
• IF system switch 38.9 MHz is sele |
STK4028MK10 STK4028MK10  |
|
|
|
where R CS = parallel combination of R14 and R15, |
STK4028MK2 STK4028MK2  |
SANYO |
SIP15 |
08+ |
|
STK4028MK5 STK4028MK5  |
SANYO |
ZIP15 |
OO |
The SN74CBTD3384C is organized as two 5-bit bus |
STK4028MK5(STK4028V) STK4028MK5(STK4028V)  |
|
|
|
The SSM2120 contains two independent level detec |
STK4028V STK4028V  |
SANYO |
|
2007+ |
As the beams attached to the central mass |
STK4028X STK4028X  |
SANYO |
模块 |
|
n Higher gain to match LM126X CMOS preamplifiers |
STK4028XI STK4028XI  |
|
|
|
DEVICE OPERATION The operating modes of the M27 |
STK402-900 STK402-900  |
|
|
|
The output power as a function of the supply vol |
STK402-920 STK402-920  |
SANYO |
HYB |
02+ |
Two different interfaces are supported on the net |
STK402-920C STK402-920C  |
SANYO |
05+/06+ |
|
The HIP6601 and HIP6603 provide the user total & |
STK402-930 STK402-930  |
STK |
SIP |
SIP |
The bq2050 measures the voltage differential betw |
STK402-940 STK402-940  |
SANYO |
HYB |
02+ |
Maximum ratings are DC values beyond which the d |
STK402-940E STK402-940E  |
|
|
|
The product term array in the FLASH370i logic bl |
STK402-950 STK402-950  |
SANYO |
HYB |
03+ |
line is at logic low and the data is latched w |
STK4030 STK4030  |
SANYO |
|
|
Bild / Fig. 8 W3 C - Dr eiphasen -We chselwegsch |
STK403-030 STK403-030  |
SANYO |
ZIP |
N/A |
Specifications Outline Dimensions Pin Connectio |
STK403-040 STK403-040  |
SANYO |
|
|
The Loop Supervision circuit monitors the state o |
STK403-050 STK403-050  |
SANYO |
HYB |
02+ |
Low Voltage Monitoring During operation, the X5 |
STK403-070 STK403-070  |
SANYO |
ZIP |
N/A |
at the transistor level and verified through mea |
STK403-070-E STK403-070-E  |
|
|
|
REF is 5V tolerant 4 pairs of programmable skew |
STK403-090 STK403-090  |
SANYO |
05+/06+ |
|
C Stand-alone MP3 Decoder C 48, 44 |
STK403-090-E STK403-090-E  |
|
|
|
Failover Features • Rapid link failure det |
STK403-090-S-E STK403-090-S-E  |
|
|
|
The HOST output current is a mirrored and scaled |
STK4030II STK4030II  |
N/A |
sanyo |
05+ |
Cathode-to-Anode Voltage Continuous Forward Curr |
STK4030MK10 STK4030MK10  |
SANYO |
|
01+ |
• STK4030MK10 (5STK4030MK10 version) ̶ |
STK4030V STK4030V  |
SANYO |
STK |
2004+ |
The transmit section of the CY7C9689 HOTLink can |
STK4030XI STK4030XI  |
|
|
|
The STK4030XI series of power modules is |
STK403-100 STK403-100  |
SANYO |
|
|
The PWR5104 and PWR5105 offer respectively 12VDC |
STK403-110 STK403-110  |
SANYO |
|
03+ |
Turn-On Time Turning Q1 in Figure 1 off, removes |
STK403-120 STK403-120  |
SANYO |
HYB |
02+ |
The in-Line Micro filter has been specifically de |
STK403-120-E STK403-120-E  |
|
|
|
LOAD SUPPLY (VBB ). This terminal is the |
STK403-130 STK403-130  |
SANSYO |
|
|
control which of the power switch pairs are turne |
STK403-130Y STK403-130Y  |
SANYO |
HYB |
04+ |
Temperature :stg max Test duration : 1000h Tem |
STK403-150 STK403-150  |
SANYO |
ZSIP15 |
O4 |
If tantalum capacitors are located on the output |
STK4032 STK4032  |
|
|
|
A HIGH on this pin when BM is HIGH selects byte b |
STK403-240 STK403-240  |
|
|
|
The Digital Visual Interface Specification, DVI, |
STK403-240A STK403-240A  |
SANYO |
ZIP |
N/A |
|
STK403-250 STK403-250  |
|
|
|
In the past 10 years, microprocessors have evolv |
STK403-250A STK403-250A  |
|
|
|
To interrupt a burst read with a Write Command, D |
STK4032II STK4032II  |
SANYO |
|
|
Notes: 1. All inputs except OE must meet setup |
STK4032V STK4032V  |
|
|
|
The MCP300X family offers existing Microchip cust |
STK4032X STK4032X  |
|
|
|
• Typical tSK(o) (Output Skew) < 250ps |
STK4034 STK4034  |
SANYO |
|
|
Bit Clock (For MPI)/Data Clock (For GCI). In MP |
STK403-430 STK403-430  |
|
|
|
The device also features split output bank power |
STK4034V STK4034V  |
|
|
|
Note 3: When the input voltage at any pin exceeds |
STK4034X STK4034X  |
SANYO |
|
|
The STK4034X family allows the user to cus |
STK4034XI STK4034XI  |
|
|
|
The master reset inputs (1MR and 2MR) are active |
STK4036 STK4036  |
|
|
|
(1) An export permit needs to be obtained from t |
STK4036II STK4036II  |
SANYO |
|
|
RJA is the sum of the junction-to-case and case- |
STK4036-II STK4036-II  |
|
|
|
Tachyon TS focuses on mass storage application |
STK4036IX STK4036IX  |
SANYO |
|
652
|
DMS (Data Management Software) allows systems to |
STK4036MK10 STK4036MK10  |
|
|
|
1. Other frequencies may be available, please con |
STK4036MK2 STK4036MK2  |
SANYO |
module |
DC/0433 |
The device offers complete compatibility with the |
STK4036MK2(STK4036II) STK4036MK2(STK4036II)  |
|
|
|
Reset In: Sets the Program Counter to zero and r |
STK4036V STK4036V  |
SANYO |
|
|
As seen in the block diagram, the module conta |
STK4036X STK4036X  |
SANYO |
|
|
The selectable 2/4/8 interpolation filters simpl |
STK4036XI STK4036XI  |
SANYO |
|
652
|
Control Signal Input. Used to enable or disable |
STK4038 STK4038  |
|
|
|
256 Independent, Bidirectional HDLC Channels Up |
STK4038II STK4038II  |
SANYO |
|
|
By combining powerful features, ease of use, and |
STK4038MK10 STK4038MK10  |
|
|
|
The device is enabled when the EN pin is connect |
STK4038MK2 STK4038MK2  |
|
|
|
Bild / Fig. 9 Grenzstrom je Zweig IT(OV)M. Belas |
STK4038MK5 STK4038MK5  |
SANYO |
|
04+ |
Supports Direct Memory Access (DMA) Bursts With |
STK4038V STK4038V  |
SANYO |
HYB |
05+ |
11.1 United States export laws and regulations p |
STK4038X STK4038X  |
SANYO |
|
|
|
STK4038XI STK4038XI  |
SANYO |
|
2007+ |
The STK4038XI is a dot matrix LCD controller and |
STK4040 STK4040  |
|
|
|
Notice that the triangle waveform linearity is s |
STK404-010 STK404-010  |
|
|
|
Minimum Dielectric Strength, Input-Output Minimu |
STK404-030 STK404-030  |
|
|
|
One of its notable features is MaverickKey uniqu |
STK404-040 STK404-040  |
SANYO |
|
04+ |
RIFA RIFA article code RC |
STK404-050 STK404-050  |
|
|
|
The Mini-ACE Plus* can optionally boot-up as a R |
STK404-050A STK404-050A  |
SANYO |
|
2300
|
deasserted. Data will be read out of the FIFO on |
STK404-070 STK404-070  |
STK |
SIP |
SIP |
|
STK404-070A STK404-070A  |
SANYO |
HYB |
03+ |
The transmitter data path consists of a transmit |
STK404-070Y STK404-070Y  |
SANYO |
|
652
|
The 80C186EB is a second generation CHMOS High-I |
STK404-070Y-E STK404-070Y-E  |
|
|
|
10-bit ADC -1LSB INL; No Missing Codes -Progra |
STK404-090 STK404-090  |
SANYO |
MODULE |
04+ |
Description 7.6 mm Common Anode Right Ha |
STK404-090S STK404-090S  |
SANYO |
模块 |
|
• Floating Channel Designed For Bootstrapp |
STK404-090S(JP) STK404-090S(JP)  |
|
|
|
Over operating temperature range (TJ = -40C to + |
STK4040II STK4040II  |
STK |
SIP |
SIP |
System support functions include: two SMBus® |
STK4040MK STK4040MK  |
st |
06+ |
500 |
CHIP ENABLE The CE input is the device selection |
STK4040MK10 STK4040MK10  |
SANYO |
SIP15 |
|
VCCI is the VCC associated with the data input p |
STK4040MK11 STK4040MK11  |
SANYO |
ZSIP15 |
95 |
The evaluation board is capable of supporting di |
STK4040MK11(STK4040XI) STK4040MK11(STK4040XI)  |
|
|
|
The Texas Instruments MSP430 family of ultralow- |
STK4040MK2 STK4040MK2  |
|
|
|
The differential inputs are AC-coupled and intern |
STK4040MK5 STK4040MK5  |
SANYO |
ZIP15 |
O2 |
BUFFER READ: Data can be read from either one of |
STK4040MK5(STK4040V) STK4040MK5(STK4040V)  |
|
|
|
If two or more UC1524 regulators are to operated |
STK4040V STK4040V  |
SANYO |
|
03+ |
This data sheet provides an overview of t |
STK4040X STK4040X  |
SANYO |
|
|
• Data mask (DM) for write data • D |
STK4040XI STK4040XI  |
SANYO |
|
|
by CMR test Electrical tests are perform |
STK404-100 STK404-100  |
SANYO |
HYB |
02+ |
DEVICE OPERATIONS The following operations can |
STK404-100S STK404-100S  |
SANYO |
|
652
|
Bursts can be synchronized to external noise sou |
STK404-100S-E STK404-100S-E  |
|
|
|
1.1 Scope. This specification covers the |
STK404-120 STK404-120  |
SANYO |
|
|
Notes: 1. VBR measured after IT applied for 300u |
STK404-120-E STK404-120-E  |
|
|
|
VBIAS (VCC, VBS 1,2,3) = 15V unless otherwise sp |
STK404-120Y STK404-120Y  |
SANYO |
模块 |
|
Input voltage. For regulation at full load, the i |
STK404-130 STK404-130  |
SANYO |
05+/06+ |
|
GROUND - Is the return for the VBIAS supply. This |
STK404-130-E STK404-130-E  |
|
|
|
Complementary clock of differential SRC clock pa |
STK404-130S STK404-130S  |
SANYO |
|
02+ |
The device contains two types of internal memory |
STK404-130S(JP) STK404-130S(JP)  |
|
|
|
Notes: 1. All voltage values, except differenti |
STK404-130Y-E STK404-130Y-E  |
|
|
|
|
STK404-140 STK404-140  |
SANYO |
HYB |
04+ |
GATE (Pin 7): Gate Drive Output Pin for Internal |
STK404-140S STK404-140S  |
SANYO |
HYB |
03+ |
The SPS product family is specially designed for |
STK404-140S-E STK404-140S-E  |
|
|
|
DC Supply Voltage Reverse DC Supply Voltage D |
STK4042 STK4042  |
|
|
|
The MAX1165/MAX1166 16-bit, low-power, successive |
STK404-240 STK404-240  |
SANYO |
|
04+ |
Three 16-bit general-purpose timers are included |
STK4042II STK4042II  |
SANYO |
HYB |
05+ |
Address Latch Enable: Output pulse for latching t |
STK4042-II STK4042-II  |
|
|
|
Software runaway is a system hazard that is diff |
STK4042IX STK4042IX  |
|
|
|
Note 4: Absolute maximum ratings are limits beyon |
STK4042MK11 STK4042MK11  |
SANYO |
ZIP15 |
O4 |
The tuning range of the AGC is subdivided into 2 |
STK4042MK11(STK4042XI) STK4042MK11(STK4042XI)  |
|
|
|
2. Tlow to Thigh = 0 to +125C for LM317MTlow to |
STK4042MK2-ZA STK4042MK2-ZA  |
|
|
|
Applications • DC-DC converters • S |
STK4042MK5 STK4042MK5  |
SANYO |
ZIP15 |
OO |
NOTES: A. CL includes probe and jig capacitance. |
STK4042MK5(STK4042V) STK4042MK5(STK4042V)  |
|
|
|
Wave shaping is incorporated into the transmitter |
STK4042V STK4042V  |
SANYO |
STK |
2004+ |
Certain applications and/or safety agencies may r |
STK4042VL STK4042VL  |
|
|
|
Note 5: Timing specifications are sample tested a |
STK4042XI STK4042XI  |
SANYO |
HYB |
N/A |
-1600.00 -1558.30 -1600.00 -1600.00 -1600.00 |
STK4044 STK4044  |
SANYO |
|
|
1. Single-Master Environment: In a singl |
STK4044II STK4044II  |
SANYO |
|
02+ |
Internal to the GS4882 and GS4982 is a robust vid |
STK4044-II STK4044-II  |
|
|
|
The TMP86FM29 is the high-speed, high-perf |
STK4044MK10 STK4044MK10  |
SANYO |
SIP15 |
|
The 6N137, HCPL-2601/2611 single-channel and HCP |
STK4044MK11 STK4044MK11  |
|
|
|
For a general estimate of ICC, the following equa |
STK4044MK2 STK4044MK2  |
SANYO |
SIP15 |
|
If the MC623 is used to measure the temper |
STK4044V STK4044V  |
SANYO |
|
|
For more information, visit our World Wide Web s |
STK4044-V STK4044-V  |
|
|
|
The chip requires a single, even-parity bit to b |
STK4044X STK4044X  |
|
|
|
The information provided herein is believed to b |
STK4044XI STK4044XI  |
SANYO |
|
|
If an ADJ-bypass capacitor is use, the amplitude |
STK4044-XI STK4044-XI  |
|
|
|
Stability The IRU1015 requires the use of an out |
STK4046 STK4046  |
SANYO |
|
|
Note: 1. Stress greater than those listed under |
STK4046II STK4046II  |
SANYO |
|
|
The HDSP-253x is ideal for applications where |
STK4046MK11 STK4046MK11  |
SANYO |
|
04+ |
low insertion loss, 0.8 dB typ. excellent isol |
STK4046MK5 STK4046MK5  |
SANYO |
|
04+ |
Note: 1. Stress greater than those listed under |
STK4046MK5(STK4046V) STK4046MK5(STK4046V)  |
|
|
|
The ISL6208 is a high frequency, dual MOSFET driv |
STK4046V STK4046V  |
SANYO |
|
04+ |
A latches in the storage mode and their outputs |
STK4046VI STK4046VI  |
SANYO |
|
04+ |
The APW7093 is a reversible energy flow, constant |
STK4046VL STK4046VL  |
|
|
|
The TO-220 Fullpak eliminates the need for addit |
STK4046X STK4046X  |
|
|
|
Note2. The BLOCK DIAGRAM does not include the Bou |
STK4046XI STK4046XI  |
SANYO |
|
|
Chip carrier material should be selected to have |
STK4048 STK4048  |
STK |
SIP |
SIP |
Provides RF Uart Functions, 12 Bit Symbols to Se |
STK4048II STK4048II  |
SANYO |
|
|
Precision fixed operating frequency (100 / 67 / |
STK4048-II STK4048-II  |
SANYO |
STK |
2004+ |
Device programming is performed a byte/word at |
STK4048MK2 STK4048MK2  |
|
|
|
A unity gain, differential amplifier is provided |
STK4048V STK4048V  |
SANYO |
|
|
Even the most conservative heat-sink design will |
STK4048XI STK4048XI  |
SANYO |
- |
- |
CAS -Before- RAS Refresh, Hidden |
STK405 STK405  |
SANYO |
|
07+ |
Clocks in the ispLSI 1032EA device are selected |
STK4050 STK4050  |
N/A |
sanyo |
05+ |
Maximum ratings are those values beyond which de |
STK405-010 STK405-010  |
SANYO |
|
2007+ |
The Erase Suspend/Erase Resume feature allows th |
STK405-020 STK405-020  |
SANYO |
|
04+ |
The receiver is manufactured in a compact, 16-pi |
STK405-030 STK405-030  |
|
|
|
The PIC12CE67X device has special features to r |
STK405-030A STK405-030A  |
STK |
07+ |
|
Features 0.2% Initial Tolerance Max. |
STK405-040 STK405-040  |
SANYO |
|
01+ |
18-bit resolution 500kHz minimum sampling rate |
STK405-050 STK405-050  |
SANYO |
模块 |
|
Notes: 1. To check the reset circuit ,the reset |
STK405-050A STK405-050A  |
SANYO |
模块 |
|
(ang) -112.66 -126.47 -132.57 -135.16 |
STK405-060 STK405-060  |
|
|
|
AØ, BØ & CØ- are the con |
STK405-070 STK405-070  |
SANYO |
05+/06+ |
|
The STK405-070 and STK405-070 are L-Band Frequen |
STK405-070A STK405-070A  |
SANYO |
HYB |
96+ |
This device contains circuitry to protect the in |
STK405-070S STK405-070S  |
SANYO |
STK |
2004+ |
First, each operational amplifier can operate wi |
STK405-080 STK405-080  |
SANYO |
|
03+ |
• High-speed access times: -- 8, 10 |
STK405-090 STK405-090  |
SANYO |
HYB |
02+ |
The LVCC4245A is manufactured using advan |
STK405-090A STK405-090A  |
SANYO |
HYB |
01+ |
10. The 7.5kΩ load represents 1 LSTTL unit |
STK4050II STK4050II  |
SANYO |
HYB |
04+ |
Proper operation requires the use of two |
STK4050MK2 STK4050MK2  |
|
|
|
A permanently enabled Watch-Dog Timer ensures op |
STK4050MK5 STK4050MK5  |
SANYO |
|
04+ |
In-system programmable 3.3V PROMs for configurat |
STK4050V STK4050V  |
SANKEN |
|
03+ |
For the most efficientuse of thesetwo control li |
STK4050-V STK4050-V  |
|
|
|
n Software selectable I/O options TRI-S |
STK405-100 STK405-100  |
SANYO |
|
03+ |
Macrocell registers can be clocked from one of s |
STK405-100A STK405-100A  |
SANYO |
|
652
|
A/D & D/A converters: which are implemente |
STK405-110 STK405-110  |
SANYO |
|
04+ |
The fan speed is measured by counting the number |
STK405-110A STK405-110A  |
SANYO |
HYB |
96+ |
The SN65176B and SN75176B differential bus trans |
STK405-120 STK405-120  |
SANYO |
HYB |
05+ |
3.3V 10% Output Transmit Power Supply. Bypass wit |
STK405-120A STK405-120A  |
SANYO |
HYB |
95+ |
The ZL5011x are cost effective devices aimed at t |
STK4052 STK4052  |
|
|
|
Schottky Process For High Speed Multiplexer Ex |
STK4060 STK4060  |
SK |
SIP |
|
NOTES 1Operating temperature range is as f |
STK4065 STK4065  |
sanyo |
|
|
The on-board RISC processor enables the I |
STK4065SLS STK4065SLS  |
|
|
|
Note 4: The maximum power dissipation must be der |
STK4067 STK4067  |
SK |
MODULE |
N/A |
The STK4067 includes a built-in oscillator and se |
STK4067L STK4067L  |
SK |
|
98 |
CAUTION: Stresses above those listed in Absolute |
STK4067-L STK4067-L  |
SK |
SIP |
|
Stresses beyond those listed under "absolut |
STK4070-070B STK4070-070B  |
SANYO |
模块 |
|
PWMs Compatible with Voltage-Mode or Current-Mo |
STK407-020 STK407-020  |
SANYO |
|
2007+ |
The power dissipation of the SC-74 is a f |
STK407-040 STK407-040  |
SANYO |
|
02+ |
The MAX3873A successfully meets the quali |
STK407-040A STK407-040A  |
SANYO |
STK |
2004+ |
The HYM72V64736B(L)T8 Series are Dual In-line Mem |
STK407-040B STK407-040B  |
SANYO |
SIP |
2001 |
Should the Buyer purchase or use a Samsung produ |
STK407-040E STK407-040E  |
|
|
|
The LVT16373 and LVTH16373 contain sixteen non-i |
STK407-050 STK407-050  |
SANYO |
HYB |
98+ |
Notes: 1. TA is the instant on case tempe |
STK407-050B STK407-050B  |
SANYO |
HYB |
02+ |
Reset: A high on this pin for two machine cycles |
STK407-050E STK407-050E  |
STK |
07+/08+ |
|
The UC385 is easy to use. The adjustable version |
STK407-051 STK407-051  |
|
|
|
The Hynix HYM72V32M636T6M Series are 32Mx64bits S |
STK407-070 STK407-070  |
SANYO |
|
|
Hardware data protection measures include a low V |
STK407-070A STK407-070A  |
SANYO |
STK |
2004+ |
H = High Voltage Level, L = Low Voltage Level, X |
STK407-070B STK407-070B  |
SANYO |
HYB |
98+ |
The STK407-070BNSH is a single-channel PWM |
STK407-070E STK407-070E  |
SANYO |
HYB |
02+ |
The following specifications apply for AGND = DG |
STK407-090 STK407-090  |
SANYO |
05+/06+ |
|
The Hyundai HYM71V16S755AT8 Series are Dua |
STK407-090A STK407-090A  |
STK |
04+ |
|
The customer¢s voice sources are recorded s |
STK407-090B STK407-090B  |
SANYO |
HYB |
00+ |
The A8282SLB output is set to 12, 13, 18, |
STK407-090E STK407-090E  |
SANYO |
SIP |
2000 |
Left/right simultaneous volume or channel 1 volum |
STK407-090E-E STK407-090E-E  |
|
|
|
ICC and ICC are dependent on output loading and |
STK407-100 STK407-100  |
SANYO |
05+/06+ |
|
This application note describes a circuit modific |
STK407-100B STK407-100B  |
SANYO |
HYB |
00+ |
The clock input is fully differential to be comp |
STK407-100E STK407-100E  |
SANYO |
HYB |
04+ |
The input clock frequency, Fin, and the internal |
STK407-110 STK407-110  |
SANYO |
|
652
|
Two Line Output Control BecauseEPROMs are usual |
STK407-120 STK407-120  |
SANYO |
|
2007+ |
The STK407-120C is an interline transfer CCD area |
STK407-120A STK407-120A  |
|
|
02+ |
The SM/SMJ320VC33 can perform parallel multiply |
STK407-120E STK407-120E  |
SANYO |
HYB |
02+ |
GHz TECHNOLOGY, INC. RESERVES THE RIGHT TO MAKE |
STK407-240 STK407-240  |
SANSYO |
|
|
The TLV320AIC2x implements the smart time divisi |
STK407-250 STK407-250  |
SANYO |
HYB |
98+ |
• High-speed access time: 8, 10, 12, 15, a |
STK407-270 STK407-270  |
SANYO |
|
04+ |
The MPC862/857T/857DSL is comprised of three mod |
STK407-290 STK407-290  |
SANYO |
|
04+ |
RS is perhaps the easiest to measure accurately. |
STK407-290K STK407-290K  |
SANYO |
SIP |
2002 |
The HAL 805 is programmable by modulating the su |
STK407-710 STK407-710  |
|
|
|
Crossover Lockout The charge pump contains two |
STK407-710K STK407-710K  |
SANYO |
HYB |
98+ |
The IC41C4400x and IC41LV4400x are CMOS DRAMs o |
STK407K-050 STK407K-050  |
|
|
|
Specifications contained in this product brief a |
STK408-040 STK408-040  |
SANYO |
|
|
Page Write Page write allows up to 64 bytes to |
STK408-040B STK408-040B  |
N/A |
SANYO |
04+ |
Analog Signal Range On Resistance, +25C |
STK408-040E STK408-040E  |
SANYO |
MODULE |
02+ |
Macrocell registers can be clocked from one of s |
STK408-080E STK408-080E  |
|
|
|
1. JA is measured with the component mounted on |
STK408-090 STK408-090  |
SANYO |
HYB |
|
The level output pin provides a signal with twic |
STK408-090E STK408-090E  |
SANYO |
|
652
|
Additional features include: readback of burst-co |
STK4083 STK4083  |
|
|
|
Both the TLE214x and TLE214xA are available in a |
STK4090S STK4090S  |
SANYO |
1900 |
SIP |
66- or 133-MHz, 64-bit, true multifunction, int |
STK-40F STK-40F  |
|
|
|
Enable pin for the Boot ROM or an external regist |
STK410-000 STK410-000  |
SANYO |
|
01+ |
Renesas Technologys HN58V65A series and HN58V66A |
STK410-010 STK410-010  |
SANYO |
HYB |
97+ |
The LPS (link power status) terminal works with |
STK410-020 STK410-020  |
|
|
|
l Up to 2.5 Gbps Bi-directional Data Links l Co |
STK410-020D STK410-020D  |
SANYO |
HYB |
04+ |
3.3 Volt Operation (5V tolerant) Programmable Wa |
STK410-030 STK410-030  |
SANYO |
HYB |
03+ |
It also provides the non-volatility of Flash wit |
STK410-030D STK410-030D  |
SANYO |
|
|
TAOperating free-air temperature−4085 |
STK410-030F STK410-030F  |
SANYO |
HYB |
04+ |
HN58X24xxx series are two-wire serial interface |
STK410-030K STK410-030K  |
SANYO |
模块 |
|
The CD4555B and CD4556B types are supplied in 16 |
STK410-090 STK410-090  |
STK |
SIP |
1998 |
The MC623 consists of a positive temperatu |
STK4101 STK4101  |
|
|
|
ISSI reserves the right to make changes to its p |
STK4101II STK4101II  |
|
|
|
Connect this pin to the upper MOSFETs gate. This |
STK4101-II STK4101-II  |
SANYO |
|
2007+ |
• Two Channel Quadrature Output wi |
STK4101IIIV STK4101IIIV  |
SANYO |
模块 |
|
When the JTAG interface in MAX 7000S devices is |
STK4101IITV STK4101IITV  |
|
|
|
guarantees lower guaranteed maximum supply curre |
STK4101MK2 STK4101MK2  |
SANYO |
SIP18 |
|
Note 4: VIHCMR minimum varies 1 to 1 with VEE. V |
STK4101MK5 STK4101MK5  |
SANYO |
|
04+ |
©Atmel Corporation 2004. All rights reserved |
STK4101V STK4101V  |
SANYO |
|
01+ |
ensure that modifications, if any, have been corr |
STK4102 STK4102  |
STEREOAMPLIFIER |
|
03+ |
• Auto-Track™ Sequencing • Out |
STK4102II STK4102II  |
SANYO |
STK |
2004+ |
Stresses beyond those listed under absolute |
STK4102MK2 STK4102MK2  |
SANYO |
SIP18 |
|
The waveform of the maximum DC applied voltage is |
STK4111 STK4111  |
|
sanyo |
05+ |
The CY7B9950 RoboClock is a low-voltage, |
STK411-110 STK411-110  |
SANYO |
|
04+ |
DESCRIPTION The VND5N07, VND5N07-1, VNP5N07FI a |
STK411-120 STK411-120  |
SANYO |
|
01+ |
Current Sharing Mode In the current sharing mode |
STK411-150 STK411-150  |
SANYO |
|
03+ |
(3) The products described in this material are |
STK4111I STK4111I  |
|
|
|
Carrier Detect. This input controls the recovery |
STK4111II STK4111II  |
SanKen |
|
N/A |
• Live Insertion and Removal Power Manager |
STK4111MK2 STK4111MK2  |
SANYO |
SIP18 |
|
(2) The technical information described in this |
STK4111V STK4111V  |
|
|
|
4. Design your application so that the product i |
STK4112 STK4112  |
SANYO |
SIP |
1999 |
There are 16 HDLC engines (one for each port) th |
STK411-200 STK411-200  |
SANYO |
|
03+ |
Flexible bit assignment is foreseen to support A |
STK411-200E STK411-200E  |
|
|
|
NOTES 1Sample tested during initial release and |
STK411-210 STK411-210  |
SANYO |
|
03+ |
BURN-IN SCREENING Burn-in screening is an option |
STK411-210E STK411-210E  |
SANYO |
HYB |
00+ |
(1) An export permit needs to be obtained from t |
STK411-210M STK411-210M  |
SANYO |
STK |
2004+ |
The attached datasheets are prepared and a |
STK411-220 STK411-220  |
SANYO |
|
|
The bq2000 detects the battery chemistry by monit |
STK411-220A STK411-220A  |
SANYO |
STK |
2004+ |
Watchdog Input. The internal watchdog timer clear |
STK411-220D STK411-220D  |
|
|
|
The DAC5687 is a dual-channel 16-bit high-speed |
STK411-220E STK411-220E  |
SANYO |
SIP-22 |
04+ |
These devices operate from a 2.5-V to 5.5-V sing |
STK411-220M STK411-220M  |
SANYO |
STK |
2004+ |
FEATURES D Integrated Drive Regulator (4 |
STK411-230 STK411-230  |
SANYO |
sanyo |
05+ |
The control input pin of the regulator. This pin |
STK411-230D STK411-230D  |
SANYO |
|
|
The factory pre-set output voltage of Power Tren |
STK411-230E STK411-230E  |
SANYO |
|
|
Power supply input pin for VCC1. When using an ex |
STK411-230E(JP) STK411-230E(JP)  |
|
|
|
Entering SIMD mode also has an effect on the way |
STK411-230M STK411-230M  |
SANYO |
STK |
2004+ |
Output Drive Capability: 15 LSTTL Loads & |
STK411-240 STK411-240  |
SANYO |
|
|
High-drive GTLP backplane interface devices feat |
STK411-240E STK411-240E  |
SANYO |
HYB |
02+ |
This IC functions in a variety of CPU systems and |
STK411-250E STK411-250E  |
|
|
|
- Logic controlled 1-CH DC motor driver - 4-CH B |
STK411-290 STK411-290  |
SANYO |
|
04+ |
regarding media compatibility in your applicatio |
STK411-290E STK411-290E  |
SANYO |
HYB |
02+ |
• HiPerFETTM technology - low RDSon |
STK4112II STK4112II  |
SK |
sanyo |
05+ |
Linearity errors of 0.5 and 1.0 LSB, and Differ |
STK4112MK2 STK4112MK2  |
SK |
02+ |
|
Sets the oscillator frequency and maximum duty c |
STK4113II STK4113II  |
|
|
|
Test Condition Vss < VIN < Vcc Vs |
STK411-550 STK411-550  |
SANYO |
HYB |
01+ |
Each transmit channel accepts parallel character |
STK411-550E STK411-550E  |
SANYO |
HYB |
02+ |
Edition 07.99 Published by Siemens AG, Bereich |
STK411-550G STK411-550G  |
SANYO |
HYB |
00+ |
The CPU core of MTV230M is compatible with the in |
STK4120 STK4120  |
SANYO |
|
07+ |
The DS1330AB provides full-functional capability |
STK412-000 STK412-000  |
SANYO |
|
|
NOTES: (1) 100% tested at rated continuous for o |
STK412-010 STK412-010  |
SANYO |
SIP |
2004+ |
The FDC10 and FDC10-W series offer 10 watts of ou |
STK412-010A STK412-010A  |
|
|
|
The LatticeECP/EC family of FPGA devices has bee |
STK412-020 STK412-020  |
SANYO |
ZIP |
N/A |
The CKE input determines whether the CLK input i |
STK412-020A STK412-020A  |
STK |
07+ |
|
The C67x CPU executes all TMS320C62x™ DSP |
STK412-020-E STK412-020-E  |
|
|
|
Cycle-by-cycle current limit provides protection |
STK412-030 STK412-030  |
SANYO |
|
03+ |
The ADXL321 is a small and thin, low power, comp |
STK412-0301 STK412-0301  |
|
|
|
n OSD Window Fade In/Fade Out n OSD Half Tone Tr |
STK412-030I STK412-030I  |
SANYO |
ZIP-18 |
N/A |
The TOSHIBA products listed in this docume |
STK412-040 STK412-040  |
SANYO |
HYB |
02+ |
IE is used to enable/disable writing into memory. |
STK412-040-E STK412-040-E  |
SANYO |
SIP |
08+ |
|
STK412-040T STK412-040T  |
|
|
|
The Radiation Hardened IS-2100ARH is a high freq |
STK412-050 STK412-050  |
STM |
DIP-42 |
02+ |
Radiation Hardened up to 1 x 106 Rads (Si) Sing |
STK412-060 STK412-060  |
STM |
DIP-42 |
02+ |
The specification of STK412-060A is identical to |
STK412-070 STK412-070  |
SANYO |
HYB |
02+ |
and SN74121 One Shots SN54221 and SN74221 Demons |
STK412-090 STK412-090  |
SANYO |
SIP |
N/A |
Bridge or stereo configuration. Few External c |
STK4120MK2 STK4120MK2  |
SANYO |
HYB |
|
Absolute maximum ratings are limiting values, to |
STK4121 STK4121  |
|
|
|
Regulation is measured at constant junction temp |
STK412-100S STK412-100S  |
|
|
|
NOTE:The CT capacitor must be connected between t |
STK412-120 STK412-120  |
SANYO |
|
04+ |
Anode of the Biasing Diode that matches the therm |
STK412-130 STK412-130  |
|
|
|
For the most current package and ordering inform |
STK412-140 STK412-140  |
SANYO |
HYB |
05+ |
3.8 AUI Interface The AUI interface consists of |
STK412-140-E STK412-140-E  |
|
|
|
Outputs are only disabled or enabled when |
STK412-150 STK412-150  |
SANYO |
ZIP |
N/A |
When the external program/data bus is used in 16 |
STK412-150(JP) STK412-150(JP)  |
|
|
|
NOTE: 1. Stresses greater than those listed und |
STK412-150M STK412-150M  |
SANYO |
MODULE |
N/A |
|
STK412-170 STK412-170  |
SANKEN |
|
03+ |
3-phase rectifier bridge 3-phase short circuit |
STK412-170-E STK412-170-E  |
|
|
|
Notes: 5. Typical values are at VCC=5.0V, |
STK4121II STK4121II  |
SANYO |
05+/06+ |
|
Configuration of a single-ended input has been |
STK4121-II STK4121-II  |
SANYO |
STK |
2004+ |
C, as in PIC12C671. These devices have EPROM typ |
STK4121MK2 STK4121MK2  |
SANYO |
SIP18 |
|
ESD voltage thresholds are dependent on the circu |
STK4121MK5 STK4121MK5  |
|
|
|
Pay particular attention that parasitic couplings |
STK4121V STK4121V  |
SANYO |
模块 |
|
The 17517 can drive two motors in two dir |
STK4121-V STK4121-V  |
SANYO |
STK |
2004+ |
(this is not the Deep Power-down mode). Driving |
STK4122 STK4122  |
|
|
|
The OPA675 and OPA676 are wideband monolithic o |
STK412-200 STK412-200  |
SANYO |
|
01+ |
DC input, toggles CDMA amplifier output between |
STK412-210 STK412-210  |
SANYO |
MOUDLE |
03+ |
|
STK412-210A STK412-210A  |
SANYO |
HYB |
02+ |
The MAX1978 operates from a single supply and pro |
STK412-220 STK412-220  |
SANYO |
|
03+ |
PFC Driver Output. This pin must be connected to |
STK412-220A STK412-220A  |
|
|
|
Thermal Resistance − Junction−toW |
STK412-220A-E STK412-220A-E  |
|
|
|
NOTES: 1. Dimensions are in inches.   |
STK412-230 STK412-230  |
SANYO |
厚膜 |
04+ |
functional operation of the device at these or a |
STK412-230C STK412-230C  |
|
|
|
Enough current should be supplied into the VCC l |
STK412-230-E STK412-230-E  |
|
|
|
Note 3: Without a heat sink, the thermal resistan |
STK412-240 STK412-240  |
SANYO |
ZIP |
N/A |
If the A5, A1, A0 address line inputs are |
STK412-240M STK412-240M  |
SANYO |
HYB |
03+ |
Added section 4.15.3 - In-System-Programmi |
STK412-290 STK412-290  |
SANYO |
SIP-18 |
04+ |
Note 9: If the product is in shutdown mode and VD |
STK4122II STK4122II  |
sanyo |
|
|
Together with separate aerials and tuners for eac |
STK4122-II STK4122-II  |
SANYO |
STK |
2004+ |
FUNCTION Input pin for oscillator. It can be con |
STK4122MK2 STK4122MK2  |
SANYO |
|
DIP |
DESCRIPTION The M27C801 is an 8 Mbit EPROM offe |
STK4122MK2(STK4122II) STK4122MK2(STK4122II)  |
|
|
|
The W83877ATF supports one PC-compatible printer |
STK4122MK2-E STK4122MK2-E  |
|
|
|
The DS89C430, DS89C440, and DS89C450 offer the h |
STK412-400 STK412-400  |
SANYO |
HYB |
04+ |
Control of the wiper (RW) position setting is acc |
STK412-410 STK412-410  |
SANYO |
HYB |
04+ |
The DS1642 is in the read mode whenever WE (write |
STK412-420 STK412-420  |
SANYO |
HYB |
02+ |
This is a dual-function pin. In the CY Standard m |
STK412-420-E STK412-420-E  |
|
|
|
The fixed 54 MHz clocking of the ADCs and datapa |
STK412-430 STK412-430  |
N/A |
sanyo |
05+ |
Leading-edge triggering (A) and trailing edge tr |
STK412-430-E STK412-430-E  |
|
|
|
Note 4 designing with this supply Worst case VI |
STK412-440 STK412-440  |
SANYO |
HYB |
03+ |
Address Inputs Byte Enable Data In / Out Dat |
STK412-470 STK412-470  |
SANYO |
|
04+ |
All unused inputs of the device must be held at |
STK412-490 STK412-490  |
SANYO |
HYB |
04+ |
|
STK412-530 STK412-530  |
|
|
|
spikes (see ISO7637 transient compatibility tab |
STK4126MK10 STK4126MK10  |
SANYO |
模块 |
|
Figure 1 shows a typical application circuit. Th |
STK4127MK2 STK4127MK2  |
SANYO |
模块 |
|
PARAMETER Reference Voltage Fb Voltage Fb Volt |
STK4130 STK4130  |
SANYO |
|
07+ |
The 74HC/HCT393 are 4-bit binary ripple counters |
STK413-000 STK413-000  |
STM |
DIP-42 |
02+ |
DATA Pin The DATA pin is the serial data |
STK413-010 STK413-010  |
SANYO |
|
2007+ |
The information provided herein is believed to be |
STK413-010A STK413-010A  |
Sanyo |
|
04+ |
The clock driver serial protocol accepts byte wri |
STK413-010B STK413-010B  |
|
|
|
NOTES: (1) dBFS refers to dB below Full-Scale. ( |
STK413-020 STK413-020  |
SANYO |
HYB |
00+ |
Supporting system speeds greater than 100 MHz an |
STK413-020A STK413-020A  |
SANYO |
MODULE |
N/A |
• Low-power, high-speed CMOS EPROM/EEPROM |
STK413-030 STK413-030  |
SANYO |
|
04+ |
Switched Mode Power Supplies: • AC-DC con |
STK413-040 STK413-040  |
SANYO |
|
04+ |
|
STK413-040T STK413-040T  |
SANYO |
模块 |
|
Stability The IRU1050 requires the use of an out |
STK4130MK2 STK4130MK2  |
SANYO |
|
|
|
STK4131 STK4131  |
SANYO |
SIP |
01+ |
Conditions Measured from input terminals to out |
STK4131-2 STK4131-2  |
SANYO |
SIP18 |
|
NOTES: 1. For conditions shown as Min. or Max., |
STK4131II STK4131II  |
|
|
|
Analog Signal Range On Resistance, +25C |
STK4131-II STK4131-II  |
SANYO |
STK |
2004+ |
The output voltage of the PT6440 Series ISRs may |
STK4131II/V STK4131II/V  |
|
|
|
The STK4131II/V is a medium-drive (50 mA), 18-bi |
STK4131MK2 STK4131MK2  |
SANYO |
SIP18 |
|
TAOperating free-air temperatureC55125C4085 |
STK4131MK5 STK4131MK5  |
|
|
|
Continuous Drain Current, VGS @ 10V Continuous |
STK4131V STK4131V  |
SANYO |
模块 |
|
The STK4131V provides the added functional |
STK4131-V STK4131-V  |
SANYO |
STK |
2004+ |
Notes: 5. LL disables outputs if TEST = M |
STK4132 STK4132  |
ST |
|
|
64Mbit of Flash Memory Page Program (up to 256 |
STK413-210 STK413-210  |
SANYO |
|
04+ |
The HT9142 has two built-in operation amplifiers. |
STK413-210A STK413-210A  |
SANYO |
ZSIP22 |
O2 |
No Internal Connection. Power-Down Control Input |
STK413-220 STK413-220  |
STM |
DIP-42 |
05+ |
Parameter Total Gate Charge (turn-on) |
STK413-220A STK413-220A  |
SANYO |
|
|
This document is a general product description an |
STK413-230 STK413-230  |
|
|
|
(1) All typical values are at TA = +25C. (2) In |
STK4132II STK4132II  |
SANYO |
05+/06+ |
|
DECODER AND RECEIVE FILTER PCM data is shifted |
STK4132-II STK4132-II  |
SANYO |
STK |
2004+ |
Input used to enable page download mode. When PA |
STK4132MK2 STK4132MK2  |
SANYO |
SIP18 |
|
The information in this document is curre |
STK4132MK2-E STK4132MK2-E  |
|
|
|
Three Input Comparators with Schmitt-trig |
STK4133 STK4133  |
n/a |
n/a |
04+ |
This series of hermetically packaged products fe |
STK4133II STK4133II  |
SANYO |
HYB |
98+ |
The product identification mode identifies the d |
STK413-400 STK413-400  |
SANYO |
HYB |
04+ |
4.4.1 Group A inspection. Group A inspecti |
STK413-410 STK413-410  |
SANYO |
|
04+ |
The ADS1208 is a 2nd-order ∆Ó (delt |
STK413-420 STK413-420  |
SANYO |
MODULE |
N/A |
Features NPT IGBT technology low sa |
STK413-430 STK413-430  |
SANYO |
HYB |
03+ |
NOTES: (1) With a balanced differential signal, |
STK413-430-E STK413-430-E  |
|
|
|
= 111, then all 4 bits are high. If TECH[2:0] = 0 |
STK413-490 STK413-490  |
SANYO |
|
04+ |
Note 1: The MAX5075 is 100% tested at TA = TJ = + |
STK413-530 STK413-530  |
|
|
|
Drain-to-Source Breakdown Voltage Gate Threshol |
STK4137MK2 STK4137MK2  |
SANYO |
|
|
For a 1.25V input, and a 22µH inductor, th |
STK4140 STK4140  |
SANYO |
模块 |
|
VBIAS (VCC, VBS1,2,3) = 15V unless otherwise spe |
STK4140MK2 STK4140MK2  |
SANYO |
|
|
|
STK4140MK5 STK4140MK5  |
|
|
|
A comprehensive evaluation system is available up |
STK4140MK5-Z STK4140MK5-Z  |
|
|
|
Lead Temperature (1.6mm or 1/16 from case for 10 |
STK4141 STK4141  |
SANYO |
|
06+ |
Figure 2 shows the outline and pin-out descripti |
STK414141 STK414141  |
|
|
|
International Rectifiers RADHard HEXFET® tec |
STK4141II STK4141II  |
SANYO |
MODULE |
N/A |
The Hyundai HYM72V32756T8 Series are 32Mx72bits S |
STK4141-II STK4141-II  |
SANYO |
STK |
2004+ |
The STK4141-II is programmed on a byte-by-byte ba |
STK4141II/V STK4141II/V  |
|
|
|
The Preliminary Information presented herein rep |
STK4141MK2 STK4141MK2  |
SANYO |
SIP18 |
|
associated with such unintended or unauthorized |
STK4141MK2-E STK4141MK2-E  |
|
|
|
The LTC®6903/LTC6904 are low power self conta |
STK4141MK5 STK4141MK5  |
|
|
|
The TSH300 is a voltage feedback amplifier feat |
STK4141V STK4141V  |
SANYO |
05+/06+ |
|
ACTIVE: Product device recommended for new design |
STK4141-V STK4141-V  |
SANYO |
STK |
2004+ |
The 74HC245; 74HCT245 is an octal transceiver fe |
STK4141X STK4141X  |
|
|
|
• Double-data-rate architecture; two data t |
STK4141X(JP) STK4141X(JP)  |
|
|
|
A Retriggerable one-shot multivibrator has an ou |
STK4142 STK4142  |
|
|
|
|
STK4142I STK4142I  |
|
|
|
DMS (Data Management Software) allows systems to |
STK4142II STK4142II  |
SANYO |
05+/06+ |
|
ODIS 14 OUTPUT DISABLE - asserting this |
STK4142-II STK4142-II  |
SANYO |
STK |
2004+ |
The DAC5687 includes several input options: sing |
STK4142MK2 STK4142MK2  |
SANYO |
|
|
Resistor Terminal A1 Wiper Terminal W1 Resistor |
STK4142MK2-E STK4142MK2-E  |
|
|
|
The Read operation of the EM39LV040 is controlled |
STK4144 STK4144  |
SANYO |
SIP22 |
|
Meets SONET requirements for jitter tran |
STK4144-II STK4144-II  |
|
|
|
Hynix HYMD116G725A(L)8M-K/H/L series incorporates |
STK4144MK2 STK4144MK2  |
|
|
|
High-drive GTLP backplane interface devices feat |
STK4145 STK4145  |
SANYO |
|
07+ |
Each device includes a voltage regulator, |
STK4145MK2 STK4145MK2  |
SANYO |
|
|
When using the internal demodulator, the oscillat |
STK4145MK5 STK4145MK5  |
SANYO |
SIP |
2001 |
The Hynix HYM76V8635HGT8 Series are Dual I |
STK4147MK2 STK4147MK2  |
SANYO |
|
|
The clear function for the LV163A devices is syn |
STK4150 STK4150  |
SANYO |
|
DIP |
Stanford Microdevices STK4150 is a high performa |
STK41502 STK41502  |
|
|
|
• 10-bit, up to 16-channel Analog-to-Digit |
STK415-090J-E STK415-090J-E  |
|
|
|
The internal VCO is based on the TLC2932 and TLC |
STK4150MK2 STK4150MK2  |
|
|
98 |
1. Stresses beyond those listed under absolute ma |
STK4150MK2Z STK4150MK2Z  |
|
|
|
(and other parameters) will be met at the specif |
STK4151 STK4151  |
|
|
|
NOTES: 1. Dimensions are in inches.   |
STK4151-2 STK4151-2  |
SANYO |
SIP18 |
|
By taking advantage of Analog Devices high-perfo |
STK415-130 STK415-130  |
|
|
|
The 100314 is a monolithic quint differential li |
STK415-170 STK415-170  |
SANYO |
|
04+ |
Biasing The positive Vcc supply voltages are app |
STK4151II STK4151II  |
STK |
SIP |
SIP |
† Stresses beyond those listed under absol |
STK4151-II STK4151-II  |
SANYO |
STK |
2004+ |
In all of these cases, each connection provides |
STK4151MK10 STK4151MK10  |
|
|
|
, LTC and LT are registered trademarks of |
STK4151MK2 STK4151MK2  |
SANYO |
SIP18 |
|
The LMV101/102/105/110 fixed-gain amplifier fami |
STK4151MK5 STK4151MK5  |
SANYO |
SIP18 |
|
Output Voltage Range FBx Threshold Voltage FBx |
STK4151MK5(STK4151V) STK4151MK5(STK4151V)  |
|
|
|
|
STK4151V STK4151V  |
SanKen |
|
N/A |
The bq2400x series ICs are advanced Li-Ion linea |
STK4151-V STK4151-V  |
SANYO |
STK |
2004+ |
The information contained herein is presen |
STK4151V/II STK4151V/II  |
|
|
|
The ADC122S101 operates with a single supply tha |
STK4151X STK4151X  |
|
|
|
Red tinted, diffused Green tinted, diffus |
STK4152 STK4152  |
sanyo |
|
|
Notes : 1. In case of module timing, command cycl |
STK4152II STK4152II  |
SANYO |
MODULE |
|
The XRT59L91 is an optimized single-chip analog |
STK4152-II STK4152-II  |
SANYO |
STK |
2004+ |
|
STK4152MK2 STK4152MK2  |
|
|
|
3. Load regulation and output voltage are measur |
STK4152MK2-E STK4152MK2-E  |
|
|
|
Multiple pulse inputs (repetitive pulse inputs) c |
STK4152MK2GP STK4152MK2GP  |
|
|
|
*NOTE: While the STK4152MK2GP can be operated at |
STK4154 STK4154  |
|
|
|
fixed off-time. CT also sets the BLANK t |
STK4154MK2 STK4154MK2  |
SANYO |
SIP |
2001 |
The Fairchild Switch FST34170 is a 17-bit to 34- |
STK4154MK5 STK4154MK5  |
SANYO |
|
652
|
Permanent device damage may occur if Absolute Max |
STK4157 STK4157  |
|
|
|
Ground pin. Complement clock of differential PC |
STK4157MK2 STK4157MK2  |
SANYO |
|
01+ |
DESCRIPTION HCF4020B is a monolithic integrated |
STK4159MK2 STK4159MK2  |
|
|
|
Programs compiled natively on the host can run o |
STK4160MK2 STK4160MK2  |
SANYO |
SIP-19 |
01+ |
When the result is rounded to fewer than 16 bits |
STK4161 STK4161  |
STK |
SIP |
SIP |
The dropout voltage is defined as the input to o |
STK4161II STK4161II  |
SANYO |
HYB |
01+ |
The SLIC employs a feedback circuit to supply a c |
STK4161-II STK4161-II  |
SANYO |
STK |
2004+ |
In addition to low distortion, the large amount |
STK4161II/V STK4161II/V  |
|
|
|
Read and write accesses to the DDR SDRAM are bur |
STK4161MK2 STK4161MK2  |
|
|
|
A programmable digital audio effects processor e |
STK4161V STK4161V  |
|
Stereo amplifier |
|
Notes: 1. Repetitive Rating : Pulse width limite |
STK4161-V STK4161-V  |
SANYO |
STK |
2004+ |
Information furnished is believed to be accurate |
STK4161X STK4161X  |
|
|
|
This document is a general product description a |
STK4162 STK4162  |
|
|
97 |
The AH25Z-2Z die type has been found to h |
STK4162II STK4162II  |
|
|
|
The HYM72V64C756T8 H-Series are high spee |
STK4162-II STK4162-II  |
SANYO |
STK |
2004+ |
Short circuit protection is provided through fol |
STK4162MK2 STK4162MK2  |
SYO |
|
98 |
DESCRIPTION Using the latest high voltage techn |
STK4162MK2-E STK4162MK2-E  |
|
|
|
CAUTION: These devices are sensiti |
STK4164 STK4164  |
SANYO |
|
07+ |
The output pull-up structure can be globally con |
STK4164II STK4164II  |
SANYO |
HYB |
00+ |
3. Load regulation and output voltage are measur |
STK4164MK2 STK4164MK2  |
SANYO |
ZIP |
98+ |
The LTC3722-1/LTC3722-2 feature adjustable synchr |
STK4164MK5 STK4164MK5  |
SANYO |
模块 |
|
feature Adjustable output power with differentia |
STK4165 STK4165  |
|
|
|
External clock option: The receiver can accept a |
STK4165MK2 STK4165MK2  |
SANYO |
05+/06+ |
|
The logic enable disables the power switch, the |
STK4167MK2 STK4167MK2  |
|
|
|
Performance warranty of products offered on this |
STK417-090 STK417-090  |
|
|
|
Problems relating to playback of sound on audio |
STK4170MK2 STK4170MK2  |
|
Jack(Available) |
|
The bq2083−V1P2 supports the Smart Battery |
STK4171 STK4171  |
|
|
|
CT: The oscillator-programming pin. Only two comp |
STK417-100 STK417-100  |
SANYO |
|
|
Glueless interface to an external 10BASE-T trans |
STK417-120 STK417-120  |
SANYO |
|
|
This N-Channel IGBT is a MOS gated, logic level d |
STK417-120(A) STK417-120(A)  |
|
DIP |
05+ |
New trench HEXFET® Power MOSFETs from Inter |
STK417-120A STK417-120A  |
|
|
|
Temperature Error Using Remote Diode of 0.13 mi |
STK417-130 STK417-130  |
|
|
|
The Programmable Interconnect Matrix (PIM) connec |
STK417-140 STK417-140  |
SANYO |
|
|
Notes: 1. Functional operation under any of the |
STK4171II STK4171II  |
|
|
98 |
The information herein is given to describe cert |
STK4171-II STK4171-II  |
SANYO |
|
2007+ |
Clock Input. CLK provides the reference signal to |
STK4171MK10 STK4171MK10  |
|
|
|
The ICS728 VCXO function consists of the externa |
STK4171MK2 STK4171MK2  |
|
|
|
These products are not designed for use in life s |
STK4171V STK4171V  |
SANYO |
HYB |
00+ |
The new generation CoolSET™-F3 provides Ac |
STK4171-V STK4171-V  |
SANYO |
STK |
2004+ |
Support for simultaneous operation of all above |
STK4171X STK4171X  |
|
Stereo amplifier |
|
Carry Lookahead Each Function Block provides a |
STK4172 STK4172  |
sanyo |
|
|
As VCE is further increased, beyond the thermally |
STK4172II STK4172II  |
|
|
|
BlueCore4-ROM Plug-n-Go has been designed to red |
STK4172-II STK4172-II  |
SANYO |
STK |
2004+ |
In encoding mode, audio data is input via the in |
STK4172II(JP) STK4172II(JP)  |
|
|
|
BOOT BLOCK PROGRAMMING LOCKOUT: The device has o |
STK4172MK2 STK4172MK2  |
SANYO |
SIP18 |
|
CAUTIONS REGARDING NOISE: Be aware that when vo |
STK4174 STK4174  |
SANYO |
|
07+ |
|
STK4174MK2 STK4174MK2  |
SYO |
|
98 |
A gear-tooth sensing system consists of t |
STK4174MK5 STK4174MK5  |
|
|
|
The NJU6048 is a high-efficiency white LED |
STK4177 STK4177  |
|
|
|
Feedback pin Chip Enable: H: Enable &nb |
STK4177MK2 STK4177MK2  |
SANYO |
|
|
Short-Circuit Output Current is a parameter that |
STK4179 STK4179  |
SANYO |
|
07+ |
A heatsink is required to keep the junction temp |
STK4180 STK4180  |
SANYO |
|
|
The SiP5630 senses the operational state of the |
STK4180MK2 STK4180MK2  |
SANYO |
HYB |
|
|
STK4181 STK4181  |
SANYO |
05+/06+ |
|
• Ultra-miniature size with universal termi |
STK4181II STK4181II  |
SANYO |
HYB |
04+ |
9.1 In no event shall DVSI be liable for any spe |
STK4181-II STK4181-II  |
SANYO |
STK |
2004+ |
READ SEQUENCE (READ): Reading the device via the |
STK4181MK2 STK4181MK2  |
|
|
|
The STK4181MK2 is a Central Office Interface Circ |
STK4181V STK4181V  |
SANYO |
HYB |
01+ |
Footnotes: 1) Standard frequency stability (20, |
STK4181-V STK4181-V  |
SANYO |
STK |
2004+ |
During a Bank Activate command cycle, Address def |
STK4181X STK4181X  |
|
|
|
2.3 External Special Function Registers (XFR) Th |
STK4182 STK4182  |
SANYO |
(LX)high-frequency |
|
Lead Configurations All of these devices are mad |
STK4182II STK4182II  |
STK |
SIP |
SIP |
This module generates a slow System Clock (32.76 |
STK4182-II STK4182-II  |
SANYO |
STK |
2004+ |
In-rush current is limited to a programmable val |
STK4182II(JP) STK4182II(JP)  |
|
|
|
Single chip 24-port 10/100M wire speed Ethernet |
STK4182MK2 STK4182MK2  |
STEREOAMPL |
N/A |
06+ |
A self-timed row precharge initiated at the end |
STK4182MK2-E STK4182MK2-E  |
|
|
|
Designed to support the requirements of convergin |
STK4183 STK4183  |
|
|
|
The TS80C54/58X2 has 2 software-selectable modes |
STK4184 STK4184  |
SANYO |
|
|
|
STK4184-II STK4184-II  |
|
|
|
PowerDrive devices significantly increase perfor |
STK4184MK2 STK4184MK2  |
|
|
|
n No special start-up sequence required between |
STK4184MK5 STK4184MK5  |
SANYO |
|
652
|
Finally, the CY7C373i features a very simple timi |
STK4185 STK4185  |
SANYO |
|
07+ |
VTEMP LOADING The VTEMP output has very weak dr |
STK4185MK2 STK4185MK2  |
STK |
DIP |
|
Note 1: Absolute Maximum Ratings indicate limits |
STK4187MK2 STK4187MK2  |
|
|
|
Port 2: Port 2 is an 8-bit bi-directional I/O por |
STK4191 STK4191  |
|
|
|
Read and write accesses to the DDR SDRAM are bur |
STK419-110 STK419-110  |
SANYO |
|
|
SUPPLY VOLTAGE, +VS to CVS OUTPUT CURRENT, wit |
STK419-120 STK419-120  |
SANYO |
|
|
Parameter Carrier Frequency Operating V |
STK419-130 STK419-130  |
SANYO |
|
|
The bq4802Y/bq4802LY contains a temperature- co |
STK419-140 STK419-140  |
SANYO |
|
|
During operation, the STK419-140/STK419-140 moni |
STK419-140A STK419-140A  |
SANYO |
HYB |
96+ |
4 PLL architecture Linear frequency programming |
STK419-150 STK419-150  |
SANYO |
ZIP20 |
97+ |
|
STK4191II STK4191II  |
STK |
SIP |
SIP |
Note 1: Thermal resistance of the TO-3 package (K |
STK4191-II STK4191-II  |
SANYO |
STK |
2004+ |
Notes: 1. Gate Open 2. Measurement using the ga |
STK4191IITW STK4191IITW  |
|
|
|
Voice within each group are combinations of diff |
STK4191MK10 STK4191MK10  |
|
|
|
CAUTION ESD (electrostatic discharge) sensitive |
STK4191MK2 STK4191MK2  |
PMC |
|
DIP |
The rate and magnitude that the PLL corrects the |
STK4191MK2-E STK4191MK2-E  |
|
|
|
† Stresses beyond those listed under absol |
STK4191MK5 STK4191MK5  |
SANYO |
|
|
Upgraded speed grade -8 numbers in Virtex-E Elec |
STK4191V STK4191V  |
|
|
98 |
Bias Modes The power amplifier may be placed in |
STK4191-V STK4191-V  |
SANYO |
STK |
2004+ |
OE controls the impedance of the output buffers. |
STK4191X STK4191X  |
|
Stereo amplifier |
|
NOTE: EP circuits are designed to meet the DC sp |
STK4192 STK4192  |
SANYO |
(LX)high-frequency |
|
The Rambus RIMM modules are offered in a 184-pad |
STK4192II STK4192II  |
|
|
|
The attached data sheets are provided by SAMSUNG |
STK4192-II STK4192-II  |
SANYO |
STK |
2004+ |
Low forward voltage VF , optimum for low v |
STK4192MK2 STK4192MK2  |
PMC |
|
DIP |
Fixed Output Voltages of 2.048 V, 2.5 V, 3 V, 4. |
STK4192MK2-E STK4192MK2-E  |
|
|
|
NOTES:2911 tbl 09 1. "X" in part numb |
STK4193 STK4193  |
|
|
|
Available in the Texas Instruments NanoStar͐ |
STK4194 STK4194  |
|
|
|
Information at the data (D) inputs meeting the s |
STK4195MK5 STK4195MK5  |
SANYO |
HYB |
01+ |
The device is designed to comply with all JEDEC |
STK4196MK10 STK4196MK10  |
SANYO |
|
|
Furthermore, the MAX104 provides latched, differ |
STK4196MK10V STK4196MK10V  |
|
|
|
Control Interface I2C Bus Interface Device and |
STK4196X STK4196X  |
|
|
|
Package drawings, standard packing quantities, t |
STK4197MK2 STK4197MK2  |
SANYO |
|
|
Max. UnitsConditions CCCSVDS = 15V, ID = 3.8A & |
STK4199II STK4199II  |
|
|
|
The XRT75VL00D incorporates an advanced crystal- |
STK4199MK2 STK4199MK2  |
SANYO |
SIP24 |
|
Certain hardware scanning patterns for the A/D Co |
STK419N STK419N  |
|
|
|
RF input pin. This pin requires the use of an e |
STK420 STK420  |
|
|
|
Sector Read With sector read, a sector address |
STK420-091 STK420-091  |
|
|
|
THESE MATERIALS ARE PROVIDED "AS IS" W |
STK4201 STK4201  |
|
|
|
CT: Short circuit timing capacitor and shutdown i |
STK420-121 STK420-121  |
SANYO |
SIP-22 |
05+ |
The VCA2619s VGA section consists of two parts: |
STK4201II STK4201II  |
SANYO |
|
|
Reset: A high on this pin for two machine cycles |
STK4201-II STK4201-II  |
SANYO |
STK |
2004+ |
The SuperFlash technology provides fixed Erase a |
STK4201MK10 STK4201MK10  |
|
|
|
The SL531 transfer characteristic has two |
STK4201MK2 STK4201MK2  |
STEREOAMPL |
|
98+ |
The recommended input capacitance is determined |
STK4201V STK4201V  |
SANYO |
HYB-22 |
03+ |
The Watchdog Timer provides an independent prote |
STK4201-V STK4201-V  |
SANYO |
STK |
2004+ |
The SN65MLVD128 and SN65MLVD129 are LVTTL-to-M |
STK4201X STK4201X  |
SANYO |
|
|
The Freescale Semiconductor accelerometer |
STK4204 STK4204  |
|
|
|
ECOS2CA221AA ECOS2CA271AA ECOS2CA331AA ECOS2CA |
STK4204MK2 STK4204MK2  |
|
|
|
The FM local oscillator consists of a transistor |
STK4204MK5 STK4204MK5  |
SANYO |
摸块 |
|
The Master begins a transmission by sending a ST |
STK4205MK2 STK4205MK2  |
|
|
|
sizing, and programmable I/O (PIO) pins on one c |
STK4209MK5 STK4209MK5  |
|
|
|
When VCC is greater than 1V and less than the UV |
STK4211 STK4211  |
|
|
|
♦ Direct IF Sampling Up to 400MHz ♦ |
STK4211II STK4211II  |
|
|
98 |
will vary with supply voltage, switching frequenc |
STK4211-II STK4211-II  |
SANYO |
STK |
2004+ |
VREFR− Rch Negative Voltage Reference Out |
STK4211MK2 STK4211MK2  |
SANYO |
SIP22 |
|
Xilinx reserves the right to make changes, at an |
STK4211MK5 STK4211MK5  |
SANYO |
SIP22 |
|
The voice data memory area of the API8208A can b |
STK4211V STK4211V  |
SANYO |
|
02+ |
Mode Select Table A LOW signal on MR overrides a |
STK4211-V STK4211-V  |
SANYO |
STK |
2004+ |
1. Rating applies when surface mounted on the mi |
STK4211X STK4211X  |
|
|
|
Deadtime High-Current Totem-Pole Dual Output Sta |
STK4214 STK4214  |
SANYO |
|
|
Notes: 1. CL includes probe and jig capacitance. |
STK42-140 STK42-140  |
SANYO |
HYB |
02+ |
Note 4 When the input voltage (VIN) at any pin ex |
STK4214M2 STK4214M2  |
|
|
|
Stress above those listed under Absolute Maximum |
STK4214MK2 STK4214MK2  |
|
|
|
• When the processor power supply voltage |
STK4215 STK4215  |
SANYO |
|
|
Note 1: LXSU has internal clamp diodes to PVSU an |
STK4215MK2 STK4215MK2  |
sanyo |
|
|
Signal Processor (DSP) C SMJ320C62x C 5- |
STK4216MK10 STK4216MK10  |
|
|
98 |
The NC7SZ74 is a single D-type CMOS Flip-Flop wi |
STK4219MK2 STK4219MK2  |
|
|
|
† Stresses beyond those listed under absol |
STK4220MK2 STK4220MK2  |
|
|
|
In order to facilitate data busing, three-state |
STK4221 STK4221  |
|
|
|
energy and achieve high linearity performance. F |
STK4221II STK4221II  |
SANYO |
05+/06+ |
|
Typical applications include sensor systems that |
STK4221-II STK4221-II  |
SANYO |
STK |
2004+ |
|
STK4221M-1 STK4221M-1  |
|
|
|
|
STK4221MK2 STK4221MK2  |
|
|
|
The 74HC/HCT153 have two identical 4-input mul |
STK4221MK2-E STK4221MK2-E  |
|
|
|
This DAC utilizes a double-buffered 3-wire seria |
STK4221MK5 STK4221MK5  |
SANYO |
SIP22 |
|
Receive synchronizing signal input. Eight requir |
STK4221V STK4221V  |
SANYO |
|
652
|
The output pulse duration is programmed by selec |
STK4221-V STK4221-V  |
SANYO |
STK |
2004+ |
Removed preliminary. Removed old CP44 pin names |
STK4224 STK4224  |
|
|
|
Features • Number of active dots: 1,557,00 |
STK4224M STK4224M  |
|
|
|
The power MOSFET outputs of these devices are si |
STK4225 STK4225  |
SANYO |
|
|
To select I2C bus or 4-Wire serial bus, so |
STK4225II STK4225II  |
SANYO |
HYB |
02+ |
This Application Brief exists as a supplement to |
STK4225MK2 STK4225MK2  |
SANYO |
|
04+ |
between 0 and 16 product terms from the product t |
STK4230MK2 STK4230MK2  |
|
|
|
• I/O-isolation 6000 VDC • Creeping/ |
STK4231 STK4231  |
SANKEN |
SOT |
00+ |
An inhibit terminal is provided that can be used |
STK4231-11 STK4231-11  |
|
|
|
PCI compatible BusCfriendly architecture includi |
STK4231II STK4231II  |
SK |
|
|
This document is a general product description an |
STK4231-II STK4231-II  |
SANYO |
STK |
2004+ |
Clocks in the ispLSI 2096VL device are selected |
STK4231MK2 STK4231MK2  |
PMC |
SIP22 |
|
The READ instruction is the only instruction tha |
STK4231MK2-E STK4231MK2-E  |
|
|
|
When the scaler/interlacer is bypassed, a second |
STK4231MK5 STK4231MK5  |
SANYO |
ZIP22 |
98 |
Preliminary product information describes produc |
STK4231V STK4231V  |
SANYO |
|
|
Note 1: Exceeding the absolute maximum rating ma |
STK4231-V STK4231-V  |
SANYO |
STK |
2004+ |
Short-Circuit Output Current is a parameter that |
STK4234MK2 STK4234MK2  |
SANYO |
|
DIP |
Figure 18.TSOP48 Lead Plastic Thin Small Outline |
STK4234MK5 STK4234MK5  |
|
|
|
Supply Current 1 Supply Current 2 R Output Volt |
STK4235 STK4235  |
|
|
|
test for dry air, and other media, are available |
STK4235MK2 STK4235MK2  |
sanyo |
|
|
Flexible 3-Wire Serial Digital Audio Input and & |
STK4235MK5 STK4235MK5  |
SANYO |
|
|
Hynix HYMD212G726(L)S4-K/H/L series is registered |
STK4241 STK4241  |
SANYO |
SIP |
06+ |
DESCRIPTION The STK4241 is a low voltage CMOS S |
STK4241II STK4241II  |
SANYO |
|
|
SIGNAL DESCRIPTIONS See Figure 1, Logic Diagram |
STK4241-II STK4241-II  |
SANYO |
STK |
2004+ |
Modulator The modulator is a direct conversion |
STK4241MK5 STK4241MK5  |
|
|
|
Code Composer Studio and XDS510 are trademarks o |
STK4241V STK4241V  |
SANYO |
|
|
SD/CT: This is the shutdown pin and also the shor |
STK4241-V STK4241-V  |
SANYO |
STK |
2004+ |
|
STK4242II STK4242II  |
|
|
|
Notes: 1. Repetitive Rating : Pulse width limite |
STK4244 STK4244  |
|
|
|
If the STBY* input (pin 8) is left open-circuit |
STK4244MK5 STK4244MK5  |
|
|
|
The input/output pins (I/O1 through I/O16) are p |
STK425-090 STK425-090  |
SANYO |
MOUDLE |
N/A |
Stresses above those listed under Absolute Maxim |
STK4250MK2 STK4250MK2  |
STK |
SIP |
1993 |
The auto identify mode allows the reading out of |
STK425-130 STK425-130  |
|
|
|
The chip is built around an ARM946ES RISC proces |
STK425-150 STK425-150  |
|
sanyo |
05+ |
The low-power consumption of < 0.75mW (typ at |
STK426/530 STK426/530  |
|
|
|
Each of the four output stages has its own zenerc |
STK426-050 STK426-050  |
STK |
SIP |
1997 |
This pin connects directly to the rectified AC li |
STK426-090 STK426-090  |
STK |
SIP |
1997 |
|
STK426-090P STK426-090P  |
STK |
SIP |
|
|
STK426-091 STK426-091  |
|
|
|
• Optimum instruction set for controller ap |
STK426-530 STK426-530  |
SANYO |
|
|
To interpolate, the chip accepts incoming data o |
STK426-530K STK426-530K  |
SANYO |
SIP |
1998 |
CASE: Void-free transfer molded thermosetting ep |
STK426-536 STK426-536  |
SANYO |
|
|
FEATURES Throughput Rate: 250 kSPS Specified fo |
STK4272 STK4272  |
SAY |
HYB |
96+ |
This automotive grade product provides a |
STK4273 STK4273  |
|
|
|
The ACS120 switch is able to sustain safely the |
STK4274 STK4274  |
|
|
03+ |
The ISL6115 has an integrated charge pump allowin |
STK4274-E STK4274-E  |
|
|
|
Flexible mapping of MUXselx to MUXx allows the |
STK4274M STK4274M  |
SANYO |
模块 |
|
RF input pin. This pin is NOT internally DC bloc |
STK4275 STK4275  |
SK |
|
|
A 1% resistor must be connected directly between |
STK4275M STK4275M  |
SANYO |
模块 |
|
Row Address Strobe Column Address Strobe Write |
STK4275MB STK4275MB  |
SANSYO |
|
99 |
Active-Low. Reset is asserted when VCC drops belo |
STK4277 STK4277  |
SK |
|
|
The MC100ES6039 is a low skew 2/4, 4/6 c |
STK4277SL STK4277SL  |
|
|
|
|
STK4278 STK4278  |
SK |
|
|
• M68HC11 CPU • Power Saving STOP |
STK4278L STK4278L  |
SANYO |
|
|
The MK1491-06 requires some inexpensive external |
STK4279 STK4279  |
SANYO |
|
03+ |
AEC-Q100† Qualified for Automotive Applica |
STK4279SL STK4279SL  |
|
|
|
Figure 6 on page 6 shows a correct trigger seque |
STK428-430 STK428-430  |
SANYO |
|
04+ |
The LNP has differential input and output capabi |
STK428-610 STK428-610  |
SANYO |
SIP |
04+ |
There are two limitations on the power ha |
STK428-610-E STK428-610-E  |
|
|
|
• The use of twin crossbar contacts en- su |
STK428-640 STK428-640  |
SANYO |
模块 |
|
The SDA is a Bi-directional pin used to transfer |
STK428-640-E STK428-640-E  |
|
|
|
C Correlated Double Sampling (CDS) |
STK429-050 STK429-050  |
SANYO |
|
|
Note 8: Skew is defined as the absolute value of |
STK4301 STK4301  |
SANKEN |
SIP |
N/A |
The TSOP48..ON1 - series are miniaturized receiv |
STK430II STK430II  |
|
|
|
The various versions of the TDA 884X/5X series a |
STK430MK3 STK430MK3  |
|
|
|
A: The value of R JA is measured with the device |
STK430MK4 STK430MK4  |
|
|
|
Features • Sensitivity in two separate ax |
STK431 STK431  |
SANYO |
|
04+ |
The COP8SAx instruction set utilizes many single |
STK4311 STK4311  |
SK |
|
|
|
STK432-050 STK432-050  |
SANYO |
HYB-14 |
02+ |
(1) For more information on the PWP package, ref |
STK432-070 STK432-070  |
SANYO |
HYB |
03+ |
Note 1: Calculated by measuring the combined osci |
STK432-070-E STK432-070-E  |
|
|
|
Operating the four memory banks in an interleave |
STK432-090 STK432-090  |
SANYO |
|
|
• Short C when two or more lines are short- |
STK433 STK433  |
SANYO |
MODULE |
N/A |
The maximum AGC (analog gain control) and DGC (d |
STK4330 STK4330  |
|
|
|
Bild / Fig. 8 W3 C - Dr eiphasen -We chselwegsch |
STK433-030 STK433-030  |
SANYO |
|
03+ |
External Memory Interface (EMIF) for Flexibility |
STK433-030-E STK433-030-E  |
SANYO |
5 |
|
Output Capacitors: The PT7700 series requires A m |
STK433-040 STK433-040  |
SANYO |
05+/06+ |
|
The SMLW010 Single-Output, Low-Profile, PCB Moun |
STK433-060 STK433-060  |
N/A |
N/A |
N/A |
C Over 3,000 Gates of PLD with 16 macro cells C |
STK433-060-E STK433-060-E  |
|
|
|
Unless otherwise stated, VDD = 3.3V 10%, no loa |
STK433-070 STK433-070  |
SANYO |
05+/06+ |
|
The LM78LXX series of three terminal positive re |
STK433-090 STK433-090  |
SANYO |
MODULE |
04+ |
The time-domain maximum slope argument can be ap |
STK433-100 STK433-100  |
|
|
|
When both clock signals (CLK_INT, CLK_INC) are l |
STK433-120 STK433-120  |
|
MODULE |
|
• True single-chip tuner |
STK433-120-E STK433-120-E  |
|
|
|
time period overlaps the ontime of an output, th |
STK433-130 STK433-130  |
|
|
|
The small size and battery-powered operation asso |
STK4332 STK4332  |
SANYO |
MODULE |
N/A |
NOTE: Preferred Tolerances and reel sizes are in |
STK433-240 STK433-240  |
|
|
|
Operating voltage VCC C Read: 2.0V~5.5V C Writ |
STK433-270 STK433-270  |
SANYO |
|
652
|
The interface between the IOBs and core logic ha |
STK433-270-E STK433-270-E  |
SANYO |
ZSIP19 |
O5 |
The MSK4351 is designed to be used with a |
STK4332II STK4332II  |
SANYO |
|
|
cal sync pulse; a burst gate or back porch clamp |
STK433-730S STK433-730S  |
|
|
|
Description • Initial release • Ad |
STK433-760 STK433-760  |
|
|
|
The STK433-760 SCSI (Small Computer System Interf |
STK433A STK433A  |
|
|
|
Generates all clocks required for single and two- |
STK435 STK435  |
SANYO |
|
|
Programmable Refresh Timer for DP84xx DRAM Contr |
STK4352 STK4352  |
|
|
|
and other linear applications in the 1800MHz to |
STK4352II STK4352II  |
SANYO |
HYB-15 |
05+ |
PARAMETER VCC Turn On Voltage VCC Turn Off Volt |
STK435A STK435A  |
|
|
|
The MX98715A contains a PCI local bus glueless i |
STK436 STK436  |
SANYO |
|
|
|
STK436(PULS) STK436(PULS)  |
sgs |
sgs |
dc94 |
The address lines on the Control In |
STK4361 STK4361  |
|
|
|
(1) The DW, PW and DSH packages are available ta |
STK4362 STK4362  |
|
|
|
Four-element contained in one package, all |
STK4362II STK4362II  |
SANYO |
|
|
! Direct RAM data display using the display RAM. |
STK4362TV STK4362TV  |
SANYO |
|
|
When power is applied to the Dallastat, the wipe |
STK436A STK436A  |
|
|
|
DYNAMIC PERFORMANCE Signal to Noise + Dist |
STK437 STK437  |
SANYO |
|
|
5. Luminance system After generating the |
STK4372 STK4372  |
|
|
|
Device features include a precision voltage refe |
STK4373 STK4373  |
SANYO |
模块 |
|
Differential amplifiers are somewhat more diffic |
STK437L STK437L  |
|
|
|
device ranging from 4 to 12 wide, with an averag |
STK437TV STK437TV  |
SANYO |
HYB |
|
Continuous Drain Current, VGS @ 10V Continuous |
STK4382 STK4382  |
ST |
|
1780
|
Members of the Texas Instruments SCOPE™ Fa |
STK439 STK439  |
SANYO |
|
|
Total harmonic Distortion Second Order CCIF In |
STK4392 STK4392  |
STK |
SIP |
SIP |
1. In Figure 1, test circuit electrolytic capaci |
STK4392II STK4392II  |
SANYO |
HYB |
01+ |
VCC Supply Voltage. The VCC Supply Voltage suppl |
STK4392IV STK4392IV  |
SANYO |
|
02+ |
The National Semiconductor STK4392IV is |
STK4392TV STK4392TV  |
SANYO |
HYB |
01+ |
The HYM72V32M636H(L)T6 Series are 32Mx64bits Sync |
STK4402 STK4402  |
ST |
|
1780
|
1.1 Greece has waited for long for character 10/ |
STK441 STK441  |
SANYO |
|
|
The receiver is inverting; the RXD pin is low |
STK441-105 STK441-105  |
ST |
|
1780
|
If you do not wish the audio processor (STK441-10 |
STK4412 STK4412  |
SANYO |
|
|
Drain-to-Source Breakdown Voltage Gate Threshol |
STK442-020 STK442-020  |
SANYO |
|
04+ |
The F157A is a high-speed quad 2-input multiplex |
STK442-030 STK442-030  |
SANYO |
|
04+ |
Typical ground pin current is only 1mA (at IOUT |
STK442-050 STK442-050  |
SANYO |
HYB-14 |
N/A |
The output turns low with the magnetic south pol |
STK442-070 STK442-070  |
SANYO |
HYB-14 |
N/A |
Optical transmitter The optical transmitter in a |
STK442-090 STK442-090  |
SANYO |
HYB |
03+ |
NOTES: (1) Binary Twos Complement coding. (2) Ra |
STK442-100 STK442-100  |
SANYO |
HYB |
02+ |
COMPLETE TELETEXT DECODER INCLUD- ING ON-CHIP |
STK442-110 STK442-110  |
SANYO |
MODULE |
N/A |
Maximum ratings are those values beyond which de |
STK442-110I STK442-110I  |
SANYO |
HYB-15 |
05+ |
NOTES: Permanent device damage may occur if ABSO |
STK442-120 STK442-120  |
STK |
07+/08+ |
|
The bq4802Y/bq4802LY provides direct connections |
STK442-120-E STK442-120-E  |
|
|
|
The BUF12800 programmable voltage reference allo |
STK442130 STK442130  |
SANYO |
|
04+ |
Notes: 5. Distribution data sample size is 500 s |
STK442-130 STK442-130  |
SANYO |
HYB |
02+ |
The STK442-130 and STK442-130 are a 10-bit Seria |
STK442-130(JP) STK442-130(JP)  |
|
|
|
|
STK442-130M-E STK442-130M-E  |
SANYO |
ZSIP14 |
O4 |
Quasi Resonant Converter Controller Internal Bu |
STK442-150 STK442-150  |
SANYO |
|
04+ |
Multipliers are designed for use where th |
STK442-170 STK442-170  |
|
|
|
The MB89960 series is a single-chip microcontrol |
STK443 STK443  |
SANYO |
HYB |
03+ |
The input terminal is used to directly control an |
STK443-030 STK443-030  |
SANYO |
|
04+ |
A unique feature of the ISL6310 is the combined u |
STK443-050 STK443-050  |
SANYO |
HYB |
01+ |
† All typical values are at VCC = 3.3 V or |
STK443-060 STK443-060  |
SANYO |
HYB(DIP) |
04+ |
Minimizes Distortion and Error Voltages On-Resi |
STK443-070 STK443-070  |
STK |
07+ |
|
The speech samples are stored directly into on-c |
STK443-070-E STK443-070-E  |
|
|
|
AMDs products are not designed, intended, author |
STK443-090 STK443-090  |
SANYO |
HYB |
02+ |
State-of-the-Art BiCMOS Design Significantly Red |
STK4432 STK4432  |
SANYO |
MODULE |
N/A |
Additional features of the Cypress PALCE22V10 inc |
STK450 STK450  |
|
|
|
CAUTION ESD (electrostatic discharge) sensitive |
STK-450 STK-450  |
|
|
|
to the load side, the effective resistance betwee |
STK453-030 STK453-030  |
SANYO |
ZIP |
05+ |
The master device can check the alarm flag status |
STK453-030A STK453-030A  |
|
ZIP-19 |
|
The 288Mbit Direct Rambus DRAMs (RDRAM®) are |
STK453-030S STK453-030S  |
SANYO |
|
04+ |
Provides low speed control functions 30 Mhz exe |
STK453-060 STK453-060  |
N/A |
NEW |
N/A |
ADC data outputs are internally connected direct |
STK4544III STK4544III  |
SK |
SIP |
|
Notes: 1. Test conditions assume signal transiti |
STK457 STK457  |
SK |
|
|
NOTE: Stresses beyond those listed under Absolut |
STK459 STK459  |
SK |
|
|
The device is optimized for balanced bus transmi |
STK4595 STK4595  |
|
|
|
Maxwell Technologies' patented RAD-PAK® pack |
STK460 STK460  |
|
|
|
These EPROMs and OTP PROMs operate from a single |
STK460A STK460A  |
|
|
|
|
STK461 STK461  |
SANYO |
|
|
NOTES: 1. The Phase Voltage is capable of |
STK463 STK463  |
SANYO |
HYB |
05+ |
The R1RW0416D is a 4-Mbit high speed static RAM |
STK464 STK464  |
|
|
|
s GENERAL DESCRIPTION The NJW1300B is a c |
STK465 STK465  |
|
|
|
75 Volt Motor Supply Voltage 30 Amp Output Switc |
STK465AS STK465AS  |
|
|
|
Valid Combinations Valid Combinations l |
STK470-010 STK470-010  |
SANYO |
HYB |
00+ |
Fixed Closed-Loop Gain Amplifier C 10 V/V (20 dB |
STK470-010A STK470-010A  |
SANYO |
HYB |
03+ |
Notes: 1. Functional operation under any of the |
STK470-020 STK470-020  |
SANYO |
HYB |
00+ |
Three types of memory are provided on the DS2751 |
STK470-020A STK470-020A  |
SANYO |
HYB |
00+ |
The internal circuit is composed of 2 stages in |
STK470-040 STK470-040  |
SANYO |
HYB |
02+ |
3-phase rectifier bridge 3-phase short circuit |
STK470-050 STK470-050  |
SANYO |
HYB |
|
The MCP3302/04 devices feature low current design |
STK470-050A STK470-050A  |
SANYO |
MODULE |
N/A |
Aperture Jitter (∆t). The standard deviatio |
STK470-070 STK470-070  |
|
|
|
Over recommended operating free-air temperature |
STK470-080 STK470-080  |
SANYO |
HYB |
01+ |
The ILD205T/ 206T/ 207T/ 211T/ 213T/ 217T are o |
STK470-090 STK470-090  |
SANYO |
HYB |
02+ |
Note 3: Although power dissipation is internally |
STK470-090B STK470-090B  |
|
|
|
Valid Combinations list configurations planned t |
STK475-010 STK475-010  |
SANYO |
ZIP/模块/12 |
04+ |
When I joined Sony, 2 speed drives had just been |
STK4773 STK4773  |
SANYO |
|
|
* Specifications will vary with foreign st |
STK4793 STK4793  |
SANYO |
MODULE |
06+ |
The positive and negative high voltage su |
STK4793TV STK4793TV  |
|
|
|
Notes: 1. The luminous intensity is measured on |
STK4803 STK4803  |
SANYO |
|
|
† The D package is available taped and ree |
STK4813 STK4813  |
SANYO |
|
|
|
STK483 STK483  |
|
|
|
The GS 702 transmitter controller has been desig |
STK4833 STK4833  |
SANYO |
|
|
The TAR5SBxx Series is comprised of genera |
STK4843 STK4843  |
SANYO |
|
|
The 256Mb DDR SDRAM operates from a differen- t |
STK4845MK2 STK4845MK2  |
|
|
|
The MB89980 series is a line of the general-purp |
STK4853 STK4853  |
SANYO |
|
|
No glitch on power-up Supports hot |
STK4863 STK4863  |
STK |
SIP |
SIP |
The 221 and LS221 devices are dual multivibrato |
STK4873 STK4873  |
SANYO |
|
|
The Hyundai HYM72V16M636AT6 Series are 16Mx64bits |
STK488-010 STK488-010  |
N/A |
N/A |
N/A |
The ADS5553 is a high-performance, dual channel, |
STK488-020 STK488-020  |
|
|
|
TOSHIBA is continually working to improve the qu |
STK488-050 STK488-050  |
SANYO |
|
|
Low side gate driver I.C. High side gate drive |
STK4893 STK4893  |
SANYO |
MODULE |
N/A |
NOTES: 1. Dimension are in inches. |
STK490-020S STK490-020S  |
SANYO |
(LX)high-frequency |
|
If your DSP and CPLD core logic are deman |
STK490-040 STK490-040  |
STK |
90+ |
DIP/模块 |
Surface mount board layout is a critical |
STK490-040S STK490-040S  |
SANYO |
(LX)high-frequency |
|
The overall offset of the STK490-040S, STK490-04 |
STK490-070 STK490-070  |
|
|
|
Notes: 1. Test conditions assume signal transiti |
STK490-070N STK490-070N  |
|
|
|
The Terminal Equipment should apply bit-wide NRZ |
STK490-070S STK490-070S  |
|
|
|
Lead Temperature (Soldering 10 sec )300 C Note |
STK490-090 STK490-090  |
SANYO |
HYB |
00+ |
Receive synchronizing signal input. Eight requir |
STK490-110 STK490-110  |
|
|
|
• Four Crystal modes, up to 40 MHz • |
STK490-110S STK490-110S  |
SANYO |
|
02+ |
Single 5 V supply: 5 V 10% Access |
STK490-140 STK490-140  |
|
|
|
Data Bus, active High. In Word mode, thes |
STK490-310 STK490-310  |
|
|
|
NEC PC, Apollo, Sun-4, and Hewlett-Packard 700 |
STK490-340 STK490-340  |
|
|
|
This device contains circuitry to protect the in |
STK4913 STK4913  |
SANYO |
|
|
Any data, prices, descriptions or specifications |
STK493-210 STK493-210  |
|
|
|
(2) The technical information described in this |
STK495 STK495  |
SANYO |
HYB |
97+ |
CURRENT COMMAND (+,-) - are differential inputs f |
STK495-020 STK495-020  |
|
|
|
† Stresses beyond those listed under absol |
STK495-030 STK495-030  |
|
|
|
Notes: 1. H = HIGH Voltage Level, L = LOW |
STK495-100 STK495-100  |
SANYO |
SIP |
2002 |
During the power-up sequence, internal logic che |
STK496-040 STK496-040  |
SANYO |
|
|
The IDT72V2101/72V2111 are exceptionally |
STK496-040B STK496-040B  |
SANYO |
|
|
Note: 3. A bypass capacitor (0.1µF) |
STK496-060 STK496-060  |
SANYO |
HYB |
02+ |
1. ICC is dependent on output loading when the d |
STK496-070 STK496-070  |
SANYO |
MODULE |
N/A |
Location 00H is an indirect addressing register t |
STK496-070C STK496-070C  |
SANYO |
|
|
All modes (except switching off the standard con |
STK496-090 STK496-090  |
|
|
|
The minimum bending radius is 45 mm. The mounting |
STK496-090C STK496-090C  |
SANYO |
ZIP15 |
OO |
The M95040 is a 4 Kbit (512 x 8) electrically er |
STK496-270 STK496-270  |
SANYO |
SIP20 |
03+ |
|
STK496-420 STK496-420  |
|
|
|
Bild / Fig. 7 Transienter innerer Wärmewide |
STK496-420Y STK496-420Y  |
|
|
|
D/A Converter Sampling Clock For Y Signal (PCK) |
STK496-430 STK496-430  |
|
|
|
Out (pin 7) This is the main timing chain |
STK496-620 STK496-620  |
SANYO |
|
|
This is an analog output which can be used as a |
STK496-620Y STK496-620Y  |
|
|
|
The X9269 is a integrated microcircuit incorpora |
STK496-630 STK496-630  |
SANYO |
MODULE |
N/A |
The L5970AD is a step down monolithic power swi |
STK499-070 STK499-070  |
SANYO |
HYB |
97+ |
Stresses beyond those listed under "absolut |
STK499-080 STK499-080  |
SANYO |
|
|
The COP8TM feature family of microcontrollers use |
STK499-090 STK499-090  |
SANYO |
05+/06+ |
|
Beneficial comments (recommendations, additions, |
STK499-120 STK499-120  |
|
|
|
HS Data; high-speed data output, outputting enti |
STK499-130 STK499-130  |
SANYO |
SIP |
2000 |
are integrated on-chip. At 60 fps, the sensor di |
STK499-140 STK499-140  |
|
|
|
Added 56F8122 information; edited to indicate dif |
STK499-210 STK499-210  |
SANYO |
STK |
2004+ |
Meet ANSI standard RS-485 and RS-422 Data rate |
STK499-220E STK499-220E  |
SANYO |
STK |
2004+ |
CS is a Chip select for the device to activate t |
STK499-230 STK499-230  |
|
|
|
Noise on the transmission media is rejected by t |
STK499-230E STK499-230E  |
SANYO |
|
|
|
STK499-240 STK499-240  |
SANYO |
STK |
2004+ |
Note 11: This specification is guaranteed but not |
STK499-240E STK499-240E  |
SANYO |
|
|
This dual function pin serves as the SYNC and SH |
STK499-290 STK499-290  |
SANYO |
STK |
2004+ |
Note 1 Stresses above those listed under Absolute |
STK499-290E STK499-290E  |
SANYO |
STK |
2004+ |
The EL2260/EL2460 are designed to drive a double |
STK49O-110 STK49O-110  |
SANYO |
|
04+ |
GND: VSS=0V System clock input terminal This te |
STK4N25 STK4N25  |
ST |
TO |
|
The charging sequence consists of four stages. T |
STK4N30 STK4N30  |
ST |
TO |
|
|
STK4N30L STK4N30L  |
ST |
TO |
|
In addition to the column address, A10(=AP) is u |
STK4N40 STK4N40  |
ST |
TO |
|
n Complete specifications at 1A load n Output v |
STK501 STK501  |
SANYO |
ZIP |
N/A |
[CAUTION] The specifications on this datab |
STK502 STK502  |
SANKEN |
|
00+ |
Stress in excess of Absolute Maximum Rat- ings m |
STK503 STK503  |
SANYO |
|
04+ |
s Sector protection Hardware method of |
STK50322 STK50322  |
|
|
|
|
STK507 STK507  |
|
|
|
The ML6102 is a group of high-precision and low- |
STK5088 STK5088  |
TI |
|
96 |
This dual 4-to-1 CMOS analog multiplexer/demulti |
STK51312A STK51312A  |
STK |
SIP |
SIP |
• Access times of 45, 55, and 70 ns • |
STK-5132 STK-5132  |
|
|
|
The TPS211x family of power multiplexers enables |
STK-5134 STK-5134  |
|
|
|
The HYM71V63M801 X-Series are Small Outline Dual |
STK-5136 STK-5136  |
|
|
|
Device operations are selected by writing JEDEC- |
STK51422A STK51422A  |
|
|
|
2. Controls low-level analog signals PhotoMOS re |
STK51423 STK51423  |
|
|
|
The ADSP-21262 SHARC DSP is a member of the SIMD |
STK51427A STK51427A  |
SANYO |
HYB |
97+ |
A Burst Read may be interrupted by another Read C |
STK5164GHI35 STK5164GHI35  |
|
DIP-40 |
98 |
The signal detectors sense and rectify th |
STK521 STK521  |
SANYO |
|
|
AGC PIN diode drive circuit for FM RF AGC |
STK5210 STK5210  |
|
|
|
The NLAS44599 is an advanced dual−in |
STK53041 STK53041  |
SANKEN |
DIP |
98 |
Port 1: Is an 8-bit bi-directional I/O port wit |
STK531 STK531  |
SANYO |
SIP10 |
01+ |
Notes: 1. All inputs except OE must meet setup |
STK5314 STK5314  |
SANYO |
|
|
Processor-Independent Pulse Width Modulation &nb |
STK5315 STK5315  |
SANYO |
|
|
G5131-25T21U G5131-26T21U G5131-27T21U G5131-2 |
STK5316 STK5316  |
SANYO |
|
|
|
STK5321 STK5321  |
|
|
|
Software selectable baud rate generator Prescal |
STK5321SL STK5321SL  |
SAY |
|
652
|
An integrated 28 V Zener diode protects each out |
STK5322 STK5322  |
SANYO |
HYB |
97+ |
device is updated. This feature does not have to |
STK5323 STK5323  |
SAY |
|
652
|
• Designed for increased operating efficie |
STK5324 STK5324  |
|
|
|
Note 1: Includes temperature rise caused by curre |
STK5325 STK5325  |
SAY |
HYB |
01+ |
Notes: 5. Test conditions assume signal t |
STK5326 STK5326  |
|
|
|
NOTES 1Oversampling disabled. Static DAC perform |
STK5330 STK5330  |
SANYO |
HYB |
98+ |
Note 2: Operating Ratings indicate conditions for |
STK5331 STK5331  |
SANYO |
|
|
Data Polling bit (DQ7). During the internal write |
STK5332 STK5332  |
SANYO |
|
|
Adaptive or Manual Delay Control for Zero Voltage |
STK5333 STK5333  |
SANYO |
|
|
The XC73144 features a power-management scheme |
STK5333S STK5333S  |
STK |
ZIP |
06+ |
RST C Input. The RST input pin contains a Schmitt |
STK5335 STK5335  |
SANYO |
|
|
2. Products and product specifications may be su |
STK5336 STK5336  |
SANYO |
|
|
Pericom Semiconductors STK5336 series of logic c |
STK5337 STK5337  |
SANYO |
|
|
After a minimum wait of 250 ns (5V operation) fr |
STK5338 STK5338  |
SANYO |
|
|
The STK5338 microcontroller is a member of the A |
STK5339 STK5339  |
SANYO |
|
|
|
STK5339A STK5339A  |
SANYO |
HYB |
99+ |
The CE input is the device selection control. Whe |
STK5339B STK5339B  |
|
|
|
1) The relationship between the VDDQ of the driv |
STK5340 STK5340  |
|
|
98+ |
All devices also available in tray quatit |
STK5342 STK5342  |
|
模块 |
|
The MSM514252A is an 1-Mbit CMOS multiport DRAM c |
STK5343 STK5343  |
|
|
|
|
STK5352 STK5352  |
|
|
|
the device has a Sector Group Protect function |
STK5353 STK5353  |
|
|
|
This document specifies SPANSION memory products |
STK536 STK536  |
SANYO |
|
04+ |
The MAX1755/MAX1756 are temperature comparators |
STK5361 STK5361  |
SANYO |
SIP8 |
|
Generates Three Voltages: 5.1V at 10mA |
STK5361L STK5361L  |
|
|
|
Fifth Generation HEXFETs from International Rect |
STK5362 STK5362  |
SAY |
HYB |
95+ |
The configuration logic has two sections: |
STK5363 STK5363  |
SAY |
HYB |
96+ |
For use with 1/4-inch optical systems Sensitivi |
STK5364 STK5364  |
SANYO |
|
96+ |
Notes: 3. CL includes probe and jig capac |
STK5371 STK5371  |
SAN |
IC |
|
PEN (Power Supply Enable) Pin 18 - This digital i |
STK5372 STK5372  |
SANYO |
|
|
The TC650/TC651 are integrated temperature senso |
STK5372H STK5372H  |
SAY |
HYB |
98+ |
The programming mode is entered by bringing SER_ |
STK5373 STK5373  |
STK |
ZIP |
06+ |
Internal registers may be accessed through eithe |
STK5382 STK5382  |
SANYO |
HYB |
95+ |
The non - linear V to I converter feeds back larg |
STK5383 STK5383  |
SANYO |
|
00+ |
Circuit Board Material: Top RF layer is .014 Get |
STK5384 STK5384  |
SANYO |
|
03+ |
(+)Sense: An external remote sense input is provi |
STK5388 STK5388  |
SANYO |
|
|
The buried macrocell also supports input register |
STK5391 STK5391  |
SANYO |
|
|
Design complexity is enhanced by the addition of |
STK5392 STK5392  |
SANYO |
|
|
The MOSFET output stage of this power ope |
STK54041 STK54041  |
SANKEN |
DIP |
98 |
When Chip Select (S) is High, the device is dis- |
STK541 STK541  |
|
|
|
1.1 Scope. This specification covers the |
STK5416 STK5416  |
|
|
|
Teccor's line of sensitive gate triacs includes d |
STK5421 STK5421  |
SANYO |
|
|
The Programmable Interconnect Matrix (PIM) connec |
STK5422 STK5422  |
SANYO |
|
|
These two schemes are shown in the 9310 data she |
STK5431ST STK5431ST  |
|
|
|
|
STK5432 STK5432  |
SANYO |
|
|
The STK5432 incorporates both over-temperature a |
STK5434 STK5434  |
SANYO |
HYB |
95+ |
A flow through pin out has been adopted to allow |
STK5436 STK5436  |
|
|
|
Assuming, the following conditions: VOUT =2.5V |
STK5441 STK5441  |
SANYO |
HYB |
95+ |
Typical represents the average reading at |
STK5443 STK5443  |
|
|
|
10-bit Resolution 1.5 Gsps Samplin |
STK5445 STK5445  |
STK |
SIP |
SIP |
1.2MHz Switching Frequency Low VCESAT Switches: |
STK5446 STK5446  |
SANYO |
|
92+ |
The STK5446 regulator is designed to provide a l |
STK5446B STK5446B  |
|
SOP |
01+ |
*Note: In order to develop, make, use, or sell re |
STK5451 STK5451  |
SANYO |
|
|
NOTE A: The oscillator generates a sawtooth wave |
STK5461 STK5461  |
|
|
|
Power supply monitoring function W |
STK5461ST STK5461ST  |
|
|
|
All parameters measured at fMAX unless noted oth |
STK5462 STK5462  |
|
|
|
2. A variety of power saving modes Attach |
STK5464 STK5464  |
|
|
|
Proven in substantial volumes, this devic |
STK5464ST STK5464ST  |
|
|
|
Notes: 1. Propagation Delays and Enable/Disable |
STK5466 STK5466  |
|
|
|
The bq2083−V1P2 uses an integrating conver |
STK5466ST STK5466ST  |
|
|
|
The delay in this mode is dependent only on the c |
STK5467 STK5467  |
SANYO |
|
07+ |
The ADR380 and ADR381 are precision 2.048 V and |
STK5467ST STK5467ST  |
|
|
|
The operational overview diagram in Figure 2 illu |
STK5468 STK5468  |
SANYO |
HYB |
01+ |
Vo Adjust: A 0.1 W 1 % resistor must be directly |
STK5471 STK5471  |
SANYO |
|
|
STK5471 Commutation Decoder Truth Table which sh |
STK5472 STK5472  |
SANYO |
|
|
These chips, properly assembled, display charact |
STK5473 STK5473  |
SANYO |
|
|
Configuration data stored in Virtex-II configura |
STK5474 STK5474  |
STK |
ZIP |
ZIP |
This device allows transmission, that is insensi |
STK5476 STK5476  |
STK |
SIP |
SIP |
Following qualification, the bq24400 fast-charge |
STK5477 STK5477  |
SANYO |
|
99+ |
Notes: 1. H = HIGH Voltage Level. L = LOW |
STK5478 STK5478  |
SANYO |
HYB |
99+ |
A resistively-coupled lower-power complementary |
STK5478A STK5478A  |
SANYO |
HYB |
02+ |
† Stresses beyond those listed under absol |
STK5479 STK5479  |
|
|
|
Hynix HYMD264G726A(L)8-M/K/H/L series incorporate |
STK5480 STK5480  |
SANYO |
|
|
Ground connection. For best performance, keep tr |
STK5481 STK5481  |
SANYO |
|
|
Figure 4 demonstrates the critical timing require |
STK5482 STK5482  |
SANYO |
|
06+ |
The TPS721xx family of LDO regulators is availab |
STK5483 STK5483  |
SANYO |
模块 |
|
1. Hitachi neither warrants nor grants licenses |
STK5484 STK5484  |
SANYO |
HYB |
98+ |
Note 2: When the input voltage (VI) at any pin e |
STK5486 STK5486  |
|
|
|
An HDLC transceiver is included on the SNIC for l |
STK5487 STK5487  |
SANYO |
|
|
Instruction Structure The next byte sent to the |
STK5488 STK5488  |
|
|
|
(*) Our SO-8 package used for Voltage Regulators |
STK5490 STK5490  |
SANKEN |
|
|
DIGITAL INTERFACE The MXD2020E/F is easily inte |
STK561 STK561  |
SANYO |
|
07+ |
Depending on your PSoC device characteristics, t |
STK561C STK561C  |
SANYO |
|
|
For A-to-B data flow, when CEAB is low, the devi |
STK561F STK561F  |
SANYO |
|
|
The SSM2165 is a complete and flexible solution |
STK563 STK563  |
SANYO |
|
|
HIGH SPEED: tPD =3.7ns (TYP.) at VCC = 5V LOW P |
STK5631 STK5631  |
SANYO |
HYB-4 |
04+ |
Philips Semiconductors uses high quality capacit |
STK5631C STK5631C  |
SANYO |
ZSIP4 |
O1 |
Microcontroller architecture Memory mapping SF |
STK5631F STK5631F  |
SANYO |
|
02+ |
The IDTQS74FCT2827T is a 10-bit buffer wi |
STK5631FS STK5631FS  |
|
|
|
1. Connect the device as follows: source to E, g |
STK5632 STK5632  |
|
|
|
The HYM7V65801B Q-Series are Small Outline Dual I |
STK5632D STK5632D  |
|
|
|
A major problem in attempting to suppress |
STK5633 STK5633  |
SANYO |
|
|
Note Differential gain and differential phase me |
STK5633F STK5633F  |
SNAYO |
module |
|
Continuous Drain Current, VGS @ 10V Continuous |
STK563A STK563A  |
|
|
|
• IDT54/74FCT240/241/244/540/541 equivalen |
STK563F STK563F  |
SANYO |
|
|
NOTES (a) For a device surface mounted on 52mm |
STK5700 STK5700  |
|
|
|
After the software data protections three-byte c |
STK571C STK571C  |
SANYO |
|
|
Hynix HYMD212G726A(L)S4-M/K/H/L series incorporat |
STK571F STK571F  |
SANYO |
|
|
The CD54AC245/3A and CD54ACT245/3A are octal-bus |
STK5720 STK5720  |
|
|
|
An additional feature of the ispLSI 3320 is the |
STK5730 STK5730  |
SANYO |
模块 |
|
The device has current-limiting and thermal shut |
STK58041 STK58041  |
SANKEN |
DIP |
98 |
Stress in excess of Absolute Maximum Ratings may |
STK583 STK583  |
SANYO |
|
07+ |
The built-in-back-to-back Zener diodes have spec |
STK583F STK583F  |
SAY |
HYB |
04+ |
The PCASTK583F consist of an 8-bit Configuration |
STK58C308 STK58C308  |
|
DIP-8 |
|
The FAN7382 is a monolithic half-bridge gate dri |
STK596KD STK596KD  |
|
|
|
(1) Offset Error is the measured deviation of th |
STK6004C STK6004C  |
SANYO |
模块 |
|
see BAT15-013 see BAT15-013 see BAT15-013 see |
STK6005 STK6005  |
SANYO |
|
|
− Read, program, and erase operations &nb |
STK6005D STK6005D  |
STK |
SIP |
|
NOTES: 1. For conditions shown as Min. or Max., |
STK6005E STK6005E  |
SANYO |
|
|
There are two feedback paths to the ZIA: one fro |
STK6006 STK6006  |
|
|
|
Notes: 1. VIL (min.) = C2.0V for pulse du |
STK6006-F3 STK6006-F3  |
SYNTEK |
PLCC |
|
Maximum ratings are those values beyond which de |
STK6009 STK6009  |
|
|
|
Chip Select : Enables or disables all inputs exce |
STK6011P1-3V STK6011P1-3V  |
ST |
PLCC |
07+ |
Cell balancing of each cell is performed via a c |
STK6011P21-5V STK6011P21-5V  |
ST |
PLCC |
2005 |
Typical characteristic curves are generated usin |
STK6011P2-5V STK6011P2-5V  |
PLCC |
|
|
Gate-to-Source Forward Leakage Gate-to-Source Re |
STK6012B022-5 STK6012B022-5  |
|
|
|
Device erasure occurs by executing the proper era |
STK6012BP22-5V STK6012BP22-5V  |
|
PLCC44 |
06+ |
Ref, XTAL power supply, nominal 3.3V Crystal in |
STK6012P12-5V STK6012P12-5V  |
|
|
02+ |
*Grounding Pin 7 will sink 75mA of current throu |
STK6012P225V STK6012P225V  |
|
|
|
For the ADS-929, offset adjusting is normally ac |
STK6012P22-5V STK6012P22-5V  |
STK |
02+ |
PLCC |
SS/TRACK (Pin 9) - Soft-start and tracking pin. T |
STK6014 STK6014  |
SANYO |
ZIP16 |
99+ |
DC Voltage from 3.0 V to 3.6 V. VDD should be b |
STK6015 STK6015  |
SONY |
|
07+ |
The EN29LV400A has separate Output Enable (OE#), |
STK6015B STK6015B  |
SONY |
模块 |
|
AMDs Flash technology combines years of Flash m |
STK6015B(HIC2) STK6015B(HIC2)  |
SK |
03+ |
模块 |
BACKPLANE TEST MODE SELECT: Controls sequencing |
STK6015C STK6015C  |
SONY |
模块 |
|
A/D converter • 10-bit resol |
STK6016 STK6016  |
|
|
|
The ADSP-21262 includes an on-chip instruction c |
STK6016B STK6016B  |
|
|
|
Collector C Emitter Saturation Voltage, IC=-300 |
STK6017 STK6017  |
|
|
99 |
The AT61162E is a Rad Tolerant module, highly-in |
STK6022 STK6022  |
|
|
|
The HYM72V64C756K8M H-Series are gold plated sock |
STK6022B STK6022B  |
|
|
|
The LTC®3720 is a synchronous step-down switc |
STK6103 STK6103  |
SK |
|
98 |
FEATURES • 3750 Vrms or 5300 Vrms I/O isol |
STK6105 STK6105  |
|
|
|
A 1 kΩ span resistor has been provided on |
STK6105-T STK6105-T  |
SANYO |
ZIP-28P |
97+ |
TI warrants performance of its products to the s |
STK6110 STK6110  |
SANYO |
|
03+ |
with mask-programmable ROM, 12 MHz for external |
STK611-011 STK611-011  |
SANYO |
MODULE |
N/A |
These 8-bit registers feature 3-state outputs d |
STK611-011A STK611-011A  |
|
|
|
A decoupling capacitor of 0.01µF must be c |
STK611-10 STK611-10  |
|
|
|
The CMX866 shares internal register addresses and |
STK6116-10 STK6116-10  |
SYNTEK |
DIP |
06+ |
Absolute maximum ratings indicate sustained limi |
STK6116K STK6116K  |
SANYO |
|
03+ |
SIGNAL DESCRIPTIONS See Figure 1, Logic Diagram |
STK6116K-10 STK6116K-10  |
|
|
|
Notes: 1. Standard packing: Carton (Tube): 40 pc |
STK6130 STK6130  |
SANYO |
|
03+ |
|
STK6153 STK6153  |
SANYO |
|
|
and NanoFree Packages Supports 5-V VCC O |
STK615-313 STK615-313  |
SANYO |
|
04+ |
The DU (Dont Use) pin does not contribute to the |
STK615-314 STK615-314  |
SANYO |
|
04+ |
The MM74HC574 high speed octal D-type flip-flops |
STK615-315 STK615-315  |
SANYO |
|
04+ |
This device contains circuitry to protect the inp |
STK615-414 STK615-414  |
SANYO |
|
04+ |
Note 4: Dynamic supply current is higher due to t |
STK620-020 STK620-020  |
SANYO |
|
01+ |
Notes: 1. Repetitive Rating : Pulse width limite |
STK620-021 STK620-021  |
SANYO |
MODULE |
N/A |
The four documents listed in Table 1 are required |
STK620-032 STK620-032  |
SANYO |
(LX)high-frequency |
|
1. TOLERANCE AND TYPE NUMBER DESIGNATION |
STK620-042 STK620-042  |
SANYO |
(LX)high-frequency |
|
Floating channel up to +600V Monolit |
STK620-411 STK620-411  |
SANYO |
|
|
Stanleys opto-wireless transceiver modules are c |
STK620-611 STK620-611  |
SANYO |
|
|
When no data transfer occurs, you can use the Po |
STK620-807 STK620-807  |
SANYO |
|
07+ |
The HT6P20A/B/D detects the logic state of the in |
STK621 STK621  |
SANYO |
|
|
Notes: 1. Test conditions assume signal transit |
STK621-010A STK621-010A  |
SANYO |
|
04+ |
The UPA831TC contains one NE856 and one NE681 NP |
STK621-011M STK621-011M  |
SANYO |
|
04+ |
NOTES: 1. For conditions shown as Max. or Min., |
STK621-012 STK621-012  |
SANYO |
|
04+ |
MIL-STD-750, method 3131. The maximum limit and |
STK621-013B STK621-013B  |
|
|
|
GENERAL SPECIFICATIONS Working Voltage:Axi |
STK621-014 STK621-014  |
SANYO |
HTB |
06+ |
4 integrated PNP band drivers (Io=40mA,Vsat=0.2 |
STK621-014-E STK621-014-E  |
|
|
|
This chapter provides a brief description of the |
STK621-015 STK621-015  |
SANYO |
MODULE |
N/A |
Introduction Safety Agency Approvals Emission S |
STK621-015A STK621-015A  |
SANYO |
|
04+ |
generate TCLK (Transmit Clock), the internal clo |
STK621-015B STK621-015B  |
SANYO |
HYB |
04+ |
Hynix HYMD18M725A(L)6-K/H/L series incorporates S |
STK621-015B-E STK621-015B-E  |
|
|
|
4096 x 8 bits Reset start address INT0; |
STK621-021 STK621-021  |
SANYO |
|
04+ |
SEG21/P11.2 SEG22/P11.1 SEG23/P11.0 SEG24/P10. |
STK621-022 STK621-022  |
SANYO |
HYB |
05+ |
NOTES: 1. See RECOMMENDED OPERATING RANGE table |
STK621-024 STK621-024  |
SANYO |
|
|
NOTES: 1. Dimensions are in inches. Metri |
STK621-024A STK621-024A  |
SANYO |
HYB |
06+ |
Internal filters in all HR300 converters provide |
STK621-025 STK621-025  |
SAKEN |
SIP-19P(大) |
99+ |
Vo Adjust: A 1 % 0.1 W resistor must be directly |
STK621-031 STK621-031  |
SANYO |
|
|
2 channel 8-bit timer/counter operation (indepen |
STK621-032 STK621-032  |
SANYO |
|
|
!Features 1) Built-in bias resistors enable the |
STK621-033A STK621-033A  |
SANYO |
HTB |
06+ |
The high common-mode input voltage range and th |
STK621-034 STK621-034  |
IPM |
MODULE |
|
Features • High sensitivity and low dark c |
STK621-034A STK621-034A  |
SANYO |
HYB |
05+ |
3 This is the continuous current drawn from the s |
STK621-034B STK621-034B  |
SANYO |
HYB |
04+ |
The COP424C COP425C COP426C COP444C and COP445C |
STK621-034B1 STK621-034B1  |
|
|
|
The PCASTK621-034B1 consist of an 8-bit Configur |
STK621-034B1-E STK621-034B1-E  |
|
|
|
Ausgabe 01.2001 Herausgegeben von Infineon AG , |
STK621-041 STK621-041  |
SANYO |
MODULE |
N/A |
READY/BUSY: The RDY/BSY pin provides the devices |
STK621-042 STK621-042  |
SANYO |
|
|
Please be aware that an important notice |
STK621-043A STK621-043A  |
|
|
|
The parts (B) and (C) of figure 3 give the volta |
STK621050 STK621050  |
|
|
|
PB0~PB7 constitute an 8-bit Schmitt trigger input |
STK621-050 STK621-050  |
SANKEN |
|
02+ |
Digital filters : For the purpose of A/D out-o |
STK621-050A STK621-050A  |
SANYO |
|
01+ |
* Maximum Ratings are those values beyond |
STK621-050B STK621-050B  |
SANYO |
|
|
During discharge and charge, the bq2050 monitors |
STK621-051A STK621-051A  |
|
|
|
1.5 V 2% 3.3-V Output Within 2 V of 1.5-V Output |
STK-621-051B STK-621-051B  |
|