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Note 5: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations by bringing CKI high. Measurement of IDD HALT is done with device neither sourcing nor sinking current; with L, C, G0, and G2CG5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to VCC; clock monitor and comparator disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register. Part will pull up CKI during HALT in crystal clock mode.
The TLC3541 and TLC3545 are designed to operate with low power consumption. The power saving feature is further enhanced with an auto-power down mode. This product family features a high-speed serial link to modern host processors with an external SCLK up to 15 MHz. Both families use a built-in oscillator as the conversion clock, providing a 2.67 µs maximum conversion time.
  The GPIB interconnects up to 15 devices over a commom set of data control liners. Three types of devices are defined by the standard: talker, listener, and controller, atthough some devices may combine functions such as talker/listener or talker/controller.   Data on the GPIB is transferred in a bit-parallel, byte-serial fashion over eight data I/O lines (/DIO[1]-/DIO[8]). A three-wire handshake is used to ensure synchronisation of transmission and reception. In order to permit more than one device to receive data at the same time, these control lines are "open collector" so that the slowest device controls the data rate. A number of other control lines perform a variety of functions such as device addressing, interrupt generation and so forth.   The TA8068 implements all functional aspects of talker and listener as defined by the 488.1-1987 Standard on a single chip.