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In addition to the power-on-reset and undervoltage-supervisor function, the TLC77xx adds power-down control support for static RAM. When CONTROL is tied to GND, RESET will act as active high. The voltage monitor contains additional logic intended for control of static memories with battery backup during power failure. By driving the chip select (CS) of the memory circuit with the RESET output of the TLC77xx and with the CONTROL driven by the memory bank select signal (CSH1) of the microprocessor (see Figure 10), the memory circuit is automatically disabled during a power loss. (In this application the TLC77xx power has to be supplied by the battery.)
If the state of the selected CAP/MAT signal is 1 and EDGE is set to detect rising edges (EDGE = 0) or, if detection of falling edges is selected (EDGE = 1) and the state of the selected CAP/MAT signal is 0, an ADC conversion will immediately be initiated when the START bits are written to. So the first conversion behaves as a level triggered event rather than edge triggered.
NOTES: 1. Unused inputs must be held HIGH or LOW to prevent them from floating. 2. DC input signal voltage specifies the allowable DC execution of differential input. 3. Differential input signal voltage specifies the differential voltage |VTR - VCP| required for switching, where VTR is the true input level and   VCP is the complementary input level. 4. Differential cross-point voltage is expected to track variations of VCC and is the voltage at which the differential signals must be crossing.
Parr number/PDF Mfg Pack D/C Descrpion
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ULN3784   ULN3784 ULN3784 PDF Download   Designed for WCCDMA base station applicat
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ULN3804A-21   ULN3804A-21 ULN3804A-21 PDF Download   1.1 Scope. This specification covers the
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ULN3812A   ULN3812A ULN3812A PDF Download 87 Note A: All data listed in the above graphs, exc
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ULN3839A1   ULN3839A1 ULN3839A1 PDF Download This MOSFET is an enhancement-mode silicon-gate
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ULN383P   ULN383P ULN383P PDF Download Up to 18-A Output Current 5-V Input Bus Wide-Ou
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