| Parr number/PDF | Mfg | Pack | D/C | Descrpion |
| XW2B-40G4 XW2B-40G4 |
Pixel Clock Input To operate in a pure master mo | |||
| XW2B-40G5 XW2B-40G5 |
The return side of the external inductor shall b | |||
| XW2Z-050B XW2Z-050B |
3.2 Manchester Encoder The Manchester encoder re | |||
| XW2Z-100B XW2Z-100B |
It has OVP functions for +3.3V,+5V,+12V outputs | |||
| XW2Z-200A XW2Z-200A |
Maximum ratings are those values beyond which de | |||
| XW2Z-200B XW2Z-200B |
TXENABLE has two purposes. In all modes, TXENABL | |||
| XW2Z-S002 XW2Z-S002 |
NOTES: 1. Dimensions are in inches. &nbs | |||
| X.D.861 X.D.861 |
Once a charge cycle begins, the bq2902 terminates | |||
| X.J.861 X.J.861 |
In contrast to the BTS 7710 G, which consists of | |||
| X0001 X0001 |
These parts are designed on an enhanced process | |||
| X0001PA X0001PA |
N/A | 06+ | 500 | 5VSBY is the bias supply of the ISL6537A. It is t |
| X0004 X0004 |
The XC9301/02 series are step-up/down DC/DC conv | |||
| X0007 X0007 |
nRF902 is a single-chip transmitter for the 868 M | |||
| X0007TA X0007TA |
HITACHI | DIP-16 | 98 | The two PWM controllers that regulate the system |
| X0018 X0018 |
SHARP | Todo el material que no es necesario fu retirado | ||
| X0018PA X0018PA |
HITACHI | DIP-14 | 98 | The X0018PA is a high-speed triple 8-bit monolith |
| X0020 X0020 |
The ISL6118 is a dual channel, fully independent | |||
| X0021 X0021 |
CLK: with each cycle of this signal a one- | |||
| X0022 X0022 |
XICOR | DIP | 04+ | The SO-8 has been modified through a customized |
| X0025CE X0025CE |
||||
| X0028 X0028 |
. | . | 2023 | 135-mΩ -Maximum (5-V Input) High-Side MOSF |
| X0028AP X0028AP |
SONY | . | 100 | The ADM666A has an additional comparator, C4, th |
| X0028PA X0028PA |
SONY | RFMs amplifier-sequenced hybrid (ASH) transceiver | ||
| X0030-2 X0030-2 |
ST | 01+ | • Internal Avalanche Rugged SenseFET R | |
| X0030-3 X0030-3 |
ST | |||
| X0034 X0034 |
10-Bit Resolution Non-Linearity: 1/2 LSB to 2 LS | |||
| X0035TA X0035TA |
SHARP | Unless otherwise noted, a positive logic (active | ||
| X0038TA X0038TA |
The CY7C1350G is a synchronous-pipelined Burst SR | |||
| X004 X004 |
The ERAL instruction erases the entire 128´ | |||
| X0040TA X0040TA |
N | 06+ | 750 | © 2002 STMicroelectronics C Printed |
| X0042CE X0042CE |
||||
| X0043 X0043 |
Two important wavelength ranges (windows 2 and 3) | |||
| X0043CE X0043CE |
HIT | Please read the General Operating Conside | ||
| X0044 X0044 |
The Mini-ACE contains internal address latches a | |||
| X0047 X0047 |
SHARP | DIP | 00+ | An on-chip state machine controls the program an |
| X0048 X0048 |
LMD is the last measured discharge capacity of th | |||
| X0048CE X0048CE |
SHARP | DIP-20 | 97+ | Hynix HYMD132G725B(L)4M-M/K/H/L series is designe |
| X0049 X0049 |
Current Settling Time, Clocked Mode Current Set | |||
| X004L36864MHZ X004L36864MHZ |
For enhanced performance, the VRE3041 has an ext | |||
| X0050 X0050 |
© 2000 Xilinx, Inc. All rights reserve | |||
| X0051 X0051 |
4.4.3 Group C inspection. Group C inspect | |||
| X0052 X0052 |
Minimum Quiet Time required between Bus Re | |||
| X0052CE X0052CE |
SONY | The CBTS3253 is a dual 1-of-4 high-speed TTL-com | ||
| X0053 X0053 |
† All typical values are at VCC = 5 V, TA | |||
| X0053CE X0053CE |
N/A | N/A | N/A | |
| X0054CE X0054CE |
This family of four, eight, and sixteen differen | |||
| X0-055BHT-20.48000 X0-055BHT-20.48000 |
NOTES 1Temperature range from C40C to +85C. 2Op | |||
| X0056GE X0056GE |
N/A | N/A | N/A | Asasecond-generationHOTLinkdevice,the CYP(V)15G0 |
| X0056GE/HD38820L02 X0056GE/HD38820L02 |
Members of the Texas Instruments SCOPE Fa | |||
| X0057GE X0057GE |
N/A | N/A | N/A | Notes: 12341. Solder pads must not be pe |
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