| Mfg | pack | D/C | Descrpion | ||
| 2-- | (1) | UL Recognized File # E-96005 Ideal for printed circuit board | |||
| 2.0 | (34) | TOSHIBA | 23-2V | 05+ | Footprint compatibility in common packages within the XC52 |
| 2.1 | (10) | CALEX | 2007 | SW: An inductor is connected between this node and VIN. The VGD (Gate Dr | |
| 2.2 | (73) | NXP | 97+ | Please take note of the differences among products before testing and dev | |
| 2.3 | (38) | VISHAY | NOTES: 1. For conditions shown as Min. or Max., use the appropriate valu | ||
| 2.4 | (32) | TOSHIBA | 04+ | solution to be used worldwide • Superior alternative to ca | |
| 2.5 | (22) | N/A | 2x2 | Mono-channel multi-level D/A converter High performance analog characteri | |
| 2.6 | (5) | NS | DIP | 8933 | The AD581 is ideal for application with the entire AD7533 series of 10- |
| 2.7 | (29) | 99 | SOP | DC bus capacitor filter with NTC inrush current limiter IR2132 | |
| 2.8 | (3) | Unlike other nonvolatile memory technologies, there is no effective wri | |||
| 2.9 | (5) | N/A | SOT-89 | 04+ | Bus integrity check feature allows the system to recover from a bus han |
| 2/1 | (22) | ||||
| 2-0 | (34) | AMP | 03+ | During power-on, RESET is asserted when the supply voltage VDD becomes hi | |
| 20- | (165) | ST | 05+ | SOP-20 | Power Factor World Wide Line Operation Over-Voltage Protection Accurate |
| 20. | (46) | 20000 | These TTL hex buffers/drivers feature high-voltage open-collector outpu | ||
| 20/ | (2) | ||||
| 200 | (546) | 1206T | The KS8721BL/SL automatically configures itself for 100Mbps or 10Mbps a | ||
| 201 | (362) | N/A | 0805BEAD | The devices in this family differ from each other in their switch- point | |
| 202 | (311) | JRC | SOP | Min. Typ. Max. UnitsConditions 30CCC CCCVVGS = 0V, ID = 250µA | |
| 203 | (183) | IC | 集成电路 | 74HC4066D | +s ELECTRICAL CHARACTERISTICS (V =3.0V,RL=8Ω,f=1kHz,1pin=2V, |
| 204 | (194) | CONEXANT | QFN | Data of C1 , C2 and C3 code bit become 1 when diodes are connected | |
| 205 | (282) | TI | The functions performed by the 470+ system module (SYS) include: • | ||
| 206 | (334) | 04+ | * UL is a registered trademark of Underwriters Laboratories, Inc. † | ||
| 207 | (307) | INTERSIL | LCC超微 | To define the active polarity of a signal, a suffix will be used. | |
| 208 | (245) | QFN | 38503 | IN | The VSC7924 is a single 5V supply, 2.5Gb/s laser diode driver with |
| 209 | (113) | IC | 集成电路 | 74HC573N | Quality Digital Audio Amplification 93-dB Dynamic Range (TDAA System) TH |
| 20A | (23) | RCA | CAN8 | 06+ | Fast synchronization. When asserted high, the transmitter substitutes the |
| 20B | (19) | IR | SMB | 05+ | DESCRIPTION The ACT02 is an advanced high-speed CMOS QUAD 2-INPUT NOR |
| 20C | (84) | TO-220 | Regulation is measured at constant junction temperature using low duty cy | ||
| 20D | (18) | TOS | TO-3P | 04+ | UL Recognized File # E-96005 Glass passivated junction &nb |
| 20E | (46) | TOPLINE | 99+ | Supports PIO mode 4, both at 16.6 Mbytes/second theoretically Sustained | |
| 20F | (31) | TO- | DYNAMIC PERFORMANCE Signal-to-Noise + Distortion (SINAD)3 To | ||
| 20G | (11) | TO-262 | 03+ | The information contained in this document does not convey any license u | |
| 20H | (20) | IBM | 98+ | QFP | The Fairchild Switch FST16213 provides 24-bits of high- speed CMOS TTL- |
| 20I | (8) | (1) The DW, PW and DSH packages are available taped and reeled. Add an R | |||
| 20J | (6) | TOSHIBA | TO3P | Dropout voltage is defined as the input-to-output differential at wh | |
| 20K | (10) | The CS4271s wide dynamic range, negligible distor- tion, and low noise ma | |||
| 20L | (56) | IR | TO | The following are trademarks of Conexant Systems, Inc.: Conexant™, | |
| 20M | (25) | MCCOY | DIP14晶振 | 91+ | bit or any arbitrary channels in ESF mode. The signaling insertion, idle |
| 20N | (32) | NIEC | 07+/08+ | The WM8802 is controlled via a 4-wire CCB compatible control interface. T | |
| 20P | (38) | MOT | 00+ | TO252-2脚半 | Case: SOD-523, Plastic Case material - UL Flammability Rating Classifica |
| 20Q | (2) | SHARP | 06+ | The battery protection monitors the battery voltage and charge/discharge | |
| 20R | (22) | TI | PLCC | (3) The products described in this material are intended to be used for s | |
| 20S | (23) | N/A | N/A | N/A | The PIP processor SDA 9188-3X handles picture reduction (decimation with |
| 20T | (18) | ICS | SOP8 | 1) CPD is defined as the value of the ICs internal equivalent capacitance | |
| 20U | (2) | N/A | The specification of 20U6P45A is identical to the specification for 20U6P | ||
| 20V | (45) | SHARP | TO263 | 91 | This advanced BiCMOS design features low operating current, adjustable |
| 20W | (8) | LEXMARK | 0804/0821 | This document is a general product description and is subject to change wi | |
| 20X | (4) | ||||
| 20Y | (2) | TOSHIBA | 23-20V | 05+ | NEC's NE552R479A is an N-Channel silicon power laterally diffused MOSFET |
| 2-1 | (327) | TYCO | 423 | Unique 1-wire interface requires only one port pin for communication Der | |
| 21- | (101) | MARUNIX | 06+ | SMD | Under-Voltage Lockout An Under-Voltage Lock-Out (UVLO) inhibits the ope |
| 21. | (17) | NO | 03+ | ||
| 21/ | (1) | • Suppresses low-frequency noise, which output from CCD by the corre | |||
| 210 | (592) | N/A | N/A | N/A | The device offers access times of 80, 90, and 120 ns, allowing high spe |
| 211 | (310) | INTEL | 04+ | NOTES: 1. All typical values are at VCC = 5 V, Tamb = 25 C 2. This is | |
| 212 | (152) | Please be aware that an important notice concerning availability, | |||
| 213 | (219) | AMD | 92+/97+ | PLCC28 | START Pin 17 - This is an open-drain pull-down digital output pin; it is |
| 214 | (129) | AD | LVPECL, PECL, ECL compatible synchronous enable: When /EN goes HIGH, the | ||
| 215 | (418) | PHI | BGA | 01+ | Parameter Total Gate Charge (turn-on) Gate - Emitter Charge (turn |
| 216 | (467) | ATI | BGA | Quad D-MOS switch Free configurable as bridge or quad-switch Optimized f | |
| 217 | (55) | IR | SOP | 00+ | Stresses beyond those listed under "Absolute Maximum Ratings" ma |
| 218 | (136) | ATI | (SX)computer IC | 03+ | The MT8985 master clock (C4i) is a 4.096 MHz allowing serial data link con |
| 219 | (75) | When valid data on the TX pins detected, the jabber timer is started. I | |||
| 21A | (10) | SMD-8 | 05+ | Input Equivalent Circuit To prevent static charges, protective diodes ar | |
| 21B | (1) | KYOCERA | 0805-105K | Notes: 1. For Max. or Min. conditions, use appropriate value specified u | |
| 21C | (17) | HIT | QFP/48 | 1998 | Burst Write Accesses The CY7C1350G has an on-chip burst counter that allo |
| 21D | (13) | NIE | 0 | The Intersil portfolio of Star*Power FETs includes a family of devices i | |
| 21E | (1) | N/A | N/A | N/A | CAUTION: These devices are sensitive to electrostatic discharge; f |
| 21F | (7) | JST | 04+ | Advanced submicron CMOS technology makes the Am79Q02/021/031 QSLAC devi | |
| 21H | (10) | 90 | LSI | 98+ | •Built-in digital delay , mixing amplifiers,input output selector |
| 21K | (3) | QFP-20P | 6+ | VRE114/115/116 devices are available in two operating temperature ranges, | |
| 21L | (28) | IBM | BGA | ||
| 21M | (13) | FAI | DIP | 02+ | At 2 GHz, the ABA-31563 offers a small-signal gain of 21.5 dB, output P1 |
| 21N | (13) | M/ST | TO-252 | Note 2 Operating Ratings indicate conditions for which the device is func | |
| 21P | (10) | INTEL | 07+ | Features ❏ InGaP HBT Technology ❏ 6mm Square, 50 Ohm Power | |
| 21R | (12) | The K1S1616B1A is fabricated by SAMSUNGs advanced CMOS technology | |||
| 21S | (16) | ST | SOP-16 | 01+ | 7. Series resistance of the resonator (ceramic resonator or crystal) shoul |
| 21T | (12) | 05+ | SMD | This is a dual-function pin. In the CY Standard mode, the FF function is | |
| 21U | (1) | The information contained herein is presented only as a guide for the app | |||
| 21V | (1) | CAUTION: Stresses above those listed in Absol24ute Maximum Ratings may ca | |||
| 21W | (15) | ATI | BGA | 5 | The BCT543 octal transceiver contains two sets of D-type latches for te |
| 21Y | (4) | KYOCERA | 4K/R | The front end also includes a 12-channel input mux that enables multiple | |
| 21Z | (2) | BI | 4X4-50K | 05+ | Configuration EPROMs for FLEX Devices Data Sheet BitBlaster Serial Downl |
| 2-2 | (30) | AMI | Product of input modulation: f = 44MHz, Df = 214MHz p-p and f = 6MHz, Df | ||
| 22- | (518) | Molex | connector | 06+ | Room = 25C, Full = as determined by the operating suffix. Typical values |
| 22. | (13) | TXC | Maxim evaluates pressure pot stress from every assembly process du | ||
| 22/ | (1) | SYM=POWMOSN .SUBCKT 501N16A 10 20 30 * TERMINALS: D G S * 500 Volt 16 A | |||
| 220 | (405) | 东芝 | 02+ | The DS1258W provides full functional capability for VCC greater than 3.0V, | |
| 221 | (372) | NS | DIP-14 | Note: 1. Package body sizes exclude mold flash and gate burrs 2. Dimensi | |
| 222 | (1280) | SIEMENS | 08+ | The D-Pak is designed for surface mounting using vapor phase, infrared, o | |
| 223 | (373) | AD | The DS1249AB provides full functional capability for VCC greater than 4. | ||
| 224 | (139) | ZENITH | 00+ | The LNP has differential input and output capability and is strappable | |
| 225 | (173) | N/A | Note: 6. Distribution data sample size is 398 samples taken from 4 differ | ||
| 226 | (81) | IC | 集成电路 | 74HCT238N | Unless otherwise stated, VDD = 3.3V 10%, no load on any output, and ambi |
| 227 | (133) | SOP8 | Circuit Breaker Sense Input: A resistor between this pin and VEE sets the | ||
| 228 | (90) | JRC | 04+ | The input thresholds are 0.8V minimum and 2.4V maximum, again well with | |
| 229 | (129) | AMP | 93+ | CPU • Operating voltage range : 2.5V~5.5V • 16Kx13 on chip R | |
| 22A | (11) | TSSOP | 05+ | cycle, an internal 10-bit counter provides the row ad- dre | |
| 22B | (2) | 22BNC-50-0-5/133 is a Darlington power transistor module with a ULTRA HIGH | |||
| 22C | (41) | ST | DIP | The CY7C646xx uses a 12-MHz crystal for low EMI. An internal oscillator a | |
| 22D | (7) | NEC | 06+ | Hewlett-Packards HSMS-2850 family of zero bias Schottky detector diodes | |
| 22E | (1) | N/A | N/A | N/A | The detected signal is full-wave rectified and integrated by use of the I |
| 22F | (7) | JST | 07+ | TAOperating free-air temperatureC55125C4085C ‡ If this devic | |
| 22G | (1) | IR | TO-254AA | 00+ | Thirteen CLB inputs and four CLB outputs provide access to the function |
| 22H | (2) | 05+ | SMD | This is the master clock input pin. The clock signal applied to t | |
| 22J | (1) | Temperature Operating5 ~ 55 C Non-operating-40 ~ 70 C &nbs | |||
| 22K | (5) | Please be aware that an important notice concerning availability, | |||
| 22L | (9) | MOT | N/A | pulse one period) on the application of each new trigger pulse. For ope | |
| 22M | (11) | PHI | 06+ | 3.3V LVTTL input for selection the current multiplier for CPU outputs Co | |
| 22N | (29) | S+M | 07+ | The 1-wire serial communication port (5Kb/s) allows an external processor | |
| 22O | (1) | ||||
| 22P | (5) | 2008 | • Compact & flat design: 22 mm .866 inch (length) 14 mm . | ||
| 22R | (12) | IR | TO-208AA (TO-48) | 00+ | DATA (Pin 8): Input/Output. Microcontroller side data I/O pin. The DATA p |
| 22S | (7) | MOT | SOP8 | The PCI-Express differential clock outputs of the ICS557-03 are open so | |
| 22T | (18) | 超微10脚 | 05+ | ||
| 22U | (61) | 08+ | The HYM72V32636H(L)T8 Series are Dual In-line Memory Modules suitab | ||
| 22V | (65) | AMD | 06+ | When operated with additional external load capacitance the rise time of | |
| 22W | (3) | STM | DIP-8 | 91+ | |
| 22Y | (3) | Sense(C): Provides the regulator with the ability to sense the set-point | |||
| 2-3 | (224) | AMP/TYCO | 9807 | Cirrus Logic, Inc. and its subsidiaries (Cirrus) believe that the informat | |
| 23- | (49) | 0 | ECCP2/P2A are multiplexed with RC1 when CCP2MX is set; with RE7 when CCP2 | ||
| 23. | (7) | ZION | SMD | 2000 | The various versions of the TDA 884X/5X series are I2C-bus controlled s |
| 230 | (243) | IDT | 04+ | SOP-3.9-16P | Spectrum. The finite Fourier transform (FFT) of the discrete-time-sampled |
| 231 | (81) | IC | 集成电路 | 74HCT374D,652 | Note 5: The maximum power dissipation must be derated at elevated tempera |
| 232 | (1494) | SOLUTION | 06+ | SOP-8 | n Sector Protection C Sectors may be locked to prevent pr |
| 233 | (126) | INFINEON | NEWBGA | 03+ | Peaking frequency calibration pin. ∗ Controlled with DC v |
| 234 | (111) | 2008 | Case: JEDEC TO-220AB molded plastic body Terminals: Plated leads, solde | ||
| 235 | (138) | 0402X8 | The Hyundai HYM71V75S1601 H-Series are 16Mx72bits ECC Synchronous DRAM Mod | ||
| 236 | (65) | IC | 集成电路 | 74HCT574D,652 | With a large amount of external memory, the B427 is able to run all of |
| 237 | (85) | IC | 集成电路 | 74HCT595D,112 | California Micro Devices's CM1406 is an EMI filter array with ESD prote |
| 238 | (66) | JRC | 04+ | The Hynix HYM71V8M655B(L)T6 Series are 8Mx64bits Synchronous DRAM Modules. | |
| 239 | (97) | AST | QFP | 07+ | Operating Voltage Range of 4.5 V to 5.5 V High-Current 3-State True Outpu |
| 23A | (22) | BI | 5X5-200K | 05+ | count in the count-down mode. Cascading of multiple packages is easily |
| 23B | (19) | BI | 5X5-2K | 04+ | Multiplexed PCI address/data bus. A bus transaction consists of an addres |
| 23C | (65) | 98 | This family is a 16M bit dynamic RAM organized 2,097,152 x 8-bit configura | ||
| 23D | (14) | MOT | 99 | † Stresses beyond those listed under absolute maximum ratings may c | |
| 23E | (4) | PULSE | SMD6高膜 | 04+ | Four sets of de-emphasis-filter coefficients support four sampling rates |
| 23F | (9) | N/A | PLCC | 07+ | ACCURACY Linearity Error(1) Linearity Match Differential Linearity E |
| 23G | (2) | COPAL | • Super bright LED for optical fiber communication • High acc | ||
| 23H | (6) | NSC | SOP20 | 01+ | A programmable receive packet interrupt scheme using a timer (RXINTT) a |
| 23J | (19) | BI | tr, tf0.11.0ns0.55 to 2.4V AC characteristics apply for parallel o | ||
| 23K | (1) | SANYO | 96 | The reliability data follows. Some of the data in this report may be gener | |
| 23L | (7) | MX | 8776 | AC97 3D audio controller Supports Serial ATA controller Fast PCI ATA/33/ | |
| 23M | (2) | CAUTION: These devices are sensitive to electrostatic discharge; follow p | |||
| 23N | (4) | A force of 1.0 Kg shall be applied to each terminal in the direction of th | |||
| 23O | (1) | The 23OB00080TCCA is an ultra-low noise, wideband amplifier that runs on | |||
| 23P | (10) | ON | TO-220 | 03+ | State-of-the-Art EPIC-B ™ BiCMOS Design Significantly Reduces Power |
| 23S | (10) | NIPPON | Maximum ratings are those values beyond which device damage can occur. M | ||
| 23T | (16) | 01+ | TSSOP-8 | Frame Synchronization signal (For MPI)/Frame Sync signal (For GCI). In M | |
| 23X | (1) | ||||
| 23Z | (85) | PULSE | SMD-8P | 1999 | Sensitivity, a commonly specified receiver parameter, provides an indicat |
| 2-4 | (23) | AMP | Maximale Streuung des Widerstandswertes bei der Temperatur T in % Nennto | ||
| 24- | (69) | ROSTRA | 02+ | PLCC44 | The ACT16241 are 16-bit buffers or line drivers designed specifically t |
| 24. | (37) | N/A | DIP | 03+ | An internal oscillator strobes power to the smoke detection circuitry for |
| 24/ | (1) | ||||
| 240 | (273) | 2007 | fixed off-time. CT also sets the BLANK time (see the section App | ||
| 241 | (120) | 500 | ST | SOP-8P | The output drivers in the HIP6602B have the capacity to efficiently switc |
| 242 | (117) | IC | 集成电路 | 74LCX126MX | DESCRIPTION Dual center tap rectifier suited for Switch Mode Power Supp |
| 243 | (47) | IR | D67 | 01 | Notes: 1. Repetitive Rating : Pulse width limited by maximum junction tem |
| 244 | (63) | Fuj | 92+ | The 244N is a high dynamic range amplifier tar- geting cable TV markets. | |
| 245 | (83) | IC | 集成电路 | 74LCX244WMX | The 8th bit of the control register is the write bit. Setting the write bi |
| 246 | (81) | TI | SMD8 | Notes: 1. For Max. or Min. conditions, use appropriate value specified u | |
| 247 | (29) | NS | DIP14陶瓷 | The SM5009 series are crystal oscillator module ICs that incorporate low | |
| 248 | (32) | NDK | 05+ | ♦ 72dB ACLR at fOUT = 61.44MHz (Single-Carrier WCDMA) ♦ | |
| 249 | (48) | IR | SOP | Thaler Corporation has developed a nonlinear compensation network | |
| 24A | (335) | MICROCHIP | 08+PBF | The Parallel Input/Output Controller (PIO) controls up to 32 I/O lines. I | |
| 24B | (10) | SOP8 | The analog input RGB signals are first sampled by three channels of 8-bit | ||
| 24C | (1057) | TRWRXRF | 05+ | DESCRIPTION The VND600PEP is a monolithic device made usingSTMicroelect | |
| 24D | (32) | N/A | module | 2005+ | Stresses beyond those listed under "absolute maximum ratings" m |
| 24E | (28) | ST | SOP8S | 2007+ | |
| 24F | (95) | STM | DIP-8P | 95+ | The DG534A/DG538A are built on a D/CMOS process that combines n-channel |
| 24G | (6) | An optional feedback resistor can be placed between the COUT terminal of t | |||
| 24H | (22) | NS | 02+ | SOP-8 | DESCRIPTION The NJW1503A is a PLL frequency synthesizer es |
| 24I | (37) | N/A | DATA POLLING: The AT28C010-12DK features DATA Polling to indicate the end | ||
| 24K | (2) | N/A | 1. Life support devices or systems are devices or systems which, | ||
| 24L | (1012) | MICROCHIP | 08+PBF | Short Circuit Applied to Output When a heavy load is applied, a large tra | |
| 24M | (15) | MOT | PLL-32 | 1998+ | VCC is the main 5V supply, which can be disabled in a PC, and VSBY is t |
| 24N | (10) | 560 | TO252 | 04+ | • 30 Mil Square Size. • Resistance Range: (Silicon |
| 24P | (23) | Honeywell | 915 | Hitachi Asia Ltd. (Taipei Branch Office) 4/F, No. 167, Tun Hwa North | |
| 24Q | (4) | Quantum | PBGA | Differential PECL compatible outputs 700 ps propagation delay input to | |
| 24R | (15) | PHILIPS | BGA | 05+ | Hold: Indicates that another master is requesting the use of the address |
| 24S | (53) | TECH FRONT | SMD24 | The OPA743 series utilizes a state-of-the-art 12V analog CMOS process an | |
| 24T | (18) | UNTSEM | 712 | NOTES: 1. Dimensions are in inches. 2. Metric equivalents | |
| 24U | (50) | FDS | SMD-8 | 05+ | 1. Connect the device as follows: source to E, gate to B, drain to C. Thi |
| 24V | (16) | Note All information contained in this data sheet has been carefully chec | |||
| 24W | (190) | CSI | SOP-8 | 2006 | The S2/SUSPEND input can be configured to shut down a customizable set of |
| 24X | (5) | • Added Reverse Type Package in ODERING INFORMATION and PIN CONFIGUR | |||
| 24Y | (7) | CSI | TSSOP8 | 05+ | High Voltage Electrically Isolated by DBC Ceramic ( Al 2 O 3) 3500 V RMS |
| 24Z | (2) | The ADR512 is a 1.2 V precision shunt voltage reference. It is designed | |||
| 2-5 | (156) | AMP/TYCO | 01+ | n 832 Mbps LVDS 16-bit serializer and deserializer interface &nb | |
| 25- | (22) | UTC | SOT-23 | 07+ | s Secured Silicon (SecSi™) Sector Factory locked and iden |
| 25) | (1) | You can determine the version of a data sheet by examining its literature | |||
| 25. | (42) | N/A | EPS0N | 04+ | |
| 250 | (407) | KOA | SOP20 | The readout procedure is shown in figure 1. This procedure is valid for a | |
| 251 | (220) | MATSUO | 06+ | Available in the Texas Instruments NanoStar and NanoFree | |
| 252 | (166) | TAIYO | 03+ | THESE MATERIALS ARE PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER E | |
| 253 | (101) | IC | 集成电路 | 74LVC08APW,112 | The 2538/2538/2538 resistance is con- stant over temperature. The typical |
| 254 | (86) | BT | QFP | 9910+ | Single Byte/Single Cycle Code Execution The efficiency is due to the fac |
| 255 | (73) | capacitance | VISHAY | 08+ | Channel B LNP Inverting Input Channel B Frequency Compensation 2 Chann |
| 256 | (149) | INTEL | BGA | N/A | Notes: 1. Test conditions assume signal transition times of 5 ns or less |
| 257 | (89) | IC | 集成电路 | 74LVC161PW-T | The parameter tOH indicates the system compatibility of this device when |
| 258 | (59) | FSC | 06+ | 530 | Catalog Symbol: JJN Current Limiting Very Fast Acting Ampere Rating: 1 |
| 259 | (75) | IOMEGA | QFP | The 40105 can be cascaded to form longer registers simply by connecting | |
| 25A | (178) | MICROCHIP | 08+PBF | • Superior Performance in Outdoor Environments • Wa | |
| 25B | (18) | SEEQ | DIP | 05+ | Refer to Fig. 12 evaluation amplifier assembly drawing. Attach a regulate |
| 25C | (273) | SANYO ELECTRIC | na | The ADC08D1500 is a dual, low power, high performance CMOS analog-to-dig | |
| 25D | (7) | TI | 798 | READ: The AT49BV/LV040 is accessed like an EPROM. When CE and OE are low | |
| 25E | (15) | Level Conversion Circuit The 25EK241 has a built-in level conversion cir | |||
| 25F | (53) | SAIFUN | 02+ | SOP8 | Similar to its analog input structure, the MAX104 features clock inputs d |
| 25G | (7) | IR | 07+ | The transmitter converts electrical PECL compatible serial data (TD and | |
| 25H | (49) | SG | 1808-500MA | The DS26F32 is a quad differential line receiver designed to meet the req | |
| 25I | (1) | 1% output voltage accuracy Low noise Only 90µA ground current at 1 | |||
| 25J | (4) | N/A | 03+ | MSOP8 | NOTE: Intersil Pb-free products employ special Pb-free material sets; mol |
| 25K | (1) | The DSP supports nested and nonnested interrupts. Each inter- rupt type | |||
| 25L | (383) | MICROCHIP | 08+PBF | The device supports low-power standby operation. When RESET is low, the d | |
| 25M | (43) | PLX | 01+ | N/A | The 25M000A dual, 8-bit, 300Msps digital-to-analog converter (DAC) provid |
| 25N | (16) | ST | SOP8 | 04+ | The phantom clock information is contained in eight registers of 8 bits, |
| 25O | (1) | n CCITT G.726 compatible at 40, 32, 24, 16 kbps n ANSI T1.301 compatible | |||
| 25P | (159) | ST | 94+ | A serial (QH) output is provided for cascading purposes. Both the shift | |
| 25Q | (2) | N/A | N/A | N/A | 3.3/5.0 VOLT SELECT: 3/5 » high configures internal circuits for 3. |
| 25R | (48) | xxxx | n/a | • SPORTs have independent framing for the receive and trans- | |
| 25S | (58) | DIP16 | AMD | Fixed regulator output (Regulator #2) C It is recommended to bypass to GND | |
| 25T | (42) | 04+ | SMD | Product term sharing is the process of using the same product term among | |
| 25U | (6) | high-frequency tube | MOTOROLA | 04+ | Write-only control and status Read multiple command for data transfer U |
| 25V | (78) | INFINEON | BGA | PWM control function Motor speed can be controlled by inputting the 0/5- | |
| 25W | (56) | ST | DIP | 91 | Conditions IO33 Pad Library Provides Interface to 3V Environment Oscilla |
| 25X | (8) | SOP8 | Receive byte clock. RBC0 and RBC1 are 62.5-MHz recovered clocks used for | ||
| 25Y | (79) | CATAYST | TSSOP-8 | 05/06+ | (5) The products and product specifications described in this material ar |
| 25Z | (9) | Note 1: The pout (W) represents the thermal rating at PRC Operation. The | |||
| 2-6 | (215) | 19 | ADC | 99+ | *) The terminating impedances depend on parasitics and q-values of matchin |
| 26- | (205) | Molex | connector | 06+ | SDRAM Controller C 2 memory banks, non-interleaved, 512 MB |
| 26. | (13) | KSS | 3225 | 06+ | |
| 260 | (86) | AD | MODEL | DESCRIPTION When 1, all subsequent reads are from the Data Memory | |
| 261 | (58) | IC | 集成电路 | 74LVC1G19GW,125 | Palladium plating is used on the terminal pins. A pin temperature (Tp) in |
| 262 | (126) | IC | 集成电路 | 74LVC2245APW | |
| 263 | (39) | TI | TSOP16 | Programmable versions of the PT6700 and PT6720 series of Excalibur ISRs | |
| 264 | (92) | IC | 集成电路 | 74LVC32AD | 1. IGBT has MOS structure and its gate is insulated by thin silicon oxide |
| 265 | (58) | NS | O7+ | Some confusion exists in the area of defining and specifying reference v | |
| 266 | (55) | AMI | QFP160 | The internal circuit is composed of 4 stages including buffer output, wh | |
| 267 | (141) | MATSUO | 06+ | Programmable options include the length of pipeline (Read latency of 2 or | |
| 268 | (25) | S | CDIP40 | M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on S | |
| 269 | (86) | AMP | AMP | 00+ | The TPS752xx or the TPS754xx are offered in 1.5-V, 1.8-V, 2.5-V, and 3.3- |
| 26A | (12) | SOP8S | 2007+ | The AD8021 is not only technically superior, but also priced considerabl | |
| 26B | (2) | IR | MODULE | The information appearing in this Data Sheet is believed to be accurate at | |
| 26C | (30) | MX | O7+ | Optocouplers (optical couplers) are designed to isolate electrical output | |
| 26D | (5) | ATMEL | 07+ | Unique 1-wire interface requires only one port pin for communication Der | |
| 26E | (5) | SOP16 | ble 5) is sent first, followed by the Least significant Byte (Table 6). | ||
| 26F | (13) | SOP16M | 2007+ | The LT®4250L/LT4250H are 8-pin, negative 48V Hot SwapTM controllers | |
| 26H | (19) | IBM | TQFP64 | 2007+ | 1.1 Scope. This specification covers the performance requirements |
| 26J | (1) | If the port is left in a forced 1394b beta only (B1, B2, or B4) mode, the | |||
| 26K | (1) | 3.1 Item requirements. The individual item requirements for device | |||
| 26L | (77) | MX | 2000 | 03+ | The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) |
| 26M | (34) | IR | 07+ | Drives External N-Channel FETs Intelligent High-Side Gate Drive Selectab | |
| 26N | (2) | TO-3P | PWM Signal Input C Connects to the internal reference, via an internal fi | ||
| 26P | (31) | Honeywell | 468 | WARNING: The recommended operating conditions are required in order to en | |
| 26S | (5) | SUMMARY DESCRIPTION The M29W400B is a 4 Mbit (512Kb x8 or 256Kb x16) no | |||
| 26T | (18) | N/A | TSSOP8 | The product specifications contained in this data sheet are subject to ch | |
| 26U | (2) | These Thyristor Surge Protective Devices (TSPD) prevent overvolta | |||
| 26V | (6) | AMD | PLCC28 | 9625+ | As shown in Equation 2 and Equation 3, large capacitor values for the in |
| 26W | (1) | n/a | 0323 | 4 | Stresses above these ratings may cause permanent damage. Exposure to abso |
| 26Y | (1) | Eight sectors with 512 Kb each Program Page Program (up to 256 bytes) i | |||
| 26Z | (3) | VITEC | 00+ | 66-MHz, 64-bit PCI host bus interface Backward compatible to standard 33 | |
| 2-7 | (48) | TYCO | N/A | 06+ | Note 2: The Absolute Maximum Ratings are those values beyond which the sa |
| 27- | (76) | PHI | TQFP-M64P | 07+ | GAPPED MODELS: Capable of handling large amounts of DC current, tighter i |
| 27. | (23) | NDK | SOT | 05+ | Medium-range Cable, satellite, and IP set-top boxes Digital video recorde |
| 270 | (110) | ST | SOP-14P | 07+ | The Rambus Direct RDRAM™ is a general purpose high-performance memo |
| 271 | (90) | INTEL | CWDIP28 | —— | Figure 4 illustrates the differential or gauge configuration in t |
| 272 | (80) | NS | O7+ | Another key feature of the C67x CPU is the load/store architecture, where | |
| 273 | (58) | IC | 集成电路 | 74LVX74MTCX | PIN DESCRIPTION This pin provides shutdown for all the regulators. |
| 274 | (90) | BEL | ++ | FET control: Optional. Output during every Read and Write access. Is prov | |
| 275 | (47) | JRC | SOP | 03+/04 | (1) Offset error is the deviation of the average code from mid-code for a |
| 276 | (69) | IC | 集成电路 | 74VHC04MTCX | The 2761 is a nonvolatile Static RAM with a full function Real-time clock |
| 277 | (53) | IC | 集成电路 | 74VHC125MTC | Elantec, Inc. products are not authorized for and should not be used wit |
| 278 | (59) | N/A | 0805TAN | The device operates with a high-frequency crystal as the main clock sourc | |
| 279 | (45) | MOTO | SMD | SMD | DESCRIPTION The ST24/25E64 are 64K bit electrically erasable programmab |
| 27A | (4) | SOT6 | 2007+ | The M95040 is a 4 Kbit (512 x 8) electrically eras- able programmable m | |
| 27B | (3) | Left Feedback Amplifier Inverting Input Left Feedback Amplifier Non-Inver | |||
| 27C | (853) | FUJ | 02+ | JLCC | sFEATURES qOperating Voltage4.7 to 13V qWOW Function |
| 27E | (34) | N/A | PLCC | 07+ | The TPS203x family of power distribution switches is intended for applica |
| 27F | (11) | SANYO | PLCC | 99+ | The 17550 operates from 2.5 V to 5.5 V, with independent control o |
| 27H | (27) | AMD/CY | DIP-32 | *1: Frequency = 824C849, 880C915 MHz, Input Signal is CW, Pin = +34 dBm | |
| 27J | (3) | 05/06+ | The power switch is an N-channel MOSFET with a maximum on-state resistanc | ||
| 27L | (54) | BGA | N/A | - Low voltage low power architecture including internal voltage r | |
| 27M | (36) | N/A | 01+ | SOP-8 | 6SDQVLRQ //& LVVXHV GDWD VKHHWV ZLWK $GYDQFH ,QIRUPDWLRQ RU 3UHOLPLQD |
| 27N | (5) | HARRIS | 大管 | 98 | Specified for 79 - , 112 - and 132 - Channel Loading Excellent Distorti |
| 27P | (14) | The HT48CA0 is an 8-bit high performance RISC-like microcontroller spec | |||
| 27Q | (1) | BGA | N/A | Firmware / tools documents B0092-SWT-01gm5115 Product Family Firmware The | |
| 27R | (1) | The M25PE80 is an 8 Mbit (1Mb x 8) Serial Paged Flash Memory accessed b | |||
| 27S | (65) | ST | N/A | 2006+ | The TMS320C54V90 is used to implement a full-featured, high-performance m |
| 27T | (4) | N/A | 06+ | 500 | RING INDICATION. It is asserted LOW by the CH1817 during the 2 second ON |
| 27U | (1) | • Bidirectional data strobe(DQS) • Differential clock inputs( | |||
| 27V | (13) | ROHM | SOT323 | Total Input Noise vs. Source Resistance In order to determine maximum si | |
| 27W | (3) | ST | Test Condition Vss < VIN < Vcc Vss < VOUT < Vcc, /CS | ||
| 27Y | (1) | MOT | SOT-23 | ||
| 27Z | (1) | Yes. The 8038 is essentially resistive. The power dissipation is then E2 | |||
| 2-8 | (79) | AMP/TYCO | N/A | High performance 20-bit Sigma-Delta ADC 118dB SNR at 78kHz output data | |
| 28- | (14) | ASP | 1997 | ||
| 28. | (19) | 5X7 | 07+ | NOTES: 1. The Phase Voltage is capable of withstanding -7V when th | |
| 280 | (213) | IC | 集成电路 | 74VHC32M | As an example, suppose a HUF76139 is chosen as the upper MOSFET. The ga |
| 281 | (111) | NO | 52 | 2005 | Notes: a. Room = 25C, Full = as determined by the operating suffix. b. |
| 282 | (169) | ST | SOP8 | 4.3 Screening (JANS, JAN, JANTX, and JANTXV levels only). Screenin | |
| 283 | (41) | IC | 集成电路 | 74VHC595M | 1. Use this component within operating temperature range. It might not be |
| 284 | (89) | IC | 集成电路 | 74VHC86N | Parameter Relay Portion (Pins 15,16) Output Characteristics @ 25 |
| 285 | (41) | QFP-44 | • Industry Standard Size • Industry Standard Pinout | ||
| 286 | (41) | 341 | TRITECH | 99+ | All parameters tested at a single temperature. Specifications are guarante |
| 287 | (20) | BB | SOP20 | 04+ | DESCRIPTION The CLP30-200B1 is designed to protect telecommunication e |
| 288 | (23) | IC | 集成电路 | 8EWF10S | * This is a stress rating only and functional operation of the device at |
| 289 | (64) | CONEXANT | QFP | 03/+04+ | The 74HC245; 74HCT245 is an octal transceiver featuring non-inverting 3-s |
| 28A | (16) | 05+ | SMD | The VCO accepts analog control inputs from the PLL filter block. The FS | |
| 28B | (18) | TI | SOP8 | The IRU1011-33 is a fixed linear regulator and it is ca- pable of supplyi | |
| 28C | (147) | 32 | MICROCHIP | ✔ ESD Protection > 40 kilovolts ✔ 500 Watts Peak Pulse P | |
| 28D | (2) | TI | SOP | 03/+04+ | Low Profile (1mm) ThinSOTTM Package Programmable Charge Current: 50mA to |
| 28E | (4) | N/A | N/A | N/A | The CMOS XC3000 Class of Logic Cell Array (LCA) families provide a grou |
| 28F | (217) | INTEL | 2001 | BGA | Power Supply Voltage When the power supply voltage (Vcc) is less than 2 |
| 28G | (3) | NIKOS | SOP-8 | 05+ | The A-to-B and B-to-A logic elements are active, regardless of the state |
| 28H | (1) | The UCC383 family of low dropout linear (LDO) regula- tors provide a re | |||
| 28J | (4) | ||||
| 28K | (3) | N/A | N/A | N/A | For applications requiring other voltages, see LM150 series adjustable |
| 28L | (29) | 04+ | SMD | These three terminal fixed voltage regulators are designed to provide 1.0 | |
| 28M | (1) | For the purpose of understanding a buck converter, Figure 1 illustrates | |||
| 28N | (6) | 448 | TO252 | 04+ | This method fails if a user applies RESET during the FPGA configuration |
| 28P | (7) | N/A | DIP-28 | 08+ | |
| 28Q | (1) | SSOP40 | These octal transparent D-type latches feature 3-state outputs designed | ||
| 28R | (3) | 05+ | SMD | The minimum bending radius is 45 mm. The mounting surface of the filters | |
| 28S | (43) | SST | 99+ | PLCC | The 1N5333-5388B JEDEC registered series of axial-leaded 5.0 watt Zeners |
| 28T | (12) | 超微8脚 | 05+ | The UCC5630A Multimode SCSI Terminator provides a smooth transition into | |
| 28V | (12) | LATTICE | O7+ | An RC network may be connected to this pin in order to hold the pin voltag | |
| 28W | (2) | Once the signal is acquired, variation in the stored-signal level during | |||
| 28X | (5) | HARRIS | QFP | 07+ | received on the OBD connection. This command shows the entire OBD buffe |
| 2-9 | (28) | Data written to the DS1267 over the 3-wire serial interface is stored in | |||
| 29- | (28) | Molex | 08+ | NOTES: 1. S.G. set to: f p 1.0 MHz; duty cycle = 50%; tr, tf, p 10 ns. | |
| 29. | (10) | KSS | 2007 | 3. Maximum power dissipation, for the SOT223 and SO8 packages, is calcula | |
| 290 | (149) | OFC | 00+ | The CE input is the device selection control. When CE goes high during a | |
| 291 | (69) | IC | 集成电路 | 95SQ015 | In 12-bit, dual-edge input mode (BSEL = low), these bits do not input pix |
| 292 | (122) | MIC | 97+ | TO263-5P | • Full Duplex Audio Signaling Processor Single Tone S |
| 293 | (1176) | QFP | TXCLK is an internally derived 1200 or 2400 Hz signal in internal mode an | ||
| 294 | (40) | IC | 集成电路 | ACS108-5SN | We reserve the right to make changes to improve technical design a |
| 295 | (70) | 96+ | SOP-24 | The 2958SC-4 provides an ISO 7816-3 compliant asynchronous answer to rese | |
| 296 | (40) | IC | 集成电路 | AD574AJN | Notes: 4. Test conditions assume signal transition time of 3 ns or |
| 297 | (29) | PH | 07+ | For users who have already designed and imple- mented the hardware port | |
| 298 | (48) | The NUP1105L provides a transient voltage suppression solution fo | |||
| 299 | (39) | SOP16 | After each 24-hour period has elapsed, the battery is connected to an inte | ||
| 29A | (8) | INFEL | QFN | OBDL (pin 12) and OBDK (pin 13) These are the active high output s | |
| 29B | (2) | AT | TSSOP-32 | 98+ | The driver output current, along with other internal operating currents, |
| 29C | (39) | AT | DIP32 | In addition to being backwards compatible with the F2MC* family architec | |
| 29D | (59) | FUJITSU | A simple LC noise reduction filter (L5 and C7) is connected between pin | ||
| 29E | (69) | SST | TSOP | The Picture Processor SDA 9290-5 is a follow-on development of the Pictur | |
| 29F | (338) | 2007 | The PT5100 modules are a series of economical, easy-to-use 1-A positive | ||
| 29H | (1) | TRANSFER FUNCTION TEST A functional diagram of the transfer function tes | |||
| 29J | (1) | The EUA5202 is a stereo audio power amplifier that delivering 2W of con | |||
| 29K | (2) | 1) CPD is defined as the value of the ICs internal equivalent capacitance | |||
| 29L | (274) | MALAYSIA | NEW | 03+ | Resale of TIs products or services with statements different from or beyo |
| 29M | (26) | MOT | DIP | All Min/Max characteristics and specifications are guaranteed over the Spe | |
| 29N | (4) | MOTOROLA | QFP0707-48 | 99+/00+/01+ | Description: The CENTRAL SEMICONDUCTOR CMPTA13, CMPTA63 series types are |
| 29P | (19) | XR | PLCC52 | N-channel enhancement mode standard level field-effect power transisto | |
| 29Q | (3) | FU | BGA | 03+ | The HR120 converters are switching regulators which use a quasi- square |
| 29R | (1) | The transmission cycle begins when the chip is selected with the CSN inpu | |||
| 29S | (9) | NEC | SOP8 | 07+/08+ | The XP161A11A1PR is an N-Channel Power MOS FET with low on-state resista |
| 29T | (2) | CMD | 02+ | USOP-10P | Each port has independent control pins: Chip Enable (CE), Read or Write |
| 29U | (2) | high-frequency tube | MOTOROLA | 04+ | The MAX3781 evaluation kit (EV kit) is an assembled demonstration board t |
| 29V | (18) | BGA | 99+ | BUFFER TO MAIN MEMORY PAGE PROGRAM WITH BUILT-IN ERASE: Data written into | |
| 29W | (4) | TSOP | STM1403C. VOUT is driven to Ground when SAL is activated (may be used w | ||
| 29Z | (3) | MALAYSA | TSOP | 03+ | Power Good Programmable versions of the PT6700 Series regulators incorp |
| 2-A | (2) | Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMON | |||
| 2A- | (2) | SA | DIP | DIP | |
| 2A( | (1) | Cypress Semiconductor Corporations (Cypresss) EZ-USB FX2LP (CY7C | |||
| 2A/ | (3) | Instrumentation sense amplifiers Ultrasound pre-amps Magnetic tape &a | |||
| 2A0 | (23) | BB | CAN | The receive section consists of an expanding DAC which drives a fifth o | |
| 2A1 | (24) | HARRIS | DIP-40 | 9948 | NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATING |
| 2A2 | (26) | BB | CAN | 00+ | Margin Dn*: When this open-collector (open-drain) input is asserted to GN |
| 2A3 | (4) | INFINEON | DIP8 | 07+ | Notes: a. Room = 25C, Full = as determined by the operating suffix. b. |
| 2A4 | (3) | BB | 八脚铁帽 | 08+ | GENERAL DESCRIPTION The NJM78M00 series of 3-Terminal Posi |
| 2A5 | (4) | 全桥 | 2. The ground pad of the CX65105 PA has special electrical and the | ||
| 2A6 | (7) | BB | SOP | 04+ | Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATING |
| 2A8 | (1) | To improve the performance of both Bluetooth and 802.11b/g co-located sys | |||
| 2A9 | (3) | GENS | SDO | 99 | ¡Ultrathin thickness 0.8mm or less. (4.93.10.7mm) ¡It is a c |
| 2AA | (10) | 24 | AGILENT | 02+ | Metallic environment and interferences Distance between two antennas E |
| 2AB | (1) | AGILENT | BGA | 04 | Case C Increased Deadtime and Deadband Mode (Voltage on Pin 9 > Pin 1 |
| 2AC | (8) | NEC | CAN3 | The ML2250 family is a 2-channel mixing speech synthesis device with an o | |
| 2AD | (7) | STM | 01+ | 20 | GENERAL-PURPOSE INPUTS: The individual GPI pins can be used for additional |
| 2AE | (3) | Agilent | QFP2828-144 | 01+ | DESCRIPTION The 2AE7-0001 is an 8 Mbit non-volatile Flash memory that |
| 2AF | (7) | AGILENT | BGA | 07+ | 8 kinds of time base/WDT clock sources 32´4 LCD driver Built-in 3 |
| 2AG | (6) | AGILENT | CGA2222 | 03+/04+ | Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications |
| 2AH | (2) | Agilehnt | †Refer to the front of the optocoupler section of the Isolation and | ||
| 2AI | (1) | Fifth Generation HEXFETs from International Rectifier utilize advanced | |||
| 2AJ | (4) | AGILENT | BGA | Multifunction Instructions Pipelined Architecture Supports Efficient Cod | |
| 2AK | (5) | China | D/S | 05+06+07+ | VREF, ISO, GND, DIFFSENSE, DIFF_CAP, TPWR, RxP, RxN (x = 1 . . . 15) VRE |
| 2AL | (10) | SAGAMI | (d) For a dual device surface mounted on 10 sq cm single sided 1oz copper | ||
| 2AM | (10) | AGILENT | BGA | 05/06+ | Input Voltage as low as 1.4V 250mV dropout @ 1A Adjustable output fro |
| 2AN | (1) | AGILENT | BGA | Note A: Characteristic data has been developed from actual products teste | |
| 2AP | (11) | DO-7 | 05+ | Diagonal 3mm (Type 1/6) 768 (H) 494 (V) approx. 380K pixels 811 (H) | |
| 2AQ | (1) | AGILENT | 00+ | PLCC-84 | 2.88MB Super I/O Floppy Disk Controller − Relocatable to 480 Diffe |
| 2AS | (14) | INFINEON | DIP8 | 03+ | The minimum VIN must meet two conditions: VIN 2.3V and VIN (VR + 2.5%) |
| 2AT | (2) | TI | TSSOP | 07+ | Maximum ratings are those values beyond which device damage can occ |
| 2AU | (4) | AGILENT | BGA | The 2AU1-0001 contains five 10BASE-T/100BASE-TX Fast Ethernet transceive | |
| 2AV | (6) | Agilent | QFP | 03+ | Each macrocell can be configured as one of the follow- ing: registered |
| 2AW | (9) | AGILENT | BGA | The 2AW4-0001/2AW4-0001/2AW4-0001 accept input volt- ages (VAB) from -3.6 | |
| 2AX | (4) | TIS | QFP | 98+ | Transmitter Input Reference Voltage. This output biases to VCC-1.3V. It is |
| 2B- | (6) | ||||
| 2B0 | (4) | 03+ | DIP | OSC1 and OSC2 are connected to an RC network or a crystal (by options) fo | |
| 2B1 | (6) | HIT | DO-35 | 05+ | NOTES 1Temperature range as follows: A Version = C40C to +125C. & |
| 2B2 | (13) | AD | 模块 | 模块 | CAUTION: These devices are sensitive to electrostatic discharge; f |
| 2B3 | (10) | HIT | DO-35 | 05+ | The chip embeds IEEE 802.3 MAC functions for each port and these function |
| 2B4 | (12) | 2004/ | VOUT(low) Low-level output voltageIOUT = 150 mA VOUT(high) H | ||
| 2B5 | (5) | AD | MOUDLE | N/A | The line on the graph shows the actual temperature that might be experie |
| 2B6 | (1) | • In-Circuit Serial Programming (ICSP™) • Internal 4 | |||
| 2B7 | (1) | Power conversion gain from 2nd LNA/mixer to 1st IF, PRFin = -50 dBm No | |||
| 2B9 | (1) | 98 | DESCRIPTION The HCC40160B, 40161B, 40162B, 40163B (ex- tended temperatur | ||
| 2BA | (9) | Agilent | 06+ | 1303 | The HYM7V73A1601B F-Series are Dual In-line Memory Modules suitable for ea |
| 2BB | (13) | PHI | 03+ | 184 | IOSShort-circuit output currentC 15C 85mA ICCSupply currentVID = 0, No |
| 2BC | (5) | No license is granted, implied or otherwise, under any patent or patent ri | |||
| 2BD | (12) | PAN | 01+ | 70 | 0VSEN (Pin 3): Overvoltage Sense Pin. Protects the high- voltage transfor |
| 2BE | (1) | AGILENT | BGA | • LPC Interface Flash C SST49LF080A: 1024K x8 (8 Mbit) | |
| 2BH | (2) | AGILENT | 03/04+ | NOTES: 1. Dimensions are in inches. Metric equivalents are given f | |
| 2BI | (7) | FUJI | The logic element for data flow in each direction is configured by two mo | ||
| 2BK | (7) | Agilent | BGA | BGA | Throughout this document, the term 2.7 V refers to the full voltage ran |
| 2BL | (3) | AGILENT | BGA | 04+ | leuchtung von Leuchtfeldern und LCD-Anzeigen geeignet. zur Direkteinkopp |
| 2BM | (2) | MODULE | MODULE | 08+ | The GS8320Z18/36T is a 36Mbit Synchronous Static SRAM. GSI's NBT SRAMs, |
| 2BN | (1) | An existing low-battery output (LBO) like that found on DC-DC converters | |||
| 2BP | (3) | HP | BGA | 0449+ | Literature Distribution Centers: USA: Motorola Literature Distribution; |
| 2BR | (1) | AGILENT | CGA3131 | 04+ | Soft phase switching + direct PWM drive PWM control based on both a DC |
| 2BS | (4) | 03+ | DIP | The KBE00S003M is a Multi Chip Package Memory which combines 2Gbit Nand Fl | |
| 2BT | (2) | Agilent | 06+ | 1310 | The IRPT1053A Power Module, shown in figure 1, is a chip and wire |
| 2BU | (1) | The SRAM has an extremely low Soft Error Rate (SER) as specified in the | |||
| 2BV | (1) | Agilent | BGA | 05+ | The SY89833L is a 3.3V, high-speed 2GHz differential Low Voltage |
| 2C0 | (11) | Bongding | 00+ | Designed for broadband commercial and industrial applications with | |
| 2C1 | (11) | LUCENT | MQFP2828 | 9713 | |
| 2C2 | (8) | HIT | DO-35 | 05+ | The output enable input is active LOW. If the output enable is active whil |
| 2C3 | (7) | HIT | DO-35 | 05+ | FEATURES Schottky Barrier Chip Guard Ring Die Construction |
| 2C4 | (6) | SHARP | 03+ | SOP-8 | Full-Featured Evaluation Board for the AD7472 EVAL-CONTROL BOARD Compati |
| 2C5 | (2) | N/A | SSOP | The M12S16161A is 16,777,216 bits synchronous high data rate Dyna | |
| 2C6 | (4) | XILINX | BGA | 07+ | Designed for use in solid state relays, MPU interface, TTL logic a |
| 2C8 | (2) | Bongding | 00+ | Timekeeping supply voltage ranging from 1.45 to 5.5V Low power consumptio | |
| 2CA | (2) | Note 1: Absolute maximum ratings are DC values beyond which the device m | |||
| 2CB | (2) | Ev = 0, test signal see fig.7, IR diode TSAL6200, IF = 250 mA IOL = 0. | |||
| 2CC | (10) | FT深圳一极代理 | 07/08+ | The 2CC101 is a feature rich, single-chip, programmable 8 channel | |
| 2CD | (1) | 07+ | The DS1258W executes a read cycle whenever WE (Write Enable) is inactive ( | ||
| 2CE | (1) | ST | BGA | 07+ | The MLX90247DSG sensor IC is integrated together with a PTC thermistor. |
| 2CJ | (6) | IOR | O7+ | In the picture-in-still (PIS) and still-in-picture (SIP) modes a field wi | |
| 2CK | (4) | China | D/S | 05+06+07+ | The Receiver utilizes a discrete silicon PIN photo-diode with an integ |
| 2CL | (5) | 02+ | The fractional-N PLL and VCO with external inductor enable the user to s | ||
| 2CM | (4) | ST | BGA0304 | Gate-to-Source Voltage C Continue - Non-repetitive Total Power D | |
| 2CP | (2) | TAOperating free-air temperature−4085C ‡ Defined by th | |||
| 2CR | (5) | TSOP16 | 2007+ | The RF5189 requires only a single positive supply of 3.0V nominal (or gre | |
| 2CS | (7) | PANASONIC | BGA | IBREAK ICLK TRST VSS VDDI VDDE NMI P65/INT3 P64/INT2 P63/INT1 P6 | |
| 2CT | (3) | MARVELL | N/A | 2006 | Integrated analog features consist of stereo line inputs with an analog b |
| 2CU | (2) | 06+ | Besides the software method, there is a hardware method to protect the top | ||
| 2CW | (4) | Europe has assigned an unlicensed frequency band of 868 MHz to 870 MHz. T | |||
| 2CY | (2) | MOT | PLCC44 | 06+ | (Non-Government standards and other publications are normally avai |
| 2CZ | (2) | TOSHIBA | After the power-up sequence of bits is transmitted, there is a listening | ||
| 2-D | (2) | DAEWOO | 2008 | Internal Memory - Character Generator ROM (CGROM) : 9,600 bi | |
| 2D- | (1) | Gain error and gain temperature coefficients are based on the ADC | |||
| 2D/ | (7) | ||||
| 2D0 | (4) | TELEDYNE ELAYS | NOTES 1Typicals represent average readings at 25C, VDD = 5 V. 2Resistor | ||
| 2D1 | (20) | BB | 93 | Notes: 1. Repetitive Rating : Pulse width limited by maximum junction tem | |
| 2D2 | (12) | BB | DIP | 00+ | The MAPI-400+100 is an extension of the Motorola MAPI-400 interface that |
| 2D3 | (5) | BB | DIP | 07+ | Stresses beyond those listed under "absolute maximum ratings" m |
| 2D4 | (2) | CONEXANT | QFP | CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RI | |
| 2D5 | (3) | N/A | N/A | N/A | Address/Data number combination - HT12D: 8 address bits and 4 data bits |
| 2D6 | (4) | NEC | The LS160 and LS162 are high speed synchronous dec- ade counters operati | ||
| 2D7 | (2) | FUJI | GTR | Chapter 6, "Instruction Set," describes the features and convent | |
| 2D8 | (1) | The 80C186EB has integrated several common sys- tem peripherals with a C | |||
| 2D9 | (4) | BB | 00+ | In contrast to a conventional p-n junction, the current in the Schottky | |
| 2DA | (1) | DIODES | SOT-523 | 05+ | Hynix HYMD116G725A(L)8-K/H/L series incorporates SPD(serial presence detec |
| 2DC | (4) | SINGATRON | CONN DC POWER JACK D=2mm 2DC-0005D100 | The integrated controller (SCC) provides the majority of the electronics | |
| 2DE | (3) | N/A | N/A | N/A | • Access times of 70, 85 ns • CMOS low power operation: &nb |
| 2DF | (5) | s Flyback Operation with Quasi-Resonant Soft Switching for Low Po | |||
| 2DG | (1) | Radiation Hardened up to 1 x 106 Rads (Si) Single Event Burnout (SEB) H | |||
| 2DH | (19) | TO92 | 05+ | Command Prefix - Each command, except the A/ command, begins with the AT | |
| 2DI | (259) | Users have access to all the relevant signal quality information, includin | |||
| 2DJ | (1) | In order to reduce the power dissipation of the FET and to increase the l | |||
| 2DM | (1) | Package drawings, standard packing quantities, thermal data, symbolizatio | |||
| 2DN | (3) | MOT | 95 | Compliant to USB specifications Low MOSFET on resistance at 5.0V 140m | |
| 2DO | (1) | The L-Series converters utilize a single-ended for- ward topology with | |||
| 2DP | (2) | ST | The S6B1713 is a driver & controller LSI for graphic dot-matrix liquid | ||
| 2DR | (2) | ||||
| 2DS | (1) | ‡ Stresses beyond those listed under absolute maximum ratings may c | |||
| 2DT | (3) | Description Reserved PCI6 Output Control 1 = enabled, 0 = forced LOW P | |||
| 2DU | (2) | BEST | TAOperating free-air temperature−55125−4085C ‡ Wi | ||
| 2DW | (8) | CAN3 | This DAC utilizes a double-buffered 3-wire serial interface that is comp | ||
| 2E- | (2) | Meets Intels Mobile 133.3MHz Chipset Three CPU Cloc | |||
| 2E1 | (4) | N/A | Communication Interfaces C 2 Serial Communication Interfaces with asyn- | ||
| 2E5 | (2) | 06+ | The output signal is adjustable between 0.5V and 4.5V (when operating with | ||
| 2E7 | (2) | 99 | SOP | FUNCTION Input pin for oscillator. It can be connected to crystal, or can | |
| 2EA | (3) | N/A | SC-70 | Data Setup Time Data Hold Time Address Set-up Time Address Hold Tim | |
| 2EB | (1) | LPC Bus Interface Based on Intels LPC Interface Specification Revi | |||
| 2ED | (8) | SIEMENS | Isense (Current Sense) The Current Sense pin senses the voltage develope | ||
| 2EE | (2) | Xilinx reprogrammable PROMs can also be programmed by the Xilinx HW-130 | |||
| 2EG | (7) | FOXCONN | 2006-2-7 | Input Termination Center-Tap. Each side of the transmitter differential in | |
| 2EH | (21) | SecSiTM (Secured Silicon) Sector region 128-word/256-byte sector for pe | |||
| 2EK | (1) | SOT6 | The Discharge Count Register (DCR) is used to update the Last Measured Di | ||
| 2EP | (1) | MODULE | MODULE | 08+ | The track/hold amplifier returns into track mode at the end of conversio |
| 2ES | (8) | Hynix HYMD132G725A(L)8M-K/H/L series is designed for high speed of up to | |||
| 2EV | (1) | The chopper stabilized amplifier uses switched capacitor techniques to el | |||
| 2EZ | (109) | EIC | DO-41 | 07+ | reliable operation, the stored energy from circuit inductance dissipated |
| 2-F | (1) | PORT D is an 8-bit output port that is preset high when RESET goes low C | |||
| 2F/ | (3) | ||||
| 2F0 | (2) | BESTA | TSOP | 02+ | HIGH SPEED: tPD = 5.5ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC |
| 2F1 | (13) | 1735 | When at least one of the reset outputs is not asserted, a pushbut- ton i | ||
| 2F2 | (5) | The IS24C08-2 and IS24C08-3 only use A2 input for hardwire addressing a | |||
| 2F3 | (2) | The HT82K628A will respond with ACK, clears its output buffer, sets all k | |||
| 2F5 | (1) | THD+N: 20-Hz HPF, 20-kHz AES17 LPF Dynamic range: 20-Hz HP | |||
| 2F8 | (2) | 05+ | SMD | • PI74FCT861/863T/864T is pin compatible with bipolar FAST™ | |
| 2FA | (6) | BOURNS | 05+ | EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process ESD | |
| 2FB | (1) | IDT70261 easily expands data bus width to 32 bits or more using the Maste | |||
| 2FC | (1) | FC | CAN12 | 03+ | Busy is active high and Section dependent but not Group dependent. Even |
| 2FE | (1) | 1. Cost The cost of both the component and the manufacturing overhead | |||
| 2FF | (1) | The LM129 and LM329 family are precision multi-current temperature-compe | |||
| 2FI | (101) | FUJI | SOP | The LM6362 family of high-speed amplifiers exhibits an ex- cellent speed | |
| 2FR | (1) | C-REX | The ATF1502ASVs flip-flop has very flexible data and control functions. T | ||
| 2FW | (5) | N/A | * On products compliant to MIL-PRF-38535, this parameter is not productio | ||
| 2G0 | (2) | 05+ | SMD | • Convex terminal array with square corners • 4 or 8 termin | |
| 2G1 | (1) | DSI | n/a | Port 3 is an 8 bit bi-directional I/O port with internal pullups. Port 3 | |
| 2G2 | (2) | Provides real time clock: − Counts seconds, minutes, hours, date | |||
| 2G3 | (2) | The ADXL278 is the fourth-generation surface micromachined iMEMS® ac | |||
| 2G4 | (2) | NS | DIP-14 | 08+ | The LM6362 family of high-speed amplifiers exhibits an ex- cellent speed |
| 2G7 | (1) | ATMEL | BGA | 2002 | • Reverse Mountable SMT LED • Diffused Optics R |
| 2GC | (2) | • Lower switching losses allow more cost-effective operatio | |||
| 2GD | (1) | Note 1: Absolute Maximum Ratings are those values beyond which the life | |||
| 2GH | (1) | INTEL | P | 03+ | *Absolute Maximum Ratings are those values beyond which damage to the dev |
| 2GM | (1) | ||||
| 2GP | (2) | ST | 02+ | 45 | count in the count-down mode. Cascading of multiple packages is easily |
| 2GW | (4) | TOSHIBA | Start Condition. START is identified by a high to low transition of the | ||
| 2H0 | (4) | NS | O3+ | QFP | |
| 2H1 | (1) | SOP | N/A | Pin Function PWM block control power supply Focus control inpu | |
| 2H2 | (5) | INFINEON | 2008 | Transmit FIFO Half-full Status Flag. When the Transmit FIFO is enabled | |
| 2H3 | (3) | N/A | N/A | N/A | Recommended Operating Conditions • Supply voltageVDD∗3.0 to 4 |
| 2H4 | (2) | An internal oscillator fixes the switching frequency at 500KHz to minim | |||
| 2HA | (1) | TI | 798 | TOSHIBA is continually working to improve the quality and the relia | |
| 2HD | (2) | ||||
| 2HO | (1) | ST | PQFP | 07+ | These outputs provide access to the outputs from the RF and refer |
| 2HP | (21) | HP | MQFP208 | 07+ | The device also features Personal Video Recording capabilities. It has a |
| 2HS | (3) | The MAX 7000 architecture supports 100% TTL emulation and high-density i | |||
| 2HT | (1) | sGENERAL DESCRIPTION The NJU7108 is a super small-sized package si | |||
| 2HX | (1) | 2HXX | 05+ | Notes 1. Output current rating may be limited by duty cycle, ambi | |
| 2I2 | (1) | Data on M inputs passed directly to the M divider. Data is latched into | |||
| 2IG | (3) | EUPEC | 2007 | ||
| 2IL | (1) | *Note: Stresses above those listed under Absolute Maximum Ratings may caus | |||
| 2IO | (2) | At turn-on, the external gate capacitor of the N-Channel MOSFET is charge | |||
| 2IV | (1) | 00 | The device offers a highly integrated solution for a satellite tuner incor | ||
| 2-J | (3) | Edition 1998-04-08 Published by Siemens AG, Bereich Halbleiter, Marketin | |||
| 2J1 | (2) | N/A | 1206T | [CAUTION] The specifications on this databook are only given for | |
| 2J2 | (1) | SOP28 | This device contains protection circuitry to guard against damage due t | ||
| 2JA | (1) | advantage series | ＢＧＡ | original stock | These N-Channel enhancement mode power field effect transistors are produ |
| 2JB | (4) | 32 | 03+ | cleared immediately, and remains cleared. If the power is restored (no | |
| 2JS | (2) | TDK | n Integrated OLED and white-LED driver n 80% efficiency n Drives up 5 | ||
| 2JY | (3) | DIP4 | Please be aware that an important notice concerning availability, | ||
| 2K- | (4) | † All typical values are at VCC = 2.5 V, TA = 25C. ‡ The bus | |||
| 2K0 | (1) | The TPS6210x family is highly efficient at both low and high output curre | |||
| 2K1 | (4) | HIT | 99+ | 10 | The IrCC UART-driven IrDA SIR and SHARP ASK modes are backward-compatible |
| 2K2 | (6) | † NOTICE: Stresses above those listed under Absolute Maximum Rating | |||
| 2K3 | (3) | For conditions shown as Max. or Min., use appropriate value specified und | |||
| 2K4 | (4) | N/A | N/A | N/A | The number formed by the full offset least significant bit register and |
| 2K5 | (1) | K | DIP | 00+ | Motorola reserves the right to make changes without further notice to any |
| 2K6 | (2) | DIP | 99+ | The information provided herein is believed to be reliable at press time. | |
| 2K7 | (1) | Guaranteed Low Skew < 25ps (max) Very low duty cycle dis | |||
| 2KB | (53) | IR | VCC = Max. VIN VHC; V IN VLC VCC = Max. VIN = 3.4V(3) VCC = Max. Ou | ||
| 2KG | (1) | Notes: (1) The VS1 and VS2 ports may remain open-circuited without damag | |||
| 2KN | (2) | The 2KNG1C6771 is a highly integrated single-chip modem IC which provides | |||
| 2KT | (1) | NEC | 228 | ESD damage can range from subtle performance degradation to complete dev | |
| 2KV | (28) | WM | Y5P | 05+ | • Reverse Mountable SMT LED • Diffused Optics R |
| 2KY | (1) | The ICL8038 waveform generator is a monolithic integrated circuit capabl | |||
| 2L- | (13) | SIEMENS | SMD | 03/+04+ | FEATURES Clickless Bilateral Audio Switching Guaranteed Break-Before-Mak |
| 2L0 | (6) | ST | 263 | 07+ | other possibility: VREF = VregLogic, VGND = VregLogic/2 For power saving |
| 2L2 | (5) | SESAR | N/A | 97 | Device programming is performed a byte/word at a time by executing the |
| 2L4 | (1) | The 2L49(LLA) is designed for use in Ethernet switch, hub, and router s | |||
| 2LA | (1) | The current through the resistor RSET determines the timing of the funct | |||
| 2LH | (1) | 6ns rise and fall time with 1000pF load 2A peak output source/sink curren | |||
| 2LN | (3) | SOP8 | These three terminal negative regulators are supplied in hermetically sea | ||
| 2LR | (1) | Note A: All data listed in the above graphs has been developed from actua | |||
| 2LS | (1) | ||||
| 2LX | (1) | Spansion LLC issues data sheets with Advance Information or Preliminary d | |||
| 2-M | (3) | © Atmel Corporation 2003. All rights reserved. Atmel ® and combin | |||
| 2M0 | (1) | Infineon | 03/04+ | MQFP44 | This product has been designed to meet the extreme test conditions and env |
| 2M1 | (4) | The 2M100DY-24 is powered by a single 3.3-V supply. The core voltage supp | |||
| 2M2 | (11) | ST8 | 9432 | Split supplies of 3.3V and 2.5V are used. The 3.3V power supply powers a | |
| 2M3 | (5) | TSSOP-86 | 00 | No Auxiliary Winding Operation Internal Output Short−Circuit Prote | |
| 2M6 | (2) | 三脚铁帽 | 08+ | The NCP5422A is a dual N−channel synchronous buck regulator | |
| 2M7 | (1) | The HY62LF16404D is a high speed, super low power and 4Mbit full C | |||
| 2MB | (575) | 04+ | The HYM72V64736(L)T8 Series are Dual In-line Memory Modules suitable for | ||
| 2MD | (1) | 01 | The time and date may be set by writing to the RTC registers. To avoid | ||
| 2MH | (1) | The standard MX29LV160BT/BB offers access time as fast as 70ns, allowin | |||
| 2MI | (16) | FUJI | The Fault output is latched high when a short-circuit output condition | ||
| 2MJ | (6) | SINGATRON | 07+ | used to reduce the width of the deadband to acceptable levels, and to ma | |
| 2MM | (3) | MC | 06+ | 13500 | CAUTION: These devices are sensitive to electrostatic discharge; follow p |
| 2MR | (2) | The TPS752xxQ or the TPS754xxQ are offered in 1.5-V, 1.8-V, 2.5-V, and 3. | |||
| 2MS | (2) | The feature set of the 80C186EB meets the needs of low power space criti | |||
| 2MV | (2) | Edition 01.2001 Published by Infineon AG , Marketing-Communication, Bal | |||
| 2MW | (1) | When the frequency of V is less than that of R the 12140 behaves | |||
| 2MX | (3) | STARRAM | 0536+ | TSOP | Since the device will not acknowledge during a write cycle, this can be u |
| 2N- | (1) | Notes: Stresses greater than those listed under MAXIMUM RATINGS may caus | |||
| 2N0 | (43) | TO:263 | Notes: 1. Dominant Wavelength, ëd, is derived from the CIE Chromatic | ||
| 2N1 | (1133) | MOT | CAN3 | 04+ | Dual chip enables allow for depth expansion without additional logic Fu |
| 2N2 | (1229) | MOT | CAN3 | NOTES: 1. All VDD pins must be connected to 3.3V power supply. 2. All VD | |
| 2N3 | (1477) | MOT | CAN | (Gbps) Synchronizable Transceivers Low Power Consumption <1.3 W at 1. | |
| 2N4 | (984) | NES | TO-5 | 02+ | The MAX8546 operates at 300kHz. The MAX8546 is compatible with low-cost al |
| 2N5 | (1397) | MOTOROLA | CAN3 | Available in the Texas Instruments NanoStar and NanoFree | |
| 2N6 | (1170) | W | TO-202 | The SDA 9188-3X processes both 50 Hz/625 and 60 Hz/525 line signals. The | |
| 2N7 | (355) | ON | SOT-23 | Note 1) The specified condition Tj=25˚C means that the test should | |
| 2N8 | (125) | MOT | CAN | less than 1 ns pk-pk. If reference jitter is greater than 1 ns pk-pk, t | |
| 2N9 | (130) | MOT | CAN3 | Case: JEDEC TO-220AB, ITO-220AB, TO-263AB molded plastic body Terminals | |
| 2NA | (1) | TO-251 | The MB81ES171625/173225 is dedicated for SiP (System in a Package), and i | ||
| 2NB | (27) | TO-251 | n OSD Window Fade In/Fade Out n OSD Half Tone Transparency n OSD overrid | ||
| 2NC | (5) | ST | TO-220 | 0728vgc+ | • New specifications • Dual frequency standard for indu |
| 2NE | (1) | ST | TO223/3 | 03+ | The fast-access register file concept contains 32 x 8-bit general-purpose |
| 2NG | (2) | Maximum ratings are those values beyond which device damage can occur. Ma | |||
| 2NH | (2) | 5V TOLERANT INPUTS HIGH SPEED : tPD = 5.0ns (MAX.) at VCC = 3V POWER | |||
| 2NQ | (1) | The L-Series converters utilize a single-ended for- ward topology with | |||
| 2NU | (1) | This datasheet contains new product information. Analog Corp. reserves the | |||
| 2-O | (2) | NAT | 3066 | The SP8480 multiplexer inputs have been de- signed to allow substantial | |
| 2P0 | (5) | MC | O7+ | (1) Stresses beyond those listed under absolute maximum ratings may cause | |
| 2P1 | (9) | MOTOROLA | SOP-8 | 04+ | I 32-level Low Voltage Detection I Brown-out Reset I Software selectabl |
| 2P4 | (3) | NEC | N/A | 05+ | The select-control (SAB and SBA) inputs can multiplex stored and real-tim |
| 2P5 | (2) | 850 | TO263 | 04+ | BACKPLANE TEST MODE SELECT: Controls sequencing through the TAP Controlle |
| 2P6 | (2) | PHIL | functional operation of the device at these or any other condition | ||
| 2P7 | (2) | PHILIPS | 2008 | MIL-STD-750, method 3131. The maximum limit (not to exceed the group A, s | |
| 2PA | (40) | PHILIPS | 有铅 | 03-05+ | The ADV7183A has a 5-line, superadaptive, 2D comb filter that gives supe |
| 2PB | (44) | PHI | SOT-323 | ADS: Adaptive Delay Set. This function sets the ratio be- tween the maxi | |
| 2PC | (44) | PHILIPS | 08+PBF | The 2PC4617RJ is a first generation very high speed bipolar integrated ci | |
| 2PD | (39) | PHI | 08+PBF | These Darlington arrays are furnished in 18-pin dual in-line plas | |
| 2PG | (6) | ＰＡＮＡＳＯＮＩＣ | The internal feedback voltage dividers central tap is connected to the no | ||
| 2PH | (5) | AD | 06+/07+ | NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pin | |
| 2PI | (11) | N/A | The LVX74 is a dual D-type flip-flop with Asynchronous Clear and Set in | ||
| 2PK | (7) | N/A | If Autovectoring is enabled (AV2EN = 1 in the INTSETUP register), the F | ||
| 2PM | (1) | Stereo 16-Bit Oversampling Sigma-Delta A/D Converter Stereo 16-Bit Overs | |||
| 2PO | (2) | PHIL | On the 20- and 28-pin parts it is recommended that all bits of Port C be | ||
| 2PP | (2) | NEC | SMD | 03+ | The absolute maximum ratings under any condition is limited by the constr |
| 2PS | (2) | PHILIPS | SMD | 02+ | Programmable teletax signal generation (12 kHz or 16 kHz) FSK generator |
| 2PT | (1) | SOP | Notes: 1 Load and Line Regulation are specified at a constant junction t | ||
| 2Q8 | (1) | NS | QDIP | N/A | The accelerated program (ACC) feature allows the system to program the d |
| 2QE | (1) | Handsets and Telecommunications Applications Two Differential Microphone | |||
| 2QS | (16) | BOURNS | O7+ | Note 2: Absolute Maximum Ratings are values beyond which the device may b | |
| 2R0 | (3) | 04+ | 1.1 Scope. This specification covers the performance requirements | ||
| 2R1 | (8) | MODULE | MODULE | 08+ | 3 1 OSCILLATOR The oscillator is controlled by a 20 MHz parallel resonan |
| 2R2 | (6) | MURATA | 00+ | The NCP1575 is a low voltage buck controller. It provides the con | |
| 2R3 | (3) | 99 | No license is granted, implied or otherwise, under any patent or patent ri | ||
| 2R5 | (36) | N/A | Voltage ratings: AC: 300 Volts (JLLN); 600 Volts (JLLS) DC: 125 V | ||
| 2R6 | (11) | Serializer-Deserializer Building-Block Chip Family Supports Serializatio | |||
| 2RA | (1) | Note: Stresses greater than those listed under MAXIMUM RATINGS may cause | |||
| 2RE | (2) | PLCC | 04+ | Notes: 1. For Max. or Min. conditions, use appropriate value specified un | |
| 2RF | (2) | When PWRDWN# is sampled low by two consecutive rising edges of DIFC, all | |||
| 2RI | (36) | N/A | Enhanced N channel FET with no inherent diode to Vcc 16:8 multiplexer fu | ||
| 2RK | (1) | PLCC | 04+ | Unlike other devices, the error amplifier in the UCC3800 family is a tr | |
| 2RN | (1) | CAN | Notes: 1. Operation of this device in excess of any of these limi | ||
| 2RR | (1) | 0323+ | Certain applications using semiconductor products may involve potential r | ||
| 2RS | (2) | AD | 06+/07+ | REGISTERED In registered mode the output pin associated with an individu | |
| 2RT | (5) | 00+ | A high performance 10 bit on-chip ADC is used to sample the 44 or 36 MHz | ||
| 2RU | (1) | High FSK Sensitivity: -106 dBm at 20 kBaud/-109.5 dBm at 2.4 kBaud (433.92 | |||
| 2RV | (1) | Information in this document is provided in connection with Conexant Syst | |||
| 2RX | (2) | NEC | Access protection (both read and write) is organized on a block basis fo | ||
| 2-S | (1) | The 74HC/HCT153 have two identical 4-input multiplexers which select t | |||
| 2S0 | (27) | ST | O7+ | • Thin smaller package size is achieved through micro-mirror | |
| 2S1 | (79) | The information contained herein is presented only as a guide for the app | |||
| 2S2 | (8) | AD | DIP | 04+ | The HYM72V32M656T6 Series are gold plated socket type Dual In-line Memory |
| 2S3 | (21) | PHILIPS | CAN3 | These devices are fully specified for hot-insertion applications using Io | |
| 2S4 | (2) | The transmit section of the CY7B951 contains a PLL that takes a REFCLK i | |||
| 2S5 | (7) | 04+ | DMOS Outputs Low r DS(on) - 0.25 Ω Maximum Linear Current Control | ||
| 2S6 | (2) | TI | DIP-20 | N/A | 4-Bit Digitally Controlled 8th-Order Lowpass Filter C fCUTOFF Adjustable |
| 2S7 | (10) | ASI | 金属帽 | Ripple current, less than 300 mΩ equivalent series resis- tance (E | |
| 2S8 | (4) | AD | new | Guaranteed Low Skew < 25ps (max) Very low duty cycle distortion < | |
| 2S9 | (3) | SANYO | TO-3P | ActiveThe device operates at full speed using the high- frequency clock. | |
| 2SA | (4783) | 排带 | When the CH7009 is operating as a VGA to TV encoder in master clock mod | ||
| 2SB | (3732) | 03+/04+ | TO-3P | These pins accept the 12 data inputs from a digital video port of a gra | |
| 2SC | (11766) | SANYO | SOT-523 | 07+（ROHS） | 0.3V, the internal NMOS FET switch turns on and the SUB display turns o |
| 2SD | (5093) | 06+ | OUTPUT DRIVE ENABLE (ODE) The ODE pin is the master output three-s | ||
| 2SF | (20) | NEC | 2000 | Moving the data from two groups of registers to four common output buse | |
| 2SH | (27) | NEC | 金属帽 | E12 | The Read operation of the EM39LV040 is controlled by CE# and OE#. Both hav |
| 2SI | (3) | With up to 200 MHz bandwidth and 2 GS/s maximum sample rate, no other col | |||
| 2SJ | (1302) | TOSHIBA | SOT-23 | Vth can be expressed as voltage between gate and source when low o | |
| 2SK | (6374) | TOS | TO-3PF | 04+ | The RC32355 incorporates an industry standard TDM bus interface t |
| 2SL | (1) | Transmitter Output Swing Control. Input that controls the output amplitude | |||
| 2SM | (2) | The LM89 is an 11-bit digital temperature sensor with a 2-wire System M | |||
| 2SN | (1) | The HY29F040A can be programmed and erased in-system with a single 5-vo | |||
| 2SP | (8) | ST | N/A | 03+ | C High-performance 32-bit RISC Architecture C High-density |
| 2SS | (11) | HONEYWELL | 06+ | High-Bandwidth Data Path (up to 500 MHz (1)) Equivalent to IDTQS3VH251 De | |
| 2ST | (39) | STM | TO264 | 08 | THD+N: 20-Hz HPF, 20-kHz apogee LPF Dynamic range: 20-Hz H |
| 2SV | (5) | NOTES 1Measured at IOUTA, driving a virtual ground. 2Nominal full-scale | |||
| 2SW | (37) | N/A | The customized communication expansion connectors on the EVB555 allows ac | ||
| 2T- | (2) | • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) | |||
| 2T4 | (1) | The CY7C4261/71/81/91V consists of an array of 16K, 32K, 64K, or 128K w | |||
| 2T6 | (2) | N/A | N/A | N/A | The Modem Control Software runs entirely on the DMT Transceiver (no ext |
| 2T8 | (1) | 05+ | High Speed Communication Line Protection USB 1.1 and 2.0 Power and Data | ||
| 2TC | (1) | N/A | Features • High sensitivity (+6dB compared with ICX087AK) • | ||
| 2TL | (5) | • Plastic package has Underwriters Laboratory Flammability | |||
| 2TP | (1) | SAMSUNG | Continuous Drain Current, VGS @ 10V** Continuous Drain Current, VGS @ 1 | ||
| 2TX | (2) | This device contains circuits to protect its inputs and outputs against d | |||
| 2TZ | (2) | TO-252/5 | The HY51V(S)17403HG/HGL is the new generation dynamic RAM organized 4,194, | ||
| 2U2 | (9) | Note: (1) The minimum DC input voltage is C0.5 V. During transitions, in | |||
| 2U7 | (1) | FEATURES 1 A Output Current at 2.5 V 0.6 V Maximum Dropout Voltage at | |||
| 2UF | (1) | The ST70138 is supplied in two packages, TQFP144 and LBGA80. The ST7013 | |||
| 2UM | (1) | MODULE | MODULE | 08+ | Distributes One Differential Clock Input Pair LVPECL/HSTL to 10 Different |
| 2UP | (1) | N/A | Data is written into memory on a low-to-highNC C No internal connection | ||
| 2V0 | (2) | N/A | SOP-8 | • Bring Shut Down (SD)/Mode pin to a logic High status. • Br | |
| 2V2 | (1) | TOSHIBA | SOT23 | Initial issue. 1. Note 1 ( Program/Erase Characteristics) is added( page | |
| 2V4 | (3) | Data is available in two 8-bit bytes from TTL-compat- ible three-state o | |||
| 2V5 | (2) | DSI | n/a | (4) The products described in this material are intended to be used for s | |
| 2VA | (1) | The CY22393, CY22394, and CY22395 are a family of parts designed as upgra | |||
| 2VN | (1) | Data Enable Low Input. This port controls the 8-bit parallel data latch a | |||
| 2VP | (6) | RELIABILITY | The ADSP-21991 provides 40K words of on-chip SRAM memory. This memory is | ||
| 2W- | (1) | Quiescent current does not increase significantly as the dropout | |||
| 2W( | (1) | Output Features: •3 - 14.318 MHz REF clocks •1 - USB_48MHz | |||
| 2W0 | (30) | HB | WOB | 05+ | Cypress Semiconductor Corporations (Cypresss) EZ-USB FX2LP (CY7C |
| 2W1 | (21) | 04+ | 4-pin signal will complete the data trasmitting/receiving. MCLK is not | ||
| 2W2 | (7) | FAGOR | The MAX4641/MAX4642/MAX4643 are monolithic, dual, single-pole/single-thro | ||
| 2W3 | (6) | 05+ | Only stops CPUCLK_CS "Complementary" clock of differential pa | ||
| 2W4 | (2) | SECON | Module | 00+ | The standard shipping format for serial types includes a lower or upper fa |
| 2W5 | (2) | All data transfers are initiated by driving the CS input low. Input data i | |||
| 2W6 | (4) | FAGOR | INPUT FRAME OFFSET SELECTION Input frame offset selection allows t | ||
| 2W7 | (2) | FAGOR | A simple sleep mode was incorporated in the module when no bus activity | ||
| 2W8 | (2) | FAGOR | New techniques such as Wavelength Division Multiplexing (WDM) further inc | ||
| 2W9 | (3) | FAGOR | The MAX1282/MAX1283 12-bit analog-to-digital convert- ers (ADCs) combine | ||
| 2WI | (1) | External DRAM is required only for full PerFlow fea- ture support (laye | |||
| 2WO | (1) | The HA12134A, HA12135A, HA12136A are silicon monolithic bipolar IC series | |||
| 2-X | (4) | SMK | 01+ | SOP28 | The Fairchild Switch FSTU3384 provides 10 bits of high- speed CMOS TTL- |
| 2X( | (1) | 2. Switch between two audio signals in a single phone, one from a | |||
| 2X0 | (3) | LUCENT | PLCC | 03+/04+ | Temperature Operating5 ~ 55 C Non-operating-40 ~ 70 C &nbs |
| 2X1 | (34) | The UT28F256 has three control inputs: Chip Enable (CE), Program Enable | |||
| 2X2 | (20) | The BS62LV4007 is a high performance, very low power CMOS Static Random A | |||
| 2X3 | (25) | CONSUMER | QFP | QFP | This will result in an input to the crystal of 50% of the rail to rail ou |
| 2X4 | (7) | ||||
| 2X5 | (8) | ||||
| 2X6 | (4) | IXIS | REGISTER HEX 09 PUNCTURE RATE ENABLE (R/W) Reset Value : Hex 10 (mode | ||
| 2X7 | (4) | ||||
| 2X8 | (6) | ||||
| 2X9 | (1) | ||||
| 2XB | (1) | IR | 04+ | 115 | The Hynix HYM7V75A801B F-Series are 8Mx72bits ECC Synchronous DRAM Modules |
| 2XC | (1) | PHILIPS | 2008 | This document contains information on products under development by INES. | |
| 2XD | (1) | For each bridge the PHASE input controls load current polarity by | |||
| 2XE | (1) | Driver-Output Enable Time to Low Level Driver-Output Enable Time to High | |||
| 2XF | (1) | The HYM72V32656AT8 Series are 32Mx64bits Synchronous DRAM Modules. The mod | |||
| 2XL | (2) | SANYO | DIP-30 | 02+ | Chip Enable Input. If logic high, all functions are enabled. If logic low, |
| 2Y1 | (1) | Note 3: Applies to both single-supply and split-supply operation. Continu | |||
| 2Y4 | (1) | The IDT77155 is a member of IDT's SWITCHStAR™ family of pro | |||
| 2YS | (1) | Cycle Control Internal High Accuracy Bandgap Voltage Reference Current | |||
| 2Z0 | (1) | FOXCONN | 06+ | 26 | The ADP3419 includes an anticross-conduction protection circuit, undervo |
| 2Z2 | (1) | Notes: *All PIO signals are shared with other physical pins. See t | |||
| 2Z3 | (1) | 东芝 | duce DMT sidelobes and out of band noise influ- ence on the receiver. O | ||
| 2Z5 | (1) | Celeritek tests the 2Z5U103S501A54 on an FR4 PC test board. FR4 w | |||
| 2Z6 | (1) | Features • Three Functions in One Package • Small 16 Pin SO | |||
| 2ZA | (1) | MICROCHIP | QFN-8P小体 | 6+ | This familiy is a 64Mbit dynamic RAM organized 16,777,216 x 4 bit configur |
| 2ZI | (1) | MICROCHIP | QFN-8P小体 | 6+ | The FPD33684 Column Driver is a direct drive, 64 gray level, 384 output, |
| 2ZP | (1) | MICROCHIP | QFN-8P小体 | 6+ | Sector data protection is afforded by methods that can disable any combin |
| 2ZS | (1) | MICROCHIP | QFN-8P小体 | 6+ | This device is intended to be used only in a half-bridge which drives in |
| 2-三 | (1) | Input IN1 serves as either the external clock input or the input to the |
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