| Mfg | pack | D/C | Descrpion | ||
| 5.0 | (30) | The TLV320AIC2x is a low-cost, low-power, highly-integrated, high-perform | |||
| 5.1 | (38) | Panasonic | 2008 | Upon power up, the chipset link can be initialized via a synchronization | |
| 5.2 | (4) | ALCATEL | 06+ | 1750 | The MSK 5115 series are highly thermally conductive devices and the ther |
| 5.3 | (8) | Both pre- and post-radiation performance are tested and specified using | |||
| 5.4 | (7) | a. Absolute maximum continuous ratings are those maximum values beyond wh | |||
| 5.5 | (15) | The SC16C554B/554DB is pin compatible with the ST16C554 and TL16C554 and | |||
| 5.6 | (13) | Panasonic | 2008 | The 48 dB gain range of the VGA makes these devices suitable for a varie | |
| 5.7 | (5) | ||||
| 5.8 | (8) | N/A | NOTES: (1) With a balanced differential signal, the positive input is 180 | ||
| 5.9 | (21) | ALABAMA, Huntsville ARIZONA, Tempe CALIFORNIA, Agoura Hills CALIFORNIA, | |||
| 5/4 | (9) | ||||
| 5/A | (1) | ||||
| 5/M | (1) | ||||
| 5-0 | (13) | NS | 96+ | CAN/6 | Note 2: The Absolute Maximum Ratings are those values beyond which the sa |
| 50- | (123) | Molex | 08+ | terminals (RS, RTC and CTC), ten buffered outputs (Q3 to Q9 and Q11 to Q | |
| 50. | (17) | N/A | DIP-4 | 08+ | • Designed expressly for Switch-Mode Power Supply and PFC ( |
| 50/ | (1) | IAC: (current proportional to input voltage) This input to the analog mul | |||
| 500 | (629) | OO | 2007 | (Note) (1) "NEC Electronics" as used in this statement means N | |
| 501 | (476) | JRC | 05+ | An output capacitor is required to maintain regulator loop stability. Un | |
| 502 | (205) | MOT;AT&T | 04+ | A buffered output-enable (OE) input can be used to place the eight outp | |
| 503 | (148) | N/A | MOLEX | 05+ | Stresses beyond those listed under absolute maximum ratings may cause per |
| 504 | (162) | CATALYST | SOP-14P | 6+ | The 504JI/504JI operate from a single +2.7V to +3.6V supply voltage and r |
| 505 | (104) | 50 | MICROCHIP | Maximum Ratings are those values beyond which damage to the device | |
| 506 | (132) | N/A | MOLEX | 05+ | The IRU1010 keeps a constant 1.25V between the out- put pin and the adjus |
| 507 | (58) | IC | 集成电路 | BFR181,E6327 | Figure 4 shows the logic in the XC5200 CLB, which con- sists of four Lo |
| 508 | (237) | AGILENT | 08+ | The X79000 series implements an SPI serial bus interface with slave add | |
| 509 | (37) | VHK | DIP28 | 04+/05+/06+/07+ | As with all power integrated circuits, the UDN2987A and UDN2987LW |
| 50A | (16) | SANYO | SOT-23 | 05+ | DCLK Edge Select, Double Data Rate Enable and Serial Data Input. This i |
| 50B | (3) | MIC | 0 | 5 | !Features In addition to the features of regular digital transistors. 1) |
| 50C | (17) | SANYO | 2008 | The CPU32+ processor is the full 32-bit extension of the CPU32 processor | |
| 50D | (2) | Hynix HYMD132725B(L)8-M/K/H/L series is designed for high speed of up to | |||
| 50E | (3) | SML | TO-220 | 07+ | RST Reset input A high on this pin for two machine cycles while the oscil |
| 50F | (9) | ST | 06+ | 500 | The SN74ALVCF162835 has series damping resistors in the device output s |
| 50G | (22) | OKI | 83 | Clocked Mode - The Terminal Equipment should apply bit-wide NRZ pulses o | |
| 50H | (28) | TOSHIBA | O7+ | FEATURES s 300 mA Output Current per Channel s Independent Over-Current | |
| 50J | (2) | TO-3P | This document contains information on one or more products under developm | ||
| 50K | (4) | The QS3VH861 HotSwitch with 10-bit flow-through pin out is a high | |||
| 50L | (17) | TI | 08+ | Thermal Design The IRU1015 incorporates an internal thermal shutdown tha | |
| 50M | (40) | —— | 模块6 | NOTES: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are | |
| 50N | (24) | 3.2 KSO8~15 These pins are direct output from the 8051 Port2 and dedicate | |||
| 50O | (1) | Complete PWM Power Control Circuitry Uncommitted Outputs for 200-mA Sink | |||
| 50P | (13) | HIT | QFP | 05+ | Package Signaling Rates† Up to 30 Mbps Low Power and High Speed D |
| 50Q | (13) | N/A | N/A | N/A | External Access enable: EA must be externally held low to enable the de |
| 50R | (25) | IR | 螺丝帽 | clocks will output on the DO pin the contents of the selected data regi | |
| 50S | (26) | NS | SOP-14 | SX | SYNC/MODE (Pin 2): Combination Mode Selection and Oscillator Synchronizat |
| 50T | (14) | The Smart 3 Advanced Boot Block, manufactured on Intels latest 0.25 &micr | |||
| 50U | (7) | N/A | The host sends this command when it detects an error in any transmission | ||
| 50V | (91) | WM | NPO | 05+ | VDETDetection Voltage Compliance RDETMINMinimum Valid Signature Resistanc |
| 50W | (57) | IR | 05/06+ | ||
| 50X | (8) | N/A | The test set described in this paper allows complete quanti- tative char | ||
| 50Y | (75) | RUBYCON | 01+ | All data valid at ambient temperature between 3.0V and 3.6V. The followin | |
| 50Z | (3) | Notes: 7. CPD is defined as the value of the internal equivalent capac | |||
| 5-1 | (548) | AMP / TYCO | Note 8 : We recommend using the regulator for the power supply which occur | ||
| 51- | (56) | TOSHIBA | BGA | 02+ | NOTES 1Linearity error here refers to integral linearity error. 2This c |
| 51. | (3) | JYEG | 04+ | Preliminary product information describes products which are in productio | |
| 510 | (485) | MOT | LCC | 2006 | Hynix HYMD264726B(L)8-M/K/H/L series is unbuffered 184-pin double data rat |
| 511 | (185) | AMIS | 06+ | QFP100 | 1. VCC and GND This IC has two VCC terminals and three GND termina |
| 512 | (114) | 336 | INTERSIL | 00+ | PORT I is an 8-bit Hi-Z input port The 28-pin device does not have a ful |
| 513 | (51) | HAR | SOP-3.9-8P | 6+ | • Asynchronous/Isosynchronous Modes C Standard CAN Controller |
| 514 | (147) | SANYO | 04+ | An 8-bit stack pointer (SP) stores addresses for stack operations. | |
| 515 | (131) | N/A | The Evaluation System is the most convenient environment for the develo | ||
| 516 | (118) | MOT | 1. Life support devices or systems are devices or systems w | ||
| 517 | (102) | advantage series | ＱＦＰ | original stock | Description Spread Spectrum Enable 0 = Spread Off, 1 = Spread On This i |
| 518 | (119) | N/A | 06+ | 500 | When HIGH, this input is used to advance the internal burst counter, contr |
| 519 | (50) | IC | 集成电路 | BSS138 | TI does not warrant or represent that any license, either express or impl |
| 51A | (21) | ON | 01+ | SOP-8 | SOP 2.5.9Process critical and key parameters 0076604 Process Qualificatio |
| 51B | (2) | S | 06+ | 500 | Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
| 51C | (42) | TEMIC | PLCC | The SY89833L is a 3.3V, high-speed 2GHz differential Low Voltage | |
| 51D | (8) | TEMIC | 01+ | PLCC44 | NOTES (a) For a device surface mounted on 25mm x 25mm FR4 PCB with high |
| 51E | (1) | nal pull-up resistor should be connected between SDA and V CC . The value | |||
| 51F | (2) | IBM | 93+ | Notes: 6. Test conditions assume signal transition time of 3 ns or | |
| 51G | (1) | ||||
| 51H | (5) | IR | DO-5 | 04 | The DP8572A (8572AM militarized version) is intended for use in micropro |
| 51L | (11) | STM | SOP/8 | 98+ | The device is entirely command set compatible with the JEDEC single-powe |
| 51M | (15) | SMD | 03+/04+ | *CPU: Socket 370 for Intel Celeron/Coppermine/Tualatin 633MHz~1.3GH | |
| 51N | (3) | NA | 03+ | The output drivers of this part have an embedded series-resistor. For DI | |
| 51O | (1) | Panasonic | SOP14S | 2007+ | The PI6C918 and PI6C919 are high-precision, low-voltage general-purpose |
| 51P | (1) | ATMEL | 2004 | ||
| 51Q | (2) | SMP | QFP | 2006 | High voltage, high current and high pulse operations, deflection circui |
| 51R | (25) | DIALOG Semi | 01+ | Operating voltage: +5.0V Programming voltage C VPP=12.2V0.2V C VCC=5.8V | |
| 51S | (9) | HIT | 94+ | SOJ | Carrier Detect/Mute Indicator/Control. When the CD/Mute output is low, th |
| 51T | (112) | JAPAN | TQFP-100 | Notes: 1. CL includes probe and jig capacitance. 2. Waveform 1 is for an | |
| 51V | (2) | N/A | SSOP | 07+ | tOFF=3.3nsTypical)andLowPower Consumption. The OE input is provided to |
| 51W | (26) | HIT | TSOP | 97+ | These devices have a 300% minimum CTR at an input current of only 0.5 |
| 51X | (1) | ||||
| 5-2 | (20) | Product Description/Features: • Low skew, Zero Delay Buffer ̶ | |||
| 52- | (11) | PHILIPS | SOT223 | 06+ | The 78P7200 is a line interface transceiver IC intended for STS-1 (51.84 |
| 52. | (7) | BENQ | TSSOP | The CD4046B types are supplied in 16-lead hermetic dual-in-line ceramic p | |
| 520 | (378) | OKI | 01+ | N/A | The CS5204−x series of linear regulators provides 4.0 A at |
| 521 | (123) | IC | 集成电路 | BT131-800D,412 | Halfbridge-Output 3; Internally contected to Highside-Switch 3 and Lowsid |
| 522 | (344) | S/PHI | CDIP16 | 9104 | Note 5: In applications where high power dissipation and/or poor package |
| 523 | (82) | IC | 集成电路 | BT136-600E | |
| 524 | (134) | HAR | SOP-3.9-8P | 6+ | Designed for Class AB amplifier applications in 50 ohm systems ope |
| 525 | (107) | IC | 集成电路 | BT148-400R,127 | The TL431, A, B integrated circuits are three−terminal prog |
| 526 | (195) | MOLEX | 07+ | When operating properly with 5V VCC (for example), /RESET will also be | |
| 527 | (145) | S/PHI | CDIP28 | ATS278 is an integrated Hall sensor with two output drivers and rotor spe | |
| 528 | (133) | molex | 07+ | The CM2009 connects between a video graphics con- troller embedded in a | |
| 529 | (98) | AMP/TYCO | 93+ | The GS82032 is a 2,097,152-bit high performance synchronous SRAM with a | |
| 52A | (5) | FAIRCHILD | QFN | 06+ | Inside 5B45 & 5B46 Modules C The 5B45/46 internal circuitry compare |
| 52C | (13) | NS | 06+ | 500 | Sensitivity and resolution are also a function of the size, shape, and c |
| 52F | (1) | ST | N/A | The entire family features JTAG for ISR and boundary scan, and is compat | |
| 52G | (4) | Address, data inputs, and all control signals are synchronized to the inpu | |||
| 52H | (3) | MAICO | SMD | † All typical values are at VCC = 3.3 V, TA = 25C. ‡ The bus | |
| 52K | (1) | 3V to 40V Input Voltage Operation Internal 1.6A Peak Current Switch Inte | |||
| 52L | (2) | QFP | Stresses beyond those listed under "absolute maximum ratings" m | ||
| 52M | (14) | IR | SOP | Fully Integrated xVCC and xVPP Switching xVPP Programmed Independent of x | |
| 52N | (2) | INFINEON | 00+ | 6. A transient suppressor is normally selected according to the working p | |
| 52P | (1) | Thresholds and Outputs The H6061 has open-drain outputs and voltage thr | |||
| 52S | (12) | N/A | DIP18 | 07+ | ESD voltage thresholds are dependent on the circuit parameters used to de |
| 52T | (2) | NS | 03+ | ||
| 5-3 | (6) | MOT | CAN6 | RLOAD = 25 W to VDD connected to pin IOUT. Sink current is controlled by | |
| 53- | (17) | IDT | QFP132 | The ISL6144 can be used in 10V to 75V systems and has an internal charge | |
| 53. | (9) | I²C uses a two-wire serial interface, comprising a bi-directional | |||
| 530 | (258) | MOLEX | 4000 | Stanleys opto-wireless transceiver modules are compatible with IrDA stand | |
| 531 | (62) | IC | 集成电路 | BTA16-800BRG | Reduced Power Consumption C 1.8 V Core Operation With 3.3 V I/Os and Supp |
| 532 | (223) | molex | 07+ | Three Fan Tachometer Inputs Three Programmable 16-bit Counter/Timers Dir | |
| 533 | (199) | MLX | SMD | 5 | The internal data word address counter maintains the last address accesse |
| 534 | (214) | AMI | 01 | The bus controller is responsible for generating 20 bits of address read | |
| 535 | (171) | AMP/TYCO | 00+ | To overcome this limitation, TI design engineers developed the patented E | |
| 536 | (198) | molex | 07+ | CRemote Sense: This is the logic 0 reference for the inputs VID0 C VID4, | |
| 537 | (78) | S | The MPC860 Quad Integrated Communications Controller (PowerQUICC™) | ||
| 538 | (86) | 97 | The CS5381 uses a 5th-order, multi-bit delta-sigma modulator followed by | ||
| 539 | (44) | CCDIP | This document is a general product description and is subject to change wi | ||
| 53A | (21) | MOTOROLA | QFP0707-32 | 97+ | • CASE: DO-13 (DO-202AA), welded, hermetically sealed metal |
| 53B | (2) | SOP | convection cooling and have an operational ambient temperature range in c | ||
| 53C | (120) | LSI | 2007 | Here we see a data line and the clock of a standard SDRAM isolated in a | |
| 53D | (10) | MOT | QFN-28 | 03+ | Sense(C): Provides the regulator with the ability to sense the set-point |
| 53E | (1) | Port 1 Port 1 is an 8-bit bidirectional I O port with internal pullups Th | |||
| 53F | (5) | NSC | 02+ | N/A | These very small, low cost filters are intended for use with A-D and D-A |
| 53G | (5) | LATTICE/AMD | PLCC | The CX65105 is internally matched for optimum linearity and efficiency. T | |
| 53H | (6) | 78 | CYPRESS | 99+ | © Philips Electronics N.V. 2000 All rights reserved. Reproduction |
| 53K | (1) | The 24XX128 supports a bidirectional 2-wire bus and data transmission p | |||
| 53L | (4) | 68 | CS | 00+ | The DS90C385A is a pin to pin compatible replacement for DS90C383, DS90 |
| 53M | (13) | IR | SOP | OUTPUT TRANSISTOR Collector-emitter Voltage BVCEO SFH600-0,1,2,3,4 SFH | |
| 53P | (3) | 00 | Similar to its analog input structure, the MAX104 features clock inputs d | ||
| 53R | (3) | Receiver gain control pin, Receiver signal output pin. Capable of contro | |||
| 53S | (19) | Transmit analog input and transmit level adjustment. AIN+ is a non-invert | |||
| 53W | (2) | The SC16C2550B is a two channel Universal Asynchronous Receiver and Tran | |||
| 53X | (1) | The LTC®6900 is a precision, low power oscillator that is easy to us | |||
| 53Z | (1) | The device has up to 37 software-configurable I/O pins, or- ganized into | |||
| 5-4 | (10) | SILICONIX | 97+ | TO-39 | • 8-Bit Digital-to-Analog Converter (DAC) C Independent Refe |
| 54- | (11) | MO | 05/06+ | The 16 1 Mux selects one of sixteen inputs E0 through E15 specified by f | |
| 54. | (2) | N/A | TOYOCOM | 05+ | FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN |
| 540 | (135) | 97 | DIP | Include 6.8uF tantalum and 0.1uF ceramic capacitors on both positive and | |
| 541 | (284) | molex | 07+ | The broadband MMIC amplifier can be directly applied to various current | |
| 542 | (75) | 97 | For packing material that is returned to us unsorted or which we are no | ||
| 543 | (69) | TI | DIP | 9210 | Feedback input. When ADJ is grounded, the device enters fixed voltage mod |
| 544 | (67) | MOT | DIP | 500 | Offset adjusting for the ADS-119 is normally accomplished at the point |
| 545 | (105) | IC | 集成电路 | BYV27-100,113 | The device provides a standard mode (100 Kbits/s) 2-line serial interface |
| 546 | (33) | The ISL6537A provides a complete ACPI compliant power solution for up to | |||
| 547 | (60) | ITT | 75 | DIP陶瓷 | 5-V/3.3-V CMOS Outputs Ioff Supports Partial-Power-Down Mode Operation |
| 548 | (51) | Molex | connector | 06+ | Supports PentiumIII, K6, and Socket 7 CPUs Designed to SiS630 & |
| 549 | (113) | FDS | QFP | 01+ | Also included in the measurement routine is logic to handle reverse-curr |
| 54A | (575) | CDIP | Both the negative and the positive power supplies must be effecti | ||
| 54B | (5) | 4.3.2 Thermal response (∆VBE measurements). The∆VBE me | |||
| 54C | (18) | NS | DIP | 8920 | Each of the LMH6628's closely matched channels provides a 300MHz unity ga |
| 54D | (4) | LT | DIP | DIP | • Multiple output clocks at different frequencies Three CPU |
| 54E | (1) | DIP16 | 05+/06+ | The EBD10RD4ADFA is 128M words 72 bits, 1 rank Double Data Rate (DDR) SD | |
| 54F | (877) | NS | SOP14 | 0026+ | A buffered output-enable (OE) input can be used to place the eight output |
| 54G | (2) | ∗2 VL setting is the VVL voltage of the vertical clock waveform, or | |||
| 54H | (695) | TI | DIP-16 | 04+ | Developed in TIs patented LBC3 BiCMOS process, the new BiMOS amplifiers c |
| 54L | (1097) | TI | DIP | 04+ | As a committed partner to the community and the environment, Vishay Sili |
| 54M | (15) | SOP16 | Load Regulation Since the IRU1010 is only a three-terminal device, it is | ||
| 54R | (3) | AD | This device contains protection circuitry to guard against damag | ||
| 54S | (269) | N/A | N/A | N/A | Output Data MSBs. When OE is LOW, the 12 most significant bits of the fil |
| 54T | (1) | If you have any questions or comments regarding this publication, please | |||
| 54V | (14) | OKI | • Low current consumption by CMOS process with high dielect | ||
| 5-5 | (137) | 0.8 FH REC ASSY 60P H=13 B=0.5 | AMP | 05+ | Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH |
| 55- | (48) | MO | 05/06+ | Rise time Reverse recovery time Storage time Soldering temperature S | |
| 55. | (11) | @eoeficia3mamnts (remrendst.ions, additions, deletions) and any @nent &am | |||
| 550 | (251) | IC | 集成电路 | BZV55-B4V3 T/R | The K5D5657ACM is a Multi Chip Package Memory which combines 256Mbit Nand |
| 551 | (165) | MSC | QFN | 2004 | Like all members of the FLASH370 family, the CY7C371 is rich in I/O resou |
| 552 | (213) | PHILIPS | 07+/08+ | Designed for ultraClinear amplifier applications in 50 ohm systems | |
| 553 | (250) | 00+ | The Preliminary Information presented herein represents a product in prot | ||
| 554 | (97) | PHI | BGA | N/A | The ADP3419 includes an anticross-conduction protection circuit, undervo |
| 555 | (381) | ST | SOP8S | 2007+ | Both a specific 32-bit ID as well as a 128-bit random ID is programmed i |
| 556 | (141) | S | 陶DIP14 | With FSK = High and ASK = Low and ENABLE = open or High, the PLL and the | |
| 557 | (95) | ICS | TSSOP-3.9-16P | 6+ | microprocessor. When the voltage on VSENSE rises above the COMMAND volt |
| 558 | (77) | TEMIC | 2008 | Notes: 4. Test conditions assume signal transition time of 3 ns or | |
| 559 | (58) | Molex 07+ | q Operating Voltage8 to 10 V 2q I C BUS Interface q TruSurround | ||
| 55A | (16) | IC | TO220 | Reading from the device is accomplished by taking Chip En- able 1 (CE1) | |
| 55C | (1) | An inductor is often described as being part of an LC filter at th | |||
| 55F | (3) | NS | PLCC-28 | 06+ | 260C for more than 10 seconds. • When shifting from preheatin |
| 55G | (2) | SANYO | 2008 | • C compiler optimized architecture: - Optional extended in | |
| 55H | (3) | IBM | QFP176 | Hewlett-Packard Application Note 923, Schottky Barrier Diode Vide | |
| 55L | (16) | FUJITSU | SOP | 04+ | The BG-LEDs are packed in cardboard boxes after packaging in anti-electros |
| 55N | (9) | MOTOROLA | 06+ | The circuits of Figures 1 and 3 depend upon the existence of an output | |
| 55O | (1) | +5V main power supply Back-up power supply (back-up capacitor connected) | |||
| 55P | (5) | ROHM | TQFP-128 | 02 | Renesas Technologys HN58V65A series and HN58V66A series are electrically |
| 55R | (13) | SOT89 | Logic supply Logic input for high side gate driver output (HO), in phase | ||
| 55S | (2) | Maximum ratings are those values beyond which device damage can occ | |||
| 55T | (3) | IMP | 98 | STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop c | |
| 55W | (1) | Input Resistor Matching Input Resistor Temp. Coefficient R | |||
| 55X | (1) | N/A | • VDDQ Power Supply to Support 5V I/O for SST39VF160Q | ||
| 55Y | (1) | 27 | SONY | O5 | • Low power, high speed FLASH/EEPROM technology • Fu |
| 5-6 | (27) | AMP/TYCO | N/A | Specifications with standard typeface are for TJ = 25˚C, and those w | |
| 56- | (11) | NS | O7+ | The read operation of the W29EE512 is controlled by #CE and #OE, both of | |
| 56. | (4) | SMD | 1999 | 66- or 133-MHz, 64-bit, true multifunction, intelligent bus master PCI- | |
| 560 | (80) | LITTLEFUSE | 12000 | The high-side driver is designed to drive low rDS(on) N-channel MOSFETs. | |
| 561 | (96) | 05+ | SMD | An output-enable (OE) input places the eight outputs in either a normal l | |
| 562 | (46) | XR | DIP | System level features - SelectRAM+™ hierarchical memory: | |
| 563 | (26) | PHILIPS | TSSOP20 | The TLV320AIC2x integrates all of the critical functions needed for most | |
| 564 | (90) | NEC | DIP64 | 2007+ | • True Dual-Ported memory cells which allow simultaneous rea |
| 565 | (103) | UTMC | SMD | While the TLV320DAC23 supports the industry standard over-sample rates of | |
| 566 | (29) | INTEL | PGA | 07+ | Stresses above those listed under Absolute Maximum Ratings may cause perm |
| 567 | (46) | S/PHI | CDIP14 | The MIC5306 is a micropower, µCap low dropout regulator designed fo | |
| 568 | (49) | IC | 集成电路 | BZX79-B9V1,133 | Hynix HYMD232G726A(L)8-M/K/H/L series is designed for high speed of up to |
| 569 | (61) | IC | 集成电路 | BZX79-C16,133 | These are the data inputs for programmable counting. Data on thes |
| 56A | (15) | Information furnished is believed to be accurate and reliable. However, S | |||
| 56B | (1) | The two banks have their own dedicated frequency select pins and can be | |||
| 56C | (11) | MT | 798 | downloaded externally. n The parameter control is made through the | |
| 56E | (1) | Thermal Design The IRU1261 incorporates an internal thermal shutdown tha | |||
| 56F | (3) | Supports the modem control interface protocol (CTRLE) Embedded high sp | |||
| 56H | (6) | IBM | BGA | This flip-flop has independent data, preset, clear, and clock inputs and | |
| 56J | (1) | SOP14 | 06+ | • Clock frequency: 166, 143, 100 MHz • Fully synchronous; a | |
| 56K | (1) | ||||
| 56L | (1) | AMKOR | . | 04+ | DIP (leads with 0.4" spacing) (lead bends for surface mount) (tape |
| 56M | (2) | INTERSIL | QFN56 | 0274+ | The eight latches of the LS373 and S373 are transparent D-type latches, |
| 56N | (6) | FA | DIP | 95 | A buffered output-enable (OE) input can be used to place the eight outp |
| 56P | (2) | POSIFLEX | QFP-M44P | 6+ | The clock driver serial protocol accepts byte write, byte read, block wri |
| 56S | (6) | INTERSIL | DIP-16 | 08+ | Differential output pair. LVPECL interface levels. Output enable Bank B |
| 56T | (2) | This advanced BiCMOS design features low operating current, adjustable | |||
| 56U | (2) | 1 LSB change around major carry, VREF = 0 V DAC latch loaded with all | |||
| 56V | (1) | NEC | SOT23 | [Data Slicing] Threshold Capacitor (External Component): Capacitor extract | |
| 56X | (6) | Notes: 1. See test circuit and waveforms. 2. This parameter is guarantee | |||
| 56Z | (1) | ||||
| 5-7 | (17) | AMP/TYCO | 0632 | † Stresses beyond those listed under absolute maximum ratings may c | |
| 57- | (41) | N/A | DDK | 05+ | The FAN53168 features a high bandwidth control loop to provide optimal r |
| 57. | (1) | ||||
| 57/ | (1) | The FS6282 is a monolithic CMOS clock generator IC designed to minimize c | |||
| 570 | (45) | ICS | 05+ | SOP-3.9-8P | Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. |
| 571 | (35) | DL | 06+/07+ | NOTE: 1. Because the gate controls are asynchronous, runt pulses are pos | |
| 572 | (30) | /\\ | SOP-3 | Digital ground reference. Connected to external crystal to excite the I | |
| 573 | (15) | AAVID THERMALLOY LLC | 01+ | The filter is followed by a base-band amplifier which boosts the de- tect | |
| 574 | (465) | SI | HC49U | 98 | SymbolConditions VIN ISS1 VIN-VOUT=1.0V VCE=VIN Is |
| 575 | (74) | Serial-test information is conveyed by means of a 4-wire test bus or TAP | |||
| 576 | (34) | SMD-24 | 04 05 | 1.1 EMI REDUCTION The COP8SAx family of devices incorporates circuitry t | |
| 577 | (20) | ATMEL | O7+ | • Ultra-miniature size with universal terminal footprint • Hi | |
| 578 | (90) | ZILOG | SOP | 03+ | * Antiparallel diode for high frequency switching devices * Antis |
| 579 | (8) | N/A | MOLEX | 05+ | 128K x 36, 256K x 18 memory configurations Supports fast access times: C |
| 57A | (8) | C Three External Clock Inputs, Two Multi-purpose I/O Pins per Chan | |||
| 57B | (2) | ROSTRA | SOP | 02+ | n PSRR at 217 Hz and 1kHz65dB (typ) n Output Power at 1kHz with VDD = 2 |
| 57C | (471) | WSI | O7+ | The LH1532 dual 1 Form A relays are SPST normally open switches that can | |
| 57D | (1) | SHARP | Note 1: All voltages are with respect to GND. All currents are positive | ||
| 57F | (30) | 05/06+ | Stresses in excess of the absolute Maximum Ratings can cause permanent da | ||
| 57G | (25) | ON | 00+ | Notes: a. Room = 25C, Full = as determined by the operating suffix. b. | |
| 57H | (2) | The AVR core combines a rich instruction set with 32 general-purpose work | |||
| 57L | (3) | WSI | CWDIP24 | —— | Hynix HYMD132725B(L)8J-J series is unbuffered 184-pin double data rate Syn |
| 57N | (2) | Note: Hitachis serial EEPROM are authorized for using consumer applicatio | |||
| 57P | (5) | IBM | NEW | 01+ | Blocking voltage : VDRM / VRRM = +/-700V Avalanche controlled : VCL typ |
| 57R | (2) | gram resistor (RP) from VCC to the Program input in accord- ance with the | |||
| 57T | (12) | ||||
| 57U | (1) | TI | 01+ | PLCC-20 | The MC68HC001 provides a functional extension to the MC68HC000 HCMOS 16-/ |
| 57V | (3) | HY | TSOP | 00+ | The HYM5V72A1604 is a 16M x 72-bit EDO mode CMOS DRAM module consisting of |
| 57W | (12) | ATMEL | BGA | Unused input pins should be tied directly to VCC or GND. Product terms | |
| 57Z | (2) | TI | DIP-8 | 05+ | Notes: 1. S-parameters include bond wires. Gate: Total 2 wire (s |
| 5-8 | (34) | MODU 2 PIN HEADER | AMP | 05+ | The size and placement of the capacitors for the main voltage bus for th |
| 58- | (4) | KYOCERA | YEYK | At the end of the rows containing the sysMEM Blocks are the sysCLOCK Phas | |
| 580 | (61) | AMD | BGA | 01+ | • Ultra-miniature size with universal terminal footprint • Hi |
| 581 | (40) | 83 | Guaranteed Low Skew < 25ps (max) Very low duty cycle dis | ||
| 582 | (29) | 00+ | OSC1 and OSC2 are connected to an RC network or a crystal (by mask option | ||
| 583 | (62) | IC | 集成电路 | BZX84C4V3LT1G | Device erasure occurs by executing the erase com- mand sequence. This ini |
| 584 | (21) | AGERE | SSOP38 | 0224+ | ISP1161A is well suited for embedded systems and portable devices that re |
| 585 | (49) | IC | 集成电路 | BZX84-C68,215 | Internal synchronous rectification greatly improves effi- ciency and elim |
| 586 | (25) | MEC | SOP24W | 2007+ | The MPC885/880 is a versatile single-chip integrated microprocessor and |
| 587 | (16) | IC | 集成电路 | BZX84C9V1 | • Internal oscillator requires no external components • I2C-bu |
| 588 | (10) | TEMIC | 01+ | DIP-40 | The control register sets the mode and signal direction for the three 8-b |
| 589 | (24) | HONEYWE | 89 | DIP镀金 | These P-Channel MOSFETs from International Rectifier utilize advanced p |
| 58A | (6) | QFP | 00+ | Full device operation requires linear VCC ramp from VDR to VCC(min) > | |
| 58B | (1) | DIP-8 | LT-06 | 99+ | Specifications 20 Watts 2.25 Watts 5.9 C/W |
| 58C | (10) | N/A | SSOP | The 58C256AT110 is the 12-bit resolution member of the TxDAC series of h | |
| 58D | (1) | NS | SOP | Antialias or Reconstruction Filtering DSP Systems Communications Systems | |
| 58E | (1) | Power Supply for the RF Section. Decoupling capacitors to the ground plan | |||
| 58F | (2) | BGA | 02+ | 16-Bit Monotonic 5-V Rail-to-Rail Output Fast Settling: 0.65 µs F | |
| 58H | (2) | All Data I/O Ports − 5-V Input Down To 3.3-V Output Level S | |||
| 58L | (87) | . | QFP-100P | 2005 | The H11GX series are photodarlington-type optically coupled optocouplers. |
| 58M | (1) | SOP16 | MAX 3000A devices provide programmable speed/power optimization. SpeedCc | ||
| 58N | (3) | Panasonic | DIP-6 | 07+/08+ | Notes: (i) Io 1(min) current of 0.1A can be divided between both outputs |
| 58P | (1) | The negative output voltage of the Power Trends PT6900 Series ISRs may b | |||
| 58R | (4) | JAT | 4532 | 05+ | Units shipped in the quarter reached 6.7 million, which is 34% higher year |
| 58S | (1) | • High performance 1:10 clock driver for general purpose ap | |||
| 58T | (1) | 00+ | High Speed: tPD = 3.5 ns (Typ) at VCC = 5 V Low Power Dissipation: ICC = | ||
| 58V | (4) | HITACHI | SSOP | 07+ | This ISOSMARTTM chipset is a pair of integrated circuits providing isol |
| 58W | (1) | N/A | N/A | 135 | For multiple FPGAs configured as a daisy-chain, or for future FPGAs req |
| 58Z | (1) | SOP28 | Input Termination Center-Tap: Each side of the differential input pair te | ||
| 5-9 | (6) | AMP/TYCO | 00+ | sizing, and programmable I/O (PIO) pins on one chip. Compared to the 80 | |
| 59- | (29) | EVERVIGHT | N/A | Notes: 1. The nominal thermal resistance of a display mounted in a socke | |
| 590 | (36) | intersil | DIP | 0728vgc+ | - Operation from single +5.0V supply - Input pull-down resistor prevents |
| 591 | (112) | VISHAY | SMD | 2008 | High current sink/source 25 mA/25 mA Four external interrup |
| 592 | (436) | VISHAY | 06+ | ||
| 593 | (665) | VISHAY | 05+ | F0o/RCK Frame Pulse Out/Receive Bit Rate Clock output (Digital). In DN mo | |
| 594 | (388) | VISHAY | 06+ | The MSK 5115 series is fully protected against reversed input polarity, | |
| 595 | (575) | VISHAY | 06+ | Low Output Noise: 90µVRMS (100kHz BW) Fixed Output Voltage: 5V Inp | |
| 596 | (3713) | TI | 07+ | FEATURES 225 ps Propagation Delay through the Switch 4.5 Switch Connect | |
| 597 | (143) | ON | DIP | 02+ | |
| 598 | (56) | ST | QFP-80 | 01＋ | Temperature data is converted from the on-chip thermal sensing element |
| 599 | (52) | ST | QFP | The Transmission Line Pulse tester implements a controlled impedance cabl | |
| 59A | (7) | SMD-8 | 05+ | The SM5009 series are crystal oscillator module ICs that incorporate low | |
| 59C | (24) | ATMEL | 97+ | DIP8 | All outputs simultaneously sink rated current DC with no thermal deratin |
| 59G | (2) | PHILIPS | 92 | PLCC-28 | Stresses beyond those listed under Absolute Maxi- mum Ratings may cause |
| 59H | (2) | 05+ | QFP | Stresses in excess of the absolute maximum ratings can cause permanent da | |
| 59J | (1) | Zener Breakdown Voltage: 6.2 − 47 Volts DC Power Diss | |||
| 59K | (3) | The ACT16241 are 16-bit buffers or line drivers designed specifically t | |||
| 59L | (1) | TOSHIBA | BGA1118 | 05+ | Operating Voltage Range of 4.5 V to 5.5 V High-Current Outputs Drive Up T |
| 59M | (1) | APPLICATION The DS55107 DS75107 dual line circuits are designed spe- ci | |||
| 59N | (4) | INFIEON | QFN-8P | 6+ | |
| 59P | (5) | VITEC | SOP | 06+ | CASE: Hermetically sealed axial-lead glass DO-35 (DO-204AH) package TERM |
| 59R | (5) | TOS | BGA | 05+ | Notes 1. Derate linearly from 25C at a rate of 2.42 mW/ C 2. Derate li |
| 59S | (30) | STM | QFP-80 | 03+ | 3. Short circuit may be to ground or either supply. Rating applies to 70o |
| 59Y | (1) | TOS | BGA | 05+ | This pin establishes the reference current for the internal current steeri |
| 5A- | (3) | 05+ | 1.0 POWER-UP/DOWN CONTROL Following power-on initialization, power-up an | ||
| 5A/ | (2) | ||||
| 5A1 | (9) | 2001 | nanoseconds at the processor pins, which translates to an approximately 3 | ||
| 5A2 | (11) | TEMIC | PLCC | ||
| 5A4 | (1) | 2. BVDSS is the absolute maximum voltage rating between drain and source | |||
| 5A6 | (10) | N/A | SOT6 | 07+ | 2. Memory Address Expansion The VP-1000A's internal 15-bit address count |
| 5A8 | (1) | When the IEEE Std. 1149.1 (JTAG) interface is used for in-system programm | |||
| 5A9 | (1) | 9711 | As shown in Figure 3, the TIE Corrector Circuit receives one of the two re | ||
| 5AA | (1) | The functionally complete 5AAC600/DC400V is packaged in a single, 24-pin | |||
| 5AC | (2) | 26 | INTEL | The SN74LVC16373A is particularly suitable for implementing buffer regi | |
| 5AD | (2) | NOTES: 1. The 732mV peak-to-peak input pulse level is specified to allow | |||
| 5AK | (4) | Public key execution unit (PKEU), which supports the following: RSA and | |||
| 5AL | (1) | 98 | • A-Port outputs have equivalent 22-Ω series resistors, so &n | ||
| 5AM | (2) | 95 | QFP | The ISL6434 monitors all the output voltages. A single Power Good signa | |
| 5AQ | (1) | The 74ALVCH16841 has two 10-bit D-type latch featuring separate D-type i | |||
| 5AR | (1) | By combining a conventional thin-film R-2R ladder DAC, a digital offset | |||
| 5AS | (1) | N/A | Notice: This document contains information on new products in production. | ||
| 5B- | (3) | 05+ | SMD | The AD7738 is similar to the AD7739 but has higher speed (8.5 kHz channe | |
| 5B0 | (6) | ADI | 07+ | International standard package JEDEC TO-247 AD IGBT and anti-parallel | |
| 5B1 | (2) | HIT | DO-35 | 05+ | or Powered-Down Low and Flat ON-State Resistance (ron) Characteristics O |
| 5B3 | (90) | ADI | 07+ | CONDITIONS IN1, IN2 and OUT BAT VBAT = 4.2V Suspend Mode Suspend Mode | |
| 5B4 | (45) | ADI | 07+ | Absolute Maximum Ratings are limits beyond which damage to the device may | |
| 5B8 | (1) | SANYO | Literature Fulfillment: Literature Distribution Center for ON Semi | ||
| 5BA | (1) | 95 | The 128-pin version of the CY7C646xx brings out the full 8051 address and | ||
| 5BD | (1) | ADI | 07+ | The IC is based on the Smart Power Technology SPT which allows bi | |
| 5BE | (1) | Acknowledge Acknowledge is a software convention used to provide a posi | |||
| 5BF | (1) | Chip Enable, Output Enable and Write Enable sig- nals control the bus o | |||
| 5BP | (1) | Bursts can be initiated with either ADSP (Address Status Processor) or | |||
| 5BU | (1) | 03 | Maximum ratings are those values beyond which device damage can occur. M | ||
| 5C- | (1) | 2008 | Freescales semiconductor products are classified into the following three | ||
| 5C0 | (10) | ST | SOP8S | 2007+ | |
| 5C1 | (9) | HIT | O7+ | ||
| 5C2 | (11) | HIT | DO-35 | 05+ | 2.7 to 3.6V SUPPLY VOLTAGE in READ OPERATION ACCESS TIME: C 70ns at V |
| 5C3 | (3) | Addresses and chip enables are registered at rising edge of clock when ei | |||
| 5C4 | (3) | MOT | SOP-28 | 99+ | (*) CPD is defined as the value of the ICs internal equivalent capacitanc |
| 5C6 | (12) | MT | DIP28 | 2007+ | Turn-On Propagation Delay Turn-Off Propagation Delay Turn-On Rise Tim |
| 5C7 | (1) | TOS | SOP14 | 04+ | The FAN4174 is designed on a CMOS process and provides 3.7MHz of bandwidt |
| 5C8 | (1) | The MX98715A contains a PCI local bus glueless inter- face, a Direct Me | |||
| 5CA | (4) | 08+ | Layout 300 ps Maximum Differential Skew Propagation Delay Times 1.8 ns ( | ||
| 5CB | (5) | TOKO | 5650 | 05+ | The IDT70V7519 is a high-speed 256Kx36 (9Mbit) synchronous Bank-S |
| 5CC | (6) | NOTES: 1. Measurements with 0.4 VIN VCC. 2. OE VIH, 0.4 VOUT VCC. | |||
| 5CD | (6) | TOKO | Fifth Generation HEXFET® Power MOSFETs from International Rectifier | ||
| 5CE | (2) | TOKO | SMD | 2001 | The W83877ATF provides two high-speed serial communication ports (UARTs), |
| 5CF | (1) | The chip supports an optional start and stop bit (either 0 or 1) that p | |||
| 5CH | (4) | MIT | SOP-8 | 08+ | WRITE CLOCK (WCLK) A write cycle is initiated on the LOW-to-HIGH t |
| 5CL | (1) | TOSHIBA | Clocks in the ispLSI 2064 and 2064A devices are se- lected using the de | ||
| 5CP | (1) | Life Support Applications These NEC products are not intended for use in | |||
| 5CQ | (1) | Functional I/O The HFBR-5710L accepts industry standard differential | |||
| 5CR | (1) | DMA Controller supports: 25 DMA channels for transfers between ADSP-2136 | |||
| 5CS | (1) | NOTES: (1) For detailed drawing and dimension table, please see end of da | |||
| 5CX | (1) | SUMIDA | 00+ | NOTE: EP circuits are designed to meet the DC specifications shown in the | |
| 5D- | (1) | The ELM312 is an interface circuit for use between high speed lo | |||
| 5D1 | (27) | N/A | •Built-in digital delay , mixing amplifiers,input output selector | ||
| 5D2 | (6) | N/A | Notes: 1. This parameter is guaranteed but not tested on Propagation Del | ||
| 5D5 | (7) | The HYM72V12C736B(L)S4 Series are Dual In-line Memory Modules suita | |||
| 5DA | (1) | • Industry Standard Size • Industry Standard Pinout | |||
| 5DC | (3) | 2007 | The 5DC090-50 also features fan fault sensing for enhancing system prote | ||
| 5DF | (3) | 292 | 2005 | TAOperating free-air temperatureC4085C † With supply voltage | |
| 5DG | (2) | • Wide supply voltage range: Vcc = 2.2 to 5.5 V • Including cl | |||
| 5DH | (1) | The EB-2100x permits three separate methods for clocking the DDX-2000. Th | |||
| 5DI | (1) | Conforms to POCSAG standard for pagers 512 or 1200 bps signal speed Sup | |||
| 5DL | (5) | TOSHIBA | Glass passivated junction. 500W Peak Pulse Power capability on 10/1000 | ||
| 5DM | (1) | 2008 | The output voltage remains at the clamp level as long as the overdrive | ||
| 5DP | (1) | These devices are fully specified for hot-insertion applications using Io | |||
| 5DS | (1) | s Data Management Software (DMS) AMD-supplied software manages | |||
| 5DV | (1) | Texas Instruments and its subsidiaries (TI) reserve the right to make cha | |||
| 5DZ | (1) | − Read, program, and erase operations from 1.8 to 2.2 V (2. | |||
| 5E0 | (3) | STM | QFP-44 | 02+ | Collector-to-Emitter Voltage Continuous Collector Current Continuous |
| 5E1 | (1) | FSC | 06+ | 2214 | Wiper Counter Register (WCR) The 5E12 contains a Wiper Counter Register |
| 5E2 | (1) | Four differential pairs of LVDS outputs Drives 50- or 100-ohm loa | |||
| 5E4 | (3) | The P82B96 offers many different ways in which it can be used as a bus i | |||
| 5E6 | (3) | At 333 MHz (3.0 ns) core instruction rate, the ADSP-21365/6 perfo | |||
| 5EA | (1) | The SOA curve should be interpreted as an absolute maxi- mum rating. Ope | |||
| 5EC | (1) | !Features 1) High speed switching. (Tf : Typ. : 20ns at IC = −3A) | |||
| 5EF | (2) | The S29C51004T/S29C51004B is a high speed 524,288 x 8 bit CMOS fl | |||
| 5EH | (8) | AMD is a trademark of Advanced Micro Devices, Inc. Award is a trademark | |||
| 5EL | (1) | N/A | 0402L | The EL6839 is a high performance, dual output, laser driv | |
| 5EM | (1) | 01 | Stresses above those listed under Absolute Maximum Ratings may cause pe | ||
| 5EQ | (1) | IR | 07+ | For Rx and Ry, the threshold is always 50% of VCC so switching levels ar | |
| 5ES | (10) | Ring provides half the two-wire con- nection to the telephone network, | |||
| 5EU | (2) | TOKO | 97 | Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds260 (2 | |
| 5F- | (1) | Four dedicated test pins observe and control the operation of the test ci | |||
| 5F0 | (1) | FSC | SSOT8 | • Wide frequency rangeC0.5MHz to 30.0MHz • User specified tol | |
| 5F3 | (3) | QFN | 06+ | The SG6846 is especially designed for SMPS with surge-current ou | |
| 5F4 | (1) | ||||
| 5F5 | (1) | 21 | ST | 03+ | Direct Stream Digital (DSD) C Dedicated DSD Input Pins C On-Chip 50 kHz |
| 5FL | (1) | TOS | TO-220F | 04+ | This device contains protection circuitry to guard against damage |
| 5FP | (1) | Parallel Mode Operation For latched parallel interfacing the LE line shou | |||
| 5FS | (1) | FAIRCHILD | 2001 | FEATURES High Slew Rate: 10 V/ s Min Fast Settling Time: 0.9 s to 0.1% | |
| 5FW | (3) | TOSHIBA | TO- | The transmitter data path consists of a transmit input buffer, pulse-sha | |
| 5G- | (1) | The C67x CPU executes all C62x instructions. In addition to C62x fixed-po | |||
| 5G0 | (1) | The 5G052 is a miniature transmitter module that generates on-off keyed ( | |||
| 5G1 | (6) | CAN-8 | 98+ | Receiver Loss of Signal, logic high, open collector compatible, 4.7K to | |
| 5G2 | (1) | /DACK /DMA Acknowledge (Input, active Low). /DACK, in conjunction with /I | |||
| 5G3 | (6) | SB | 07+/08+ | Insertion of the SNAPHAT housing after reflow prevents potential batter | |
| 5G5 | (1) | Digital clock dividers provide three customizable clock fre- quencies fo | |||
| 5G6 | (2) | MOS | 00+ | FLEX 8000 devices provide a large number of storage elements for applica | |
| 5G8 | (3) | high-frequency tube | MITSUBIS | 04+ | A general-purpose data register file is contained in each processing ele |
| 5G9 | (3) | DIP-14 | Cycle-by-cycle current limiting, soft start, under-voltage lock-ou | ||
| 5GA | (10) | ＶＩＳＨＡＹ | To define the active polarity of a signal, a suffix will be used. | ||
| 5GD | (1) | 03 | 3.2 Qualification. Devices furnished under this specification shal | ||
| 5GH | (2) | N/A | N/A | N/A | This pin provides the output current range adjustment by means of a resis |
| 5GJ | (1) | 05+ | 4.4.2 Group B inspection. Group B inspection shall be conducted in | ||
| 5GL | (1) | TOS | TO-220F | 04+ | Input Termination Center-Tap: Each side of the differential input pair CLK |
| 5GM | (1) | 05+ | Note 1: All devices are production tested at +25C. All temperature limits | ||
| 5GP | (1) | The HT24LC02 is a 2K-bit serial read/write non-volatile memory device usi | |||
| 5GU | (1) | TOSHIBA | 04+ | SDRAM read and write accesses are burst oriented starting at a selected | |
| 5GW | (5) | TOSHIBA | TO- | Low Noise: 20µVRMS (10Hz to 100kHz) Low Quiescent Current: 25&micr | |
| 5H0 | (14) | FSC | DIP8 | This is the timing reference frequency which is the transmit frequency d | |
| 5H1 | (1) | • Rated isolation voltage (RMS includes DC) VIOWM = 1000 VR | |||
| 5H2 | (1) | HARRIS | 1998+ | QFP/67 | The TOSHIBA 5H2C4203 a photocoupler which combines a GaAlAsIRED as the em |
| 5H3 | (3) | TOSHIBA | DIP42 | 06+ | 1394b-2002 at S100, S100B, S200, S200B, S400, and S400B Signaling Rates ( |
| 5H6 | (1) | Right channel serial data input. Both LDATA and RDATA are assumed to be M | |||
| 5HK | (4) | 02 | PLL-LPF (Pin 3): Phase Locked-Loop Filter Pin. This is the output of the | ||
| 5HM | (1) | 02 | transmitted to the silicon diaphragm. The MPXHZ6400A series pressure sens | ||
| 5HN | (24) | 三洋 | 12000 | 07+ | MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to th |
| 5HP | (17) | SANYO | SOT-23 | 05+ | The EM785840 series are 8-bit RISC type microprocessor with low po |
| 5HQ | (1) | Table 3.1 - LAN91C100FD Pin Requirements Table 5.1 - Internal I/O Space M | |||
| 5HR | (1) | 05+ | DIP | There are a total of 16 global clock lines, with eight available per qua | |
| 5HT | (2) | The MAX1540/MAX1541 dual pulse-width modulation (PWM) controllers provide | |||
| 5HW | (4) | FILTER RAD'L CF 820MHZ | 05+ | *Stresses above those listed under "Absolute Maximum Rat- ings" | |
| 5I6 | (1) | SOP/8 | 06+ | During normal CRT operation, internal arcing may occasion- ally occur. | |
| 5IH | (1) | MICROCHIP | QFN-8P小体 | 6+ | These Intersil RS-485/RS-422 devices are BiCMOS 3.3V powered, single tr |
| 5IM | (2) | 04+ | Address Inputs for 32M x 64 modules Bank Selects Data Input/Output Row | ||
| 5IN | (1) | † Stresses beyond those listed under absolute maximum ratings may c | |||
| 5IR | (3) | 01+ | QFP-144 | A rising edge on PWM initiates the turn-off of the lower MOSFET (see Timi | |
| 5-J | (1) | Supply Voltage Differential Input Voltage (Note 8) Input Voltage Input | |||
| 5J0 | (1) | 3. Load regulation and output voltage are measured at a constant junction | |||
| 5J8 | (5) | TOS | SOP | 06+ | The CM3004 is a very-low-dropout regulator that offers both fixed outpu |
| 5JE | (2) | MORIYAMA | SOP-28P | 05+ | Note: 1. Enhancement mode technology employs a single positive Vg |
| 5JF | (1) | ||||
| 5JL | (1) | TOS | TO | The information provided herein is believed to be reliable at press time. | |
| 5JS | (1) | TO263 | • Decodes MPEG2 MP@ML, MPEG1 video bitstreams • Decode DVD, S | ||
| 5JU | (1) | TOS | TO-220 | Caveat: This calculation has assumed that the voltage drops due to the v | |
| 5JZ | (1) | QFP | 07+ | (1) The marketing status values are defined as follows: ACTIVE: Product | |
| 5K1 | (2) | Zener Voltage (VZ) is measured with junction in thermal equilibrium with | |||
| 5K3 | (1) | • Available on Both Encoder Modules (HEDS-9000 Serie | |||
| 5K4 | (3) | MIT | DIP | 2006 | (1) LED CURRENT CONTROL The NJU6052 incorporates the LED current c |
| 5K6 | (2) | Complete System Solution for interfacing SmartMediaTM (SM) or xD Picture | |||
| 5K9 | (1) | Max. UnitsConditions CCCSVDS = 50V, ID = 3.3A 22ID = 3.5A 5 | |||
| 5KB | (2) | SANKEN | 02+ | 220 | The MIC863 is a dual low power operational amplifier in SOT23-8 package |
| 5KE | (4) | The MPX12 series device is a silicon piezoresistive pressure senso | |||
| 5KK | (1) | Repetitive rating; pulse width limited by max. junction temperature. Pul | |||
| 5KO | (2) | The Preliminary Information presented herein represents a product in prot | |||
| 5KP | (173) | VISHAY | R-6 | 2008+ | NOTES: (1) Includes the effects of amplifiers input bias and offset curre |
| 5KR | (1) | Hynix HYMD132G725A(L)8-K/H/L series incorporates SPD(serial presence detec | |||
| 5KS | (3) | • TOSHIBA is continually working to improve the quality and reliabil | |||
| 5KU | (1) | decoders. Several standard interfaces, like I2C/L3, I2S or RDI are imple | |||
| 5KV | (1) | WM | SL | 05+ | NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value |
| 5L0 | (14) | 05+ | The Hynix HYM71V8M655HC(L)T6 Series are Dual In-line Memory Modules | ||
| 5L2 | (1) | G | CDIP-28 | The EP111 is specifically designed, modeled and produced with low | |
| 5L3 | (1) | If a system designer needs more than 16 outputs with the features just de | |||
| 5L4 | (2) | TI | BGA152 | The GS4882 and GS4982 determine odd/even field information by comparing v | |
| 5LB | (1) | MICROCHIP | USOP-8P | 6+ | Memories C 16K to 60K bytes Program memory (ROM,OTP and EPROM) |
| 5LC | (4) | TO-220 | NOTE: Preferred Tolerances and reel sizes are in bold. We reserve the ri | ||
| 5LE | (6) | Hynix HYMD116M645A(L)8-K/H/L series is unbuffered 200-pin double data rate | |||
| 5LN | (17) | SANYO | SOT-23 | 05+NOPB | Serial Clock (SCL). This input signal is used to strobe all data in and |
| 5LP | (18) | SANYO | SOT-23 | 05+ | Register-usage rules influence placement of input and results within the |
| 5LS | (2) | NA | 02+ | The CMOS bq3285E/L is a low- power microprocessor peripheral providing a | |
| 5LV | (1) | IDT | 00+ | PLCC | AP03N70 series are specially designed as main switching devices for unive |
| 5LW | (1) | 02 | Information furnished by MEMSIC is believed to be accurate and reliable. | ||
| 5-M | (2) | ∗1 DC bias is applied within the CCD, so that this pin should be gr | |||
| 5M0 | (24) | 3575 | 01+ | Selectable dual output or bi-phase operation Direct drive for N-cha | |
| 5M2 | (1) | 12000 | 07+ | Features • IXYS advanced low Qg process • Low gate charge an | |
| 5M3 | (1) | FASTCAT | QFP | 01+ | Please be aware that an important notice concerning availability, |
| 5M4 | (3) | Mitsubishi | TSSOP | BUFFER READ: Data can be read from either one of the two buffers, using d | |
| 5M5 | (6) | MIT | DIP | 2006 | This pin adjusts the peak current limit of the Sense FET. The feedback 0. |
| 5M6 | (1) | 96 | NOTES: 1. The device may be operated outside recommended frequency range | ||
| 5MD | (3) | The SK-2910 Series of quartz crystal oscillators provide DPECL Fast Edge | |||
| 5MF | (2) | Empty or Full Fault Flag: empty Fault is updated on the rising edge of CK | |||
| 5MK | (1) | MRS initializes the read and write pointers to zero and sets the output re | |||
| 5ML | (1) | HARRIS | 07+ | FEATURES 11 LDOs Optimized for Specific CDMA Subsystems 4 Backup LDOs f | |
| 5MM | (6) | ||||
| 5MQ | (4) | N/A | SMD | 07+ | • 500-ps max. Total Timing Budget™ (TTB™) window • |
| 5MV | (1) | 00 | All instructions (Table 1), addresses and data are transferred MSB @ | ||
| 5MX | (2) | JAPEN | 95+ | Write Enable 1 (WEN1). If the FIFO is configured for program- mable flags | |
| 5N0 | (7) | NEC | SOP/40 | 94+ | Notes: 1. CL = Load capacitance: includes jig and probe capacitance. |
| 5N1 | (11) | TOYO | 04 | Rail-to-Rail Input and Output Small SOT-23 Package Gain Bandwidth Produc | |
| 5N2 | (13) | SMD-8 | 05+ | The 5N20 is enabled through the Chip Select (CSb) pin and is accessed via | |
| 5N3 | (6) | † All characteristics are measured with a 0.33-µF capacitor a | |||
| 5N4 | (3) | Collector-emitter voltage peak value Collector-emitter voltage (open ba | |||
| 5N5 | (7) | 07+ | TO-220 | The HYM72V32M736B(L)T6 Series are Dual In-line Memory Modules suitable for | |
| 5N6 | (7) | UTC | TO-220F | 08+ | The purpose of this 54C/74C Family Characteristics applica- tion note i |
| 5N7 | (2) | . | . | 01+ | Stresses beyond those listed under Absolute Maximum Ratings may cause per |
| 5N8 | (1) | The KM4110 (single) and KM4120 (single with disable) are low cost, volta | |||
| 5N9 | (2) | FAIRCHIL | TO-220 | 06+ | The Hynix HYM76V8755HGT8 Series are Dual In-line Memory Modules sui |
| 5NA | (1) | 仙童 | 07+ | TO-220 | The Rambus RIMM modules are offered in a 184-pad 1 mm edge connector pad |
| 5NC | (1) | Clock inputs CLK+ and CLK- may also be driven with positive referenced EC | |||
| 5ND | (2) | LT | QFN | ||
| 5NK | (3) | ST | TO-220F | 04+ | Inter-Integrated Circuit Serial Ports (I2C0, I2C1). The C672x includes tw |
| 5NP | (3) | HIFN | CGA42.5*42.5 | N/A | FEATURES D BiCMOS Version of UC3846 Family D 1.4-mA Maximum |
| 5NR | (5) | DAC08 applications include 8-bit, 1 µs A/D converters, servo motor | |||
| 5NS | (1) | NOTES 1Measured at IOUTA, driving a virtual ground. 2Nominal full-scale | |||
| 5NT | (1) | The state of the data line represents valid data after a Start condition | |||
| 5NU | (1) | This is an N-Channel enhancement mode silicon gate power field eff | |||
| 5NX | (2) | ST | 05+ | SOP-28 | C Supports both Firmware Hub (FWH) and LPC Memory Read and Write C |
| 5O0 | (1) | 3Dfx | 05/06+ | Motorola reserves the right to make changes without further notice to any | |
| 5OQ | (1) | For high-density packaging applications, the UCN5818EPF is furnish | |||
| 5OU | (1) | Programmable Features (525p/625p) 8 Oversampling (216 MHz Output) | |||
| 5P0 | (10) | ST | SOP8 | Note 2: The Absolute Maximum Ratings are those values beyond which the sa | |
| 5P1 | (1) | This notice outlines changes made to the first and second printings of th | |||
| 5P2 | (8) | N/A | QFP-44 | Table 3.1 - LAN91C100FD Pin Requirements Table 5.1 - Internal I/O Space M | |
| 5P3 | (6) | TOSHIBA | DIP-48 | 07+ | Notes: 7. Test conditions assume signal transition time of 5 ns or |
| 5P4 | (10) | NEC | TO-251 | 04+ | 1. Test conditions: T = 25º C, Supply Voltage = +5 V, Device Voltage |
| 5P5 | (4) | N/A | • 0.23 µm Process Technology • Single 3.0 V read, progr | ||
| 5P6 | (5) | NEC | TO-251 | 04+ | rupt input with pull up (23 pins only). 3 of the digital I/O pins serve |
| 5P8 | (3) | ||||
| 5P9 | (1) | TOS | BGA | 01+ | The LDO is used to filter the ripple on CPO and to set an output voltage |
| 5PA | (1) | 00 | Precanceller Disable. When held to Logic 1, the internal path from LOUT t | ||
| 5PC | (1) | Hynix HYMD564G726(L)8M-K/H/L series incorporates SPD(serial presence detec | |||
| 5PF | (6) | ST | SOT223 | Stop Condition. STOPis identified by a low to high transition of the SDA | |
| 5PG | (2) | MITSUBISHI | (LX)high-frequency | Fast recovery time characteristics Electrically isolated base plate Indu | |
| 5PI | (1) | slope going through 0 at the sampling point. This, expanded out gives u | |||
| 5PN | (2) | Gain error and gain temperature coefficient are based on the A/D c | |||
| 5PO | (1) | ||||
| 5PR | (1) | AVX | 06+ | A linear voltage regulator can be broken down into four essential buildin | |
| 5PV | (1) | 01 | n High Temperature Operation to 125˚C n IEEE 1149.1 (JTAG) Complia | ||
| 5Q0 | (10) | FSC | TO-220 | 00+ | 2) Verify that a shunt is installed on jumper JU3 (SYNC). 3) Connect a +2 |
| 5Q1 | (10) | FAIRCHILD | T03P | 02+ | ALU AND CPU REGISTERS The ALU can do an 8-bit addition subtraction logic |
| 5Q3 | (1) | ＦＡＩＲＣＨＩＬＤ | PA0~PA7 constitute an 8-bit bidirectional input/output port with S | ||
| 5R- | (1) | International Rectifiers RAD-Hard HEXFETTM technol- ogy provides high p | |||
| 5R2 | (2) | The MHF Series is designed to provide full power operation over the inpu | |||
| 5R3 | (4) | The Am29LV320M/TB is a 32 Mbit, 3.0 volt single power supply flash memo | |||
| 5R4 | (3) | VISHAY | DIP-14P | 0128+ | The QDR operation is possible by supporting DDR read and write operations |
| 5R6 | (2) | Four stereo 24-bit multi-bit sigma delta DACs are used with oversampling | |||
| 5R8 | (1) | LOGIC | LCC84 | 95+ | In contrast to the BTS 7710 G, which consists of the same chips in an P-D |
| 5RA | (2) | ULA | DIP22 | 07+ | Note 6: Care must be taken to ensure TSTC and THTC are met so input data |
| 5RG | (2) | The 5RG42 MultiKey has three, 384-bit read/write data partitions, each | |||
| 5RI | (1) | Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Inp | |||
| 5RL | (2) | N/A | SOT23 | 00+ | The information provided herein is believed to be reliable; however, C&am |
| 5-S | (1) | AMDs Flash technology combines years of Flash memory manufacturing expe | |||
| 5S0 | (9) | N/A | SAMSUNG | 04+ | The Hyundai HYM72V16M656TU6 Series are Dual In-line Memory Modules |
| 5S1 | (15) | PLCC44 | 96+ | Equivalent input rise time bandwidth assumes a first-order input response | |
| 5S2 | (10) | The DS1543 has a lithium power source that is designed to provide energy | |||
| 5S4 | (1) | N/A | N/A | The TL594 contains two error amplifiers, an on-chip adjustable oscillator | |
| 5S5 | (10) | MODULE | MODULE | 08+ | The procedures for the thermal design of the SI-7300A are as follows: ( |
| 5S7 | (4) | AD | DIP | 04+ | Uses inexpensive 4 MHz reference crystal FIN capability greater than 120 |
| 5SB | (1) | Parameter VDD to GND VOUTA, VOUTB, VBZ to GND Digital Input Voltages to | |||
| 5SC | (10) | TO-252 | This is to advise Samsung customers that in accordance with certain terms | ||
| 5SD | (18) | ABB | MODULE | Foxs current JITO®-2 line is offered in the following ranges: • | |
| 5SE | (3) | A low level at the preset (PRE) or clear (CLR) inputs sets or resets the | |||
| 5SF | (1) | BELFUSE | N/A | For packing material that is returned to us un- sorted or which we are | |
| 5SG | (12) | ABB | SOP | Available in various package configurations, these two families of dete | |
| 5SK | (3) | MPX53 series pressure sensors are available in differential and ga | |||
| 5SL | (3) | ||||
| 5SN | (24) | ABB | SOP | Power Dissipation and Thermal Characteristics D Suffix, Plastic Package | |
| 5SO | (1) | Flash Architecture Multiple 4-Mbit Partitions Dua | |||
| 5SQ | (3) | AVX | 06+ | Current-controlled Output Current Source with 4 Input Channels Low-power | |
| 5SS | (2) | This composite device allows high density mounting by unit : mm incorpor | |||
| 5ST | (3) | microprocessor. When the voltage on VSENSE rises above the COMMAND volt | |||
| 5SU | (1) | The bq29312A provides safety protection for over- charge, overload, sho | |||
| 5SW | (1) | CD4053BC is a triple 2-channel multiplexer having three separate digital | |||
| 5T0 | (1) | The IS93C56-3 is a low cost 2,048-bit, non-volatile, serial E2PROM. It i | |||
| 5T1 | (1) | The SDA 9188-3X processes both 50 Hz/625 and 60 Hz/525 line signals. The | |||
| 5T8 | (2) | 10 | RTCOH | O2 | Between t7 and t8, the converter reaches its peak current limit which i |
| 5T9 | (4) | IDT | TSSOP-7.2-48P | 6+ | On-Chip Data RAM 1 Kbyte Critical Variable Storage Single-Cycle Access |
| 5TB | (1) | QFN | 05+ | CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic ch | |
| 5TF | (1) | Choke Coil (L1). If the winding resistance of the choke coil is too high, | |||
| 5TG | (1) | The5TG0136xxxfamilyofmicroprocessor supervisory circuits monitor system | |||
| 5TH | (2) | TOSHIBA | TO-3P | The Fairchild Power Switch(FPS) product family is specially designed for | |
| 5TN | (1) | 03 | Address setup time with respect to W Chip select 1 setup time Chip sel | ||
| 5TQ | (2) | producing n sets of encrypted (ciphertext) blocks. Decryption is handled | |||
| 5TS | (1) | Drop-in replacement for IBM AT computer clock/calendar Pin compatible wi | |||
| 5TT | (2) | The ADF4360-6 is a fully integrated integer-N synthesizer and voltage co | |||
| 5TU | (5) | TOSHIBA | TO-220 | 02+ | 12bit input, Black Level, White Balance Filter size 5x5 Filter size : |
| 5TV | (1) | Note 1: Absolute Maximum Ratings are those values beyond which the life | |||
| 5U6 | (1) | REGISTERED In registered mode the output pin associated with an individu | |||
| 5UF | (1) | YAMAHA | 2002 | The melting temperature of solder is higher than the rated temper | |
| 5UL | (2) | AMD FusionE86SM partners provide an array of products designed to meet cr | |||
| 5V0 | (5) | SOT6 | 2007+ | The Am27C256 is a 256-Kbit, ultraviolet erasable pro- grammable read-on | |
| 5V4 | (2) | TOSHIBA | 05+ | Frequency converter comprise an FM transmitter with switchable output pow | |
| 5V9 | (20) | N/A | IDT | 04+ | After determining which clock edge to use, a start and stop bit, appende |
| 5VB | (2) | Ground pin. Complimentary clock of differential pair CPU outputs. These | |||
| 5VD | (1) | Shindengen | TO-263 | 08+ | Available in the Texas Instruments NanoStar and NanoFree |
| 5VE | (25) | N/A | SSOP-16 | This N-Channel MOSFET has been designed specifically to improve the ove | |
| 5VO | (1) | (14) Interrupts: 21-source, 10-vectored interrupts 1) Three prior | |||
| 5VR | (1) | Programs compiled natively on the host can run on the target. Programs n | |||
| 5VU | (3) | TOS | less than 1 ns pk-pk. If reference jitter is greater than 1 ns pk-pk, t | ||
| 5W- | (3) | 北京海声 | N/A | 20 | SD/CT: This is the shutdown pin and also the short-circuit timing pin. Pu |
| 5W0 | (1) | TOSHIBA | SMD | 03+/04+ | AC characteristics are guaranteed by design and characterization. PWC = ( |
| 5W1 | (21) | 3.3.1 Lead material and finish. Lead material shall be Kovar or Al | |||
| 5W2 | (10) | 1 ms instruction cycle time Fourteen multi-source vectored interrupts se | |||
| 5W3 | (8) | Reception output H voltageVroH Reception output L voltageVroL Transmissi | |||
| 5W4 | (5) | These 4-bit magnitude comparators perform comparison of straight binary | |||
| 5W5 | (9) | TOS | SMD | 2002 | Meets or exceeds PC133 registered DIMM specification 1.1 Spread Spectru |
| 5W6 | (6) | At the burst's end the voltage on Cs, which is on the order of a few ten | |||
| 5W7 | (2) | will vary with supply voltage, switching frequency and the external MOSFE | |||
| 5W8 | (4) | The bq2014 measures the voltage differential between the SR and VSS pins. | |||
| 5W9 | (2) | N/A | LPCC | 00 | SECTOR ERASE: As an alternative to a full chip erase, the device is organi |
| 5WF | (1) | The SN74CB3T16212 operates as a 24-bit bus switch or as a 12-bit bus exch | |||
| 5WH | (1) | 100% production tested. 100% production tested at 25C and sample tested | |||
| 5WI | (1) | N/A | QFP80 | 07+ | In addition to its masked-ROM versions, the H8/3048 Series has a ZTATT |
| 5X2 | (2) | The high efficiency of the HPR2XX Series means less internal power dissi | |||
| 5X5 | (4) | SAMPLE | QFP-32 | 99 | • JEDEC registered 1N5985 to 1N6031 • Similar to operating |
| 5X8 | (1) | CYRIX | 06+ | 240 | The A128 devices contain the following: • ARM7TDMI 16/32-Bit RISC |
| 5XM | (1) | 03 | The design has been optimized to achieve the high accuracy associ- ated | ||
| 5XT | (1) | Four independent IEEE 802.3- compliant 10BASE-T or 100BASE- TX ports in | |||
| 5XX | (2) | n/a | 03+ | Magnitude of Common Emitter Small-Signal Short-Circuit Forward Current | |
| 5Y0 | (1) | IRS | 06+ | SMD | The power supply of the device must start its ramp from 0.0 V. Functional |
| 5Y2 | (1) | • CATV Systems Operating in the 47 to 870 MHz Frequency Range • | |||
| 5Y3 | (1) | The IRU3137 controller IC is designed to provide a low cost and high perf | |||
| 5Y7 | (1) | ||||
| 5YF | (6) | † Design targets only. Not tested in production. NOTE 4: In the e | |||
| 5YH | (4) | Control Signal Input. Used to control whether LUMA or CHROMA TRS ID's ar | |||
| 5Z2 | (2) | ON | 05+ | DIP | ÈJAPower dissipation95C/W NOTES: 1. Stresses beyond those |
| 5Z3 | (1) | TOSHIBA | DIP-2 | Synchronous active low chip enable. CE1 and CE2 are used with CE2 to enab | |
| 5Z4 | (1) | System designers have the option of embedding PowerPacket-specific control | |||
| 5Z6 | (1) | N/A | TSSOP | 07+ | The internal circuit is composed of 3 stages including buffer output, wh |
| 5ZH | (2) | AVX | 06+ | INVALID OP-CODE: If an invalid op-code is received, no data will be shif | |
| 5ZI | (1) | MICROCHIP | QFN-8P小体 | 6+ | ESD damage can range from subtle performance degradation to complete devi |
| 5ZS | (1) | MICROCHIP | QFN-8P小体 | 6+ | Note 1: TA=25C unless otherwise specified. Note 2: ESD applied to input |
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