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  Mfg pack D/C Descrpion
6.0 (22)  Package drawings, standard packing quantities, thermal data, symbolizatio
6.1 (17)  EPSON N/A 08+   for this lower supply voltage operation, in which case the sensiti
6.2 (24)  KYOCERA ELCO The 6.20051E12 is stable for gains of 10 and greater and uses traditiona
6.3 (63)  N/A 1206   3.5 Marking. The part shall be marked with the PIN listed in 1.2 h
6.4 (8)  MOT 00+ PLCC52   Product reliability information can be found at http://www.fairchi
6.5 (2)  AMDs Flash technology combines years of Flash memory manufacturing exper
6.6 (5)  Margin Up: When this input is asserted to GND, the out- put voltage is in
6.7 (2)  Write Protect Pin and Write Disable Instructions of both Hardware and So
6.8 (19)  NATIONAL 2008 Note 4: Electrical Table values apply only for factory testing conditions
6.9 (2)  Using the first option, the user can program the part on the candy board
6.C (1)  An electrical circuit model is shown in Figure 1-4. The coupling capacit
6-0 (11)  Microchip received QS-9000 quality system certification for its worldwid
60- (16)  HARTING 01+ See SOA curves or consult factory for appropriate derating. The set-poin
60. (5)  90 COMPLETE TELETEXT DECODER INCLUD- ING ON-CHIP 8 PAGES MEMORY, REDUC- I
600 (185)  XP 06+ 500 The MC68EC000 brings the performance level of the M68000 Family to cost l
601 (100)  MSOP 02+ The SMSC 4-port hub controller supports the Session Request Protocol (SRP)
602 (119)  Infineon 03/04+ SOP16 The Simtek STK14C88-3 is a fast static RAM with a nonvolatile element in
603 (52)  IC 集成电路 CAT25C128VI-TE13 Microchip received QS-9000 quality system certification for its worldwi
604 (58)  TRIQUINT QFN-48 The equalizer improves the cable-induced jitter; the data slicer restor
605 (47)  BGA The 605089TWN offers comprehensive filtering for TV, set top box o
606 (62)  ELMOS SMD 05+ The accuracy of this derivation depends on how closely the impedance of t
607 (44)  SOP-16 98+ RC units in standard design (lead length 30 mm) and with L < 24 mm and
608 (52)  S/PHI CDIP 91 NOTES: A. CL includes probe and test-fixture capacitance.   B. Phas
609 (200)  LOGIC QFP 07+ • JEDEC registered 1N746 thru 1N759A and 1N4370   thru 1N4372
60A (9)  Notes: (1) The Inhibit (pin 3) has an internal pull-up, which if left ope
60B (1)  DESCRIPTION Transil diode arrays provide high overvoltage pro- tection
60C (24)  97 Parameter Supply Voltages   Positive Supply Voltage (VCC to GND) &
60D (3)  JRC 1250 Current sensing is accomplished by reading the voltage developed across
60E (22)  IR TO-247 08+ NOTES: 1. Industrial temperature range product for the 15ns speed grade i
60F (1)  98 W83877TF is made to fully comply with MicrosoftTM PC97 Hardware Design Gui
60G (3)  LATTICE PLCC The criterion above is sharper than the standard (incorrect) time-domain
60H (17)  N/A BGA Rating to 200V VBR For surface mounted applications Reliable low cost co
60J (1)  The SG117A Series are 3-terminal positive adjustable voltage regulators
60K (9)  JRC TO-3P 04+ The AD7877 is a 12-bit successive approximation ADC with a synchronous s
60L (5)  APM TO-252 05+ The reset threshold is either the internal defined VRT voltage (typical 4
60M (17)  LT Tutte le informazioni contenute sul presente manuale sono state accuratam
60N (18)  100 TO262 1. Use this component within operating temperature range. It might not be
60P (6)  ST SMD 02+ Melexis Inc. reserves the right to make changes without further notice to
60Q (5)  TAIWEN TO-252 02+ FSD273 is a band selected version of the ZMDC953. Product is supplied in
60R (29)  LITTLEFUSE 08+ 3000 :KHQ D SURGXFW KDV EHHQ LQ SURGXFWLRQ IRU D SHULRG RI WLPH VXFK WKDW QR F
60S (12)  IR DO-5 04 The Fairchild Switch FST34170 is a 17-bit to 34-bit high- speed CMOS TT
60T (3)  WARNING: The recommended operating conditions are required in order to en
60W (5)  IR 00+ TV SVHS OUTPUT MODE The device supports SVHS video format. The SVHS mode
60X (1)  SOP16S 2007+ The Intel 87C54 is a single-chip control-oriented microcontroller which i
60Z (5)  SPRAGUE DIP-14 08+ .040 x .040 inch .001 inch. .010 .0015 inch. Aluminum 15,000Å mi
6-1 (203)  SN 06+ 500 12. Measured by the voltage drop between A and B pins at the indicated cu
61- (7)  EVERLIGHT ORG PACKING 08+ The CY7C53120L8/3150L supports all the functionality of the 5V CY7C531x0
610 (169)  IC 集成电路 CAT810LEUR-T External Access enable: EA must be externally held low to enable the dev
611 (170)  AMP na
612 (119)  TI   When the Output Enable Input (E0) is HIGH, the outputs are forced
613 (92)  HAR CDIP24宽 NOTES: 1. Minimums are guaranteed but not production tested. 2. This pa
614 (147)  EITREND 01+ In the HEDS-6540 / HEDL-6540 the output of the comparator for the ind
615 (78)  MOTO SMD SMD When the CMI/ECL pin is low the chip is in ECL mode and a fiber optics tr
616 (101)  SYMBIOS QFP128   This series employs the Schottky Barrier principle in a large area
617 (92)  AMP/TYCO N/A Input/Output Capacitors: The PT6340 regulator series requires a 100µ
618 (58)  • Plastic package has Underwriters Laboratory   Flammability
619 (69)  PHILIPS (LX)high-frequency The MacroDens™ PKF 5000 I series true component level on-board DC/D
61A (7)  600 TEVES 99+ It contains two groups of 2 bit latches controlled by an enable input (
61B (2)  The AIC1722A is a 3-pin low dropout linear regulator. The superior charac
61C (40)  TOREX 05+ The CS4271s wide dynamic range, negligible distor- tion, and low noise ma
61D (1) 
61E (1)  TOKO 00+ The LP2950 and LP2951 are micropower voltage regulators with very low q
61F (15)  SOP-16 As with most timing specifications, phase noise measurements have issues
61G (2)  LATTICE/AMD PLCC The audio DAC uses Micronas proprietary multibit sigma-delta technique.
61K (1)  01 The shaft locking device consists of a tapered nut tightening a slotted
61L (39)  MOT 1728
61M (13)  SOP28 For output ports when in "ON" condition for reflective switch.
61N (2)  2000 AGILENT 03+ Note 2: At elevated temperatures, device power dissipation must be derate
61P (1)  The MPC860 Quad Integrated Communications Controller (PowerQUICC™)
61R (2)  NEC N/A Note 1: Absolute Maximum Ratings are those values beyond which the life
61S (2)  ISSI 9902+ The LT®1568 is an easy-to-use, active-RC filter building block with r
61T (2)  When the voltage drop to the positive input of the comparator (i.e. VB) is
61X (1)  N/A N/A N/A By combining a conventional thin-film R-2R ladder DAC, a digital offset
61Z (6)  FIL-MAG 2007 The ABT162244 contains sixteen non-inverting buffers with 3-STATE output
6-2 (4)  上海上一 n/a Stability The IRU1010 requires the use of an output capacitor as part of
62- (42)  WDC O7+ Interrupt Request (Open Drain Output): an output indicating an unmasked H
62. (6)  Finder RELAY 06+ ¡The circuit application examples in this publication are provided
620 (132)  IC 集成电路 CD4016BCM The EC4558 consists of two high performance opera- tional amplifiers. T
621 (62)  ST QFP The DAC8580 is a 16-bit, high-speed, low-noise, voltage-output DAC desi
622 (162)  GENNUM QFN 04 The response is thus a logarithmic curve; each doubling of Cs increases
623 (67)  TOSHIBA SOP ISSI reserves the right to make changes to its products at any time witho
624 (46)  IC 集成电路 CD4512BE 868MHz, 902-928MHz Bands OOK and FSK Demodulation Low Current Consump
625 (69)  IC 集成电路 CD4541BE BRAKE - is a pin for commanding the output bridge into a motor BRAKE mode
626 (114)  HY dip/sop 0728vgc+ 3.5 nV//Hz Unity-Gain Bandwidth . . . 10 MHz Typ Common-Mode Rejection R
627 (47)  SMD-16 05+ Note:  6. Full Device AC operation requires linear VCC ramp from VD
628 (167)  HIT 00+ Drain-Source Voltage  Gate-to-Source Voltage Continuous Drain Cur
629 (38)  MITSUBISHI stock
62A (4)  1000 TI Smoke Detection Circuit C The smoke comparator compares the ionization cha
62C (21)  ISSI 08+ 233 Kansas St., El Segundo, California 90245 U.S.A. Tel: (310) 322 3331.
62E (4)  ** BGA 00+   Although the Motorola accelerometers contain internal 2kV ESD pro
62F (3)  89 PANASONIC ∗ In order to measure at Ta Tj (pulse measurement), fluctuations in
62G (278)  77 PANASONIC The above calculation is conservative: with VCC = 2.7V and the three tran
62H (5)  ATMEL 06+ QFP * Low Forward Voltage. * Low Switching noise. * High Current Capacity *
62I (2)   DVDD is the power supply for the I/O pins while CVDD is the power s
62J (1)  † Stresses beyond those listed under absolute maximum ratings may c
62K (1)  HYUNDA TSOP 2000  with a single bar completely filling the primary hole. •In or
62L (25)  ISSI 08+ While line regulation is specified down to 13 volts, the typical AD581 w
62M (4)  TOSHIBA TSSOP 07+ Flammability Classification 94V-0 Dual rectifier construction, positive
62N (3)  MOT PLCC-28 Selects Burst Order. When tied to GND selects linear burst sequence. When
62O (5)  AVX 06+ Electrical Characteristics (Notes 2, 7) Limits in standard typeface are f
62P (74)  ST SOP † Package drawings, standard packing quantities, thermal data, symb
62R (3)  ST 00+ The functional block of the MX98905 consists of the integration of the
62S (9)  ISSI BGA0608 02+ The FCT373T and FCT573T consist of eight latches with three-state outpu
62T (16)  N/A N/A N/A ➀ Typical at TA = +25C under nominal line voltage and balanced &qu
62U (3)  N/A 99 Not all applications must (or can be) designed for short- circuit protec
62V (2)  NEC SOT89 5.1 Module Interface Connectors 5.2 Module Connector Pin Configuration 5
62W (11)  HIT  High-speed access time: 8, 10, 12, and 15 ns  CMOS low power
62X (1)  OKI DIP18 00+ µ PD789167 with improved A/D µ PD789104A with improved time
62Z (1)  Multi-Protocol Serial Communications Controller Full IrDA v1.1 Implement
6-3 (9)  • BuiltCin interface for PC/XT™/AT® or compatible   b
63- (9)  TOKO 4M-560 Endurance   93AA461M1M25C, Vcc = 5.0V, Block Mode   93AA56/66
63. (1)  n Space saving SOT23 or SC70 5-lead surface mount   package n Ultr
630 (120)  ST PLCC 1 Dead-Time Delay Programming Input. Connect a resistor from DLY to GND to
631 (47)  IC 集成电路 CLC016AJQ/NOPB   FEATURES 8-18V Supply Operating Range 16 MHz Maximum Oscillator
632 (57)  IC 集成电路 CLRC63201T/0FE,112 Conforms to POCSAG standard for pagers 512 or 1200 bps signal speed Sup
633 (48)  96 QFP There are two kinds of logic blocks, the Programmable Functional Unit (PF
634 (39)  MMI CDIP24 The RESET (SVS, POR, or power on reset) output of the TPS752xxQ initiates
635 (52)  MMI DIP 06+ The Fairchild Switch FST32211 provides up to 48-bits of high-speed CMOS
636 (110)  TOKO 6M-100 CAPACITOR SELECTION   To minimize ripple voltage, output capacitors
637 (46)  TYO 0 4 Internally current controlled to cover extended range of 70 cm. Cur
638 (34)  MMI DIP 84 read data from the device will result in I/O6 toggling between one and
639 (22)  IC 集成电路 CS03-088 Clock generation Pulse dialing support Overload detection Low-profile 1
63A (15)  HITACHI DIP 07+/08+ Replace any reference to Flash Interface Unit with Flash Module, added not
63B (12)  HIT   1.1 Scope. This specification covers the performance requirements
63C (13)  QFP20 NOTES: (1) Spurious-Free Dynamic Range refers to the magnitude of the lar
63E (1)  ST SDIP 0
63F (2)  IBM SOJ28 Footnotes: 1) Standard frequency stability (20,25,50ppm & others ava
63G (3)  TOS QFP-80
63H (3)  142 PHILIPS 97+ • 2.5V 5% Power Supply. • Byte Writable Function. • En
63J (1) 
63K (1)  This high performance LED has been designed for Datacom, Telecom or G
63L (9)  HIT QFP 07+/08+   The 33394 is a multiCoutput power supply integrated circuit with h
63M (28)  2007   The NSE with a single QDR™ (Quad Data Rate) interface is int
63P (19)  SP 05/06+ Notes: 1. All typical values are at 25C and with a 3.3V supply 2. tsk(p
63R (11)  MMI 84+ DIP24陶瓷 The CD4020B and CD4040B types are supplied in 16-lead hermetic dual-in-li
63S (59)  MMI   Operating temperature range is: C40C to +85C.   Guaranteed b
63T (7)  ST QFP 07+ Data is written through COEF_DATA (7-0) and its destination is determined
63U (4)  MOT   Software and Register Compatible with   SMSC's Proprietary
63V (11)  eight CAT24FC02 may be individually addressed by the system. The last b
63W (2)  Absolute maximum ratings indicate sustained limits beyond which damage to
63X (12)  SP 05/06+ ITU-T and ANSI Tone Detection per channel Per channel Power Down Functi
63Y (23)  RUBYCON 0505 6,345 Port 1 is an 8-bit bi-directional I/O port. Port pins P1.2 to P1.7 provid
63Z (3)  6. Solder Gap Identification (See Figure 2): Each solder gaps respective
6-4 (1)  SH Notes: 1. For Max. or Min. conditions, use appropriate value specified un
64- (14)  IOR D-PAK 06+ The manufacturer and device codes may also be read via the command registe
64. (5)  EPSON DIP-4 08+ Detection current: 10mA Excluding contact bounce time Half-wave pulse
640 (517)  AMP n/a 00   PIN DESCRIPTION The PWM output of the switching controller. This p
641 (244)  ST PLCC 1 In most applications, the chip address inputs A0, A1, and A2 are hard-w
642 (41)  SOP-8 The ISD1810 devices offer single-chip solutions with 8 to 16 seconds of r
643 (233)  N/A QFP 07+   Capacitor mounted close to the power module helps ensure stabilit
644 (120)  IC 集成电路 CS5532-ASZ The EL5172 and EL5372 are single and triple high bandwidth amplifiers des
645 (49)  AMP 06+ The LM2471 is an integrated high voltage CRT driver circuit designed fo
646 (146)  DELCO 03/04+ High data rate, 5 MHz typical (NRZ) Free from latch up and oscilliation
647 (30)  N/A DIP 07+ PA0~PA7 constitute an 8-bit bidirectional input/output port with Schmitt
648 (23)  INTERSIL SOP-20P 07+ International Rectifiers RADHard HEXFET® technol- ogy provides high
649 (49)  PHILIPS 2008 This device operates from a single 3.3-V supply. The device has integrate
64A (11)  PHILIPS QFP 99+ organized as 525,288 words by 16 bits. It is fabricated using ISSI's hi
64B (7)  SOP 96 In addition to the H-LUT input control multiplexers (shown in box "
64C (10)  QFP44 During the pre-equalizing, vertical sync and post equalizing periods, com
64D (3)  MOT PLCC28 03/+04+ Case: JEDEC TO-220AC, ITO-220AC & TO-263AB molded plastic body Term
64F (67)  2007 WP#/ACC input accelerates programming time   (when high voltage is
64G (12)  IBM QFP-48 Junction Temperature Calculation: TJ = TA + (PD x JA). JA assume device i
64H (7)  POWER MOS TECHNOLOGY 2A peak rating HIGH GAIN BANDWIDTH PRODUCT 150MH
64I (2)  04+ The SRC input of the bq2060 measures battery charge and discharge current
64K (4)  MOSYS 06+ 500 When 16/68# pin is at logic 1 for Intel bus interface, this output become
64L (32)  CSI O7+ The CD54AC161 and CD74AC161 devices are 4-bit binary counters. These sync
64M (4)  ? LCC44 1775.70 1775.70 1775.70 1775.70 1775.70 1775.70 1775.70 1775.70 14
64P (11)  TI QFN 5) Next, a heat sink with lower sa than the one calcu-   lated in S
64R (1)  TI QFN 05+ The MAX3060E features slew-rate-limited drivers that minimize EMI and red
64S (3)  INTERSIL • For indirect jumps and calls that use a 16-bit DAG   address
64T (5)    Ratiometricity simply means the output offset voltage and sensiti
64W (37)  SP 05/06+ There are 4 input signals for the OSD Processor, which are serial data (SD
64X (14)  SP 05/06+   The 64X203 2.5V differential (DDR) clock buffer is a user-selectab
64Y (13)  SP 05/06+ Min/Max limits are guaranteed by design, test or statistical analysis. T
64Z (10)  SP 05/06+ Frequency signal inputs for PFD. The reference frequency signal (fREF-IN)
6-5 (44)  2008 Edition 03.98 Published by Siemens AG, HL SP, Balanstraße 73, 81
65- (10)  MOTOROLA 2008 • Precision Output Voltage Regulation   - Differential Remote
65. (2)  Stresses beyond those listed under "Absolute Maximum Ratings" ma
650 (311)  DIP40 2007+ Inputs Are TTL-Voltage Compatible Internal Look-Ahead for Fast Counting
651 (66)  IC 集成电路 CY62137CV30LL-70BAIT
652 (89)  SOP-3.9-8P 6+ The TDA8931 is a switching power stage for high efficiency class-D
653 (31)  DIP-40P 86+ 1~4 Cell Alkaline Battery Operating Range Output Voltage Range: 2.5V~5.0
654 (43)  CABLETRON QFP 03/+04+ L - Low-Terminal Potentiometer. This is the low terminal of the potentiom
655 (77)  IC 集成电路 CY7C281A-30PC The hardware data protection measures include a low VCC detector automati
656 (89)  AT&T PLCC 05+ The LVTH18512 and LVTH182512 scan test devices with 18-bit universal bus
657 (43)  IC 集成电路 CY7C64713-56LFXC The base timer is an 8-bit counter with a 1MHz clock source. The base time
658 (143)  HITACHI 94+ SOP-7.2-32P † Not more than one output should be tested at a time, and the dura
659 (24)  N/A QFP RTCF: Real Time Clock Fail BitVolatile This bit is set to a 1 after a to
65A (17)  DIP-8 En1 (Bump A2): Enable pin for the internal PMOS FET switch (Figure 2: P1
65B (2)  MOT BGA The Microchip name and logo, the Microchip logo, PIC, PICmicro, PICMASTE
65C (14)  杂厂 DIP DIP Note: Stresses greater than those listed under MAXIMUM RAT- INGS may c
65D (2)  Infineon QFN   Experiments have shown that the MOSFET drain voltage will ring fo
65E (1)  SOP16 Designing both unmanaged and managed solutions is straightforward. The c
65F (2)  Lattice PBGA256 2007+ See Power Dissipation in the Applications section for more information re
65G (1)  LATTICE/AMD PLCC addressed to this node is received, or conditionally when a PHY interrupt
65H (5)  TI DIP8 08+ Both the differential data (DIN, DINQ) and clock inputs (CKIN, CKINQ) are
65J (1)  All of the register outputs are set to a low level during power-up. Extra
65L (20)  TI 2008 HY57V28420HC(L)T is offering fully synchronous operation referenced to a
65M (2)  N/A N/A 07+   Figure 3 illustrates the differential/gauge die in the basic chip
65N (4)  ON 263 07+ The 65N02R contains sixteen non-inverting buffers with 3-STATE outputs.
65P (14)  SST SOP42 0206162-A The 256K bytes of Flash program memory are used to store the application
65R (3)  S/PHI DIP 07+
65S (5)  Suhner N/A 2   The marketing status values are defined as follows: ACTIVE: Produ
65T (3)  code to stay in the device while data in the rest of the device is upda
65U (1)  NSC SOP- 8 The CY7C024V/025V/026V and CY7C0241V/0251V/036V are low-power CMOS 4K,
65V (7)  HIT INVALID OP-CODE: If an invalid op-code is received, no data will be shift
65W (1)  HIT 95+ TSOP/32   These Hall-effect switches are designed for magnetic actuation usi
65X (5)  IBM 01+ The SN65176B and SN75176B differential bus transceivers are integrated ci
65Z (2)  Fil-Mag DIP8 With FSK = High and ASK = Low and ENABLE = open or High, the PLL and the
6-6 (10)    Each channel consists of a TTL/CMOS-compatible logic input gated
66- (10)  CLEARLOGIC O7+ Enables the associated DDR2 SDRAM command decoder when low and disables th
66. (5)  EPSON DIP-4 2004 The Hynix HYM71V16655AT8 Series are 16Mx64bits Synchronous DRAM Modules.
660 (89)  AMKOR SSOP 07+   For proper operation, the current limit resistor (RCL) must be co
661 (85)  Zilog DIP 07+ NOTES:   1. Dimensions are in inches.   2. Metric equivalents
662 (45)  IC 集成电路 DAC121S101CIMM/NOPB Short lead time, since the P2ROM is programmed at the   final stage
663 (63)  DELCO DIP24 98+ Compatible with SPI Bus Serial Interface (Positive Clock SPI Modes) Si
664 (77)  ICS TSSOP-3.9-16P 6+ This pin can be connected to either VSS, VCC or left floating. An
665 (116)  IC 集成电路 DCP010505BP The ADSP-21365/6 contains three megabits of internal SRAM and four megab
666 (62)  00 The nominal value of the RF choke, L1 is 100 nH. At frequencies below 100
667 (40)  19 8-A Rated Output Current Replaces PT6500 Series High Efficiency (91% for
668 (47)  XICOR O7+ Data flow is controlled by the direction-control (DIR) and output-enable
669 (58)  FCI 06+ 17
66A (5)  SOP28   Designed for PCN and PCS base station applications with frequencie
66C (6)  IOR SOP-8 06+ 2.3 External Special Function Registers (XFR) The XFR is a group of regis
66D (2)  SOP16 The A-to-B enable (CEAB) input must be low in order to enter data from A
66E (2)  "Advance" product information describes products that are in de
66F (7)  A1RPAX DIP-4 08+ Absolute Maximum Ratings (If not specified Tl=25)   ItemSymbolCond
66G (2)  Yes. The 8038 is essentially resistive. The power dissipation is then E2
66J (3)  SOP20 06+ Triple-channel video amplifier Supply voltage up to 115 V 80V Output
66K (2)  Supports a 33-MHz, 64-bit PCI host bus interface with a 264 MB/sec maxim
66L (4)  Continuous Drain Current, V GS @ 4.5V Continuous Drain Current, V GS @
66M (1)  Circuit Breaker Sense Input: The current-limit threshold is set by connec
66N (3)  ZXM SOP-3.9-8P 6+ Power Thyristor/Diode Module PK110F series are designed for various rect
66P (19)  ZXM SOP-3.9-8P 6+ • Digital Audio Interface that includes two precision clock  
66R (1)  The CY7C436X3AV is a synchronous (clocked) FIFO, meaning each port empl
66S (4)  A linear voltage regulator can be broken down into four essential buildin
66U (1)  The HYM72V32M656B(L)T6 Series are Dual In-line Memory Modules suitable for
66W (4)  more than 99% when deselected (CE HIGH or both BLE and BHE are HIGH). The
66X (1)  The IS25C64-2 is a 1.8V (1.8V-5.5V) 64K-bit (8192x8) electrically Erasa
66Z (5)  SPRAGUE DIP DIP SALES AND SERVICE   Honeywell serves its customers through a world-
6-7 (6)  SONS Vdd=2.3V~2.7V, TA = -25C to 85C(E) / -40C to 85C(I), unless otherwise spec
67- (27)  LUCENT BGA 01+ W83877TF is made to fully comply with MicrosoftTM PC97 Hardware Design Gui
67. (1) 
670 (94)  ICS 04+ SOP Absolute Maximum Ratings (If not specified Tl=25)   ItemSymbolCond
671 (141)  IC 集成电路 DP2-5G52-M3 Multiply Accumulate Unit for fast signed multiply or mul- tiply-accumula
672 (131)  N/A MOLEX 05+ The ADC12DL065 is a dual, low power monolithic CMOS analog-to-digital c
673 (48)  QFP64 Conditions Measured from input terminals to output terminals, shortest
674 (116)  N/A MOLEX 05+ This flip-flop has independent data, preset, clear, and clock inputs and
675 (34)  IC 集成电路 DS1302S+ The ADC channel is a chain of programmable amplifier, band-pass filter, si
676 (18)  N/A MOLEX 05+ Figure 12 is a block diagram of a system that uses a passive or losser t
677 (24)  QFP208 When executing a jump instruction, conditional skip ex- ecution, loading
678 (37)  N/A SOP8 N/A If there is one single characteristic that justifies the existence of CMO
679 (83)  IC 集成电路 DS1805Z-010 The BT1074Bi is a BiCMOS monolithic integrated RF transceiver. In addition
67A (6)  MOT 99 Stanford Microdevices 67A07 is a high performance cascadeable 50-ohm amp
67B (2)  MITSUMI 06+ and NanoFree Packages Supports 5-V VCC Operation Inputs Accept V
67C (35)  DIP   The information in this book has been carefully reviewed and is be
67E (2)  SOP16 The dc specifications refer to the condition where the digital outputs ar
67F (34)  AIRPAX SALE--STOCK!! 08+ Notes:  5. Test conditions assume signal transition time of 5 ns or
67G (1)  Note 6: The fOP frequency specification specifies a minimum clock period
67L (42)  AIRPAX TO-220 06+ Features • IXYS advanced low Qg process • Low gate charge an
67M (3)  SOP16 The blocks in the memory are asymmetrically ar- ranged, see Tables 3 an
67N (3)  NEC SSOP20 (1) Offset error is the deviation of the average code from mid-code for a
67P (13)    Designed for WCCDMA base station applications with frequencies fro
67S (3)  N/A N/A N/A Note:  6. Full Device AC operation requires linear VCC ramp from V
67W (28)  BI 03+ Note 1: Dropout is caused by either minimum control voltage (VCTRL) or mi
67X (18)  These pins switch the ICs operating state from active (S0, S1/S2) to S3 a
67Y (17)  The bq2050H Lithium Ion Power Gauge™ IC is intended for battery- p
67Z (9)   Active: 10 mW/MHz, (typ)  Standby: 36 µW (max) On
6-8 (11)  Derate linearly above 70oC free air temperature at a rate of 0.8 mA/C. D
68- (4)  MITSUMI 05+   Parameter Remote On/Off Signal Interface  (VI = 0 V to 75
68. (6)  FEATURES High Slew Rate: 10 V/ s Min Fast Settling Time: 0.9 s to 0.1%
68/ (1)  The TPS773xx or TPS774xx is offered in 1.5-V, 1.6 V (TPS77316 only), 1.8-
680 (203)  AMI QFP100 Glueless Interface Between the Peripheral Component Interconnect (PCI) Bu
681 (79)  MOLEX NA   C System Speeds > 100 MHz   C Flip-flop Toggle Rates >
682 (46)  ADI DIP 2000 1. These values of VI are used to test DC electrical characteristics only
683 (64)  DPTV QFP 0318+ WRITE PROTECT: The write protect pin (WP) will allow normal read/write op
684 (56)  IC 集成电路 DS3487M/NOPB The C6203 device program memory consists of two blocks, with a 256K-byte
685 (57)  STM 6750 This pin is a CMOS output structure which by receiving the HKS and HFO s
686 (69)  BGA 03+ Notes: 1. TC is defined as case temperature, the temperature of the under
687 (32)  MOTO CDIP40 00+ As shown in the sample calibration curve shown below (Figure 3), the mea
688 (31)  BI O7+ No external component required. Programmable output current control by E
689 (18)  IC 集成电路 DS80C320QCG+ The LNP has differential input and output capability and is strappable
68A (9)  MOT DIP 2001 If the auto-increment flag is set, the three low order bits of the Contr
68B (18)  F 04+ Note 1: Absolute maximum ratings are DC values beyond which the device m
68C (19)  EXAR PLCC44 16-Bit Output For Use in Microprocessor-Based Systems Very High-Speed SN
68D (1)  SOP16 When using the board as a stand alone unit or with the HSC- INTERFACE BO
68E (5)  MOT Widebus+ Family DOC Circuitry Dynamically Changes Output
68F (1)  2500 MOT Output clock. This pin is selectable under processor control to be either
68H (83)  PLCC Clock 155.52MHz (LVDS output). Differential outputs for the 155.52 MHz cl
68J (2)  ON Semiconductor andare trademarks of Semiconductor Components Industries
68K (2)  System address / data bus low byte. These lines make up the least signif
68L (3)  MOT • ispDesignEXPERT™ C LOGIC COMPILER AND COM-   PLETE ISP
68M (6)  SOP16 The MAX4729/MAX4730 are available in small 6-pin SC70 and 6-pin µDF
68N (8)  The HCPL-7850/7851 is an isolation amplifier that provides accurate,
68P (7)  PARAMETER Error Comparator Section Input Bias Current Input Offset Volt
68S (1)  MOT Note 1: Specifications at -40C are guaranteed by design and not production
68T (2)  N/A SOP- 8 Signal input pin. An internal matching circuit, configured with resisto
68U (19)  KEMET The device is organized as a dual 12-bit bus switch with separate output
68V (6)  NEC SOD123 • Pin- and function-compatible with CY7C1020V33 • High speed
68W (13)  BOU96 07+ Left/right simultaneous volume or channel 1 volume is controlled by this
68X (48)  SOP16S 2007+   Unless otherwise noted CC=18pF, RC=2.2KΩ, VCC= 150VDC and sp
6-9 (2)  • SuperFAST HIGH DENSITY IN-SYSTEM   PROGRAMMABLE LOGIC  
69- (10)  18 MICROCHIP 99+ The 69-0750 is a non-inverting 8-bit Bidirectional Transceiver designed
69/ (1)  FEATURES AD5305: 4 Buffered 8-Bit DACs in 10-Lead MSOP   A Version
690 (63)  IC 集成电路 DS8922AM IF-Compensation Demodulator Chrominance Filter Frequency Demodulator
691 (84)  N/A SOP- 8 Note: Some revisions of this device may incorporate deviations from publi
692 (38)  TOK PLCC28 In North America, Caller ID uses the voiceband data transmission interfac
693 (32)  DPTV QFP 0334+ The bq2014 Gas Gauge IC is in- tended for battery-pack or in-system inst
694 (47)  DIP   This 16-bit bus transceiver is built using advanced dual metal CMO
695 (21)  MIC 05+ SMD 8042 Software Compatible 8 Bit Microcomputer 2k Bytes of Program ROM 25
696 (29)  IC 集成电路 DS90LV032ATMX/NOPB Notes:   1. Dimensions are in inches.   2. Metric equivalents
697 (10)  N/A QFP 07+ • XACT Development System runs on 386/486/   Pentium-type PC,
698 (77)  BI DIP-16 08+ Memory encompasses 16 KB of Flash for program storage, 256 bytes of SRAM
699 (50)  BI O7+ These N-Channel enhancement mode power field effect transistors are produ
69A (7)  SOP16 OUTPUT DRIVE ENABLE (ODE)   The ODE pin is the master output three-s
69C (2)  97 SSOP The maximum graphics resolution supported is 1280 x 1024 in 16 Million
69D (4)  MOT The 69D-12A/69D-12 contains a micropower bandgap reference voltage sourc
69E (3)  SOP28 When HIGH, this input is used to advance the internal burst counter, contr
69F (2)  SOP16 2. R2 (100 Ohm) and C8 (10 nF) can be included if further power supply de
69G (3)  PHIL 05+ The bq2083−V1P2 contains 512 bytes of internal data flash memory,
69J (1)  Ground Bit 1, Most Significant Bit (MSB) Bit 2 Bit 3 Bit 4 Bit 5 Bi
69L (2)  51 MX 04+ • Low VCE (on) Non Punch Through IGBT Technology. • Low Diod
69M (1)  DIP8 Output Voltage The fixed voltage LDO voltage regulators are simple to us
69N (2)  PH TO-220 This data sheet has been carefully CORPORATION • 5980 NORTH SHANN
69P (1)  TO263 Typical Data is at TA = +25C and VCC = 5 V and is for design information o
69S (1)  LEACH (LX)high-frequency The ZiLOG ZHX1010 SIR transceiver provides an efficient implementation of
69X (2)  2. R2 (100 Ohm) and C8 (10 nF) can be included if further power supply de
6A0 (13)  TI QFN64 08+PB Wake-up Function for a Microcontroller with Preamble Detection 1 mVrms Se
6A1 (21)  MIC R-6 2008+ The FAN53168 features a high bandwidth control loop to provide optimal r
6A2 (13)  HIT DO-35 05+ its simplicity, however, this method will fail if the FPGA receives an
6A3 (2)  HIT DO-35 05+ The device is entirely command set compatible with the JEDEC single-powe
6A4 (6)  台湾 When using the FOD2741, power supply designers can reduce the component c
6A6 (1)  DIODES 0401 (1) An export permit needs to be obtained from the competent authorities
6A8 (2)  GAT: Gate drive for an external N-channel protection power MOSFET. When e
6A9 (2)  Channel 0 Blue (U) Video Input. Input for Blue component video channel o
6AA (6)  N/A N/A N/A In addition, the devices are static designs which offer a wide range of
6AB (6)  ST 05+ SOP-20 Zener Voltage Range − 3.3 V to 200 V ESD Rating of Class 3 (>16
6AC (3)  NEC 68 The VCO requires one external capacitor C1 (between C1A and C1B) and one
6AD (1)  SOP16 Reading lights (car, bus, aircraft) Portable (flashlight, bicycle) Mini
6AE (8)  The TLC2272/4 also makes great upgrades to the TLC272/4 or TS272/4 in sta
6AF (1)  SOP16 Data flow from A to Y is controlled by the output-enable (OE) input. Th
6AG (1)  The 6AGK1C1631 integrates six deserializer devices into a single chip.
6AH (2)  ST An additional improvement of the driving capability may be achieved by u
6AI (3)  ST SOP 07+ Terminate outputs with 50Ω to VCC - 2V or use an equiv- alent Theve
6AK (2)  TOSHIBA 05+ Operating Voltage Range of 4.5 V to 5.5 V High-Current 3-State Outputs Dr
6AL (2) 
6AM (7)  01 The digital serial interface can be configured for 3-wire operation and
6AO (1)  ST SOP28 Internal cold-junction compensation largely corrects errors arising from
6AP (5)  N/A Note 7: Switch on resistance is calculated by dividing VIN to SW voltage
6AS (2)  Delay from CKI Rising Edge to ALE Rising Edge Delay from CKI Rising Edge
6AV (1)  not used, reserved; always write a zero to this bit setting this bit prev
6AW (8)  DIP8 DESCRIPTION The LD1085 is a LOW DROP Voltage Regulator able to provide
6AY (1)  Device bus operations are initiated through the internal command regist
6B- (2)  FH 05+ Case: JEDEC DO-204AC molded plastic over a passivated junction Terminal
6B0 (1)  NSC O7+ International standard package miniBLOC (ISOTOP compatible) Isolation
6B1 (7)  HIT DO-35 05+ The BAfffLBSG (the fff indicates the output voltage value) is a low-satur
6B2 (10)  718 单排 07 Notes: 1. See test circuit and waveforms. 2. This parameter is guarantee
6B4 (3)  Toshiba 07+/08+ The GS4882 and GS4982 feature an internal color burst filter for minimiza
6B5 (5)  ADI 07+ These 8-bit flip-flops feature 3-state outputs designed specifically fo
6B6 (1)  NEC 四脚铁帽 08+ The HT48CA0 is an 8-bit high performance RISC-like microcontroller spec
6BA (1)  SOP16
6BB (2)  AMI PLCC 9406   This device contains protection circuitry to guard against damag
6BC (13)  SOP24 Unless otherwise specified, the following specifications apply over the o
6BD (8)  SOP16 The TLC5941 is a 16-channel, constant-current sink, LED driver. Each ch
6BE (1)  SOP16 Connect this pin to the 3V3DUAL output. In sleep states, the voltage at t
6BG (1)   Supports Provisions of IEEE 1394-1995 Standard for High Performance
6BI (1)  1735 Data flow from A to Y is controlled by the output-enable (OE) input. Th
6BK (1)  Information furnished is believed to be accurate and reliable. However, S
6BM (2)  100 天龙伟业 靳先生 BANDWIDTH: 20MHz SLEW RATE: 30V/µs FAST 16-BIT SETTLING TIME LOW
6BP (8)  ADI 07+ The device operates from a wide supply range from 2.35 V to 5.25 V. The l
6BT (1)  SMD-8 04 05 The AD5379 contains 40, 14-bit DACs in one CSPBGA package. The AD5379 pr
6C- (1)  At the output of all CCD's, transported pixel charge (electrons) is conv
6C0 (2)  The internal VCO is based on the TLC2932 and TLC2933s ring oscillator. It
6C1 (7)  HIT DO-35 05+ A common ground is required between the input and the output voltages.
6C2 (3)  HIT DO-35 05+   Full-step (2 phase) and half-step operation are externally selecta
6C3 (1)  • 0.23 µm Process Technology • Single 3.0 V read, progr
6C4 (2)  The T8xC51SND1 provides all necessary features for man machine interface
6C8 (1)  Senses motion of ring magnet targets Integrated filter capacitor
6C9 (1)   V ds,clamp Drain to source clamp voltage R ds(on) Drain to source
6CA (2) 
6CC (1)  This specification is established by characterization and not 100% tested.
6CD (5)  SOP16 Performance   Latest processor technology,   Intel® Penti
6CE (8)  SOP16 NOTES:   1. Dimensions are in inches.   2. Metric equivalents
6CF (1)  The VSP2272 device is a complete mixed-signal processing IC for digital
6CH (2)  Sop8 Applications for the MCP300X family include data acquisition, instrumenta
6CN (1)  BUFFALO QFP 00+ 3.3V Operation with 5V Tolerant Buffers ACPI 1.0b/2.0 and PC99a/PC2001 Co
6CP (1)  Maximum ratings are those values beyond which device damage can occur. Ma
6CV (1)  SANYO 1823 An on-chip oscillator eliminates the need for an external crystal oscilla
6CW (53)  IR TO-252 05+  The attached datasheets are prepared and approved by SAMSUNG Electr
6-D (2)  The 6-DP is a fast SRAM with a nonvolatile EEPROM element incorporated
6D/ (6) 
6D0 (1)  Registers 0, 1, 2, 4, 6, 8, 9, and A contain Time of Day data in BCD. Ten
6D1 (18)  FUJI SOP  − Dynamic Range: 113 dB  − THD+N: 0.001%  &#
6D2 (1)  N/A HEXFRED diodes are optimized to reduce losses and EMI/RFI in high frequen
6D5 (4)  FUJI 6GTR Wide Operating VCC Range of 0.8 V to 3.6 V Optimized for 3.3-V Operation
6D7 (2)  N/A USING THE SP304 POWER SUPPLIES The SP304 requires 12V and +5V for full
6DA (1)  04+ The ISL6564 senses current by utilizing patented techniques to measure th
6DE (1)  Port 1: Port 1 is an 8-bit bi-directional I/O port with internal pull-ups
6DF (4)  This data sheet has been carefully checked and is believed to be reliable,
6DH (1)  The SLC90E66 supports two IDE channels for up to four IDE devices in eithe
6DI (211)  FUJI N/A When the ORG pin is connected to VCC, the (x16) orga- nization is selec
6DJ (1) 
6DL (6)  JRC SQFP120 2007+ mode range to operate with inputs at +3.4V with respect to the negative
6DM (1)  6DMY 05+   NCS2510 is a 1.0 GHz current feedback monolithic operational ampl
6DR (4)  K&L OSCILLATEK 06+ The UC3823A,B/3825A,B oscillator is a saw tooth. The rising edge is gov
6DS (6)  GPS PLCC28 03/+04+ Continuous Drain Current, VGS @ -10V Continuous Drain Current, VGS @ -1
6DT (4)  FUJI MODULE 00+ The maximum power that can be safely dissipated by the AD8152 is limited
6DV (3)  NORTEL PLCC 2000 The MGF431xG series super-low-noise HEMT(High Electron Mobility Transist
6E0 (1)  Voltage Control Oscillator (bit LCD= 0). This pin is used to control the
6E1 (1)  In addition to the column address, A10(=AP) is used to invoke autoprechar
6E2 (1)  The ML6428 is a dual monolithic continuous time video filter desig
6E4 (1)  N/A Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pull-ups
6EC (1)  The Am29LV017D is a 16 Mbit, 3.0 Volt-only Flash memory organized as 2,
6ED (5)   Notes ; 1O Repetitive Rating : Pulse Width Limited by Maximum Junc
6EE (1)  The TAP controller is fully synchronous to the TCK signal. Input data is
6EF (3)  STM SOP-20 04+ • The information contained herein is presented only as a guide for
6EG (1)  • 1.27 mm (0.050 in.) pitch contact arrangement in two   rows
6EH (3)  * On products compliant to MIL-PRF-38535, this parameter does not apply.
6EL (1)  address, and I/O pins that permit independent, asynchronous access for re
6EQ (1)  NOTES:   1. Dimensions are in inches.   2. Metric equivalents
6ES (3)  SIEMENS 变频器/扩展模块EM 06+ Notes: 1Stresses above those listed under Absolute Maximum Ratings may c
6ET (1)  __________________________________________________________________________
6-F (1)  N/A 00+ DIP-18 The ADG3232 is a level translator 2-1 mux designed on a sub- micron proc
6F1 (5)  DSI n/a To allow for dc coupling to ADCs, its unique output common-mode control
6F2 (2)  IR DO-203AA (DO-4) 00+ † All typical values are at VCC = 3.3 V, TA = 25C. ‡ The bus
6F4 (1)  IR DO-203AA (DO-4) 00+   The current source provides a closely regulated zener current, wh
6F6 (5)  IR DO-203AA (DO-4) 00+ PGND: Output Stage Ground. To keep output switching noise from critical
6F8 (1)  IR DO-203AA (DO-4) 00+ • 16-bit I/O timer   16-bit free-run timer : 1 channel  
6F9 (1)  01+ The 6F9W7507 is a single-chip audio digital signal processor incorporati
6FA (3)  ST SOP-20 The HPND-4028 and 4038 beam lead PIN diodes are designed for low capaci
6FG (1)  01+ Figure 3 is a photograph of the various waveforms present- ed during this
6FL (31)  DSI n/a DESCRIPTION The 74AC138 is an advanced high-speed CMOS 3 TO 8 LINE DEC
6FP (1)  CAUTION: THIS IS AN ESD SENSITIVE DEVICE The following briefly describes
6FR (6)  Note: 1. A write cycle occurs during the overlap of a low CS and a low WE
6G2 (1)  5V Output Current: 100mA (VIN 3V) 3.3V Output Current: 80mA (VIN 2.5V)
6GB (8)  IR GBU 00+ Hynix HYMD216646A(L)6J-J series incorporates SPD(serial presence detect).
6GI (1)  1735 This is a positive edge-triggered sequential phase detector using an RS-
6GJ (2)  The HR700 Series converters offer low noise on both the input and output
6H- (1) 
6H0 (3)  TXC na Temperature :stg max Test duration : 1000h Temperature : Tstg min Test
6H1 (3)  HP DIP8 02+ The transceiver is fully compatible with the IEEE 802.3 standard for aut
6H2 (1)  NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATI
6H3 (1)  Positive driver supply pin for the ADC12DL065s output drivers. This pin
6HA (2)  ST DIP16 07+ The 6HAM607501716 and 6HAM607501716373 are single and triple high bandwid
6HB (5)  ST (14) Interrupts: 21-source, 10-vectored interrupts   1) Three prior
6HC (5)  ST 06+ 550 Clock synthesizer Power management Reset controller MPC555 decrementer
6HD (1)  • Selects between 1 of 2 inputs, and provides 12   precision,
6HE (8)  ST QFP80 2007+ Data are shifted in through the serial port C (SDC0, , SDC3) at the risin
6HF (2)  ST N/A Precision Fixed Operating Frequency KA1M0265R (70kHz) , KA1H0265R (100k
6HI (1)  ST QFP80 2007+ This document contains device-specific information. Additional informat
6HK (10)  STM SOP-28 04+ Notes: (for Tables 2 & 3)  1. Dominant wavelength is derived fr
6HL (1)  By using the control signal CS, SK and data in- put signal DI, these ins
6HM (3)  01+ DIP   Typical data are for initial design estimations only, and assume o
6HN (3)  1 DIP When presented with a composite video input signal, the GS4882 outputs co
6HP (9)  01+ SOP switch either ac or dc loads. Connection B, with the polarity and pin
6HR (1)  ST 01+ 88 The PD# signal is used to bring all clocks to a low level in an orderly
6HU (3)  STM 04+ 38   Blanking in the RF or mixer sections of the receiver removes most
6I. (1)  The command sequences are written by applying a low pulse on the WE or
6IG (2) 
6-J (1)  • Instructions adapted for high-level languages: Function entry/exi
6J1 (2)  The ISO150 is a two-channel, galvanically isolated data coupler capable
6JK (1)  Hynix HYMD116725B(L)8J-J series is unbuffered 184-pin double data rate Syn
6K0 (2)  SAMSUNG SOP72 00+ Lead Temperature (soldering, 10s)+260C (1) Stresses above these ratings
6K1 (1)  Absolute maximum ratings indicate sustained limits beyond which damage to
6K2 (1)  The 6K2996 introduces Single-Instruction, Multiple-Data (SIMD) processing
6K4 (1)  CVBS1, 2 Y and C outputs - NTSC (pedestal enabled) Maximum output, rela
6K5 (2)  will vary with supply voltage, switching frequency and the external MOSFE
6K6 (1)  The LPC47M14x* is a 3.3V (5V tolerant) PC99 compliant Super I/O controller
6K8 (2)  N/A 1. Hitachi neither warrants nor grants licenses of any rights of Hitachis
6KA (6)  GS 128K x 36, 256K x 18 memory configurations Supports high system speed: C
6KE (1)  • Full-Duplex Audio Processing for AMPS/   NAMPS Cellular Syst
6KV (8)  WM Y5P 05+   The power dissipation of the TSOP−6 is a function of the dr
6L. (1)  PERIPHERALS 32-Bit, 33 MHz, 3.3 V, PCI 2.2 Compliant Bus Interface &nbs
6L1 (2)  SDRAM LCC/54 01+  SRAM • Power dissipation   Operating : 40 mA Max &n
6L2 (2)  TOS TSSOP Maximum ratings are those values beyond which device damage can occur. Ma
6L8 (2)  SDRAM LCC/54 01+ Package drawings, standard packing quantities, thermal data, symbolizatio
6LB (6)  TI The XC95144 is a high-performance CPLD providing advanced in-system pro
6LC (2) 
6LP (1)  (AVDD3.3 = DVDD3.3 = AVCLK = +3.3V, AVDD1.8 = DVDD1.8 = +1.8V, GND = 0, fC
6LS (3)  AVX 06+ 128K x 72 (9M) or 64K x 72 (4.5M) Data and Mask cells Full Ternary Conten
6-M (1)  MINI 2000+ Systems using more than one converter for power management functions of
6M0 (3)  仙童 07+ TO-220 All limits at temperature extremes are guaranteed via correlation using s
6M1 (2)  Frequency Mode Select. This three-level input selects the frequency range
6M4 (3)  TQS QFN 98+ NOTES:  1. Dimensions are in inches.  2. Metric equivalents ar
6M6 (1)  Output pin. If an inrush current flows (e.g., from a lamp), the current i
6M8 (2)  MITSUBISHI 05+ The Intersil ISL422XE devices are 2.7V to 5.5V powered RS-232 transmitte
6MB (666)  N/A Many boards will not need any tuning capacitors, but for consistent lon
6MC (18)  MARCON . 09+ The HC393 and HCT393 are 4-stage ripple-carry binary counters. All coun
6MH (1)  ★Original and new, Special price! ★Original and new, Special price! 07+
6MI (5)  FUJI Size and connector type match existing humidity modules. Stable, linear
6ML (1)  Peak harmonic or spurious noise is defined as the ratio of the rms value
6MM (2)  N/A The AC533 devices are octal transparent D-type latches with 3-state out
6MP (3)  Note 1 Absolute Maximum Ratings are those values beyond which the safety
6MR (1)  Zener Voltage (VZ) is measured with junction in thermal equilibrium with
6MV (3)  Line Input: Differential AMI inputs to the chip. Should be transformer co
6N0 (5)  MOTOROLA Schematic capture, automatic place and route Logic and timing simulatio
6N1 (197)  99/01+ The DS1642 is guaranteed to keep time accuracy to within 1 minute per mon
6N2 (2)  © 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, regi
6N3 (5)  Input Frequency Output Clock Rise Time Output Clock Fall Time Output Cl
6N4 (4)  TXC   functional operation of the device at these or any other condition
6N5 (1)  ON TO-220 0728vgc+ DRIVER-OUTPUT ENABLE/DISABLE TIMES Driver-Output Enable Time to Low Level
6N6 (2)  AAT TO-220/F 08+ Near-Depleted Battery Preconditioning Monitors Battery Temperature Bui
6N7 (1)  The signal on the current sense input pin is connected to the input of th
6N8 (9)  ST Description The ACMD-7401 is a miniaturized duplexer designed using Agil
6N9 (1)    The AP2011 integrates Pulse-width-Modulation (PWM) control circuit
6NB (1)  1735 Absolute maximum ratings are those values beyond which damage to the devi
6NF (1)  The Rambus® RIMMTM module is a general purpose high- performance memo
6NK (2)  ST TO-220F 06+ EPROM power switching characteristics require careful device decoupling.
6NT (2)  MOTO SMD SMD Information furnished by Calogic is believed to be accurate and reliable.
6P- (1)  The normalized gain plots in the Typical Performance Characteristics sec
6P1 (2)  ON 252 07+ Dual Channel 1 Form A Extremely Low Operating Current High-speed Oper
6P2 (4)  This manual describes the characteristics of typical optocouplers. Also i
6P3 (2)  The filters have a 4th-order Butterworth characteristic with an op
6P4 (1)    The marketing status values are defined as follows: ACTIVE: Produ
6P6 (1)  FUJI 03+ When the IC is enabled (TXEN high) a phase locked loop locks the output
6P7 (1)  Drives External N-Channel FETs Intelligent High-Side Gate Drive Selectab
6PA (1)    32 million packets/second (line rate) aggregate • switching
6PC (11)  The BAfffLBSG (the fff indicates the output voltage value) is a low-satur
6PF (1) 
6PH (1)  Notes; (1) Repetitive Rating: Pulse Width Limited by Maximum Junction Te
6PI (2)  OUTPUT VOLTAGE LIMITERS Default Limit Voltage Minimum Limiter Separati
6PS (1)   TAOperating free-air temperature−55125−4085C NOTE 5: A
6PT (1)  The ABTH18502A and ABTH182502A scan test devices with 18-bit universal bu
6PZ (1)    TAOperating free-air temperature−4085C NOTES: 4. VCCI is th
6QB (1)  . SOT-23 05+/06+ Each BTL driver has an associated BUS GND pin that acts as a signal retu
6QC (1)  . SOT-23 05+/06+ removal of EEPROM devices. DMS will also allow the system software to b
6R0 (4)  Infineon 07+ TO-3P The rectifier schottky barrier diode forward-direction voltage drop
6R1 (34)  In order to detect whether the boot block feature is set on or not, users
6R2 (2)  The PGA2320 is a high-performance, stereo audio volume control designed
6R3 (38)  MODULE MODULE 08+ The CDC7005 is a high-performance, low-phase noise, and low-skew clock sy
6R6 (29)  FUJI MODULE N/A (1) Stresses beyond those listed under absolute maximum ratings may cause
6R7 (1)  The information, diagrams, and other data in this manual are correct and
6RE (1)  The Am29DS323D family consists of 32 megabit, 1.8 volt-onl y flas h mem
6RH (2)  Note 1: Absolute Maximum Ratings are limits beyond which damage to the de
6RI (113)  1735 When calculating synchronous frequencies, use tS1 if all inputs are on t
6RT (2)  At + 25C, the leakage current shall not exceed the value listed in the S
6RU (1)  FUJI 03+ The FIN1218 and FIN1216 receive and convert the 3 serial LVDS data stre
6RY (1)  MODULE MODULE 08+ Input voltage range: 2.7V to 6.0V Dual, independent 150mA LDOs Error f
6S0 (4)  PHILIPS 01+ N/A The HSDL-3600 is a low-profile infrared transceiver module that provid
6S1 (3)  SANSUNG The AUP family is TI's premier solution to the industry's low-power needs
6S2 (2)  MOTOROLA 00+ The I/O cell also includes a programmable flow-through latch or register
6S4 (1)  To measure the performance of the sensor in the module, a sensor test mod
6S6 (4)  ST SOP20W 2007+ The lamp current is monitored by means of an external shunt resistor. If
6SA (4)  SANYO 2008+ NOTES 1Stresses above those listed under Absolute Maximum Ratings may ca
6SC (3)  The device can readily control keys over graphical LCD panels or LEDs whe
6SD (4)  MODULE 3. Circuit board traces from the DAAs TIP and RING   pins must excee
6SE (2)  SANYO 2008+ n Higher gain to match LM126X CMOS preamplifiers n 0V to 3.75V input ra
6SH (2)  SANYO 2008+ The ZL40518 is a laser diode driver for high speed operation of a grounded
6SI (1)  600 QFP Run: CPU on, peripherals on Idle: CPU off, peripherals on Sleep: CPU
6SM (1)  Note 3: Operating Ratings indicate conditions for which the device is fun
6SP (4)  SANYO 2008+ Gain-Bandwidth Product (G +5) Gain Peaking 0.1dB Gain Flatness Bandwi
6SS (1)  Block check character is transmitted/received as two successive charact
6ST (5)  (MAX2700/MAX2701 EV kit (Figure 3), VCC = +3.0V, TA = +25C, SHDN = GAIN_SE
6SV (16)  SANYO 1200000 The SY89113U is a 2.5V low jitter, low skew, 1:12 LVDS fanout buffer opti
6SW (1)  Start Watchdog Timer A high on this pin during reset starts the watchd
6SX (2)  N/A The plastic package carries Underwriters Laboratory Flammability Classifi
6T1 (1)  These Intersil RS-485/RS-422 devices are BiCMOS 3.3V powered, single tr
6T2 (1)  The MAX1233/MAX1234 are complete PDA controllers in a 5mm 5mm, 28-pin QF
6TE (1)  2. Data labelled Typ is not to be used for design purposes but is intende
6TL (2)  TSOP * PC/104: PC/104 connector for 16-bit ISA Bus * IrDA: One TX/RX IrDA head
6TP (33)  N/A Revision History Features and General Description Pin Description Power
6TQ (13)  IR TO-263 Compatible with Microsoft WinXP, WinME, Win2K SP3&4, Apple OS10 and L
6TS (1)  N/A Vsat: Saturation voltage of the output switch. VF: Forward voltage drop
6U8 (2) 
6UJ (1)  SOP16 BLOCK WRITE protection for top 1/8, top 1/4, top 1/2 or the entire memory
6UP (2)  1. Package is non-polarized. Parts may be on reel in orientation illustra
6V0 (1)  AGC/equalizer block handles from 0 to 15dB of cable loss Loss-of-lock (LO
6V1 (2)  ST SOP NOTES: 1. Metric equivalents are given for general information only. 2.
6V2 (2)  PANA The HY29F400s sector erase architecture allows any number of array sect
6V5 (2)  ST SOP-8 00+ Leads are Readily Solderable Lead and Mounting Surface Temperature for S
6V8 (1)  COL[2]; Disables Management Interface and selects the Full Duplex operati
6VF (2)  NIHON 00+ Output drive power down C An active low signal that controls the power-do
6VJ (1)  Pin 14 (output) is suitable for controlling a power MOSFET. During the ac
6VM (2)  At output switch point, VO 1.4V, RS = 0Ω with VCC+ from 5V to 30V
6VQ (7)  NIHON 06+ SOT-252 Applying a LOW to the INIT input causes an immediate load of the programm
6VS (2)  • 2.0 µA Typical Quiescent Current • Input Operating Vo
6VV (1)  The bq2085 uses an integrating converter with continuous sampling for t
6W1 (7)  500 MHz, 500 mV −3 dB bandwidth, AV=2 400 MHz, 2VPP −3 dB b
6W2 (6)  1735   3.5.1 Certification/compliance mark. The certification mark for de
6W4 (6)  • Excellent sound quality by adopting 4800bps CELP   speech c
6WA (2)  N The LH28F800BG-L/BGH-L are high-performance 8 M-bit SmartVoltage flash
6WV (1)  This evaluation kit being sold by TI is intended for use for ENGINEERING
6WW (2)  Figure 13 is an oscilloscope photograph of a ramp voltage being sampled
6-X (1)  Widebus Family Supports SSTL_2 Data Inputs Outputs Meet SSTL_2 C
6X- (1)  In the radio section of the handset, the TD-SCDMA radio section requires
6X1 (5)  TXC 08+ Watchdog Input. The internal watchdog timer clears to zero on the falling
6X2 (2) 
6X3 (2)  BEL 0 2   4.3 Screening (JANTX, JANTXV, and JANS levels only). Screening sha
6X6 (2)  CYPRESS BGA 01+ The transmit/receive (T/R) input determines the direction of the data flo
6X7 (1)  only when the reference frequency divided by this ratio is within the DCX
6X8 (1)  When interpolating, the user should normally bring SYNC HIGH for at leas
6Y0 (3)  Clock output traces should use series termination. To series terminate
6Y1 (1)  C Seven 16-KB blocks Auto Erase (chip & block) and Auto Program C
6Y2 (1)  These circuits are completely compatible with most TTL families. Inputs a
6Y5 (1)  MONYAMA 40 Dual MOSFET Drives for Synchronous Rectified Bridge Adaptive Shoot-Throug
6YE (1)  2000 Power Management Four power saving modes: On, Doze,  Standby, Susp
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