| Mfg | pack | D/C | Descrpion | ||
| 8.0 | (23) | NO | An internal loop filter moderates the response of the VCO to the | ||
| 8.1 | (13) | SGUGCA | SOP-6 | 01+ | More than 105 operations when applying the nominal switching capac |
| 8.2 | (25) | N/A | 1. Added DDR333 function 2. Updated DDR333 test specification 3. Deleted | ||
| 8.3 | (14) | KDS | SOT | 05+ | SO-8 package with over 1A continuous output current Capable of 2A pulse |
| 8.4 | (8) | MAX312CUE0C to +70C16 TSSOP MAX312C/D0C to +70CDice* | |||
| 8.5 | (6) | PANASONIC | 93 | Program memory - bytes60K48K32K60K48K32K16K16K RAM (stack) - bytes2048 | |
| 8.6 | (18) | 20 | S3 | 99+ | Output voltage can be programmed using the on-chip DAC or an external pre |
| 8.8 | (7) | Broadcom®, the pulse logo, MIB AutocastTM and Connecting everything&re | |||
| 8.9 | (9) | l Up to 2.5 Gbps Bi-directional Data Links l Compliant with 1X / 2X Fib | |||
| 8/1 | (4) | ||||
| 8/3 | (1) | ||||
| 8/A | (1) | ||||
| 8/H | (1) | ||||
| 8-0 | (13) | MOT | PLCC44 | 05+ | The HYM7V65801B F-Series are Dual In-line Memory Modules suitable for easy |
| 80- | (25) | AMI | PLCC68 | 00+ | Computer used for compiling and linking target programs Computer that is |
| 80. | (4) | 晶振 | 3. The PT4120/40 series incorporates an Under Voltage Lockout (UV | ||
| 800 | (189) | N/A | QFP-44 | to that code position, and there is no need to replicate this information | |
| 801 | (129) | UTC | DIE | 08+ | Additional features of the Cypress PALCE22V10 include a synchronous prese |
| 802 | (102) | PHILPS | PLCC44 | 03/+04+ | Member of the Texas Instruments Widebus Family TI-OPC Ci |
| 803 | (95) | TOSHIBA | SMD | 9603 | The device is designed to comply with all JEDEC standards set for Synchro |
| 804 | (55) | IC | 集成电路 | HCS301SN | Min/Max limits are guaranteed by design, test or statistical analysis. T |
| 805 | (75) | KEC | TO-92 | 2008+ | The device is optimized for use in many indus- trial and commercial appl |
| 806 | (101) | 05+ | QFP | Low operating frequencies can become a concern if they are in the audibl | |
| 807 | (124) | MICRO LI.. | PLCC | PLCC | The Secure Microcontroller Family (DS5000FP, DS5001FP, DS5002FP, and ass |
| 808 | (60) | IC | 集成电路 | HEF4013BT,652 | NOTES: 1. Typical values are at VCC = 3.3V, TA = 25C. 2. Not more than |
| 809 | (30) | FUJ | 90 | NOTE: EP circuits are designed to meet the DC specifications shown in the | |
| 80A | (7) | YCL | 94+ | • 1 kV/µs Minimum Common Mode Rejection • Comp | |
| 80C | (229) | SIEMENS | O7+ | Broadcom®, the pulse logo, ContentAwareTM, and Connecting everything&r | |
| 80D | (7) | The built-in-back-to-back Zener diodes have specifically been designed to | |||
| 80E | (13) | The XR16L27521 (2752) is a low voltage dual universal asynchronous rece | |||
| 80F | (1) | The CY7C133/143 has a flow-through architecture that facili- tates repeat | |||
| 80G | (2) | TOSHIBA | PLCC | 99+ | A capacitive load on the regulators output will appear as a short circui |
| 80H | (1) | 9 | 3. Low duty cycle pulse techniques are used during testing to maintain th | ||
| 80L | (17) | OSE | SSOP80 | 07+ | Each Peppermint board features a preprogrammed CY22393 embedded onto th |
| 80M | (2) | NS | SMD | 2000 | Features • Serial Input Bus • Two Squib Outputs • LowC a |
| 80N | (12) | NS | TO-252 | 00+ | The small size of ceramic capacitors makes them ideal for 80N02 applicati |
| 80P | (6) | INFINEON | TO263-2.5 | 06+ | CAUTION: These devices are sensitive to electrostatic discharge. F |
| 80R | (3) | DSI | n/a | The analog signal input. Internally biased at VDD/2, this input requires | |
| 80S | (15) | IR | 05/06+ | Each slave carries an address. The data transfer is initiated by a start | |
| 80U | (3) | ||||
| 80V | (2) | Test mode select. One of four terminals required by IEEE Standard 1149.1- | |||
| 80X | (6) | ASM | SOP-8 | 04+ | VOUT = adj (.7V min), 1.2, 1.5, 1.6, 1.8, 1.875, 2.5, 3.3V 2.5V VIN 5. |
| 80Z | (15) | N/A | Each DAC has a high-impedance differential current output, suitable for s | ||
| 8-1 | (50) | SOCKET, 1Pole, Series = RP/ RT/ RY, Terminal Type | TYCO RELAYS | 05+ | Case: JEDEC TO-220AB, ITO-220AB & TO-263AB molded plastic body Term |
| 81- | (12) | PQFP-208 | 98 | Because the overcurrent protection voltage is preset, the threshold curre | |
| 81. | (3) | KDS | 2512 | 04+ | The memory cell outputs Q and Q use ground and VCC levels and provide c |
| 810 | (171) | HAR | CDIP | —— | s Three-Terminal Adjustable Or Fixed Output Voltage s Guaranteed |
| 811 | (83) | Microsemi | SOT-223 | 00+ | Automatic flow control: The UART automatically handles either or both in |
| 812 | (101) | ST | PLCC44 | Notes: 1. For Max. or Min. conditions, use appropriate value specified u | |
| 813 | (48) | UTC | TO-92 | 08+ | Busy is active high and Section dependent but not Group dependent. Even |
| 814 | (89) | UTC | O7+ | ||
| 815 | (23) | N/A | SOP-16P | 07+ | A 6:1 stereo input multiplexer is included for selecting between line l |
| 816 | (81) | RAY | 9911 | As shown in the sample calibration curve shown below (Figure 3), the meas | |
| 817 | (41) | AMI | 00+ | PLCC84 | CS to WR Setup time WR to Status delay WR pulse width CS to WR Hold |
| 818 | (26) | 2008 | The UT51C164 is high speed 5V EDO DRAMs organized as 256K bit X 16 I/O and | ||
| 819 | (11) | IC | 集成电路 | HEF4072BP,652 | Tantalum Capacitors Tantalums are acceptable on the output bus but only |
| 81A | (6) | NITSUKO | QFP80 | The conversion process and data acquisition are controlled using CS and | |
| 81C | (74) | UTC | O7+ | ||
| 81D | (17) | The LM123 is a three-terminal positive regulator with a pre- set 5V outp | |||
| 81E | (4) | N/A | TSSOP | 07+ | The TPS3820/3/5/8 devices incorporate a manual reset input, MR. A low lev |
| 81F | (23) | FUJITSU | TSSOP-50 | This device is ideal for applications requiring level translation. When | |
| 81G | (20) | MARVELL | TSSOP | 04+ | Member of the Texas Instruments Widebus Family TI-OPC Ci |
| 81J | (2) | † Stresses beyond those listed under absolute maximum ratings may c | |||
| 81L | (2) | NAT | IC | An external sense resistor limits the maximum charge current as a safety | |
| 81M | (2) | QFP0707-48 | 97+ | The CP3SP33 contains a CR16CPlus CPU core. This core improves upon the | |
| 81N | (9) | UTC | TO-92 | 08+ | Notes a. CSTRAY < 5 pF on COSC. After Start-Up, VDD of w 3 V. b. The |
| 81R | (2) | NOTE A: The oscillator generates a sawtooth waveform on RC. During the RC | |||
| 81S | (1) | The nominal value of the RF choke L1 is 100 nH. At frequencies below 10 | |||
| 81V | (15) | FAIRCHILD | 1997 | ADJ: In the adjustable version, the user programs the output voltage with | |
| 8-2 | (11) | B | ZIP8P | 00+ | The 128-I/O 2128VE contains 128 I/O cells, while the 64- I/O version co |
| 82- | (50) | IR | 2DIO: | Features include soft-start, input undervoltage lockout (UVLO) and Powe | |
| 82. | (2) | 01+ | SOP | This is a dual function pin. In the IDT Standard mode, the EF function is | |
| 820 | (138) | SOP18W | 2007+ | ||
| 821 | (143) | N/A | N/A | N/A | Lamp and Ignition are cooperative. Either can turn on the device w |
| 822 | (209) | TYCO 02+ | The sensor can operate in three interface modes: master, snapshot | ||
| 823 | (49) | IC | 集成电路 | HEF4514BT,652 | The 56F802 supports program execution from either internal or external me |
| 824 | (71) | IC | 集成电路 | HEF4520BT,653 | Parameter Positive Supply Voltage (VCC to GND) Negative Supply Voltage |
| 825 | (145) | INTEL | BGA1515 | 04+ | The HYM7V75A801B F-Series are Dual In-line Memory Modules suitable for eas |
| 826 | (106) | RADISY | NEW | 03+ | Dome Packages The HLMP-6xxx Series dome lamps for use as indicators use |
| 827 | (49) | INTER-TEL | QFP | 2003+ | |
| 828 | (69) | 0 | 07＋ | 220573 | The GS71024 is a high speed CMOS static RAM organized as 65,536 words b |
| 829 | (34) | ior | tso-223 | 01+ | Cycle-to-cycle jitter definition: The variation period between adjacent c |
| 82A | (13) | SOT23-5P | 6+ | The WT6148/ WT6160 is a microcontroller for digital controlled monitor. It | |
| 82B | (10) | Chips | 88 | All instructions (Table 1), addresses and data are trans- ferred MSB &# | |
| 82C | (371) | OKI | DIP40 | 04+ | Gen Note: Exceeding the Absolute Maximum Ratings may damage the device. |
| 82D | (12) | 00+ | BGA | Users have access to all the relevant signal quality information, includin | |
| 82F | (3) | IBM | 07+ | Description The HSMx-C220 is the smallest and the most efficient ChipL | |
| 82G | (19) | MOTOROLA | BQFP132 | The VRE114 series voltage references have the ground terminal bro | |
| 82H | (25) | S/PHI | 28 | • Designed for industrial and telecommunications applicatio | |
| 82K | (4) | ble 5) is sent first, followed by the Least significant Byte (Table 6). | |||
| 82L | (3) | TI | 00+ | Data transmission for the DPSK mode requires that data ultimately be tran | |
| 82M | (28) | TLE 4729 G is a bipolar, monolithic IC for driving bipolar stepper motors | |||
| 82N | (3) | UTC | SOT-23 | 08+ | The MAX1392/MAX1395 micropower, serial-output, 10-bit, analog-to-digital |
| 82P | (19) | IDT | 07+ | CAOUT: This is the output of the wide bandwidth current amplifier and on | |
| 82R | (3) | tively near distance as shown in Fig. 1, a spot is produced at (a). Whe | |||
| 82S | (123) | PHILIPS | 1250 | Low Power Dissipation I2CCBus Format (2Cwire type; SDA, SCL) Data Transf | |
| 82U | (2) | LSI | DIP | 2004 | This device contains circuitry to protect the inputs against damage due |
| 82V | (20) | IDT | 07+ | Fifth Generation HEXFETs from International Rectifier utilize advanced pr | |
| 82Y | (1) | SMD-8 | 05+ | TheSN55LVDS31,SN65LVDS31, SN65LVDS3487, and SN65LVDS9638 are differenti | |
| 82Z | (1) | This data sheet contains data from the product specification. Phili | |||
| 8-3 | (21) | The C0 input controls the pinout configuration of the 1:2 pinout from reg | |||
| 83- | (26) | MHS | 90 | The three RGB channels are identical and their pin assignments may be int | |
| 83. | (6) | BENQ | 03+ | The Master Reset (MR) is an asynchronous active low input. When MR outpu | |
| 830 | (93) | IC | 集成电路 | HGTP7N60C3D | The MGA-71543 features a minimum noise figure of 0.8 dB and 16 dB avail |
| 831 | (72) | 97 | Œ120 V AC resistive load (CHB type) 30 V DC resistive load (C | ||
| 832 | (37) | AD | SOP | 03+/04 | The initial set-up sequence programs the two blink rates/duty cycles for |
| 833 | (43) | IC | 集成电路 | HIN202EIBN-T | An alternative to the Bank Erase in the Flash bank is the Block or Sector |
| 834 | (29) | INTERSIL | SOP8 | 02+ | Bus timing data is shown in Figure 4 and Figure 5. Data transfer may be i |
| 835 | (39) | NULL | 08+ | The leading-edge 0.15 µm / 0.12 µm CMOS 8-layer metal proces | |
| 836 | (62) | HTACHI | 04+ | DESCRIPTION The SuperMESH™ series is obtained through an extreme | |
| 837 | (20) | 3COM | BQFP100 | SOP TSOP-I(Standard) TSOP-I(Reversed) smaller TSOP-I(Standard) smaller | |
| 838 | (69) | N/A | The device integrates complete interfaces to mono microphones. External c | ||
| 839 | (28) | ICS | O7+ | Tiny SOT−353 and SOT−553 Packages 2.7 ns TPD at 5 V (typ) So | |
| 83A | (8) | TEXAS | SOP-14 | 99+ | TAOperating free-air temperatureC4085C NOTE 3: All unused inputs o |
| 83B | (4) | SMC | DIP | 94+ | Multiple devices can be concatenated by using the CEO output to drive t |
| 83C | (123) | 98 | The DS1258W 3.3V 128k x 16 Nonvolatile SRAM is a 2,097,152-bit, fully stat | ||
| 83D | (1) | The chip supports up to 64 K MAC addresses and up to 255 port-based Virtua | |||
| 83F | (1) | This series is designed with discrete diodes for complete isolation. Each | |||
| 83G | (3) | NETICS | QFP208 | Notes: 1. For Max. or Min. conditions, use appropriate value specified u | |
| 83H | (1) | PARAMETER Current Limit Section CS Threshold Set Current CS Comp Offset | |||
| 83J | (2) | The microcontroller allows the support of all data packets of Bluetooth | |||
| 83M | (3) | 2-, 3-, or 4-Cell Secondary Protection Low Power Consumption ICC < 2 & | |||
| 83N | (1) | PHIL | Byte 1 bit 7: Reserved 6: 0=Stream Mode, 1=Remote Mode 5: 0=Disabled, | ||
| 83S | (3) | ATMEL | 03+ | QFP80 | The LTC ®1698 is a precision secondary-side forward converter control |
| 83T | (1) | The phase locked loop (PLL) synthesizer is completely integrated, includi | |||
| 83X | (5) | time period overlaps the ontime of an output, therefore, it shortens the | |||
| 83Z | (1) | • IEEE 802.3z Gigabit Ethernet Compliant • Supports 1.25 Gb | |||
| 8-4 | (2) | 96 | Software design support and automatic place-and-route provided by Altera | ||
| 84- | (15) | ASAT | LPCC | 00 | The SPS product family is specially designed for an off-line SMPS with |
| 840 | (208) | AUGAT | 05/06+ | High-side high current switch with active low Enable Up to 2.4A continuou | |
| 841 | (66) | DDC | SSOP8 | 03+/04+ | In case that the ZC signal disappears for more than 3 seconds, the chip w |
| 842 | (107) | IC | 集成电路 | HY27UF081G2M-TPCB | Switching behavior is most easily modeled and predicted by recogn |
| 843 | (28) | ICS | TSSOP-3.9-24P | 6+ | Receive PCM Signal Output (Output). 128 kbps to 4096 kbps serial PCM out |
| 844 | (31) | IC | 集成电路 | HY57V561620CT-H | The L-Series was developed using a proven con- servative design methodo |
| 845 | (44) | F | SOP16M | 2007+ | 5V TOLERANT INPUTS HIGH SPEED: tPD = 7.5ns (MAX.) at VCC = 3V LOW POWE |
| 846 | (44) | 246 | N/A | O0 | The AT40KAL FPGA offers a patented distributed 10 ns SRAM capability wher |
| 847 | (49) | T | SOP | 03/+04+ | The NCS2002 is an industry first sub−one volt operational am |
| 848 | (83) | IC | 集成电路 | ICE2A265 | |
| 849 | (18) | INTERSIL | SOP8 | 02+ | Collector-to-Emitter Voltage Continuous Collector Current Continuous |
| 84A | (3) | Infineon | 02-04+ | Drain-to-Source Breakdown Voltage 100 Gate Threshold Voltage …2.0 | |
| 84B | (3) | NS | 05+ | Ground connection. For best performance, keep traces physically short an | |
| 84C | (56) | In addition, the L1 instruction memory and L1 data memories may be confi | |||
| 84D | (2) | TEXAS | SOP-14 | Multiscan 1H, 2H, HDTV and SVGA applications 6 Convergence channels 1 | |
| 84F | (8) | IBM | 82+ | Multipliers are designed for use where the output voltage is a li | |
| 84H | (5) | FAI(HARRIS) | N/A | 01+ | Signal Processor (DSP): - SM/SMJ320VC33-150 - 13-ns Instruction C |
| 84J | (1) | • This catalog has only typical specifications. Therefore,therearen | |||
| 84L | (15) | MOT | DIP-16 | These devices feature 3-state outputs designed specifically for driving h | |
| 84N | (3) | NEC | TO-220 | 04+ | The CPU core can use on-chip rather than external memory. This eli |
| 84P | (5) | This document is a general product description and is subject to change wi | |||
| 84S | (2) | This is the maximum deviation from a straight line pass- ing through the | |||
| 84T | (3) | BGA | The 33702 provides the means to efficiently supply the Power | ||
| 84U | (1) | SOT-23 | 05+ | An external resistor, RSET, connected to pin 6 is used to set all timing | |
| 84V | (31) | FUJITSU | 02+ | The ON Semiconductor 74FST3244 is an 8−bit, high performance | |
| 84W | (10) | BI | While a single output may be used alone (includ- ing a coupling capacitor | ||
| 84X | (2) | n 5A sink/3A source current capability n Two channels can be connected | |||
| 8-5 | (15) | The 2 series of decoders are capable of decod- ing informations that con | |||
| 85- | (14) | MOT | SOP-16 | The nominal value of the RF choke L1 is 100 nH. At frequencies below 10 | |
| 85. | (1) | iButtons are used with port adapters as a hardware based protection sys | |||
| 850 | (109) | Molex | connector | 06+ | Each 85003-0177 has a unique 64-bit identification code, which allows mult |
| 851 | (152) | AMIS/IWATSU | PQFP-144P | 04+ | Power up State Programming At power up in serial mode the six control bit |
| 852 | (49) | PLCC | The Fairchild Switch FST3125 provides four high-speed CMOS TTL-compatibl | ||
| 853 | (70) | MOLEX | na | Maximum Tri-State Enable Time VCC = 2.0V VCC = 4.5V V | |
| 854 | (47) | IC | 集成电路 | ICL7660SCPAZ | Notes * Indicates JEDEC registered data. 1. The current transfer ratio |
| 855 | (129) | N/A | N/A | N/A | The 8550DA is a monolithic driver for controlling air-core (or different |
| 856 | (89) | IC | 集成电路 | ICM7555CD/01 | constructed in eight-pin, hermetic, dual-in-line, ceramic packages. T |
| 857 | (30) | PHILPS | SMD | 03/+04+ | DESCRIPTION The M4Txx-BR12SH SNAPHAT top is a detach- able lithium pow |
| 858 | (73) | MSC | SOIC | 04+ | The interrupt controller unit (ICU) provides a flexible means for reque |
| 859 | (37) | IC | 集成电路 | IMX1T110 | The EN29LV400A has separate Output Enable (OE#), Chip Enable (CE#), and Wr |
| 85A | (6) | 00+ | SOP | The Master begins a transmission by sending a START condition. The Mast | |
| 85B | (3) | SEEQ | CDIP | CDIP | The MD1810 has four inputs which individually control four outputs. It al |
| 85C | (70) | INTEL | DIP | The 128MB Direct Rambus RIMM module consists of eight 128M Direct Rambu | |
| 85E | (10) | IR | TO | Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pullups. | |
| 85F | (5) | VISHAY | SOP08 | 07+ | 1A, 1B, 1C = SPST N.O., SPST N.C., SPDT 2A, 2B, 2C = DPST N.O., DPST N.C. |
| 85G | (2) | WAVE | QFP | 98+ | SIGNAL DESCRIPTIONS See Figure 1, Logic Diagram, and Table 1, Signal Na |
| 85H | (62) | IBM | QFP | 98+ | Sample: NR-SD-24V, 10 pcs. Contact voltage: 100 mV Contact current: 1 |
| 85L | (4) | AP | 252 | 07+ | In the second phase, the row of sensor plates is discharged with a curren |
| 85M | (1) | The high-side switch (Q1) is designed with specific emphasis on reducing | |||
| 85N | (6) | 78 | TO252 | 04+ | HY57V56820T is offering fully synchronous operation referenced to a positi |
| 85O | (1) | • High Jitter Tolerance • Sampling Rate: Up to 216kHz • | |||
| 85Q | (1) | Description This HEXFET® Power MOSFET is specifically designed for | |||
| 85R | (2) | Pb−Free Packages are Available Small Compact Surface Mountable Pac | |||
| 85S | (8) | Addresses and chip enables are registered at rising edge of clock when ei | |||
| 85T | (3) | TO252 | 06+ | The Erase Suspend/Erase Resume feature allows the host system to pause a | |
| 85U | (1) | HIT | DIP | 1998 | On a 2 V supply, the Sx and Sy thresholds are approaching half the suppl |
| 85Y | (3) | MOTOROLA | ZIP | The ispLSI 1032EA is a High Density Programmable Logic Device containin | |
| 8-6 | (1) | The Input/Output logic timing diagram is shown in Figure 1. For proper ope | |||
| 86- | (2) | 04+ | DIP | READY/BUSY: The RDY/BSY pin provides the devices ready/busy status when | |
| 860 | (120) | N/A | DIP18 | 04+ | • UltraFast Non Punch Through (NPT) Technology • Low |
| 861 | (94) | IC | 集成电路 | IP5005CX11/LF,135 | • Supports Cypresss Ultra37000™, Ultra37000V™, |
| 862 | (106) | SOP | An enhanced, multiple cell security scheme is provided that prevents re | ||
| 863 | (66) | D-SUB ACCESSORIES | FRAMATOME | 05+ | Backplane Transceiver Logic (BTL) is a signaling standard that was inve |
| 864 | (67) | IC | 集成电路 | IR2101PBF | Wait or Transfer Acknowledge. When configured as wait, this signal is as |
| 865 | (65) | FCI | 08+ | The ADSP-21991 instruction set provides flexible data moves and multifun | |
| 866 | (19) | TSMD | The MARC4 microcontroller consists of an advanced stack-based 4-bit CPU c | ||
| 867 | (11) | VICOR | 2007 | Precision fixed operating frequency (100 / 67 / 50KHz ) Pulse by pulse | |
| 868 | (10) | EXAR | 04+ | The HYM72V64736B(L)T8 Series are Dual In-line Memory Modules suitable for | |
| 869 | (34) | Molex | Tube | Gennum Corporation assumes no responsibility for the use of any circuits | |
| 86A | (10) | DELTA | Lead temperature (Soldering, 10 s)300C (1) Stresses beyond those listed | ||
| 86B | (2) | The Hynix HYM76V8755HGT8 Series are Dual In-line Memory Modules sui | |||
| 86C | (149) | S3 | QFP208 | A high input impedance, high-gain, broadband RF amplifier permits | |
| 86D | (3) | ZILCG | 06+ | 500 | PWM Comparators Two comparators are provided to perform pulse width mod |
| 86E | (16) | ZILOG | SMD | Notes: 1. For Max. or Min. conditions, use appropriate value specified u | |
| 86F | (1) | Manages Total Power Between a USB Peripheral and Battery Charger Minimal | |||
| 86H | (26) | N/A | 06+ | 500 | An input capacitor of 2.2µF (nominal value) or greater, connected |
| 86J | (1) | External Memory Interface (EMIF) for Flexibility and Expansion. The extern | |||
| 86L | (17) | ZILOG | DIP | 99+ | Supply voltagePin 1 Input voltagePin 2, 3, 4, 7, 9, 14, 15 Output curre |
| 86M | (1) | The megapixel CMOS image sensor features Digital- ClarityMicrons breakth | |||
| 86P | (1) | SOP | 07+ | Note 1) The specified condition Tj=25˚C means that the test should | |
| 86S | (5) | ADSC write accesses are initiated when the following condi- tions are sat | |||
| 86T | (1) | MSOP8 | 06+ | VDETDetection Voltage Compliance RDETMINMinimum Valid Signature Resistanc | |
| 86X | (1) | 75 | O6 | DES is a block cipher that uses a 56-bit key to encrypt 64-bit blocks of | |
| 8-7 | (11) | 二极管 | Depending on your PSoC device characteristics, the digital and analog sy | ||
| 87- | (11) | Unknown | |||
| 87/ | (1) | CAUTION: These devices are sensitive to electrostatic discharge; follow p | |||
| 870 | (153) | DIP | The following briefly describes a procedure for evaluating the high effic | ||
| 871 | (69) | IC | 集成电路 | IR2121PBF | The UC3823A,B/3825A,B performs fixed frequency pulse width modulation c |
| 872 | (156) | AMP/TYCO | 04+ | 255 | The skew between CLKOUT and the CLKA/B outputs is not dynamically adjuste |
| 873 | (117) | N/A | 500 MSPS Maximum Update Rate DAC WCDMA ACPR C 1 Carrier: 76 dB Centered | ||
| 874 | (132) | FAIRCHLD | SOT-23 | 3.3V version of PI49FCT805/806 Extremely low output skew: 0.5 | |
| 875 | (133) | N/A | AD | 04+ | |
| 876 | (82) | CEJ | 98 | True Dual-Ported memory cells which allow simultaneous access of the same | |
| 877 | (175) | IC | 集成电路 | IR2161SPBF | Provides Direct Input/Output (DIO) Interface for Management Access and Co |
| 878 | (104) | MOT | 02+ | PLCC44 | The bar antenna is the most critical device of the complete clock receiv |
| 879 | (50) | ★★★ | 00 | suitable for Low Noise, Low Power applications and specially in battery | |
| 87A | (19) | PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to- | |||
| 87B | (1) | N/A | 00+ | SSOP | NOTES: 1. A17 is a NC for IDT70V3399. 2. All VDD pins must be connected |
| 87C | (328) | ATMEL | 04+ | PLCC-44P | INPUT Minimum Common-Mode Input Voltage(4) Maximum Common-Mode Input V |
| 87D | (1) | N/A | The lamp current is monitored via an external shunt resistor, RShunt and | ||
| 87F | (10) | AMD | PLCC | Jitter-free operation is maintained over the full temperature and VCC ran | |
| 87G | (5) | NS | PLCC44 | 02+ | Drift compensation (Figure 1-7) is performed by making the reference lev |
| 87H | (21) | KEC | QFP | 2000 | |
| 87K | (5) | MOT | DIP-14 | Absolute Maximum Ratings are those values beyond which damage to the devi | |
| 87L | (7) | 2008 | Low cost, general duty, non-environmental MIL-C-5015 type connectors. Ava | ||
| 87M | (1) | FUJ | BGA | (1) LED CURRENT CONTROL The NJU6052 incorporates the LED current c | |
| 87N | (1) | PH | Junction Temperature Calculation: TJ = TA + (PD x JA). The JA numbers ar | ||
| 87P | (4) | TOS | DIP | The DDU7C relies on a stable power supply to produce repeatable delays wi | |
| 87S | (4) | A/N | QFN | 02 | Te xas Instrume nts and its subsidiarie s (TI) re se rve the right to mak |
| 87T | (1) | TI | SOP-8 | High Efficiency: Up to 95% Very Low Quiescent Current: Only 10µA D | |
| 87W | (5) | Nonmultiplexed address bus Processor operates at the cloc | |||
| 87X | (3) | 72 | SHARP | 95+ | Data Bus, active High. In word mode, these pins provide a 16-bit |
| 8-8 | (6) | N/A | SOP-28 | 4. EMI/RFI Suppression. The capacitor/ inductor network should be | |
| 88- | (9) | N/A | QFP | - SYN=0. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines | |
| 88. | (1) | ||||
| 880 | (75) | TECHNICS | SOP32 | Functional Tests (In Freescale Test Fixture, 50 ohm system) VDD = 28 Vdc, | |
| 881 | (85) | JAT | 4532 | 05+ | NOTES: 1. When dc coupling to the OSCin pin is used, the pin must be driv |
| 882 | (80) | FUJITSU | The customer¢s voice sources are recorded sec- tion by section into | ||
| 883 | (68) | SSOP | 03+/04 | On the secondary side, three output voltages are produced across winding | |
| 884 | (31) | IC | 集成电路 | IRAMS06UP60APBF | Guaranteed Logic HIGH Level Guaranteed Logic LOW Level Standard Input(4) |
| 885 | (40) | 9818 | Information furnished is believed to be accurate and reliable. However, S | ||
| 886 | (21) | SSOP | 05+ | ||
| 887 | (71) | IC | 集成电路 | IRF054 | The 3-STATE control gate operates as two input and such that if either |
| 888 | (39) | 950721 | NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATIN | ||
| 889 | (66) | 88953-131 FCI RoHS COMP. | 05+ | The PTN78020A is a series of high-efficiency buck-boost-integrated switch | |
| 88A | (10) | QFP | The device can readily control keys over graphical LCD panels or LEDs whe | ||
| 88B | (1) | In the multiplexed channel mode, the parallel interface accepts 8-bit-wid | |||
| 88C | (101) | MARVELL | QFN | 2004 | The HD74LV2G14A has triple inverters with schmittCtrigger inputs in a 8 p |
| 88D | (2) | ZiLOG | O7+ | The EasyVoiceTM has a built-in RC oscillator which requires only one ext | |
| 88E | (190) | MARVELL | 06+散新 | QFP | The internal data word address counter maintains the last address accesse |
| 88F | (5) | BGA | MARVELL/PBF | 0601+ | Built-in wideband video amp85MHz @ -3dB (4VP-P output) Matched (0.1dB or |
| 88G | (6) | AMD | PLCC | Interrupt requests may be generated internally by on-chip processe | |
| 88H | (34) | CISCO | BGA | 07+ | n Sector Protection C Any combination of sectors may be l |
| 88I | (72) | MARVELL | BGA | 05+ | Non-repetitive current pulse per Figure 5 and derate above TA = 25C per |
| 88J | (2) | TAIWAN | BGA | 03+ | provided by an active LOW chip enable (CE1), an active HIGH chip enable |
| 88K | (1) | Note: 6. Full Device AC operation requires linear VCC ramp from VD | |||
| 88L | (4) | TO-263 | 06+ | The UCC5672 Multi-Mode Low Voltage Differential and Single Ended Ter- mi | |
| 88M | (26) | SANYO | SIP3 | Zero input - output delay Frequency range 10 - 133 MHz (3.3V) 5V toler | |
| 88N | (5) | NEC | TO-220 | 04+ | The thermal coefficient is reduced to 600 PPM/C, which is equivalent to |
| 88P | (5) | QFP80 | The 3B Series of Signal Conditioning I/o Subsystems provide a low-cost, | ||
| 88R | (1) | N/A | reducing the video output level is to incorporate a dual tuned circuit i | ||
| 88S | (39) | 1000 | MARVELL | The MSK 620(B) is a very high frequency video amplifier system cap | |
| 88T | (2) | SMD | 05+ | Note: Stresses greater than those listed under MAXIMUM RATINGS may cause | |
| 88W | (46) | MARVELL | LQFN64 | 04+ | This N-Channel IGBT is a MOS gated, logic level device which is intended |
| 88X | (5) | MARVELL | BGA | 04+ | For example, if a block of data is to be transferred from RAM to an I/O |
| 88Z | (2) | MARVELL | BGA | 313 | The bq2014 recognizes a valid battery whenever VSB is greater than 0.1V t |
| 8-9 | (9) | AMI | PLCC | 01+ | • Low current consumption by CMOS process with high dielect |
| 89- | (2) | N/A | PLCC-28 | 00 | A device that acknowledges must pull down the SDA line during the ackno |
| 89. | (1) | ||||
| 890 | (141) | FCI | 08+ | PWM current drive is integrated with 8 bits of control. Four bits are glo | |
| 891 | (93) | 97 | The APX9142 is an integrated Hall Effect Sensor IC designed for electric | ||
| 892 | (65) | N/A | FIXED-LENGTH BURST READS: During a fixed-length burst mode read, four, ei | ||
| 893 | (43) | IC | 集成电路 | IRF3315STRLPBF | Case: SOD-123, Plastic Plastic Material: UL Flammability Classification |
| 894 | (80) | N/A | MOLEX | 05+ | Further more, the two control modes -ON/OFF of loading, FOUT amplifier, |
| 895 | (21) | MOT | QFP100 | The HC74 devices contain two independent D-type positive-edge-triggered | |
| 896 | (21) | IC | 集成电路 | IRF4905S | |
| 897 | (23) | FREESCALE | 05+ | PLCC52 | The XP161A0390PR is an N-Channel Power MOS FET with low on-state resista |
| 898 | (151) | IC | 集成电路 | IRF5210SPBF | Split supplies of 3.3V and 2.5V are used. The 3.3V power supply powers a |
| 899 | (117) | BI | 04+ | DIP | Zarlink Semiconductor provides prescaler evaluation boards. These are pri |
| 89B | (1) | Momentarily connecting the Manual Reset input pin (MR) to GND forces a r | |||
| 89C | (109) | STC | 05+ | PLCC/44 | 3. Devices are ESD sensitive, use appropriate ESD precautions. The device |
| 89E | (41) | SST | PLCC | 07+ | Figure 5. Block diagram of 2 GHz production test board used for Noise Fig |
| 89F | (16) | SST | 07+ | The attached datasheets are provided by ICSI. Integrated Circuit Solution | |
| 89G | (12) | TO220 | IOR | 04+ | As data bytes are received and transmitted via the serial I2C-bus, a pac |
| 89H | (1) | VCC is the main 5V supply, which can be disabled in a PC, and VSBY is t | |||
| 89J | (1) | SOP14 | 06+ | programming the ADC into the desired mode. The THS1009 consists of two | |
| 89L | (10) | STC | 05+ | Module Definition 4 specifies a serial definition protocol. For th | |
| 89M | (2) | NS | SMD | 02+ | As VCE is increased, the power dissipation of the transistor increases un |
| 89P | (25) | ACER | DIP-20 | 08+ | (2) The technical information described in this material is limited to sh |
| 89R | (1) | Copyright © 2003 SigmaTel, Inc. All rights reserved. All contents of | |||
| 89S | (17) | AT | Optocoupler, precision reference and error amplifier in sing | ||
| 89V | (23) | SST | 711 | To limit maximum duty cycle, the internal clock pulse blanks both outpu | |
| 89W | (2) | Through dynamic, symmetric-mutual authentication, data encryption, and th | |||
| 89X | (3) | IBM | 93 | SOJ-26 | L = 25-50 MHz, M = 50-300 MHz, U = 300-400 MHz Upper range coupling 0.75 |
| 8A- | (4) | FH | 05+ | Single amplifiers are offered in SOT-23 packages and duals in a 10-pin MS | |
| 8A/ | (1) | Hardware data protection measures include a low V CC detector that autom | |||
| 8A0 | (4) | BI | 0009+ | SOP16 | To prevent oscillations, place the output capacitor between the ou |
| 8A1 | (10) | BI | SOP | 07+ | NOTES: 1. See Test Conditions under TEST CIRCUITS AND WAVEFORMS. 2. Thi |
| 8A2 | (12) | 96 | Note 1: Absolute Maximum Ratings are those values beyond which the life | ||
| 8A3 | (10) | Bi | SOP16 | 91+ | MuxIt is a family of general-purpose, multiple-chip building blocks for i |
| 8A4 | (5) | N/A | SIP-10 | 08+ | B4-pin serial interface BKey scanning (6 4 matrices) BProgramming dis |
| 8A6 | (1) | BI | SOP | 9926 | 15) Sweep the power supply to 5.5V. Verify that the LED module rem |
| 8A8 | (1) | Full-Scale Gain Error Bipolar Mode Gain Error Bipol | |||
| 8A9 | (28) | PT | 2003 | DIP-16 | • SuperWIDE HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC |
| 8AA | (3) | Using the Schottky Barrier principle with a Molybdenum barrier metal. Thes | |||
| 8AB | (3) | SOP8 | 05+ | Figure 2 on Page 5 shows one sample configuration of a SPORT using the p | |
| 8AC | (1) | Applications • Rugged with UltraFast Performance • Be | |||
| 8AF | (10) | IR | B-47PP | 00+ | VDD (Pin 2): Gate Drive Supply Pin. This is the supply pin for the gate |
| 8AM | (2) | N/A | 1206 | The Hynix HYM76V16635AT8 Series are 16Mx64bits Synchronous DRAM Modules. | |
| 8AZ | (1) | These devices feature 3-state outputs designed specifically for driving h | |||
| 8B- | (3) | FH | 05+ | Left/Right Clock Word Clock Clock Input Data Input No Connection Dig | |
| 8B0 | (8) | N/A | TSSOP16 | Notes: 1. See test circuit and waveforms. 2. This parameter is guarant | |
| 8B1 | (16) | ZIP-8P | 00+ | Like XC3000A, the XC4000E family has Soft Startup. When the configuratio | |
| 8B2 | (3) | Unless otherwise noted, a positive logic (active High) convention is as | |||
| 8B3 | (4) | Limiting values are given in accordance with the Absolute Maximum Rating | |||
| 8B4 | (4) | • Auto precharge/precharge all banks by A10 flag • Possible t | |||
| 8B5 | (1) | 96 | This series of Zener diodes is offered in the convenient, surface | ||
| 8B6 | (1) | BI | SOP | 9936 | Collector-Emitter Cutoff Current VCE = 50 Vdc VCE = 75 Vdc |
| 8B8 | (2) | In-rush current is limited to a programmable value by control- ling the | |||
| 8BA | (2) | 29 | SANYO | 98 | Measuring Diode Parameters The measurement of the five elements which ma |
| 8BC | (1) | Fast access times: 8.5 ns, 9 ns, 10 ns Internal self-timed write cycle | |||
| 8BJ | (2) | MITSUBISHI | SOP8 | 07+/08+ | See the Terminology section. These specifications include full temperatur |
| 8BS | (2) | SOP8 | 1.2.1 RHA designator. Device classes Q and V RHA marked devices me | ||
| 8BT | (1) | CMD | TSOP-8 | Note 5: For IOS, the use of high-speed test apparatus and/or sample-and-h | |
| 8BX | (2) | Reference Voltage Input or Output. This pin can be configured as either a | |||
| 8C0 | (5) | ZILOG | DIP | 9628+ | Features Include: Ideal for 1U High / Low Profile Applications Active |
| 8C1 | (5) | ST | SOT-89 | 06+ | 2) Digitize the modulated signal at a 1MHz rate, allowing aliasing to p |
| 8C2 | (2) | There are two identical horizontal shift registers: one at the top of the | |||
| 8C4 | (2) | PIHER | NOTES: 1. For conditions shown as Min. or Max., use the appropriate valu | ||
| 8C5 | (2) | The Mini-ACE contains internal address latches and bidirectional data buf | |||
| 8C7 | (1) | SAGAMI | 4M-3R3 | 04+ | Slew-Rate Control (Input): A capacitor connected between this pin and gr |
| 8CC | (1) | MIAO | 模块 | N/A | The 8CCR0512DT is a 7-watt 8CCR0512DTF MOSFET Amplifier Module fo |
| 8CL | (1) | IR | SMD-0.5 | 00+ | The device is organized as a 16-bit switch. There are two 8-bit switches |
| 8CT | (1) | TSOP8S | 2007+ | LCD voltage calibration Manufacturer identity Seal bit One time progr | |
| 8D- | (2) | 热敏电阻 | (5) When designing your equipment, comply with the range of absolute maxi | ||
| 8D0 | (6) | 08+ | Notes: 1. For conditions shown as Max. or Min., use appropriate value sp | ||
| 8D1 | (1) | This document describes part-number-specific changes to recommended opera | |||
| 8D2 | (1) | Motorola reserves the right to make changes without further notice to any | |||
| 8D3 | (1) | VBIAS (VCC, VBS 1,2,3) = 15V unless otherwise specified. The VIN, VTH and | |||
| 8D5 | (2) | • Synchronous Operation. • 2 Stage Pipelined operation with 4 | |||
| 8DA | (1) | Most modules operate from clocks derived from Main Clock or a PLL clock. | |||
| 8E0 | (1) | ZILOG | 06+ | The error signal from the optocoupler is fed into this input. It is loade | |
| 8E1 | (3) | 98 | The TK2050 operates by generating a high frequency switching signal based | ||
| 8E2 | (3) | Wrap Enable. This pin is active HIGH. When asserted, the high-speed serial | |||
| 8E3 | (2) | AIMLT | 04+ | PLCC | Members of the Texas Instruments Widebus™ Family Output Ports Have |
| 8E4 | (1) | The REF_SEL input determines whether the single-ended CMOS reference input | |||
| 8EF | (1) | A capacitive load on the regulators output will appear as a short circui | |||
| 8EQ | (1) | IR | 18-pin LCC | 00+ | The PKF series of DC/DC power modules are manufactured in surface mount t |
| 8ES | (2) | to program the ADC into the desired mode. The 8ESW08 consists of four a | |||
| 8ET | (29) | IR | TO | n LM78L05 in micro SMD package n Output voltage tolerances of 5% over | |
| 8EW | (31) | IR | TO | • Notebook Computers, Desktop PCs, Palmtop Computers (Win C | |
| 8F0 | (2) | NSC | 03+ | DIP (leads with 0.4" spacing) (lead bends for surface mount) (tape | |
| 8FL | (1) | 2008 | slave devices in the I 2C protocol with all memory operations synchroni | ||
| 8FM | (1) | The TPS752xxQ or the TPS754xxQ are offered in 1.5-V, 1.8-V, 2.5-V, and 3. | |||
| 8FT | (1) | BVDSSDrain-to-Source Breakdown Voltage ∆BV DSS /∆TJ Temperatu | |||
| 8FW | (1) | The MSM514252A is an 1-Mbit CMOS multiport DRAM composed of a 262,144-word | |||
| 8FY | (1) | To ensure good thermal conductivity, the backside of the FM20 die is dir | |||
| 8G0 | (2) | ST | SOT-89 | 06+ | to the load side, the effective resistance between the regulator and the |
| 8G1 | (6) | CENTRAL | SOT-89 | Functional Description The internal crystal oscillator uses the ex | |
| 8GB | (9) | IR | GBU | 00+ | TDIR Direction Control TTL Levels EDIR Direction Control ECL Levels |
| 8GS | (1) | The SSM2275 and SSM2475 are ideal for application in high performance au | |||
| 8GT | (1) | Notes: 4. Test conditions assume signal transition time of 3 ns or | |||
| 8-H | (1) | FAIRCHILD | 2008 | The Radiation Hardened IS-2100ARH is a high frequency, 130V Half Bridge | |
| 8H- | (1) | • IN-SYSTEM PROGRAMMABLE 5V In-System Programmability (ISP | |||
| 8H1 | (1) | SDRAM Controller C 2 memory banks, non-interleaved, 512 MB | |||
| 8H3 | (1) | With a 144 pin package, low power consumption, various 32-bit timers, 8-c | |||
| 8HD | (1) | The ISL6527 makes simple work out of implementing a complete control and | |||
| 8HG | (1) | PLCC | 04+ | 5V TOLERANT INPUTS AND OUTPUTS HIGH SPEED: tPD = 6.0 ns (MAX.) at VCC | |
| 8IC | (1) | N/A | sot-89 | 05+ | The ADR380 and ADR381 are precision 2.048 V and 2.500 V band gap voltage |
| 8-J | (1) | The ADE77631 features proprietary ADCs and fixed function DSP for high a | |||
| 8J0 | (3) | SMD-16 | 05+ | The products may contain design defects or errors known as errata, which | |
| 8J1 | (5) | Note that each device data sheet guarantees these points in the table o | |||
| 8J3 | (1) | SOP | Error amplifier inverting Soft start and SCP setting capacitor connecti | ||
| 8J4 | (1) | HT1626 is a peripheral device specially designed for I/O type MCU used to | |||
| 8J7 | (1) | NA | 05+ | Operating voltage: 2.2V~3.6V Ten bidirectional I/O lines Six schmitt tri | |
| 8JC | (1) | PLCC | 04+ | - Removed all references to XCLKS, since function is removed. - typo - r | |
| 8JD | (1) | 99 | OSC IN/ These pins form an on-chip reference oscillator when a seri | ||
| 8JU | (1) | ||||
| 8K0 | (4) | SOT89 | Register oriented 8/16 bit CORE with RUN, WFI, SLOW, HALT and STOP mode | ||
| 8K1 | (2) | ST | SOT-89 | 06+ | Features lRF capable MOSFETs lDouble metal process for low gate |
| 8K2 | (1) | Recommended Application: ALI - Aladdin V™ - mobile style chipsets O | |||
| 8KV | (1) | 24 Hour Time If the MIL bit of the HR register is 1, the RTC will use a | |||
| 8L0 | (12) | COTO | DIP | 80 mW into 600 Ω From a 12-V Supply at 0.00014% THD + N Current-Fe | |
| 8L1 | (6) | BI | SOP-16 | 99+ | Added 32-Mbit density Added 98H as a reserved command (Table 4) A1CA20 |
| 8L2 | (1) | BGA | 99+ | Caution: Stresses beyond those listed under Absolute Maximum Ratings may | |
| 8L3 | (2) | FAIRCHILD | 01+ | SOT23 | Supports EGSM LNA and mixer for RF to IF conversion 12 dB or 20 dB switc |
| 8LA | (1) | 02+ | SOP-8 | Figure 4 shows the ADR512 serving as an external reference to the AD7533 | |
| 8LD | (1) | The Fairchild Switch FST3125 provides four high-speed CMOS TTL-compatibl | |||
| 8LM | (1) | 2008 | 10-W/Channel Into an 16-Ω Load From a 17-V Supply Up to 92% Effici | ||
| 8LP | (3) | ALPHA | DIP-8 | Note 1: The Absolute Maximum Ratings are those values beyond which the sa | |
| 8LQ | (1) | N/A | SOP- 8 | The 17517 can drive two motors in two directions one at a time or | |
| 8LS | (3) | 05+ | SMD | Thermal Design The IRU431L is offered in the plastic 8-pin SOIC or the s | |
| 8-M | (1) | The SN74CBTD3384C is a high-speed TTL-compatible FET bus switch with low | |||
| 8M0 | (2) | This IC is a voltage regulator IC developed using the CMOS process. Super | |||
| 8M1 | (5) | Notes 1. Applies to both outputs. 2. Maximum combined output power is | |||
| 8M3 | (3) | The TPS752xx or the TPS754xx are offered in 1.5-V, 1.8-V, 2.5-V, and 3.3- | |||
| 8M7 | (1) | Enable Pin Applying a voltage of 0.4V or less at the Enable pin will di | |||
| 8M8 | (1) | When WP is low, nonvolatile writes to the 8M821G/45 are disabled, but t | |||
| 8MA | (2) | Left/right simultaneous volume or channel 1 volume is controlled by this | |||
| 8MH | (2) | After the erase instruction is entered, CS must be brought LOW. The fal | |||
| 8ML | (1) | The M58LW064D is a 64 Mbit (8Mb x 8 or 4Mb x16) non-volatile memory tha | |||
| 8MM | (2) | N/A | The CY7C1353F is a synchronous flow-through burst SRAM designed specifica | ||
| 8MS | (2) | MITSUBISHI | BGA | 01+ | Nonmultiplexed address bus Processor operates at the cloc |
| 8MX | (2) | The digital controlled potentiometer is implemented using 255 resistive | |||
| 8N0 | (1) | Stresses above those listed under Absolute Maximum Ratings may cause per | |||
| 8N1 | (2) | These N-Channel power MOSFETs are manufactured using the | |||
| 8N2 | (4) | 2003 | RESET/Output Enable input (when SER_EN is High). A Low level on both the | ||
| 8N4 | (1) | CAOUT: This is the output of the wide bandwidth current amplifier and on | |||
| 8N5 | (2) | ST | After a conversion, output data is stored in a latch separate from the s | ||
| 8N6 | (2) | TO-220 | NEW | The PWM signal is the control input for the driver. The PWM signal can en | |
| 8N7 | (1) | DESCRIPTION The VN750PEP is a monolithic device designed in STMicroelec | |||
| 8N8 | (1) | TO-3P | Before a byte can be reprogrammed, the main memory block or parameter blo | ||
| 8N9 | (1) | TO-220 | 00+ | As soon as the first word has rippled to the output, the data- out | |
| 8NA | (1) | ST无头 | TO-220 | 05+ | reliable operation, the stored energy from circuit inductance dissipated |
| 8NC | (1) | PLL1 generates a frequency that is equal to the reference divided by an 8 | |||
| 8NH | (1) | ST | QFN | 05+ | DC PERFORMANCE(4) Open-Loop Transimpedance Gain (ZOL) Input Offset Vol |
| 8NJ | (1) | SHORT FRAME SYNC OPERATION The COMBO can utilize either a short frame sy | |||
| 8OH | (1) | The UC3823A,B/3825A,B performs fixed frequency pulse width modulation c | |||
| 8P0 | (2) | Antenna Driver Stage with Adjustable Antenna Peak Current for up to 1.5 A | |||
| 8P1 | (1) | ST | SOT-89 | 06+ | RF output and bias pin. Bias should be supplied to this pin through an ext |
| 8P2 | (3) | NEC | . | N/A | This single-pole, double-throw, non-reflective switch consumes less tha |
| 8P4 | (18) | NEC | 05+ | LP and CP are best measured on the HP8753C, with the diode terminating a | |
| 8P5 | (2) | Maxim evaluates pressure pot stress from every assembly process du | |||
| 8P6 | (1) | NEC | TO-251 | 04+ | Notes: (i) For operation below 0 C the external capacitors m ust bave sta |
| 8P8 | (2) | The HYM72V32M636H(L)T6 Series are 32Mx64bits Synchronous DRAM Modules. The | |||
| 8PA | (1) | VID0-4 are the input pins to the 5-bit DAC. The states of these five pins | |||
| 8PC | (1) | Surface mountable hermetic optocoupler with leads trimmed for butt joint | |||
| 8PF | (2) | OMRON | Relay(new original) | Before registration of a decoded tone pair, the receiver checks for a vali | |
| 8PI | (5) | The DS1249 devices execute a read cycle whenever WE (Write Enable) is in | |||
| 8PO | (2) | ||||
| 8Q9 | (2) | SMD-24 | 05+ | The sensors are designed for industrial and automotive applications and | |
| 8QC | (1) | ||||
| 8R0 | (2) | 1 | 05+ | Operating virtual junction temperature, TJC 40125C † Minimum inpu | |
| 8R1 | (1) | N/A | An external resistor RCF is recommended be- tween the slider of the con | ||
| 8R6 | (1) | 20 | 95+ | GENERAL DESCRIPTION The LM2650 evaluation board is provided as a tool fo | |
| 8RB | (1) | The device can be organized as four 12-bit, two 24-bit, or one 48-bit b | |||
| 8RH | (1) | For optimum thermal performance in a natural convection application, the | |||
| 8S- | (1) | Notes: 1. For Max. or Min. conditions, use appropriate value specified u | |||
| 8S0 | (11) | SOP-3.9-8P | 6+ | † Stresses beyond those listed under absolute maximum ratings may c | |
| 8S1 | (4) | N/A | Two independent DMA channels Programmable interrupt contr | ||
| 8S2 | (1) | 1 Allowable ambient temperature against % coil voltage (max. insi | |||
| 8S8 | (1) | SOT5 | • REPLACES APEX FDHC461 • –55º TO +125ºC OPERATI | ||
| 8SD | (1) | NSC | O7+ | Notes: Repetitive rating; pulse width limited by max. jun | |
| 8SO | (3) | CARSEM | O7+ | The power dissipation of the SOT-563 is a function of the pad siz | |
| 8SP | (1) | N/A | SOP-16 | Jumpers JU1, JU2, and JU3 are provided to set the operating mode of the M | |
| 8SS | (1) | High performance 90 ns access time 25 ns page read times | |||
| 8ST | (1) | 98 | Boot PROM data line 0(EECS=0): boot PROM or flash data line 0. EEPROM da | ||
| 8T- | (1) | Stresses beyond those listed under Absolute Maxi- mum Ratings may cause | |||
| 8T0 | (2) | S/PHI | CDIP14 | 91 | The device also provides the functions of receive equalization (optiona |
| 8T1 | (1) | Software design support and automatic place-and-route provided by Altera | |||
| 8T2 | (5) | MOT | DIP | 2006 | This output configuration enables a simple matching to any kind of antenn |
| 8T3 | (2) | (2) The technical information described in this book is intended only to | |||
| 8T9 | (4) | Note 1: Do not exceed switch-to-input voltage limitation. Note 2: For swi | |||
| 8TC | (1) | These devices consist of two independent voltage comparators that are d | |||
| 8TP | (2) | N/A | Functional I/O The HFBR-5710L accepts industry standard differential | ||
| 8TQ | (17) | IR | 07+ | The circuit diagram used in the temperature display application is shown | |
| 8TW | (3) | Block write protection is enabled by programming the status register with | |||
| 8U9 | (1) | CS falling edge to first SCLK falling edge. SCLK logic high pulsewidth. | |||
| 8UN | (1) | ______ 1/ Stresses above the absolute maximum rating may cause permanent | |||
| 8V0 | (1) | The interface between the IOBs and core logic has been redesigned in th | |||
| 8V1 | (3) | TI | 07+ | If pin 3 (input ON) is continuously closed, the delay time, td, still ela | |
| 8V2 | (1) | Macrocell registers can be clocked from one of several global, local or | |||
| 8V9 | (1) | !Features 1) Built-in bias resistors enable the configuration of an &nbs | |||
| 8X- | (4) | Housed in SOIC−8 or PDIP−8 package, the NCP1201 enhanc | |||
| 8X1 | (2) | The QS3VH257 HotSwitch Quad 2:1 multiplexer/demultiplexer is a hig | |||
| 8X2 | (2) | * All MC145026 devices manufactured after date code 9314 or 314 are guara | |||
| 8X3 | (7) | S | CPGA | In many applications, the card or tag manufacturer may choose to overwr | |
| 8X4 | (3) | This pin is used to supply Vcc to the modulator circuits. A RF bypass ca | |||
| 8X6 | (2) | S/PHI | CDIP28 | 90/91 | Packaged in a 32-pin, side-brazed, metal-sealed, ceramic TDIP, the func |
| 8X8 | (24) | 1000 | sFEATURES qInternal Y/C separator circuit qNTSC matching for Composite | ||
| 8Y1 | (1) | replacement; Electrically Erasable (EE) technology allows reprogrammabili | |||
| 8Z- | (2) | N/A | o dcOutput Duty Cycle48 NOTE 1: Defined as skew between outputs at the | ||
| 8Z2 | (2) | TOKYO | 模块 | 08+ | Address/Data number combination - HT12D: 8 address bits and 4 data bits |
| 8Z4 | (2) | 94/95 | SOT5 | The HS-22620RH is a radiation hardened, dual bipolar operational ampli& | |
| 8ZN | (1) | The integrated high performance USB transceivers allow the ISP1563 to han |
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