| Mfg | pack | D/C | Descrpion | ||
| F.2 | (1) | 376 | MI | 97+ | CRS[3:1] are dual purpose pins. When RESET is active, the value on these |
| F.7 | (1) | Notes: 1. The algebraic convention, where the most negative value is a m | |||
| F.B | (1) | N/A | Maximum ratings are those values beyond which device damage can occur. M | ||
| F.L | (1) | Housed in a small 24-pin DDIP or SMT (gull-wing) package, the functional | |||
| F.S | (1) | • Fault Protected 16-Channel 12-Bit A/D Converter with Sampl | |||
| F/B | (1) | ||||
| F/C | (1) | ||||
| F/S | (1) | ||||
| F/T | (2) | ||||
| F/V | (1) | ||||
| F-0 | (1) | Support for one Fibre Channel port Support for 1-Gb and 2-Gb serial int | |||
| F0- | (1) | A fast, high precision differential input stage permits consis- tent pro | |||
| F00 | (80) | N/A | N/A | Hynix HYMD264G726A(L)8-M/K/H/L series is designed for high speed of up to | |
| F01 | (44) | N/A | 2005 | 3. Die Attach a. Eutectic Eutectic die attach can be accom- plished by | |
| F02 | (27) | C & K 07+ | DATEL makes no representation that the use of its products in the circuit | ||
| F03 | (16) | ST | SOT23-5L | Note 7: The current source is connected internally between VIN and VIOUT. | |
| F04 | (19) | T | N/A | 07+ | ON Semiconductor andare trademarks of Semiconductor Components Industries |
| F05 | (41) | 2008 | This device is another member of Broadcom's 0.13µ Gigabit copper PH | ||
| F06 | (46) | N/A | 0603F | The CA3080 and CA3080A are similar in generic form to conventional oper | |
| F07 | (9) | TOSHIBA | DIP5CAN | 00+ | • Two digitally controlled potentiometers and two voltage co |
| F08 | (75) | GaAs | 04+ | (2) The technical information described in this book is intended only to | |
| F09 | (12) | N/A | The RC4700 ALU consists of the integer adder and logic unit. The | ||
| F0G | (2) | Max. UnitsConditions VVGE = 0V, IC = 250µA V/C VGE = 0 | |||
| F0L | (2) | The Photovoltaic DC Relay (PVD) is a single-pole, normally open solid s | |||
| F0V | (1) | The temperature is measured by a diffused resistor with a positive | |||
| F0X | (3) | The DS1543 is available in two packages (28-pin DIP and 34-pin PowerCap m | |||
| F-1 | (30) | SEMITEC | LL34 | The H6061 is a combined initialiser, watchdog and voltage monitor. The c | |
| F1- | (33) | TEMIC | QFP | 04+ | Notes: 1. All typical values are at 25C and with a 3.3V supply 2. tsk(p |
| F10 | (216) | MOSPEC | TO-220 | 05+ | The ISL9G2060EG3, ISL9G2060EP3, and ISLPG2060ES3 are a Low Gate Charge |
| F11 | (72) | TI | QFP-M100P | 6+ | tdotditmstcksrl_txensrl_tclksrl_txdsrl_rclksrl_rxensrl_rxdsrl_clsnmii_srls |
| F12 | (109) | RST Reset input A high on this pin for two machine cycles while the oscil | |||
| F13 | (19) | The HS I2C™-compatible module is a reference solution for implement | |||
| F14 | (24) | ST | SOT-23-5L | • IEEE 802.3u D5 repeater and management compatible • Suppor | |
| F15 | (35) | SOP16 | 06+ | The NCP5422A is a dual N−channel synchronous buck regulator | |
| F16 | (174) | MOSPEC | TO-220 | 05+ | n No special start-up sequence required between clock/data and /P |
| F17 | (97) | Vishay | 08+ | A powerful program sequencer controls the flow of instruction execution, | |
| F18 | (80) | CRYDOM | The preamble (Figure 9 on page 10) with up to 320 periods of the 125 kHz | ||
| F19 | (3) | Readable in-band and out-of-band flow control status Programmable specia | |||
| F1A | (11) | * Internal Constructure with GPRC (Glass Passivated Rectifier Chip) | |||
| F1B | (6) | KEC | TO-220 | 04+ | Notes: 1. For Max. or Min. conditions, use appropriate value specified u |
| F1C | (28) | 22 | TEMIC | 99+ | In EDO page mode read cycle, the data-out is held to the next CAS cycles |
| F1F | (5) | ORIGIN | SMA | 05+ | The TLC372 has internal electrostatic discharge (ESD) protection circuits |
| F1H | (6) | 1.2.1 RHA designator. Device classes Q and V RHA marked devices me | |||
| F1J | (23) | ORIGIN | SMA | 05+PB | Storage Temperature, TS Operating Temperature, TA Lead Solder Tempera |
| F1L | (2) | 07+/08+ | 1) Can select center frequency and Q value of Bass characteristic | ||
| F1N | (13) | N/A | N/A | N/A | Input Amplifier/Buffer Figure 2 shows a simplified schematic of t |
| F1P | (8) | ORIGIN | SMA | 05NOPB | Address, active High. These 18 inputs, combined with the DQ[15]/A[ |
| F1S | (12) | ORIGIN | SOD-6 | For applications where efficiency is a prime consideration, the buck cont | |
| F1T | (7) | N/A | SOP8 | 07+ | Housed in SOIC−8 or PDIP−8 package, the NCP1200 repres |
| F1V | (4) | ORIGIN | SMA | 05+ | The JEDEC MO-127 12-pin Power Dip™ package (see Package Ou |
| F1X | (2) | cmac | cmac | dc04 | A common use of the F157A is the moving of data from two groups of regis |
| F-2 | (8) | SEMITEC | LL34 | Zener Voltage Range − 3.3 V to 200 V ESD Rating of Class 3 (>16 | |
| F2- | (5) | N/A | QFP | Drive Circuits The pin arrangement in these products is the same | |
| F2. | (1) | The ICS601-01 is a low cost, low phase noise, high performance clock sy | |||
| F20 | (66) | TO-220F | 07+ | AMDs Flash technology combined years of Flash memory manufacturing expe | |
| F21 | (51) | FAIRCHILD | . | 05+ | ta = DS0*/DS1* to the assertion of DTACK* (slave access time). tr = Brx* |
| F22 | (13) | FAI | SOT-223 | FEATURES 225 ps Propagation Delay through the Switch 4.5 Switch Connect | |
| F23 | (10) | RENESAS | QFP | 07+ | Note 1: Calculated by measuring the combined oscillator and prescaler supp |
| F24 | (32) | DIP | 97 | 1.1 Program Memory Organization The TLC154/155 have a 9-bit Program Count | |
| F25 | (40) | MITSUBISHI | QFP- | 07+/08+ | Varistors with flanged leads provide better positioning on printed-circu |
| F26 | (19) | ON.semi | SOP-14 | 01+ | The following Functional Description describes the base architecture of |
| F27 | (19) | 00+ | SOP-8 | Data# Polling (DQ7) When the SST39VF160Q/VF160 are in the internal Pro- | |
| F28 | (41) | FAIRCHILD | . | 05+ | Maximum ratings are those values beyond which device damage can occur. M |
| F29 | (41) | SYCMOS | 99/00 | Low-Power Dissipation Increases ADSL Line Card Density Low THD of -88 dB | |
| F2A | (2) | device against low energy spikes (see ISO7637 transient compatibility t | |||
| F2C | (3) | 91 | pulses. This will result in some low frequency ripple, although the LED c | ||
| F2D | (1) | The F2DE60421-52/F2DE60421-52 are 8-bit, high performance, RISC architect | |||
| F2E | (1) | Several register bits (bit 0 to bit 93) are used to control circuit opera | |||
| F2F | (3) | ZEPETRONIX | SSOP | 0509+ | Ceramic Capacitors Above 150 kHz the performance of aluminum electrolyti |
| F2G | (6) | 92+ | An active-high input enables the Host mode. Data is written to the com- | ||
| F2H | (1) | ST | TO-220F | 07+ | A complete PLL (phase-locked loop) can be implemented if the synthesizer |
| F2J | (8) | ORIGIN | SOT | 05+ | * All specs and applications shown above subject to change without prior |
| F2L | (3) | 2057 | 05+ | Bidirectional 4-bit input/output ports. Schmitt trigger input and CMOS ou | |
| F2M | (7) | via an RF or an infrared transmission medium upon receipt of a trigger si | |||
| F2N | (4) | N/A | N/A | N/A | Absolute Maximum Ratings indicate sustained limits beyond which damage to |
| F2P | (4) | MOT | SMD | A sophisticated interrupt structure recognizes up to eight interrupt level | |
| F2Q | (2) | The inhibit function is provided by the Inhibit* control, pin 1. If pin | |||
| F2S | (3) | MIC | In the IDT Standard mode, the FF function is selected. FF indicates whet | ||
| F2T | (3) | IETEX | 247 | Analog composite video signal output or Cb or B signal output current dri | |
| F2U | (2) | IT | 05/06+ | The MAX6672/MAX6673 operate from 2.4V to 5.5V with a maximum supply curre | |
| F2W | (3) | fct | fct | dc01 | The HYM72V64C736T4M Series are 64Mx72bits ECC Synchronous DRAM Modules. Th |
| F-3 | (7) | SEIKOEPSON | 1500 | 01+ | Second, keep the maximum currents relatively large (1mA or 2mA) to minim |
| F3- | (5) | N/A | N/A | N/A | (For a single-phase input unit) An example of the I/O voltage characteri |
| F3. | (1) | Notes: 3. CPD is defined as the value of the internal equivalent capacita | |||
| F30 | (64) | HARRIS | TO-251 | 07+ | Note 5: Maximum ambient temperature (TA-MAX) is dependent on the maximum |
| F31 | (69) | TI | 00+ | QFP-L148P | RSEN: This pin is used to sense the voltage across the synchronous rectif |
| F32 | (40) | stock | The VSP2272 device is a complete mixed-signal processing IC for digital | ||
| F33 | (50) | 06+ | QFN-28 | n Mask optional for built-in RC oscillator with an external resis | |
| F34 | (15) | BGA | Choose R4, then calculate R3. The value of R4 should be large enough suc | ||
| F35 | (14) | N/A | DIP | 2006 | The REF inputs can be changed dynamically. When changing from one refere |
| F36 | (5) | The products listed in this document are designed to be used with ordinar | |||
| F37 | (20) | FAIRCHIL.. | CDIP | IC = 1.0 µAdc, VCE = 5.0Vdc IC = 10 µAdc, VCE = 5 | |
| F38 | (19) | MIT | QFP | 04+ | The FCT240T devices are octal buffers and line drivers designed to be e |
| F39 | (5) | NICHICON | A:6.3V/33UF | 08+ | DSD quantization noise in the digital domain, and the resulting multi-le |
| F3A | (5) | div | div | dc80+ | PRODUCT IDENTIFICATION: The product identification mode identifies the d |
| F3B | (1) | PLL3 generates a frequency that is equal to the reference divided by an 8 | |||
| F3D | (2) | siLicon | SOP-24 | 92 | First of all, the voltage difference need only be a few hundred millivol |
| F3F | (2) | These are the reference voltage inputs. They may be placed at any volta | |||
| F3G | (2) | TOS | TO-200 | The equalizer improves the cable-induced jitter; the data slicer restor | |
| F3H | (3) | SOP-8P | 1997 | • Compliant to the latest IrDA physical layer specification | |
| F3J | (2) | TOSHIBA | TO-220 | The MPX5050 series piezoresistive transducer is a stateCofCtheCart | |
| F3M | (2) | • Synchronous Operation. • 2 Stage Pipelined operation with 4 | |||
| F3N | (2) | N/A | N/A | 00+ | 300 ps propagation delay input to output 50 ps propagation delay dispers |
| F3P | (2) | MIETEC | DIP-16 | 08+ | The F157A is a high-speed quad 2-input multiplexer Four bits of data fro |
| F3S | (3) | HARRIS | TO-263 | 99年 | RAM organized as 131,072 words by 16 bits. It is fabricated using 1+51's |
| F3T | (2) | TAI TIEN | N/A | Efficiency up to 86% 1500VDC Isolation MTBF > 1,000,000 Hours 2:1 Wi | |
| F3W | (2) | It is a single-pin crystal oscillator, operating at the series resonant | |||
| F-4 | (6) | SEMITEC | LL34 | 05+ | This encapsulated power module can be used in a wide variety of applicati |
| F4- | (31) | Retry Counter The X76F102 contains a retry counter. The retry counter a | |||
| F40 | (93) | FSC | 05+ | 6.7MHz Y and C filters, with CV out for NTSC or PAL 75Ω cabl | |
| F41 | (68) | . | . | 04+ | Input and Output Voltages With 3.3-V VCC) Typical VOLP (Output Ground Bou |
| F42 | (22) | TI | 0149 | NOTES: 1. Typical values are at VCC = 3.3V, TA = 25C. 2. Not more than | |
| F43 | (48) | FX | SMD晶振 | 06+ | If the magnetic field exceeds the threshold levels, the current source |
| F44 | (16) | BGA | This is a data port that can be programmed to bring out internal signals | ||
| F45 | (26) | F | DIP-8 | DIP-8 | Linearity errors of 0.5 and 1.0 LSB, and Differential Non-linearity to |
| F46 | (6) | NVIDIA | BGA | BGA | Low Profile (1mm) ThinSOTTM Package Programmable Charge Current: 50mA to |
| F47 | (16) | HARRIS | CDIP-16 | High and low band filters are included to shape the amplitude and phase r | |
| F48 | (12) | HD | 03+/04 | Maximum ratings are those values beyond which device damage can occur. Ma | |
| F49 | (15) | IR | VGD: The VGD pin which is coarsely regulated around 9V and is primarily | ||
| F4A | (5) | AKM | SSOP-16 | 08+ | When 16/68# pin is at logic 1, the Intel bus interface is selected and t |
| F4B | (1) | Enhanced Parallel Port (EPP) Compatible - EPP 1.7 and EPP 1.9 (IEEE 1284 | |||
| F4D | (2) | The program begins with an overview of stress analysis principles. Follow | |||
| F4E | (2) | 扁6脚 | 04+ | The EFJ2803 is a high reliability EMI filter for use with the DAC | |
| F4F | (3) | N/A | N/A | N/A | The asynchronous mode is used for communication withasynchronousterminals |
| F4H | (5) | TI | SOP | Note 1: Absolute Maximum Ratings indicate limits beyond which damage to t | |
| F4I | (1) | Each port has independent control pins: chip enable (CE), read or write | |||
| F4J | (1) | clock cycle Interleaved auto refresh mode Programmable burst lengths and | |||
| F4K | (2) | CRFree-running conversion rateCS at 0 V668770 conv/s † All t | |||
| F4L | (2) | When the DRAIN pin of the LT4250L is above VEE by more than VDL or VGATE | |||
| F4N | (2) | N/A | N/A | N/A | The UT28F256 PROM incorporates special design and layout features which |
| F4P | (3) | ANDREW | N/A | The following charts show measured performance of the PA module in low- | |
| F4S | (1) | ||||
| F4U | (2) | ||||
| F-5 | (47) | SEMITEC | LL34 | The XP152A01D8MR is a P-Channel Power MOS FET with low on- state resista | |
| F5- | (3) | The active polarity of SHP/SHD (active high or active low) can be chosen | |||
| F50 | (50) | FUJ | 03+ | SOP/8 | After each 24-hour period has elapsed, the battery is connected to an inte |
| F51 | (25) | 00+ | The receivers double-conversion architecture requires careful frequency p | ||
| F52 | (15) | MOT | SMD | This three terminal positive adjustable voltage regulator is designed to | |
| F53 | (17) | PHI | SOP8S | 07+ | The recommended dose of ultraviolet light for erasure is a wavelength of |
| F54 | (130) | N/A | DIP/14 | 06+ | OUTPUT VOLTAGE LIMITERS Default Limiter Voltage Minimum Limiter Separa |
| F55 | (6) | ST | SOT23-5 | • International standard package, JEDEC TO-240 AA • | |
| F56 | (8) | 1 | QFP | Up to 12 DCM blocks are available. To generate de-skewed internal or ex | |
| F57 | (8) | MOT | SMD | PROGRAM/ERASE SUSPEND C Read other Blocks/Sectors during Progra | |
| F58 | (2) | IR | O7+ | This document is a general product description and is subject to change wi | |
| F59 | (20) | TI | 07+ | Notes: (i) Io1(min) current of 0.1A can be divided between both outputs, | |
| F5A | (4) | JYEG | 0351+ | The PT3660 Excalibur™ Series is a 30-A rated, dual-output i | |
| F5C | (47) | -- | -- | -- | The conditions at the binary-select inputs and the three enable inputs se |
| F5D | (6) | FAIRCHILD | |||
| F5E | (11) | FSC | 06+ | 500 | The bq4847 Real-Time Clock Mod- ule is a low-power microprocessor periph |
| F5F | (1) | The F5FK20B provides a compact 3 mm 4.9 mm packaged solution for 256-po | |||
| F5H | (3) | FAI | DIP/4 | 03+ | The I/O and logic functions of the FPGA and their associ- ated interconn |
| F5J | (1) | (6) Output Driver Control Function By setting HALTB pin to L, hig | |||
| F5K | (13) | TO-220 | The CLB can thus be used as an asymmetrical dual-port RAM, with F being | ||
| F5L | (5) | N/A | 08+ | Complete Programmable Device Can Combine Glue Logic and Structured | |
| F5M | (1) | 3000 | Each of the 3 high-side and 3 low-side drivers is capable of driving curr | ||
| F5S | (3) | SANKEN | Note 5: The output pins RST and RST have an internal pull-up to VMAX of | ||
| F5X | (2) | Active low RESET. Pulled up to VDD with internal resister. Bottom voltage | |||
| F5Y | (1) | During discharge and charge, the bq2014 monitors VSR for various threshol | |||
| F5Z | (2) | PLX | QFP- | 07+/08+ | Integrated tracking capacitor Senses motion of ring magnet or ferrous t |
| F-6 | (2) | Notes: 1. Repetitive Rating : Pulse width limited by maximum junction tem | |||
| F6- | (1) | 3. Cleaning For organic contamination use a warm rinse of trichloroethan | |||
| F60 | (12) | TI | 05+ | PLCC | the transmitted frequency to exceed its 0 01% tolerance The frequency ma |
| F61 | (13) | N/A | N/A | N/A | Maximum ratings are those values beyond which device damage can occur. M |
| F62 | (15) | 15 | STATS | 03+ | NOTES: (1) dBFS refers to dB below Full-Scale. (2) Percentage accuracies |
| F63 | (7) | TOSHIBA | NOTES: (1) Stresses above these ratings may cause permanent damage. Expo | ||
| F64 | (130) | QFP | The CMX866 can be made to perform a variety of low-level functions with th | ||
| F65 | (63) | 94 | Information at the data (D) inputs meeting the setup time requirements is | ||
| F66 | (12) | FAIRC | SOP-8 | The Blackfin processor instruction set has been optimized so that 16-bit | |
| F67 | (2) | ALTERA | 00+ | BGA | A capacitive load on the regulators output will appear as a short circui |
| F68 | (40) | F | DIP | 88 | s Complies with Universal Serial Bus Specification Rev. 2.0 s The |
| F69 | (14) | CHIP | QFP120 | © 2001-2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, | |
| F6A | (3) | - | SMD | 07+/08+ | State-of-the-Art BiCMOS Design Significantly Reduces ICCZ 3-State True O |
| F6C | (35) | FUJITSU | MLFP | 2000 | The SY89328L is a differential LVPECL-to-LVTTL translator and an |
| F6E | (7) | FUJITSU | 2005 | Hynix HYMD264G7268-K/H/L series is registered 184-pin double data rate Syn | |
| F6G | (1) | The unity gain stable LM4925 is both a mono differential output (for BT | |||
| F6P | (3) | ON | 02+ | The bq26220 works with the host controller in the portable system to im | |
| F6S | (2) | FAIRCHILD | TO220F5 | 05+ | It provides a 350MHz large-signal bandwidth at 2.8Vp-p output voltage, a |
| F6U | (1) | CHRONTEA | PLCC-44 | 97 | *Grounding Pin 7 will sink 75mA of current through Pin 7 creating a hig |
| F-7 | (5) | SEMITEC | LL34 | † All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25C. | |
| F7- | (3) | SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - | |||
| F70 | (34) | SOP | 1. TOLERANCE AND TYPE NUMBER DESIGNATION The JEDEC type numbers s | ||
| F71 | (166) | MIT | The Mini-ACE contains internal address latches and bidirectional data buf | ||
| F72 | (41) | 92 | The basic unit of logic on the ispLSI 1032E device is the Generic Logic | ||
| F73 | (107) | IOR | O7+ | The AIC111 IC design specification serves to provide product development | |
| F74 | (194) | N/A | N/A | N/A | (6) Comply with the instructions for use in order to prevent breakdown an |
| F75 | (39) | NICHICON | 03+ | 1. Intersil Pb-free products employ special Pb-free material sets; | |
| F76 | (20) | F | 98 | SOP-8 | On-chip factory firmware supports in-circuit serial download and debug m |
| F77 | (5) | KA | DIP8 | Parameter Relay Portion Output Characteristics @ 25C Load Volta | |
| F78 | (37) | IOR | SOP8 | 99+ | Timing is measured at pin threshold, with 50 pF external capacitive loa |
| F79 | (19) | 882 | IOR | 04+ | Supports PIO mode 4, both at 16.6 Mbytes/second theoretically Sustained |
| F7A | (1) | FAIRCHILD | QFN | 06+ | The DMA controller is a state-driven address and control signal generato |
| F7F | (1) | FAIRCHILD | 05/06+ | The Input/Output logic timing diagram is shown in Figure 1. For proper op | |
| F7N | (5) | MOT | 06+ | 500 | The sensor turns to high current consumption with the magnetic south po |
| F-8 | (5) | N/A | QFP-44 | Note 1: Absolute Maximum Ratings indicate limits beyond which damage may | |
| F80 | (39) | INTEL | 04+ | QFP | These diodes are optimized to reduce losses and EMI/ RFI in high frequenc |
| F81 | (21) | EPSON | 07+ | NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATI | |
| F82 | (143) | KOREA | 96 | Note 1: All currents into device pins are positive; all cuttents out of d | |
| F83 | (11) | SMS | O7+ | In a running motor, a current will flow through the resistor RSENSE resu | |
| F84 | (21) | CHIP | QFP176 | The 7.6 mm (0.3 inch) and 10.9 mm (0.43 inch) LED seven segment displ | |
| F85 | (4) | H | 01+ | PLCC-20 | Notes: 1. The nominal thermal resistance of a display mounted in a socke |
| F86 | (11) | FSC | 04+ | The QS32XVH2245 HotSwitch is a high bandwidth, 16-bit bus switch. | |
| F87 | (9) | CHIPS | QFP | 04+ | The ADSP-21991 has 4K word of on-chip ROM that holds boot routines. The |
| F88 | (4) | NICHICON | Industry Standard MICROWIRE Bus Single Supply Voltage: C 4.5 to 5.5V | ||
| F89 | (3) | F | 99 | SOP-8 | 1024 bits, 16 kbits or 64 kbits Electrically Programmable Read On |
| F8A | (2) | SMD-8 | 05+ | In addition to DATA polling the ATF8A659 provides another method for dete | |
| F8E | (3) | The product term select multiplexer (PTMUX) allocates the five product te | |||
| F8H | (1) | SEM | SOP/8 | To achieve the ever-present need for smaller, faster, lighter devices tha | |
| F8K | (1) | TOYO | 01+ | (layout including place & route, timing analysis, and back-ann | |
| F8L | (2) | SHINDENG | TO-220 | 02+ | |
| F8P | (1) | NS | 拆 | TO-220 | Replace any reference to Flash Interface Unit with Flash Module, added not |
| F8S | (1) | NSC | SO-8 | 06+ | Instruction cycle time of 2 ms for COP912CH and 2 5 ms for COP912C Three |
| F8T | (1) | The D-Pak is designed for surface mounting using vapor phase, infrared, o | |||
| F-9 | (1) | The unique feature of the F-9334PC is that the DCXO is in fact the primar | |||
| F90 | (36) | fsc | fsc | dc78 | Collector-to-Emitter Breakdown Voltage Continuous Collector Current (Fi |
| F91 | (11) | NICHICON | 07+ | Shutdown Control Input. The regulator is fully enabled when a logic high | |
| F92 | (43) | NICHICON | . | 09+ | CH1 Soft-Start Input CH5 Enable Input CH6 Enable Input Step-Up Conv |
| F93 | (280) | NICHICON | 06+ | Bidirectional 2-bit input/output port. Each bit can be a wake-up i | |
| F94 | (32) | SINGAPORE | AH285 is a monolithic fan motor controller with Hall sensors capability. | ||
| F95 | (142) | NICHICON | A | Notes: 11. Test conditions assume signal transition time of 1V/ns or less | |
| F96 | (35) | FAI | 84 | Notes: 1. All inputs except OE must meet setup and hold times for the L | |
| F97 | (7) | NICHICON | 16V10UF-C PB-FREE | 05+ | The device also features split output bank power supplies which enable |
| F98 | (9) | N/A | 0603TAN | The power factor controller section consists of the LinFinity LX1562 Powe | |
| F99 | (6) | FSC | 06+ | 500 | Port 3, I/O. Port 3 functions as both an 8-bit, bidirectional I/O port an |
| F9A | (2) | Fairchild | QFN-16 | 05+ | The AT17A Series Configurator enters a low-power standby mode whenever nC |
| F9B | (1) | TRUMPION | QFP128 | 9942+ | • Robust High Voltage Termination • Avalanc he Energy Specifi |
| F9E | (1) | The HT82K628A will respond with ACK, clears its output buffer and prepare | |||
| F9H | (2) | JAT | 05+ | INTRODUCTION National Semiconductor (NSC) is committed to provide ap- p | |
| F9L | (1) | The HLMP-0X0X series of rectangular lamps are direct replace- ments for A | |||
| F9N | (2) | The MAX1512 is a programmable VCOM-adjustment solution for thin-film tran | |||
| F9Z | (5) | FFFFGGF | 07+ | NOTES: 1. See Test Conditions under TEST CIRCUITS AND WAVEFORMS. 2. Thi | |
| FA- | (40) | EPSON | 06+ | teristics and internal reliability and qualification tests are based on | |
| FA0 | (26) | 01+ | SOP | push-pull outputs which are sequentially pulsed in groupings of bursts; a | |
| FA1 | (213) | NEC | SOT-23 | 05+ | • The DAGs generate 24-bit addresses for data fetches from t |
| FA2 | (19) | TQFP100 | 08+ | When VCC is between 0 to 1.5V during power up or power down, the device | |
| FA3 | (78) | FUJI | SOP-8 | 04+ | The external voltage supply is connected to this pin. A high quality rese |
| FA4 | (33) | NEC | 06+ | 2000 | The CAT24FC02 supports the I2C Bus data transmission protocol. This Int |
| FA5 | (179) | FUJI | SOP-8 5.2mm | 08+ | Frame Pulse ST-BUS/GCI 8.192 Mb/s (CMOS tristate output). This is an 8 k |
| FA6 | (9) | FLEXTRONICS | BGA | 0509+ | IXYS Corporation • 3540 Bassett Street • Santa Clara, CA 9505 |
| FA7 | (153) | FUJITSU | SOP | 2000 | It is possible to connect the Data In and Data Out pins together. Howev |
| FA8 | (59) | FSC | QFP | 07+ | RF output and bias pin. Bias should be supplied to this pin through an |
| FA9 | (3) | The software protection is a register based read and write protection i | |||
| FAA | (7) | N/A | NSC | 04+ | The ISL9R30120G2 is a Stealth™ diode optimized for low loss perfor |
| FAB | (7) | DIP-16 | Rectifiers advanced line of power MOSFET transistors. The efficient geo | ||
| FAC | (11) | TEW | NA | Stresses beyond those listed under Absolute Maximum Ratings may cause per | |
| FAD | (14) | MAX | O7+ | 1) Mount the 0.01µF decoupling capacitor on the component side of | |
| FAE | (1) | FE | QFN/7*7 | 03+ | The Fairchild Switch FSTD16211 provides 24-bits of high- speed CMOS TTL |
| FAF | (4) | NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATI | |||
| FAG | (22) | STANLEY | 2001 | SMD | TRB Transmitter or receiver select. A logic low at TRB selects the rece |
| FAH | (7) | arcotronics | arcotronics | dc00 | The ICS clock generator is a slave/receiver, I2C component. It can read ba |
| FAI | (76) | FAI | BGA | N/A | • 100,000 erase/write cycle Enhanced Flash program memory t |
| FAJ | (16) | FAIRCHILD | 07+ | nance of 1 050 cd/m2, and using a color temperature conversion filter LB- | |
| FAK | (2) | These N-Channel enhancement mode power field effect transistors are produ | |||
| FAL | (8) | SAMSUNG | QFP | 00+ | TTL/CMOS Output Bank Synchronization Control. Internal 25kΩ pull-dow |
| FAM | (4) | FUJ | DIP | 04+ | A capacitive load on the regulators output will appear as a short circui |
| FAN | (1286) | FARADAY | 超薄TO263-5P | 6+ | Ratiometricity simply means that the output offset voltage and se |
| FAO | (4) | 99 | Note 1: All devices are 100% production tested at TA = +25C. Specification | ||
| FAP | (29) | LITEON | 04+ | The FAP15R is a single chip duplex synchronous to asynchronous converte | |
| FAR | (185) | FUJITSU | SYMBOL PARAMETER Gate Driver IGONGATE Pin Current IGOFFGATE Pin Current | ||
| FAS | (92) | GLOGIC | QFP128 | The MSAU300 series has limitation of maximum connected capacitanc | |
| FAT | (3) | MICRO SEMI | 06+ | 805 | The 512K EPROM and OTP PROM are programmed using the TI SNAP! Pulse progr |
| FAV | (1) | DP0_RST functions as a hub reset when a 1.5-kΩ resistor is connecte | |||
| FAW | (1) | SOT-252 | The FAW1537PAB and FAW1537PA are 8Cbit latches, one addressed with | ||
| FAX | (6) | N/A | N/A | N/A | CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic ch |
| FAY | (1) | n Variable power management n Packaged in 6-lead SOT-23 (ADC081S101 als | |||
| FAZ | (1) | FAIRCHILD | SOP8L | Non-inverting 3-state outputs 2-way asynchronous data bus c | |
| FB- | (2) | AFTEK | 805 | 05+ | ded Program Algorithm which is an internal algorithm that automatically |
| FB/ | (3) | PHI | QFP52 | 07+ | An alternative to the Bank Erase in the Flash bank is the Block or Sector |
| FB0 | (24) | PHI | SMD | NOTES: 1. Typical values are at VCC = 5.0V, TA = 25C. 2. Max value is g | |
| FB1 | (103) | NEC | |||
| FB2 | (70) | TI | QFP | 00+ | SUMMARY High-Performance 32-Bit DSPApplications in Audio, Medica |
| FB3 | (23) | The Raytheon RM3183 line receiver is the companion chip to the RM3182 li | |||
| FB4 | (17) | IR | TO-220 | International Rectifier radiation hardened HEXFETs have been characteri | |
| FB5 | (14) | fagor | fagor | dc01 | Frame check sequence is transmitted/received as 16 bits following the l |
| FB6 | (12) | FUJITSU | 03+ | The NCP1575 is a low voltage buck controller. It provides the con | |
| FB7 | (14) | SIEMENS | SOP8 | 03+ | Members of the Texas Instruments Widebus Family A-Port Outputs |
| FB8 | (16) | NO | These enhancement-mode (normally-off) transistors utilize a vertical DMO | ||
| FB9 | (10) | IR | TO-220 | • Acquisition: C Feature selection via special function reg | |
| FBA | (35) | SanRex | SOP | NOTES: 1. VDD, OPTX, and VDDQX must be set to appropriate operating level | |
| FBB | (1) | Dropout Voltage The input/output Voltage differential at which the regul | |||
| FBC | (14) | N/A | Four of the nine instructions end with the transmission of the instructi | ||
| FBD | (6) | sgs | sgs | dc95 | Senses motion of ring magnet targets Integrated filter capacitor |
| FBE | (7) | AMI | The applied external reference input voltage (VREF) determines the full- | ||
| FBF | (10) | FRANCE | FBF033 | The FBF033 operates at supply voltages down to 1.8V, although the digital | |
| FBG | (19) | THOMSON | 触点脚-10P瓷 | 07+/08+ | Shift clock signal input for the PCMIN and PCMOUT signal. The frequency, |
| FBH | (12) | N/A | ENCV Variable clock enable (TTL compatible input) - This input directly c | ||
| FBI | (22) | fagor | fagor | dc00 | Three Fan Tachometer Inputs Three Programmable 16-bit Counter/Timers Dir |
| FBK | (2) | Shutdown. When SHUTD input is low, the internal clock is stopped and the | |||
| FBL | (24) | 螺栓 | On a semi-log plot (as shown in the Agilent catalog) the current graph | ||
| FBM | (149) | TAIYO | 1206 | 04+/05+ | ALO,BLO,CLO - are the logic inputs for controlling the switching of the |
| FBN | (20) | HARRIS | 2008 | Split power supply: The receiver circuit only is connected to a regulated | |
| FBO | (2) | Base Stations: Single/Multicarrier UMTS, CDMA, GSM Communications: Fixed | |||
| FBP | (5) | MOTOROLA | CAN3 | The FBP-00-045 is a high dynamic range driver amplifier in a low-cost su | |
| FBQ | (1) | N/A | • Superior Performance in Outdoor Environments • Wa | ||
| FBR | (59) | FUJITSU | Relay(new original) | Note: 10. Test Conditions of Harmonic Intermodulation Suppression: | |
| FBS | (10) | 3.2 KSO8~15 These pins are direct output from the 8051 Port2 and dedicate | |||
| FBT | (18) | SG | 95+ | LO IN=-4dBm See note 1 and 2. Mixer Preamp ON Mixer Preamp OFF Mixe | |
| FBU | (4) | fag | n/a | The differential reference input features No-Reference detect capability | |
| FBW | (1) | (1) Ideal input span; does not include gain or offset error. (2) This i | |||
| FBZ | (1) | 66- or 133-MHz, 64-bit, true multifunction, intelligent bus master PCI- | |||
| F-C | (1) | ||||
| FC- | (57) | GTS | DIP | 99+ | Microprocessor loading is random access and asynchronous. Like parallel l |
| FC0 | (38) | Surface mount board layout is a critical portion of the total des | |||
| FC1 | (222) | SANYO | 08+ | • Message bit rates up to 1 Mbps • Conforms to CAN 2.0B ACT | |
| FC2 | (68) | CONEXANT | QFP | 00+ | The OPA342 series rail-to-rail CMOS operational amplifiers are designed |
| FC3 | (12) | TYCO | SOP | The block diagram (Figure 1) shows the parasite-powered circuitry. This ci | |
| FC4 | (11) | LUCENT | MODULE | N/A | The FIFO contains overflow circuitry to disallow additional writes when |
| FC5 | (10) | N/A | CAN12Pin | 08+ | Absolute maximum ratings define parameter limits which, if exceeded, may |
| FC6 | (7) | ALTERA | 05+ | BGA | The SecSi™ (Secured Silicon) Sector is an extra 256 byte sector ca |
| FC7 | (14) | MOT | SOP | 03+ | The HT818D0 has a built-in RC oscillator which requires only one extern |
| FC8 | (61) | SANYO | SOT-163 | 05+PB | completion of update Separate battery pin 2 4V operation |
| FC9 | (13) | SANYO | SOT-163 | 05+ | The Si9167 is a high-frequency synchronous dc-to-dc switching buck regu |
| FCA | (41) | N/A | N/A | N/A | The CBTS3253 is a dual 1-of-4 high-speed TTL-compatible FET multiplexer/ |
| FCB | (52) | FAIRCHILD | TO-263(D2PAK) | 08+ | International Rectifiers RADHardTM HEXFET® MOSFET technology provid |
| FCC | (75) | N/A | The 32K x 8 Radiation Hardened Static RAM is a high performance 32,768 | ||
| FCD | (30) | wickmann | wickmann | dc00 | Stresses beyond those listed under Absolute Maxi- mum Ratings may cause |
| FCE | (4) | 01 | Low-level control input voltage (C inputs)0 † Frequen | ||
| FCF | (58) | NIEC | TO-220 | 05+ | Sixteen-input data selector/multiplexer, with enable Eight-input data sel |
| FCG | (5) | MARUWA | 1206-333K 250V | Operating voltage: 2.2V~3.6V Ten bidirectional I/O lines Six schmitt tri | |
| FCH | (113) | NIEC | TO-220F | 06+ | 1. Corrected the errataJan. 10, 2005 2. Revised typical value of ISB from |
| FCI | (55) | N/A | |||
| FCJ | (5) | sie | sie | dc80 | This advanced BiCMOS design is pin compatible with the industry standard |
| FCK | (12) | SANREX | 04+ | ||
| FCL | (9) | NIHON | TO-220 | 08+ | The 100314 is a monolithic quint differential line receiver with emitter- |
| FCM | (100) | N/A | The ADS800 employs digital error correction to provide excellent Nyquis | ||
| FCN | (46) | fujitsu | fujitsu | dc99 | The ARF Series EMI filter has been designed to pro- vide full complianc |
| FCO | (7) | ||||
| FCP | (29) | CORNECC | 0805-222 | 05+ | Dual-Port RAM for 32-bit-or-more word systems. Using the IDT MASTER/SLAV |
| FCQ | (24) | The CD54AC374/3A and CD54ACT374/3A are octal D-type, three-state, posit | |||
| FCR | (143) | DAHZAN | 01+ | Composite Video Output A 75 Ω termination resistor with short trace | |
| FCS | (9) | AD | 06+/07+ | ||
| FCT | (130) | HARRIS | The MAX2654 operates in the GPS frequency of 1575MHz with 15.1dB of gain, | ||
| FCU | (18) | N/A | N/A | N/A | Note 2: Absolute maximum ratings are those values beyond which damage to |
| FCV | (3) | A MOSFET pass element delivers high output current with an input- | |||
| FCX | (104) | RIVER | SMB | 05+ | Note 3: The maximum allowable power dissipation is a function of the maxi |
| FCY | (2) | sie | sie | dc74 | The LVXC3245 is a 24-pin dual-supply, 8-bit configurable voltage interfa |
| FCZ | (8) | 38777 | The 1-Wire CRC is generated using a polynomial generator consisting of a | ||
| FD- | (88) | N/A | N/A | N/A | Information in this document is provided in connection with Conexant Syst |
| FD0 | (9) | 9725+ | SOP | DESCRIPTION The STV5346 decoder is a computer-controlled teletext devic | |
| FD1 | (180) | NSC | DIP14 | Advanced Process Technology Ultra low On-Resistance Provides Higher Effic | |
| FD2 | (45) | FAIRCHILD | QFP84 | 0046+ | NOTES: (1) Stresses above these ratings may cause permanent damage. Expo |
| FD3 | (49) | sgs | sgs | dc78+ | Supported by FPGA Foundation™ and Alliance Development Systems - |
| FD4 | (29) | Specifications Outline Dimensions Pin Connections and Short Description | |||
| FD5 | (21) | 1735 | The I2C bus is a simple two-wire bidirectional serial interface. It contr | ||
| FD6 | (42) | eupec | IGBT+DIO | Notes: 7. CPD is defined as the value of the internal equivalent capac | |
| FD7 | (19) | FUJITSU | DIP | 00+ | The Application Engineering group is available to assist you with the |
| FD8 | (24) | • CMD: is a bidirectional command channel used for card initializati | |||
| FD9 | (13) | IR | 2000 | 00+ | The MSP430x11x2 and MSP430x12x2 series are ultralow-power mixed signal mi |
| FDA | (36) | TOKO | To activate this mode, the programming equipment must force 12.0 V 0.5V | ||
| FDB | (178) | FAIRCHILD | TO-263 | 05+ | Motorola reserves the right to make changes without further notice to any |
| FDC | (563) | SMC | TQFP-100 | 97+ | The 11C90 and 11C91 are high-speed prescalers designed specifically for |
| FDD | (252) | LG | This circuit demonstrates the operation of a stepper motor, and | ||
| FDE | (4) | fct | fct | dc04 | Product Features: •25-bit 1:1 or 14-bit 1:2 configurable registere |
| FDF | (49) | N/A | Inputs Are TTL-Voltage Compatible Parallel Register Inputs/Binary Counte | ||
| FDG | (124) | FAIRCHILD | SOT-363 | 07+（ROHS） | 36 macrocells with 800 usable gates Available in small footprint packages |
| FDH | (59) | CAUTION: These devices are sensitive to electrostatic discharge; f | |||
| FDI | (16) | FAIRCHILD | TO-262(I2PAK) | 08+ | LINE BUILD-OUT: The Line Build-Out function controls the amplitude in DS |
| FDJ | (8) | FAIRCHIL | SC75-6 | 05+ | The MT8985 device provides both functions and allows existing systems base |
| FDK | (3) | FAIRCHILD | 05/06+ | Note: Stresses greater than those listed under MAXIMUM RATINGS may caus | |
| FDL | (73) | FAIRCHILD | The CS8920As Ethernet Media Access Control (MAC) engine is fully compli | ||
| FDM | (81) | FSC | Power 56 | 08+ | (1) For Tape & Reel Packaging, add a TR suffix to the end of the Part |
| FDN | (167) | FAIR | An on-chip Peripheral Data Controller (PDC) transfers data between the on | ||
| FDP | (191) | FAIRCHILD | TO-220 | 05+ | Synchronizer and Baud Rate Selection Linear Receive Strength Signal Indic |
| FDQ | (10) | N/A | SMD | 1996 | Ideal for space critical applications, the LM4040 precision voltage ref |
| FDR | (40) | FAIR | 12000 | 07+ | 64-Bit SDRAM interface 66 MHz to 100 MHz frequency range Direct inte |
| FDS | (1244) | FSC | with A10 defining auto precharge) to select one location out of the memor | ||
| FDT | (29) | 2008 | Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds260 (2 | ||
| FDU | (63) | FAIRCHILD | TO-251 | 08+ | International Rectifier does not recommend the use of this product in aer |
| FDV | (59) | N/A | Cellular - CDMA/FM/JCDMA Output Power-11-8dBm Output Frequency6001078MHz | ||
| FDW | (99) | FSC | TSS0P | 03+ | The VDP 313xY is a video IC family of high-quality sin- gle-chip video |
| FDX | (4) | FSC | SOP8 | 1999 | Note 4: TPPOS is a measure of transmitter output pulse position in compar |
| FDY | (10) | FSC | SC89 | 08+ | 1. Characteristics in stand-alone mode • 3-bit ADPCM •Sampli |
| FDZ | (30) | FAIRCHILD | BGA-6 | 06+ | Ground connection. For best performance, keep traces physically short an |
| F-E | (1) | The LT®3439 is a push-pull DC/DC transformer driver that reduces con | |||
| FE- | (7) | N/A | DIP8 | N/A | Extended Data Out (EDO) Operation CAS-Before-RAS ( CBR) Refresh High-Imp |
| FE0 | (14) | VICOR | MODULE | A buffered output-enable (OE) input can be used to place the eight outp | |
| FE1 | (22) | FAIRCHILD | SMD-8 | This document is a general product description and is subject to change wi | |
| FE2 | (61) | 04+ | Consider the simplified power op amp shown in Figure 1. Output transisto | ||
| FE3 | (46) | FARADAY | PLCC | 05+ | Stresses beyond those listed under absolute maximum ratings may cause per |
| FE4 | (1) | SANYO | SDIP-64 | 08+ | FEATURES • Normally Open, Single Pole Single Throw Operation ̶ |
| FE5 | (6) | gi | n/a | The information provided herein is believed to be reliable at press time. | |
| FE6 | (17) | The FE68B02CP is a low cost high speed JFET input operational amplifier | |||
| FE7 | (4) | N/A | SOP | N/A | The IDT72T4088/72T4098/72T40108/72T40118 are exceptionally deep, |
| FE8 | (7) | fee | fee | dc98 | Notes: 1. The anode side of the device is denoted by a hole in the |
| FE9 | (1) | TI | 33 | DIP | DR1 is available on the TP3070 only; DR0 is available on all devices. T |
| FEA | (3) | Freescale | 08+ | The A29L008 is an 8Mbit, 3.0 volt-only Flash memory organized as 1,048,57 | |
| FEB | (44) | SIEMENS | PLCC-44 | Forward-Current Transfer Ratio IC = 15 Adc, VCE = 4.0 Vdc | |
| FEC | (18) | LUCENT | NEW | 01+ | The RTC provides a set of continuously running counters driven by separat |
| FED | (3) | TO-3P | 07+ | PARAMETER Soft-Start Section Charge Current Power Good Section Fb1 Low | |
| FEE | (16) | UART channel B Receive Data or infrared receive data. Normal receive data | |||
| FEF | (6) | PHILIPS | 00+ | DIP | |
| FEG | (3) | fenwal | fenwal | dc74+ | Serial data input A/B. The serial information (data) received from seria |
| FEJ | (4) | TAI TIEN | 0639+ | NOTES 1Measured single-ended into 50 ý load. 2Output noise is mea | |
| FEL | (4) | ALCATEL | QFP-44 | 99 | |
| FEM | (10) | SAMSUNG | 04+ | ❇1This value can change due to the switching frequency, environmen | |
| FEN | (7) | GI | TO | Internal registers include available capacity, temperature, scaled avail- | |
| FEO | (2) | The ADE7763 provides a serial interface to read data and a pulse output | |||
| FEP | (105) | VISHAY | TO-3P | 07+ | Hynix HYMD232646A(L)8-M/K/H/L series is designed for high speed of up to |
| FER | (2) | The special built-in green functions allow the efficiency to be optimum | |||
| FES | (118) | GULF | TO-263 | 2007 | 180-240V AC input, 50/60 Hz 3-phase rectifier bridge 3-phase, short cir |
| FET | (37) | N/A | On-chip peripheral functions include a 16-bit free-running timer (FRT), 8 | ||
| FEU | (1) | Flexible control options for power management are available when the seri | |||
| FEV | (2) | 国产 | DIP | The Am29PDS322D is a 32 Mbit, 1.8 V-only Flash memory organized as 2,09 | |
| FEX | (1) | Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that | |||
| FEZ | (1) | schurter | schurter | dc02 | A HIGH level on MBB chooses a mailbox register for a Port B Read or Write |
| FF- | (2) | Stresses beyond those listed under absolute maximum ratings may cause per | |||
| FF0 | (28) | JAE | pins together. When the PE input is LOW, the LS195A appears as four comm | ||
| FF1 | (74) | EUPEC | 1000A,1700V | 07+特价模块 | There are two limitations on the power handling ability of a tran |
| FF2 | (36) | N/A | The IS25Cxx is enabled through the Chip Select pin (CS) and accessed vi | ||
| FF3 | (29) | 100 | 天龙伟业 | 靳先生 | |
| FF4 | (46) | ROHM | SSOP-16 | 2003+ | *On products compliant to MIL-PRF-38535, this parameter is not production |
| FF5 | (9) | EUPEC | SOP | !Features 1) Each high-performance filter, 6dB amplifier, and 75Ω d | |
| FF6 | (24) | The MAX1698 evaluation kit (EV kit) is a fully assembled and tested circu | |||
| FF7 | (7) | ! Economical cost, prompt delivery! ! Wide varieties of values ! Choice | |||
| FF8 | (17) | EUPEC | SOP | Notes: VZ is programmable from -2V to +7V. IOL & IOH programmable | |
| FF9 | (1) | INFINEON | PrimePack2 | 08+ | Data Bus, active High. In word mode, these pins provide a 16-bit |
| FFA | (83) | KA | TO- | Notes: 4. Test conditions assume signal transition time of 3 ns or | |
| FFB | (30) | FAIRCHILD | ★Original and new, Special price! | 08+ | The USB port of the EZ-USB AT2 is connected to a host computer directly o |
| FFC | (6) | MOTO | SMD | 2000 | Solderability: 90% coverage after 5 second dip in 235C solder following |
| FFD | (8) | 2.3 Order of precedence. In the event of a conflict between the te | |||
| FFE | (5) | tdk | tdk | dc96 | SMDI will provide the detailed layout (AutoCad format) to users wishing t |
| FFF | (2) | PIN DESCRIPTION This pin controls the gate of an external MOSFET f | |||
| FFG | (2) | DIP-28 | POWER MOS TECHNOLOGY 2A peak rating HIGH GAIN BANDWIDTH PRODUCT 150MH | ||
| FFH | (7) | KA | TO- | Sample tested during initial release and after any redesign or pro | |
| FFI | (1) | ORIGIN | SOD-6 | 05+ | For applications requiring other voltages, see LM150 series adjustable |
| FFK | (15) | This document is a general product description and is subject to change wi | |||
| FFL | (10) | KA | TO- | Device Addressing Following a start condition the master must output the | |
| FFM | (40) | RECTRON | 07+ | Information on this input is transferred to the internal data latches dur | |
| FFP | (195) | FAIRCHILD | TO-220 | 06+ | Screen tested 100% on each device at -55 C, +25 C and +125 C temp., subgr |
| FFS | (7) | SAMTEC | 08+ | No output filter required for inductive transducers Selectable gain of | |
| FFT | (1) | FREETECH | 03+ | 1 Life support devices or systems are devices or systems which (a | |
| FFV | (1) | ¡The circuit application examples in this publication are provided | |||
| FFY | (3) | 未提供 | 2008 | The CNY64/ CNY65/ CNY66 consist of a phototrans- istor optically couple | |
| FFZ | (2) | SAM | DIP24 | 07+ | Note: Stresses greater than those listed under "Absolute Maximum Rat |
| F-G | (1) | These N-Channel enhancement mode power field effect transistors are produ | |||
| FG- | (2) | HEADLINE | QFP-44P | 02+ | ADVANCE INFORMATION NOTE The product is in a development phase and specif |
| FG0 | (3) | 06+ | The Current Transfer Ratio (CTR) ranges from 100% to 200%. It also has an | ||
| FG1 | (15) | 1735 | KS7333 is a product used in video camera systems, such as camcorders and | ||
| FG2 | (11) | 1735 | The crystal or clock frequency chosen must be twice the required process | ||
| FG3 | (4) | 1735 | Power247™ PowerEdge™ PowerSaver™ PowerTrench® QF | ||
| FG4 | (7) | 1735 | (a full wave circuit has twice these efficiencies) As the frequen | ||
| FG5 | (1) | PHILIPS | Chip select. A high-to-low transition on CS resets the internal counters | ||
| FG6 | (9) | 1735 | • CATV Systems Operating in the 40 to 870 MHz Frequency Range • | ||
| FG8 | (1) | NOTES: 1. Dimensions are in inches. 2. Metric equivalents | |||
| FG9 | (6) | temperature range are assured by design, characterization and correlation | |||
| FGA | (45) | TSCM | O7+ | Furthermore, this circuit block compares the input signal to a threshold, | |
| FGB | (14) | FAIRCHILD | TO-263 | 08+ | RAM organized as 131,072 words by 16 bits. It is fabricated using 1+51's |
| FGC | (14) | MITSUBISHI | THY | Loop enable. When LOOPEN is high (active), the internal loop-back path is | |
| FGD | (4) | FSC | TO-252(DPAK) | 08+ | Figure 3 is a schematic of the FGD2N40L DEMO Card, and Figure 4 s |
| FGF | (1) | The serializer enters the high-impedance mode when the DEN pin is driven | |||
| FGG | (3) | Note: Human Body Model ESD test performance for this product was demonstr | |||
| FGH | (30) | FAIRCHILD | TO-247 | 08+ | HY57V561620C is offering fully synchronous operation referenced to a posit |
| FGI | (1) | INFINEON | 2008 | Third-Order IMD Input Voltage Noise Input Current N | |
| FGK | (1) | ＦＡＩＲＣＨＩＬＤ | AP1128 is a linear regulator designed as a cost-effective solution for ac | ||
| FGL | (20) | 97 | 116dB CMRR Independent of Gain Maximum Offset Voltage: 10µV Maximu | ||
| FGM | (2) | 100 | 天龙伟业 | 靳先生 | This is the gate drive output for the Main FET. The totem pole output ha |
| FGP | (29) | N/A | PLCC | 07+ | ♦ Adjustable Accurate DPWM Frequency with Sync Function |
| FGR | (6) | FSC | SSOT8 | Unicorn shipping package includes a complete set of field proven software | |
| FGS | (9) | INTEL | 00+ | For both the Write Lock and Write Configuration com- mands, part of the | |
| FGT | (2) | ZILOG | SMD | 95+ | Note 8: Skew is defined as the absolute value of the difference between t |
| FGV | (25) | N/A | N/A | 2004 | The actual performance of the circuit shown in Figure 4 is plotted in F |
| FGW | (3) | FSC | TSSOP8 | Once activated, the link-on output will continue active until the LLC be | |
| FH- | (12) | ZIP-15P | Notes: 3. CL includes probe and jig capacitance. 4. All inp | ||
| FH0 | (13) | N/A | N/A | Positive excursions of input voltage may exceed the power supply level. A | |
| FH1 | (282) | HRS | 07+ | Hynix HYMD216M726A(L)6-J/M/K/H/L series is unbuffered 200-pin double data | |
| FH2 | (40) | M/A-COM | High current sink/source 25 mA/25 mA Four external interrupt pins Time | ||
| FH3 | (3) | F3 | QFP | 05+ | Clock output traces should use series termination. To series terminate |
| FH4 | (55) | 10 | NEC | 9021 | The Constant, B, related to the failure mechanism is derived from either |
| FH5 | (1) | The CPU features two sets of functional units. Each set contains four uni | |||
| FH6 | (5) | 00+ | selectable genuine 10-bit A/D converter with 8 multiplexed inputs Ful | ||
| FH7 | (2) | PECL, LVPECL, ECL, LVECL, HSTL Clock or Data Inputs. Internal 75kΩ | |||
| FH8 | (1) | 96 | The ADSP-21365/6s two data address generators (DAGs) are used for indire | ||
| FH9 | (1) | SOP | 05+ | DESCRIPTION This Power Mosfet is the latest development of SGS-THOMSON | |
| FHA | (17) | TOS | SMD | Hynix HYMD512G726(L)4-K/H/L series is designed for high speed of up to 133 | |
| FHB | (9) | JAT | 0805-121 | 05+ | QEB125 single output DC/DC converters provide up to 125 watts of output po |
| FHC | (14) | N/A | Fast Function Blocks The Fast Function Block has 24 inputs which can be | ||
| FHD | (4) | N/A | 07+ | N/A | |
| FHE | (1) | MOT | PLCC52 | 07+ | Philips provides a sophisticated API running on the internal 80C51, all |
| FHF | (1) | WJ | SOT-89 | 02+ | • Same form, fit, and function as SSTL16877 • Full DDR 200/266 |
| FHG | (2) | 06+ | PLCC-68 | has a shorter erase time; the total energy consumed during any Erase or | |
| FHI | (2) | INTERSIL | QFN | N/A | |
| FHK | (1) | 04+ | SOT-3 | The relay control output is an open-collector Darlington circuit with an | |
| FHL | (3) | N/A | † Stresses beyond those listed under absolute maximum ratings may c | ||
| FHM | (2) | ROHM | QFP | The GND terminals of the ISL6537A provide the return path for the VTT LDO | |
| FHN | (5) | tosh | tosh | dc98 | The available range of SPD series pressure sensors allows for a wide rang |
| FHP | (26) | FS | 07+ | The SDA 525x contains a slicer for TTX, VPS and WSS, an accelerating acqu | |
| FHR | (4) | FUJI | 1. Be sure to connect the amplifier to 50 Ω RF in/ out cabl | ||
| FHS | (10) | MOT | SOP-28 | 96+ | To reset the VTRIP voltage, apply a voltage between 2.7 and 5.5V to the |
| FHT | (14) | FENGHUA | N/A | N/A | CDIM (Pin 1): Dimming Capacitor. Connect the pin to GND with a 0.022&micr |
| FHV | (1) | FENGHUA | N/A | N/A | International Rectifiers R6 technology provides superior power MOSFETs |
| FHW | (38) | N/A | 0805L | Flexible control options for power management are available when the seri | |
| FHX | (40) | FUJI | to minimize the number of control pins, 3-level inputs (HIGH-MID-LOW) ar | ||
| FHY | (3) | FUJ | 2005+ | BGA35*35 | |
| FHZ | (2) | PHI | SMD | 04+ | The read operation of the W29EE512 is controlled by #CE and #OE, both of |
| FI- | (161) | CERATECH | Attention please! The information herein is given to describe certain co | ||
| FI0 | (1) | FUJI | 06+ | SOP | By providing external feedback, the FI005-TE16B gives users flexib |
| FI1 | (12) | FAIRCHILD | 05/06+ | Crystals can be made to resonate either at the fundamental frequency, o | |
| FI2 | (7) | APPLICATION NOTES POWER CONSIDERATIONS Each output has an | |||
| FI3 | (3) | FI | DIP-5 | 07+/08+ | Pb−Free Package is Available Highly Stable Oxide Passivated Juncti |
| FI6 | (1) | Provides real time clock: − Counts seconds, minutes, hours, date | |||
| FI7 | (4) | 97 | LCD voltage calibration Manufacturer identity Seal bit One time progr | ||
| FI8 | (2) | TEM | 491 | FEATURES 225 ps Propagation Delay through the Switch 4.5 Switch Connect | |
| FI9 | (1) | The TLK4250 device is a four-channel, multi-gigabit transceiver used in h | |||
| FIA | (18) | FAIRCHILD | SOP | 07+ | Edition 1997-08-01 Published by Siemens AG, Bereich Halbleiter, Marketin |
| FIB | (6) | IR | TO-220 | Case: JEDEC DO-214AA molded plastic body Terminals: Solder plated, solder | |
| FIC | (15) | PQFP | 97+ | The conditional skip is activated by instruction. Once the condition is m | |
| FID | (13) | ST | DIP | 07+ | • 3.3V LOW VOLTAGE, ZERO POWER OPERATION JEDEC Compatible 3 |
| FIE | (2) | SIERAWIRELESS | QFP-80 | 01 | • Less current drain. • Accept 16Ω load drive. • |
| FIF | (1) | The internal circuit is composed of 3 stages including buffer output, wh | |||
| FIG | (1) | 1735 | The attached datasheets are provided by SAMSUNG Electronics. SAMSUN | ||
| FIH | (1) | 325 | Three key features make current-feedback amplifiers outstanding for aud | ||
| FII | (7) | IXYS | 1. Hitachi neither warrants nor grants licenses of any rights of Hitachis | ||
| FIL | (11) | FiLe | DIP | 3. The maximum allowable power dissipation of any TA (ambient temperature) | |
| FIM | (11) | HM | DIP | 2006 | At turn-on, the external gate capacitor of the N-Channel MOSFET is charge |
| FIN | (169) | FS | 07+ | The bq26220 works with the host controller in the portable system to im | |
| FIO | (2) | YUAN | QFP | 97+ | Table 1. Bluetooth Mini module interface definitions Pin#NameTypeN |
| FIP | (16) | nec | nec | dc90 | I/O port with bit-programmable pins; Schmitt5 trigger input or push-pul |
| FIR | (3) | Mechanical Characteristics • Reel Options: MBR0530T1 = 3,000 per 7 | |||
| FIS | (16) | HARRIS | 01+ | TO-263 | An on-chip oscillator eliminates the need for an external crystal oscilla |
| FIT | (17) | The attached datasheets are prepared and approved by SAMSUNG Electr | |||
| FIW | (1) | low insertion loss, 0.8 dB typ. excellent amplitude unbalance, 0.15 dB | |||
| FIX | (3) | ALTERA | SMD | 06+ | In environments that are particularly noisy it may be neces- sary to add |
| FIZ | (1) | MaverickKey unique hardware programmed IDs are a solution to the growing | |||
| F-J | (1) | FORSTAR | N/A | Item Bypass pin voltage (H) Bypass pin voltage (L) | |
| FJ- | (2) | PLCC44 | 03/+04+ | Receive synchronizing signal input. Eight required bits are selected from | |
| FJ0 | (3) | ST | 06+ | 6300 | Single-chip powerline networking controller with IEEE802.3u MII interfac |
| FJ1 | (5) | FJ | PLCC | 00+ | The device will support SVHS mode for three encoder interface formats. Th |
| FJ2 | (4) | ST | PLCC | The FJ2314BCE is a stereo audio power amplifier primarily designed for | |
| FJ3 | (2) | • Low power CMOS technology - Maximum write current 3 mA at | |||
| FJ9 | (2) | TDK | For example, S/H1 should not be commanded into the sample mode until al | ||
| FJA | (51) | FAIRCHILD | TO-3P | 08+ | Because the PMOS device behaves as a low-value resistor, the dropout volt |
| FJB | (4) | FAIRCHIL | TO-263 | 07+ | This document is a general product description and is subject to change wi |
| FJC | (18) | FAIRCILD | SOT-89 | 06+ | Features • Resistant to High Humidity and Common Automotive Media |
| FJD | (7) | FAIRCHIL | TO- | Virtex devices provide better performance than previous generations of | |
| FJE | (7) | FAIRCHILD | TO-126 | 08+ | MPC8xx core that incorporates memory management units (MMUs) and instruct |
| FJH | (4) | FS | 07+ | +15V - is the low voltage supply for all the internal logic and isolated | |
| FJL | (12) | FS | 07+ | The following specifications apply for AGND = DGND = DGND(I/O) = 0V, VA = | |
| FJM | (4) | FAI | DIP | 86 | When operating properly with 5V in (for example), VOUT will also be abou |
| FJN | (61) | FAIRCHILD | 2005 | A MEMSIC accelerometer is most sensitive to changes in position, or til | |
| FJP | (94) | FAIRCHILD | TO-220 | 08+ | The 74HC/HCT158 are quad 2-input multiplexers which select 4 bits of da |
| FJS | (1) | ||||
| FJT | (6) | Where TJ = Junction Temperature PD = Total Power Dissipati | |||
| FJV | (37) | FAIRCHILD | 07+ | The output at pin 5 is at a ÒhighÓ state when the PLL is ou | |
| FJX | (53) | FAI | SOT-323 | 05+ | The highly integrated ISD1000A Series contains all the basic functions re |
| FJY | (9) | FSC | SOT-523F | 08+ | |
| FJZ | (5) | FAI | SOT-523 | 05+ | The A3946 is designed specifically for applications that req |
| FK- | (5) | MINI | 08+ | The UART transmits data, sent to it over the peripheral 8-bit bus, on the | |
| FK0 | (3) | MIT | DIP16 | Loss of Lock indicator output. 4 Logic 1 indicates loss of lock. | |
| FK1 | (43) | MITSUBIS | TO- | In such cases a mechanical shutter is needed to shield the array from inc | |
| FK2 | (26) | MIT | TO-220 | 06+ | The popular 1N5985 thru 1N6031 series of 0.5 watt Zener Voltage Regulators |
| FK3 | (11) | PCS | 2008 | Note 7 Tested limits are guaranteed to Nationals AOQL (Average Outgoing Q | |
| FK4 | (1) | ST | SOT23-5L | † Stresses beyond those listed under absolute maximum ratings may c | |
| FK5 | (1) | 2008 | The digital visual interface (DVI) specification is an industry standard | ||
| FK6 | (1) | ZNR | 06+ | Synchronization and shutdown pin. This pin may be used to synchronize the | |
| FK7 | (5) | TI | QFP | 05+ | improve its serial transmission characteristics. These encoded character |
| FK8 | (1) | TFK | ZIP7 | 2007+ | Disclaimer: The contents of this document are subject to change without n |
| FK9 | (2) | TEMIC | 2007 | *COMMENT Stresses above those listed under Absolute Maximum Ratings may | |
| FKB | (1) | MOT | TSOP8 | 05+ | Battery Life Logic Level Gate Drive − Can Be Driven by Logic ICs |
| FKC | (43) | 1360 | can default to one of four preselected offsets Dedicated serial clock inp | ||
| FKD | (7) | 256-byte SecSi™ (Secured Silicon) Sector Factory locked and | |||
| FKF | (2) | The FKF2454I is a peripheral device which interfaces to almost any Liquid | |||
| FKI | (5) | MOT | 2008 | which includes the control and status registers of the on-chip peripher | |
| FKK | (2) | S | SOP-14P | 91+ | Lead temperature, Tsol, 1,6 mm (1/16 inch) from case for 10 seconds |
| FKM | (1) | 10 X 1000 ms, nonCrepetitive 1 square copper pad, FRC4 board FRC4 boar | |||
| FKN | (3) | FAIRCHILD | 06+ | Device logic is automatically configured to the users speci- ʂ | |
| FKP | (123) | wima | wima | dc99 | Note 1: Absolute Maximum Ratings are those values beyond which the life |
| FKS | (43) | wima | wima | dc96 | Figure 4 illustrates the differential or gauge configuration in t |
| FKT | (2) | Each of these Schottky-clamped data selectors multiplex- ers contains in | |||
| FKV | (4) | SANKEN | 06+ | 3/TO-263 | product terms per output. Of the 16 outputs, 8 outputs have 4 product t |
| FL- | (7) | DIP | 93/94 | The differential inputs D_, D_ can be configured to accept a single-ende | |
| FL0 | (33) | SPMSION | SOP-8 | 05+ | The CMPIN pin drives data slicer DS1, which convert the analog signal fro |
| FL1 | (76) | VALOR | 1997 | DIP | VCC IOUT Short Circuit protected to ground. Maximum reliability is ob |
| FL2 | (9) | IOR | TSO-229 | 06+ | mable process. In addition, the chip offers various pack- aging for flexi |
| FL3 | (23) | N/A | 1206L | C40 >Ta > +85 C Over Vin range Over Io range Includes set-point, | |
| FL4 | (16) | CRYSTAL | The HR300 parts use the same manufacturing procedures and quality contro | ||
| FL5 | (6) | MIT | TO-220F | 04+ | 2nd generation HighSpeed-Technology for 1200V applications offers: - los |
| FL6 | (4) | The battery can also be set into a quasi-over-discharged state even when | |||
| FL7 | (6) | TEMIC | 2008 | If the centering error is less than 25 ppm, no adjustment is needed. If | |
| FL8 | (3) | 97 | All outputs are capable of driving 2Vpp, AC or DC coupled, into either a | ||
| FL9 | (4) | IOR | TSO-223 | 05+ | Maximum Recurrent Peak Reverse Voltage Maximum RMS Bridge Input Voltage |
| FLA | (30) | JAT | 05+ | The processors divide/multiply function contains all the instructions of | |
| FLB | (3) | Output data enable C Used to indicate time of active video display versus | |||
| FLC | (114) | RIVER | 3R3-3225 | Notes: 1. CL = Load capacitance: includes jig and probe capacitance. | |
| FLD | (73) | FUJ | 0 | The OPA682s low 6mA supply current is precisely trimmed at 25C. This tri | |
| FLE | (45) | 01 | SIGNAL DESCRIPTIONS See Figure 2 and Table 1. Address Inputs (A0-A16). | ||
| FLF | (5) | The injection-current effect control allows signals at disabled analog in | |||
| FLH | (35) | SIEMENS | DIP | This is a dual function pin. In the IDT Standard mode, the FF function is | |
| FLI | (93) | GENESIS | 0449+ | Analog Input CMRR Leakage Current at 25C Input Impe | |
| FLJ | (47) | sie | sie | dc76 | Differential analog input pins. With a 1.0V reference voltage the differ |
| FLK | (20) | FUJI | The Hitachi HM62V8100I Series is 8-Mbit static RAM organized 1,048,576-wo | ||
| FLL | (113) | FUJITSU | 02+ | and Chip Erase, Erase Suspend and Resume are written to the device in c | |
| FLM | (115) | Eudyna | 射频管 | The SC-A1460 Series of quartz crystal oscillators provide enable/disable | |
| FLN | (4) | FCS | 05+ | Gain Bandwidth Product: 2 MHz (typ.) Supply Current: IQ = 170 µA | |
| FLO | (2) | Should the system reset, while a Block or Sector Erase or Word Program is | |||
| FLP | (3) | YONGYUT | QFP-32P | 02+ | The 5T929 will lock to, and track, a valid CLKIN signal; LOCK wil |
| FLQ | (2) | sie | sie | dc80 | The FLQ125 is a 2.5-GHz mixer for WLAN and RF telecommunications equipmen |
| FLR | (18) | The PS381 has two normally open (NO) switches. The PS383 is a dual, singl | |||
| FLS | (35) | PHILIPS | 98+ | TSOP20 | The system clock inputs. All address and command lines are sampled on the |
| FLT | (68) | 2 | 03+ | INTERSIL | Glueless Interface Between the Peripheral Component Interconnect (PCI) Bu |
| FLU | (20) | FUJI | The FLU073XJ is an advanced high speed CMOS 2Cinput OR gate fabri | ||
| FLV | (5) | 319 | s 16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package. s 8 | ||
| FLX | (8) | Eudyna | 高频管 | The BS616LV4018 is a high performance, very low power CMOS Static Random | |
| FLY | (21) | sie | sie | dc74 | The ADuC842 also incorporates additional analog functionality with two 1 |
| FLZ | (32) | FAIRCHILD | 06+ | The EC000 core offers sixteen 32-bit registers and a 32-bit program count | |
| FM- | (18) | OPTO-SENSOR | 06+ | Note: Agilent Technologies encoders are not recommended for use in s | |
| FM0 | (14) | MOT | 98 | Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. | |
| FM1 | (199) | FAIRCHILD | SOT-23 | 06+ | Byte program and Chip erase Auto program and Auto erase Program/erase |
| FM2 | (619) | RECTRON | 07+ | The third, transient power due to internal capacitance takes exactly the | |
| FM3 | (213) | RECTRON | 07+ | Each Address ALU can update one address register from its respective addr | |
| FM4 | (129) | RECTRON | 2008+ | Notes: 1. Measurements at 900MHz were made using an ICM fixture with a do | |
| FM5 | (96) | FORMOSA | 06/07+ | • 64 8 RAM • 16-bit auto reloadable counter/timer • 5-c | |
| FM6 | (17) | FM | SOP-8 | 07+ | 500Msps Conversion Rate 7.0 Effective Bits Typical at 250MHz 1.2GHz Anal |
| FM7 | (25) | INTERPOINT | 模块6 | 96/99+ | Notes: a. Signals on SX, DX, or INX exceeding V+ or VC will be clamped & |
| FM8 | (72) | FAIRCHILD | SOT-23 | 06+ | Note 9: If the product is in shutdown mode and VDD exceeds 3.6V (to a max |
| FM9 | (179) | FSC | SOP8 | 99+ | Thus the first step in designing the antenna circuit is to measure the b |
| FMA | (69) | ROHM | SOT-153 | 05+ | The SN74CB3T16211 is organized as two 12-bit bus switches with separate o |
| FMB | (103) | SANKEN | TO-220F | 04+ | • 2A/3.3V, 5V, 5.1V, 9V, 12V output low dropout voltage reg |
| FMC | (168) | FUJITSU | (LX)high-frequency | The 18-bit FMC1819L2005/126 bus-interface flip-flop is designed for 2.3V | |
| FMD | (34) | FDS | O7+ | The Fairchild Power Switch(FPS) product family is specially designed for | |
| FME | (18) | SANKEN | TO-220F | 04+ | To improve the performance of both Bluetooth and 802.11b/g co-located sys |
| FMF | (1) | AND Flash Memory: (2048 + 64) bytes (More than 16,057 se | |||
| FMG | (164) | SANKEN | TO-3P | 08+ | will vary with supply voltage, switching frequency and the external MOSFE |
| FMH | (3) | FSC | TO3P | 05+ | The g-cell is a mechanical structure formed from semiconductor m |
| FMI | (3) | (LX)high-frequency | The FAN2500/01 allows the user to utilize a wide variety of capacitors c | ||
| FMJ | (2) | 三肯 | TO-220 | 05+ | Description The HSDL-3612 is a low-profile infrared transceiver module |
| FMK | (21) | FAIRCH | SMD | 00+ | Software features Program Suspend & Resume: read other sector |
| FML | (59) | ROHM | SOT-153 | 06+NOPB | The ST70138 is supplied in two packages, TQFP144 and LBGA80. The ST7013 |
| FMM | (518) | FAIRCHILD | 99+ | The K4S560432E / K4S560832E / K4S561632E is 268,435,456 bits synch | |
| FMN | (11) | ROHM | SOT-153 | The EP7311 uses its powerful 32-bit RISC processing engine to implement | |
| FMO | (6) | PHI | 00+ | SOP | PROPAGATION DELAY TIME: tPD = 40ns (TYP.) at VDD = 10V CL = 50pF HIGH |
| FMP | (55) | ROHM | SOT-153 | The Am79Q02/021/031 Quad Subscriber Line Audio- Processing Circuit (QSL | |
| FMQ | (37) | ROHM | SOT-153 | 05+ | When battery charging is initiated, the charger enters the prequalificati |
| FMR | (8) | N/A | 05+ | TO | RF and LO frequency range coverage from 400 to 3500 MHz and IF coverage |
| FMS | (179) | FAIRCHILD | 05/06+ | Table 2-0007A/2096V1. One output at a time for a maximum duration | |
| FMT | (5) | TONYO | SOP | 0515+ | Hynix HYMD132725B(L)8J-J series incorporates SPD(serial presence detect). |
| FMU | (41) | ROHM | SOT-153 | 05+ | The 16-bit processor is designed for efficient data execution by having di |
| FMV | (4) | LTEC | |||
| FMW | (58) | ROHM | SOT-153 | Short lead time, since the P2ROM is programmed at the final stage | |
| FMX | (34) | If necessary, a REF instruction can be circumvented by means of a skip ope | |||
| FMY | (30) | ROHM | The HYM72V32C736T8 Series are Dual In-line Memory Modules suitable | ||
| FMZ | (1) | ROHM | 05++ | SOT-153 | The bus controller is responsible for generating 20 bits of address read |
| FN- | (4) | 9122 | All channels nominally accept AC coupled 1Vpp signals. Select- able 0dB | ||
| FN0 | (5) | TO | Fairchild | 99+ | FUNCTION SWITCHING The device provides functions switching pins for both |
| FN1 | (118) | TO-18 | 99+ | The FCT374T devices are high-speed, low-power, octal D-type flip-flops, f | |
| FN2 | (35) | FUNCTION | DIP-20 | 00+ | This document is a general product description and is subject to change wi |
| FN3 | (47) | SANREX | 04+ | Output Power at 3Ω Load - 2W/ch at VDD=5V - 800mW/ch at 3V Low | |
| FN4 | (33) | SCHAFFNEER | |||
| FN5 | (10) | VISHAY | CAN4 | CLBs provide the functional elements for implementing the users logic. | |
| FN6 | (20) | ORIGIN | DO-214 | 1. Corrected the errata 2. Updated DC parameters to RMS Values 3. Revise | |
| FN9 | (17) | ST | BGA | Output skew with respect to the REF input is adjustable to compens | |
| FNA | (7) | NS | SOP | 06+ | Any commands written to the chip during the embedded programming cycle wi |
| FNB | (2) | PLCC69 | PROPAGATION DELAY Propagation delay for all 54C/74C devices is guarantee | ||
| FND | (33) | ROHM | QFP/48 | 96+ | 2.7 V to 3.6 V power supply 5 V tolerant digital inputs 24-bit data p |
| FNE | (2) | Composite type with an N-Channel Sillicon MOSFET unit : mm | |||
| FNF | (2) | The Montreal Protocol ( 1987) and its London Amendments ( 1990) intend to | |||
| FNG | (5) | MXIC | SOP/44 | 01+ | Stresses beyond those listed under "absolute maximum ratings" m |
| FNI | (2) | NEC | High-speed consumer electronic ports ESD protection of PC ports, includ | ||
| FNM | (13) | GENERAL FEATURES Programmable DAC Gain Control Sync Outputs in All Modes | |||
| FNP | (2) | Input Filter: To facilitate the high output fast trqansient performance, | |||
| FNQ | (25) | The LVTH18512 and LVTH182512 scan test devices with 18-bit universal bus | |||
| FNR | (8) | SOP | 05+ | Power supply voltage +13V, 0V or +5V, -8V Built-in polarity ID circuit B | |
| FNT | (1) | ST | QFP | 99 | Note 4: C PD is defined as the value of the internal equivalent capacitan |
| FNW | (2) | 4.3 Screening (JANTX AND JANTXV levels only). Screening shall be in | |||
| FO2 | (2) | Hardware compliant with IEEE Std. 1532 in-system programmability (ISP) s | |||
| FO8 | (3) | Description SS2 Spread Spectrum control bit (0=down spread, 1=Center spr | |||
| FO9 | (2) | Maximum ratings are those values beyond which device damage can occur. M | |||
| FOA | (11) | The SPT5230 voltage output will swing from +3.0 V to +4.99 V for VCS2 = | |||
| FOB | (1) | FAIRCHILD | V434Y | The write all (WRALL) instruction programs all registers with the data | |
| FOC | (3) | The Secured Silicon Sector is an extra sector capable of being permanentl | |||
| FOD | (480) | FAIRCHILD | 04/05+ | Drain-to-Source Breakdown Voltage Gate Threshold Voltage ➃ Gate | |
| FOG | (2) | The memory array of the FOG8894 can be sectored in two ways simply by usi | |||
| FOJ | (2) | The VHC125 contains four independent non-inverting buff- ers with 3-STAT | |||
| FOL | (37) | FAIRCHILD | 05/06+ | Each PIC block encompasses two PIOs (PIO pairs) with their respective sys | |
| FOM | (1) | FAIRCHILD | 05/06+ | Thermal Sensitive Layer Over a 0.35 µm CMOS Array Image Zone: 0.4 x | |
| FON | (4) | All voltages are referenced to ground (GND). Positive currents fl | |||
| FOQ | (3) | The HYM7V65801B F-Series are Dual In-line Memory Modules suitable for easy | |||
| FOR | (14) | TO92 | TOSHIBA | 03+ | Device erasure is performed on a block basis and occurs by executing the |
| FOS | (4) | TQFP1010-44 | 02+ | Changes in field strength at the device face caused by a moving tar | |
| FOX | (66) | FOX | 2007+PB | Under normal start-up conditions, devices will not begin to regulate until | |
| F-P | (3) | TSOP | 1997 | and sets the output buffer in the 3-state condition. MR can be left fl | |
| FP- | (17) | SHARP | QFP | 2004 | The AT40KAL is designed to quickly implement high-performance, large gate |
| FP. | (1) | MOT | PLCC52 | 07+ | • Programmable output from 2.1V to 3.5V using integrated 4- |
| FP0 | (29) | DL | 06+/07+ | NOTES: 1. For conditions shown as Min. or Max., use the appropriate valu | |
| FP1 | (172) | These unconditionally stable amplifiers are designed for use as general | |||
| FP2 | (105) | SANYO | SOT89-7 | 05+ | The device also features split output bank power supplies which enable |
| FP3 | (41) | SANYO | SOT89-7 | 05+ | Maximum Transmission Rate 200 RS-232 RECEIVER Input Voltage Range-15 |
| FP4 | (23) | SANYO | 2008 | The main counter, Nominal Available Capacity (NAC), represents the availa | |
| FP5 | (56) | N/A | N/A | N/A | RST Pin The RST pin is normally driven high and will be clocked |
| FP6 | (36) | SANYO | SOT89-5 | 06+ | Peak RF input level, pin RFIN, to overload the demodulator with the AGC o |
| FP7 | (14) | DIP | After determining which clock edge to use, a start and stop bit, appended | ||
| FP8 | (5) | SANKEN | TO220F | During the rise and fall time interval when switching a resistive load, | |
| FP9 | (3) | NS | LLP | Digital feedthrough error is defined as the area of the impulse injected | |
| FPA | (16) | GPS | 06+ | PLCC-68 | HY57V561620 is offering fully synchronous operation referenced to a positi |
| FPB | (8) | FSC | SMD模块 | 04+ | Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pullups. |
| FPC | (18) | *Stresses greater than those listed above may cause permanent damage to th | |||
| FPD | (83) | Filtr | (LX)high-frequency | The OPA681 sets a new level of performance for broadband current feedbac | |
| FPF | (87) | FS | 07+ | Free E86 family information such as data books, users man ual s , data | |
| FPG | (2) | PLCC | N/A | Typical Values, TA = 25˚C Input Offset Voltage1mV max TCVos (FPGA | |
| FPH | (10) | 4PIN | • automotive - AC drives - starter generator for 12/ | ||
| FPI | (9) | JAT | 3M-100K | 05+ | • Benchmark Efficiency Above 20KHz • Optimized for Welding, |
| FPJ | (1) | the device has a Sector Protect function which hardware write protects | |||
| FPK | (15) | Red Negative Analog Input No Connect, (Note 5) Green Positive Analog | |||
| FPL | (3) | The UCC3808A is a family of BiCMOS push-pull, high-speed, low-power, puls | |||
| FPM | (2) | ALTERA | PQFP100 | 00+ | Broadcom®, the pulse logo, and Connecting everything®, and QAMLink |
| FPN | (17) | PHI | QFP44 | 01+ | Each FPM transmits and receives data at the full Fibre Channel r |
| FPP | (8) | ORIGIN | SOD-123 | 05+PB | 2-, 3-, or 4-Cell Series Protection Control Can Directly Interface With t |
| FPQ | (11) | FA… | † Stresses beyond those listed under absolute maximum ratings may c | ||
| FPR | (2) | FAIRCHILD | SOP14 | 1997 | Ground Rail. +3.3 Volt Power Supply. This active LOW output indicates th |
| FPS | (14) | YAMAICHI | 04+ | 1. To achieve specified performance, all power supply pins should | |
| FPT | (12) | 027 | Notes: 1. For conditions shown as Max. or Min., use appropriate value sp | ||
| FPW | (1) | The MTC50150 is a low cost ADSL bridge and LAN router. One 10/100Mbits Et | |||
| FPX | (32) | This EOL notification announces the cessation of manufacture of the device | |||
| FQ0 | (1) | Hitachi | NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X | ||
| FQ1 | (50) | PHILIPS | The LPS (link power status) terminal works with the S5_LKON terminal to m | ||
| FQ2 | (17) | N/A | PLCC | 07+ | crystal-less jitter attenuator with a 32 or 64 bit FIFO can be placed e |
| FQA | (177) | FIFO status flags monitor the extent to which each FIFO buffer h | |||
| FQB | (320) | FAIRCHILD | TO | This is the active high output drive signal for the (first) phase A win | |
| FQC | (1) | FSC | TO-220 | 0728vgc+ | When setting S1 at a high level or S2 at a low level, the chip are |
| FQD | (275) | FAIRCHILD | 00+ | The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 | |
| FQF | (4) | FAIRCHILD | TO-220F | 04+ | ia SELECT A [1]K€Ú7ñ AUDIO ØË ï |
| FQG | (4) | FSC/仙童 | DIP8 | 05环保 | • RKE - Remote Keyless Entry. • PKE - Passive Keyless Entry. |
| FQH | (12) | 仙童 | 06+ | TO-3P | footprint. The drain copper area is 0.0019 sq. in. (or 1.22 sq. mm). Thi |
| FQI | (244) | FAIRCHILD | TO-262(I2PAK) | 08+ | • Viewing Angles Match Traffic Management Sign Requi |
| FQL | (24) | N/A | QFP-46 | Conceptually, the port clocks CKA and CKB are free- running, perio | |
| FQN | (8) | HBA | 04+ | Parameter VDD to GND RFB, ROFS, R1, RCOM, and VREF to GND Logic Inputs | |
| FQP | (451) | FAIRCHILD | TO-220 | 05+ | Watchdog Timer The Watchdog Timer circuit monitors the microprocessor a |
| FQR | (1) | An integrated soft-start feature brings all outputs into regulation in a | |||
| FQS | (7) | FSC | SOIC | 08+ | Any and all SANYO products described or contained herein do not have speci |
| FQT | (23) | FAIRCHIL | TO- | GHz TECHNOLOGY, INC. RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER N | |
| FQU | (167) | FAIRCHILD | TO-251(IPAK) | 08+ | |
| FQV | (44) | HBA | BGA | Guaranteed Low Skew < 25ps (max) Very low duty cycle dis | |
| FQY | (3) | 仙童 | 06+ | TO-3P | I.2 - Read Operation The address of the first register to read is progra |
| F-R | (1) | ||||
| FR- | (27) | SOP | Beneficial comments (recommendations, additions, deletions) and any pertin | ||
| FR0 | (9) | 38 | TO252 | 04+ | Hynix HYMD264G726(L)4M-K/H/L series incorporates SPD(serial presence detec |
| FR1 | (127) | The HUB/HOST input changes the reference signal for the clock generator. | |||
| FR2 | (43) | MIC | DO-15 | 2008+ | The FR207 is capable of driving a Flash LED with a pulsed current of 40 |
| FR3 | (81) | M/A-COM | Features 1) Synchronous rectification enables high efficiency 2) Built- | ||
| FR4 | (8) | Figure 2 shows the outline and pin-out descriptions for the packaged devi | |||
| FR5 | (8) | RL | 07/08+ | Note 1: All voltages are with respect to GND. All currents are positive | |
| FR6 | (15) | MIC | R-6 | 2008+ | The ZL5011x is capable of assembling user-defined packets of TDM traffic |
| FR7 | (2) | 1735 | Replace any reference to Flash Interface Unit with Flash Module, added not | ||
| FR8 | (10) | RECTRON | TO-220 | 04+ | The data contained in the data stream can also affect lock time. If a spe |
| FR9 | (17) | 72 | TO252 | 04+ | Undervoltage Lockout UVLO (undervoltage lockout) prevents the output MOS |
| FRA | (18) | TSC | TO-220 | 2008+ | Each device requires only a single 3.0 volt power supply for read, progra |
| FRB | (4) | ztx | ztx | dc95 | The MT8985 master clock (C4i) is a 4.096 MHz allowing serial data link con |
| FRC | (13) | All typical values are at VCC = 3.3 V, TA = 25C. This is the bus-hold m | |||
| FRD | (68) | N/A | Stability The IRU1015 requires the use of an output capacitor as part of | ||
| FRE | (15) | JAT | 402 | 05+ | Har d war e Res et , ac t iv e L o w. Provides a hardware method of reset |
| FRF | (14) | TAIWAN | TO-220 | 08+ | In the Bellcore SR-TSV-002476 Issue 1 off-hook protocol, the CPE should n |
| FRG | (16) | THOMSON | 02+ | The digital receiver has four reconfigurable channels and provides extra | |
| FRH | (6) | NIHON | TO-220 | 06+ | Description Digital VDD (for Output Drivers) Data Output Bit 0 Data O |
| FRI | (7) | SMB | 2 PHASE OPERATION WITH SYNCRHONOUS RECTIFIER CONTROL ULTRA FAST LOAD | ||
| FRJ | (32) | ＶＩＳＨＡＹ | Notes: 1. NC pins are not connected to the die. 2. E3 (DNU) | ||
| FRK | (3) | HARRIS | 04+ | RXD_0[1:0] RXD_1[1:0] RXD_2[1:0] RXD_3[1:0] RXD_4[1:0] RXD_5[1:0] RX | |
| FRL | (21) | N/A | N/A | N/A | Notes: Stresses greater than those listed under MAXIMUM RATINGS may caus |
| FRM | (30) | FUJITSU | 光纤 | RESET: This is an active high input which clears the Command, Status, Req | |
| FRN | (52) | N/A | N/A | N/A | • IN-SYSTEM PROGRAMMABLE 3.3V In-System Programmability Us |
| FRO | (8) | PHOENIX | SOP | The power dissipation approximation is a result of power transferred to | |
| FRP | (26) | FAIRCHILD | TO-220 | 05+ | The Fairchild Switch FSTD32211 provides up to 48-bits of high-speed CMO |
| FRQ | (1) | NIHON | TO-220 | 06+ | (BLE) is LOW, then data from I/O pins (I/O 1 through I/O8), is written i |
| FRS | (91) | FAGOR | 06/07+ | The HYM5V72A804A H-Series is a 8Mx72-bit EDO mode CMOS DRAM module consist | |
| FRT | (1) | RFMD | NOTE: H = Input Voltage High Level, h = Input voltage high one set-up tim | ||
| FRU | (2) | Note that the level 7 interrupt is also level sensitive, and must be held | |||
| FRV | (1) | In this example 5V power-supplies were used, with the IC flip- flop pow | |||
| FRW | (1) | N/A | 0402X2 | Reduced parts count and high efficiency add to the reliability of the HP | |
| FRX | (4) | 93 | Electrical Characteristics: Unless otherwise specified, all limits are est | ||
| FS- | (25) | 30 | 99+ | The two VREF pins (A3 and T3), are connected together internally by appro | |
| FS0 | (61) | NA | 00+ | Thermal Resistance − Junction−to−Case Total Power Dis | |
| FS1 | (444) | EUPEC | MODULE | These lamps are made with an advanced optical grade epoxy, offering s | |
| FS2 | (200) | MIT | TO-3PF | 04+ | The data strobe, associated with one data byte, sourced whit data transfer |
| FS3 | (220) | 三菱/MIT | TO-220 | 05+ | 1. Built with adjacent die from a single wafer. 2. Contact the Diodes, |
| FS4 | (49) | FOCUS | QFP-80 | 0513+ | Integral nonlinear error refers to the deviation of each in- dividual cod |
| FS5 | (233) | 三菱/MIT | TO-220 | 05+ | System operation has been enhanced by the addition of common asynchronou |
| FS6 | (150) | AMI SEMI | 04+ | Stresses above those listed under Absolute Maximum Ratings may cause perm | |
| FS7 | (194) | MIT | TO-3P | 04+ | The XC9536XV is a 2.5V CPLD targeted for high-perfor- mance, low-voltage |
| FS8 | (128) | FORTUNE | 00+ | Following the eight SCLK cycles that input an address/command byte to writ | |
| FS9 | (10) | LEXAR | LQFP | 446 | FEATURES • Current Limit Protection • l/O Isolation, 5300 VR |
| FSA | (238) | FS | 07+ | The motor is directly driven by IRF511 power MOSFETS in this des | |
| FSB | (90) | 64-Bit SDRAM interface 66 MHz to 100 MHz frequency range Direct inte | |||
| FSC | (52) | FSC | 06+ | TAOperating free-air temperature−4085C NOTES: 4. VCCI is the | |
| FSD | (128) | FAIRCHILD | ★Original and new, Special price! | 08+ | Short sample gate dwell times after the X edge can be used to limit the |
| FSE | (13) | 2000 | The design has been optimized to achieve the high accuracy associ- ated | ||
| FSF | (22) | NIEC | TO-220 | 05+ | 1. VIH (max) = 3.0V AC.The overshoot voltage duration is 3ns. 2. VIL (mi |
| FSG | (12) | I2C Receive mode should be enabled (i.e., RCEN bit should be set) only | |||
| FSH | (30) | NIEC | TO-220F | 04+ | 2DESCRIPTION In a 1.4 x 7 x 7mm low-profile Ball Grid Array pack- age, |
| FSI | (8) | ALPHA | 08+ | Software design support and automatic place-and-route provided by Altera | |
| FSJ | (1) | 3.3V power supply Clock frequency: 133MHz (max.) Si | |||
| FSK | (17) | AMIS | PLCC-20P | 02+ | 1. Fast QCK: the falling edge of the clock qualifies the nibble da |
| FSL | (143) | TOKO | 2520-220K | 05+ | Purchase of I2C components from Maxim Integrated Products, Inc., or one |
| FSM | (79) | N/A | 1WR | 05+ | The Hynix HYM76V8C735HGT8 Series are Dual In-line Memory Modules su |
| FSN | (22) | The 82C37A is an enhanced version of the industry standard 8237A Direct | |||
| FSO | (14) | FOX ELECTRONICS | 01+ | SOP-4 | When the FSO-2 begins a READ mode, it trans- mits 8 bits of data, relea |
| FSP | (46) | FC | CDIP40 | 8705 | The Fairchild Switch FST34170 is a 17-bit to 34-bit high- speed CMOS TT |
| FSQ | (33) | NIEC | TO-220 | 06+ | Fully static operation and Tri-state output TTL compatible |
| FSR | (18) | LG | 03+ | operating temperature range are assured by design, characterization and c | |
| FSS | (97) | SANYO | As the beams attached to the central mass move, the distance from | ||
| FST | (454) | FAIRCHILD | TSSOP | 03+ | • HIGH PERFORMANCE E2CMOS® TECHNOLOGY fmax = 180 MHz Ma |
| FSU | (42) | FUJITSU | 05+ | These three terminal negative regulators are supplied in hermetically sea | |
| FSV | (8) | TO92S | ZTX | 03+ | Characterized by a very low reverse Capacitance the PIN Diode FSV020 wa |
| FSW | (5) | Memories C Internal Memory: up to 128 Kbytes Single Voltage FLAS | |||
| FSX | (14) | FUJI | 03+ | • Speeds: 12, 15, 20, 25, 35, 45, 55, and 70ns • Battery Bac | |
| FSY | (2) | SANREX | • High reliability, achieved by the combination the planar type and | ||
| FSZ | (2) | When used as a position sensor, the output of the sensor consists of 3 di | |||
| F-T | (1) | scribed in Table 3.), terminated by an acknowl- edge bit. When writing | |||
| FT- | (9) | LCC | 06+ | Modulo periferico di conversione digitale-analoghica ad alta risoluzione | |
| FT0 | (16) | Hitachi | The two-chip combination of a DSP and a DSM device is ideal for systems | ||
| FT1 | (58) | 100 | 天龙伟业 | 靳先生 | Maximum Sample Rate: 170 MSPS 14-Bit Resolution No Missing Codes Power |
| FT2 | (43) | FUN-JIN | DIP-20 | 08+ | CBR refresh is utilized by bringing CAS low earlier than RAS (see paramet |
| FT3 | (13) | 1735 | October 10, 2001: Revised AC timing characteristics in Tables 5, 6 | ||
| FT4 | (19) | MOT / PH | CAN3 | 00+ | The FT40 has an AutoShutdown™ function that puts the device into a |
| FT5 | (83) | FUJ | SIP-12 | 08+ | 1) Mount the 0.01µF decoupling capacitor on the component side of |
| FT6 | (48) | FUJITSU | 07+ | In order to saturate the power switch and reduce conduction losses, ade | |
| FT7 | (16) | FORTECH | DIP | 94+ | Besides the ac-coupling capacitors C1 through C4 in the input and output |
| FT8 | (16) | 1735 | Should the system reset, while a Block or Sector Erase or Word Program is | ||
| FT9 | (3) | MALASIA | DIP-16 | 9407+ | The ON Semiconductor 74FST3257 is a quad 2:1, high performance mu |
| FTA | (12) | sgs | sgs | dc91 | A number of the FTA0D0105MBA can be stacked for applications requiring mo |
| FTB | (11) | thomson | thomson | dc95 | 2) Limiting the external clock frequency to 12 MHz AND making sure the on- |
| FTC | (20) | FTC | QFP | 01+ | The device supports low-power standby operation. When the reset input (RS |
| FTD | (62) | SANYO | An open drain FAULT pin will indicate that a fault has occurred. The fa | ||
| FTE | (22) | QLOGIC | BGA | 07+ | The resistor array is composed of 99 resistive ele- ments. Between each |
| FTF | (7) | FUJI | SOP | s Meets or exceeds the requirements of ANSI TIA/EIA-644 Standard s Low-V | |
| FTG | (1) | TSSOP | 04+ | The CM3016-48 is fully protected, offering both overload current limitin | |
| FTH | (6) | DIP | 95+ | functional operation of the device at these or any other conditions beyon | |
| FTK | (7) | CD4053BC is a triple 2-channel multiplexer having three separate digital | |||
| FTL | (4) | Besides greater speed, the microcontroller includes a second full hardware | |||
| FTM | (21) | FIBERXON | SOP | * TOSHIBA is continually working to improve the quality and reliability of | |
| FTN | (1) | The HC4017 is a high speed silicon gate CMOS 5-stage Johnson counter wi | |||
| FTO | (1) | The operation mode of the FTOH104ZF,VP is determined by a combina | |||
| FTP | (10) | FSC | TO-220 | 99+ | Operating Range In the operating range the functions given in the circui |
| FTR | (95) | CHIP | 00+ | Notes: 1. An initial pause of 200 µs is required after power | |
| FTS | (115) | FAI | SOT-23 | 04+ | DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . - |
| FTT | (4) | The vertical sync interval is detected by integrating the composite sync | |||
| FTU | (4) | enabled and synchronous loading occurs on the next clock pulse. Clockin | |||
| FTV | (5) | The ATF1502ASV offers the option of programming all input and I/O pins so | |||
| FTZ | (14) | ROHM | 153-5.6V | The input/output logic timing diagram is shown in figure 1. For proper op | |
| FU- | (78) | KEYENCE | Control of the wiper (RW) position setting is accomplished via the two in | ||
| FU0 | (1) | Anti Cross−Conduction Protection Circuitry Floating Top Driver Acc | |||
| FU1 | (6) | IR | TO-251 | 07+ | • Plastic package has Underwriters Laboratory Flammability |
| FU2 | (3) | N/A | SIP3 | 07+ | ICSI reserves the right to make changes to its products at any time withou |
| FU3 | (6) | When writing data to the memory it responds to the 8 bits received by a | |||
| FU4 | (8) | Accuracy (each DAC) Integral linearity error Diffential l | |||
| FU5 | (2) | FUA | TO8 | 07+/08+ | In the receive path, the input amplifier sums the signals from the line |
| FU6 | (17) | Unless otherwise noted, a positive logic (active High) convention is as | |||
| FU8 | (4) | SLMSX | QFP | 01+ | Stresses above those listed under Absolute Maximum Ratings may cause per |
| FU9 | (8) | 86 | TO251 | 04+ | GERMANY, Langenhagen/ Hanover49(511)789911 GERMANY, Munich49 89 92103-0 |
| FUA | (15) | NS | Typicals and limits appearing in normal type apply for TJ = 25˚C. L | ||
| FUB | (2) | MOT | TSOP8 | reverse bias leakage currents, and are typically less than 1pA at room t | |
| FUC | (2) | The CM3004 is supplied in a space-saving, 8-lead power SOIC package whi | |||
| FUD | (6) | stock | One of its notable features is MaverickKey unique IDs. These are factory | ||
| FUE | (5) | FAROR | 06/07+ | The FUES1A is an integrated Family Applications Development System (FADS) | |
| FUF | (19) | FAGOR | The PT5100 modules are a series of economical, easy-to-use 1-A positive | ||
| FUH | (1) | • New specifications • Dual frequency standard for indu | |||
| FUJ | (7) | ORIGIN | SOD-6 | 05+ | ©2002 by ZiLOG, Inc. All rights reserved. Information in this publica |
| FUL | (1) | Microchip received ISO/TS-16949:2002 quality system certification for its | |||
| FUN | (5) | N/A | DIP28 | 07+ | The transmitter contains a laser driver circuit that drives the modulati |
| FUO | (1) | 3000 | |||
| FUR | (1) | IBM, PC/XT and PC/AT are registered trademarks and PS/2 is a trademark o | |||
| FUS | (43) | IPD | 2007 | It is recommended that tantalum capacitors have a minimum voltage rating | |
| FUV | (2) | 18 | ST | 01+ | Single-chip powerline networking controller with IEEE802.3u MII interfac |
| FV0 | (2) | FVT | * Static-sensitive device. Unused devices must be stored in conductive m | ||
| FV1 | (3) | NXP | SOT-323 | 08+PB | High Power Switching Regulator Controller for DDR Memory Termination VOU |
| FV2 | (5) | N/A | SOP8S | 07+ | After the calculations are performed for a particular crystal, the oscill |
| FV3 | (3) | 1. One output at a time for a maximum duration of one second. VOUT = 0.5V | |||
| FV4 | (2) | PAN | 05+ | Generates Programmable CPU Clock Output (50 MHz, 60 MHz, or 66 MHz) Gene | |
| FV5 | (15) | int | int | dc99 | H = high level, L = low level, X = dont care, h = high level one setup ti |
| FV7 | (1) | Note 1 Absolute Maximum Ratings indicate limits beyond which damage to th | |||
| FV8 | (51) | INTEL | PGA | 00+ | The 8-bit Status Register contains the Control Word Register, the status |
| FVA | (1) | MOT | TSOP8 | 05+ | 1) CPD isdefined as the value of the ICsinternal equivalent capacitance w |
| FVB | (1) | MOT | TSOP8 | 05+ | output voltage for longer talk time. The DC/DC converter is available i |
| FVC | (3) | LUCENT | 1465 | AH281 is a monolithic fan motor controller with Hall sensors capability. | |
| FVD | (9) | 日立 | 12000 | 07+ | present. The Schmitt trigger amplifier on the input simplifies the coup |
| FVE | (1) | Note 3: The maximum power dissipation must be derated at elevated tempera | |||
| FVF | (1) | Self--Test The sensor provides a self--test feature that allows t | |||
| FVM | (2) | TOSHIBA | *1: Frequency = 824C849, 880C915 MHz, Input Signal is CW, Pin = +34 dBm | ||
| FVP | (3) | 仙童 | 金属帽 | 841 | Pin-for-Pin compatible with AMD® Am186ES/188ES devices All features |
| FVR | (1) | 2000 | This device is specified for an operating temperature range of -40C to +8 | ||
| FVT | (1) | SWITCHING PERFORMANCE Maximum Conversion Rate Minimum Conver | |||
| FVW | (4) | NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may | |||
| FW- | (18) | SAMTECH | 03+ | Recommended Application: VIA PM133 chipset Output Features: •2 - | |
| FW0 | (7) | N/A | In NORMAL mode, DPLL #2 provides the CEPT/ST-BUS compatible timing signals | ||
| FW1 | (48) | N/A | N/A | N/A | Unless otherwise specified, the following specifications apply for AGND = |
| FW2 | (90) | samtec | samtec | dc00 | DIGITAL INTERFACE The MXD2020E/F is easily interfaced with low cost mic |
| FW3 | (62) | SANYO | SMD-8 | 03+ | An on-board temperature sensor protects the modules internal circuitry a |
| FW4 | (7) | N/A | System Reference Clock The SiW3500 chip can use either an external cryst | ||
| FW5 | (3) | SANYO | SOP8 | Multi-channel Rch input A Multi-channel Cch input A Multi-channel SLch i | |
| FW6 | (7) | 100 | 天龙伟业 | 靳先生 | EIDE Interface Supports PIO Transfer Rates to 22 MBytes/sec Supports u |
| FW7 | (2) | The VCA2619 also features low crosstalk and outstanding distortion perf | |||
| FW8 | (550) | INT | 06+ | 500 | (3) Inductor Selection A 10uH inductor is recommended for most ap |
| FW9 | (4) | QXFORD | TQFP | OSOP Series resistor networks feature a space saving 25 Mil lead pitch | |
| FWA | (4) | 05+ | 3/SOT-23 | The linear relationship of torque output to current input of the | |
| FWB | (1) | MOT | Further more, the two control modes -ON/OFF of loading, FOUT amplifier, | ||
| FWC | (2) | The Buck regulator is a synchronous rectifier PWM regulator with | |||
| FWD | (15) | FINISAR | 05+ | Escape Characters - An escape sequence may be entered while in data mod | |
| FWE | (7) | TIA/EIA-644 Standard Low-Voltage Differential Signaling With Typical Out | |||
| FWF | (10) | AMPHENOL | 220 | Lets look at what determines the output frequency. Start by examining t | |
| FWG | (1) | ROHM | SOT25 | 1995年 | As shown in the functional block diagram on Page 1, the ADSP- 21262 uses |
| FWH | (4) | The F157A is a high-speed quad 2-input multiplexer Four bits of data fro | |||
| FWI | (24) | INTEL | BGA | 03+ | The R5101G Series are microprocessor power management ICs with high |
| FWJ | (3) | For the TPS774xx, the power good terminal (PG) is an active high output, | |||
| FWL | (20) | N/A | 3225 | In FM mode the FM mixer, the FM RF-AGC and the 1st IF FM amplifier at pi | |
| FWM | (1) | At turn-on, the external gate capacitor of the N-Channel MOSFET is charge | |||
| FWP | (7) | INTEL | N/A | 2006+ | This series of hermetic packaged MOSFETs are ideally suited for low volta |
| FWS | (15) | 710 | |||
| FWT | (1) | SEOUL ELEC | 04+ | Note 12: Ripple voltage should measured at COUT electrode on good layout | |
| FX- | (21) | 2-WIRE BUS The two-wire bus is defined as a Serial Data line(SDA), and | |||
| FX/ | (3) | ||||
| FX0 | (34) | N/A | N/A | N/A | Hynix HYMD264726A(L)8J-J series incorporates SPD(serial presence detect). |
| FX1 | (39) | N/A | N/A | N/A | Automatic test equipment High speed instrumentation Scope and logic anal |
| FX2 | (69) | MITSUBISHI | TO-220 | 06+ | CAUTIONS:The BiCMOS inherent to the design of this component increases th |
| FX3 | (68) | CML | QFP | 00+ | An address sequence is started when the control section of the Sequence |
| FX4 | (45) | CML | QFP | 02+ | State-of-the-Art Advanced BiCMOS Technology (ABT) Widebus Design |
| FX5 | (62) | SANYO | 00+ | The ability to swing rail-to-rail at the outputs (see Applications sec- | |
| FX6 | (85) | CML | PLCC24 | PLCC24 | DESCRIPTION The ST3237E is a 3V to 5.5V powered EIA/ TIA-232 and V.28/ |
| FX7 | (11) | CML | NEW | N/A | Installations intended to meet UL and CUL requirements must follow the ins |
| FX8 | (57) | SANYO | SOT89-6 | 05+ | WRITE PROTECT: The write protect pin (WP) will allow normal read/write op |
| FX9 | (19) | The SCE100-ES Evaluation System provides demonstration, prototype devel | |||
| FXA | (2) | PHI | QFN | Featuring continuous load current ratings to 500 mA for each of t | |
| FXC | (5) | sgs | sgs | dc80+ | DESCRIPTION The FXC3B15B is a monolithic integrated circuit fabricated |
| FXD | (1) | NIHON | cant bits of this captured value (01) are required by IEEE Std 1149.1. | ||
| FXF | (1) | MURATA | 05+ | SMD | NOTES *Same as FXFM-040070J. 1Measured in IOUT mode. 2Measured in V OUT |
| FXL | (16) | FAIRCHILD | ★Original and new, Special price! | 08+ | When the PAR/SER pin is low the chip is in serial mode. Serial data is in |
| FXO | (19) | IKANOS | BGA | 07+ | NOTES: 1. Chip Enable references are shown above with the actual CE0 and |
| FXR | (3) | Notes: 1. See test circuit and waveforms. 2. This parameter is guarantee | |||
| FXS | (15) | IKANOS | This 18-bit universal bus transceiver is built using advanced dual | ||
| FXT | (48) | PHI | 08+PBF | Added output voltage maximum value and note to clarify in Table 10-1.; als | |
| FXX | (2) | LITTELFUSE | 08+ | to be transmitted to the sensor diaphragm. The gel die coat and durable | |
| FXZ | (1) | AUK | SOT-23 | 04+ | • The information in this document is current as of July, 2001. The |
| F-Y | (1) | QFP | 95 | Advanced, Integrated Speech Synthesizer for High-Quality Sound. Operates | |
| FY1 | (20) | MITSUBISHI | SOP8 | 07+ | the new command code of 8 bits (1st byte of the proto- col.) If the X76 |
| FY3 | (2) | MITSUBISHI | 07+/08+ | A current sense circuit senses the output current of MOSFET switch. If ou | |
| FY4 | (10) | N/A | TSSOP-8 | 2004 | The product information and the selection guides facilitate selection of |
| FY5 | (5) | MIT | SOP | 98+ | Figure 6 on page 6 shows a correct trigger sequence. The positive edge of |
| FY6 | (5) | MITSUBISHI | 07+/08+ | ON/OFF Control Input. ON/OFF is referenced to GND. Drive ON/OFF above 1.38 | |
| FY7 | (7) | Panasonic | Transmitter Differential Input. Input accepts AC- or DC-coupled differenti | ||
| FY8 | (6) | IR | O7+ | Please be aware that an important notice concerning availability, | |
| FYA | (3) | FSC | TO-3PF | 3 | HIGH SPEED: tPZ = 3.9 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC |
| FYD | (11) | FAIRC | TO-252(DPAK) | 07+ | The information contined here concerns products in the formative or desig |
| FYE | (1) | 96 | Notes: 1. The luminous intensity IV is measured at the peak of the spati | ||
| FYH | (4) | nec | nec | dc07 | Description This HEXFET® Power MOSFET is specifically designed for |
| FYL | (3) | N/A | N/A | 04+ | Use Opti-MEM® I Reduced Serum Medium (Catalog no. 31985-062) to dilut |
| FYM | (6) | N/A | QFP | 2006 | Q and Q outputs. This device can be used for shift register applications |
| FYP | (43) | FAIRCHILD | TO-220 | 08+ | Input Channel A No Internal Connection Internal Reference Supply Bia |
| FYQ | (1) | ph | ph | dc96 | The only controlled copy of this BIF document is the electronic read-only |
| FYV | (5) | FAI | SOT-23 | 05+ | ITH (Pin 18): Error Amplifier Compensation Point. The current comparator |
| FZ0 | (6) | ORIGIN | SOD-723 | 05+PB | I/O WRITE: I/O Write is a bidirectional active low three-state line. In t |
| FZ1 | (102) | N/A | RSL (Pin 4): The slew control resistor sets the maximum current and volta | ||
| FZ2 | (24) | N/A | Note 2: Absolute maximum ratings are those values beyond which damage to | ||
| FZ3 | (11) | eupec | 820 | When ENABLE is low, the DATA and CLOCK inputs are disabled internally. As | |
| FZ4 | (24) | 100 | 天龙伟业 | 靳先生 | Meets Intels Mobile 133.3MHz Chipset Three CPU Cloc |
| FZ5 | (3) | eupec | 06+ | No output filter required for inductive loads Externally configurable g | |
| FZ6 | (16) | 100 | 天龙伟业 | 靳先生 | voltage (150 mV at full load). Therefore, compared to many other regula |
| FZ7 | (2) | Single Event Effect (SEE) Hardened Neutron Tolerant Identical Pre- an | |||
| FZ8 | (34) | N/A | The VI input monitors the bus-side voltage for both under- voltage and | ||
| FZ9 | (7) | EUPEC | 模块 module | and 4 to 40 V Low current consumption of less than 0.8 mA Integrated out | |
| FZA | (1) | MAXIM | SOT23-3 | 05+ | When S/S and PWMIN pins are not used, set the input to the L level voltag |
| FZB | (3) | 05+ | SOP-3 | ||
| FZC | (7) | J.S.T | N/A | 2004 | Voice within each group are combinations of different fixed memory sect |
| FZD | (2) | 06+ | SOP-3 | Right Hand Decimal Point 1. Overflow Character • C | |
| FZE | (9) | Infineon | SOP20 | 03+ | Resistors R1 and R2 provide a DC input impedance to ground. The input si |
| FZF | (1) | SIEMENS | DIP | The converters incorporate a fixed frequency single for- ward topology | |
| FZG | (1) | MAXIM | SOT23-3 | 05+ | When 16/68# pin is at logic 1 for Intel bus interface, this output become |
| FZH | (69) | SIEMENS | DIP | A default serial loader program in the Boot ROM allows In-System Program | |
| FZI | (1) | N/A | SIEMES | 04+ | Xilinx in-system programmable products provide a mini- mum endurance le |
| FZJ | (19) | programmable address/data which meet vari- ous applications. The program | |||
| FZK | (3) | SIEMENS | DIP | 07+ | © 2002 PLX Technology, Inc. All rights reserved. PLX and the PLX log |
| FZL | (23) | DIP16 | 2007+ | THESE MATERIALS ARE PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KI | |
| FZM | (1) | Ripple current, less than 100 mΩ equivalent series resis- tance (E | |||
| FZN | (2) | SIEMENS | Make connection to B side with pink wire for Light ON Make connection | ||
| FZO | (2) | 100KEP circuits are designed to meet the DC specifications shown in the a | |||
| FZT | (243) | ZETEX | 04+ | The MAX3873 successfully meets the quality and reliability standar | |
| FZU | (1) | The 556C/W for the SOTC23 package assumes the use of the recommen | |||
| FZW | (1) | Two TTL/CMOS compatible inputs select the gain for all eight ampli- fier | |||
| FZY | (1) | sie | sie | dc89 | The Cypress EZ-USB TX2 is a Universal Serial Bus (USB) specifica |
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