| Mfg | pack | D/C | Descrpion | ||
| G.S | (1) | The leadless chip carrier (LCC) package represents the logical next ste | |||
| G/S | (1) | ||||
| G-0 | (2) | 05+ | SMD | Address Latch-Enable Output. This pin functions as a clock to latch the e | |
| G00 | (19) | DLE | III. Measurements The circuit was fabricated on a "Quickchip" t | ||
| G01 | (7) | ROHM | SOP8 | This new generation of Trench MOSFETs from Zetex utilizes a unique structu | |
| G02 | (5) | 05+ | in the buffer register. The Data Ready flag goes low (0) when the most s | ||
| G03 | (5) | G | DIP4 | 0510+ | Note 4: Electrical Table values apply only for factory testing conditions |
| G04 | (5) | N/A | DIP | 07+ | These N-Channel power MOSFETs are manufactured using the |
| G05 | (14) | MORNSUN | 08+ | The device features single 3.0 V power supply operation for both read and | |
| G06 | (12) | MARVEL | 05+ | The insertion loss measurement was taken by connecting two baluns back to | |
| G07 | (12) | 06+ | SMD | ‡ All typical values are at VCC = 5 V, TA = 25C. For I/O ports, | |
| G08 | (9) | 06/07+ | Note 3: The Absolute Maximum Ratings are those values beyond which the sa | ||
| G09 | (7) | 96 | The digitally controlled potentiometer is implemented using 63 resistiv | ||
| G0L | (1) | NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATING | |||
| G0X | (1) | FUNCTIONAL DESCRIPTION The LS257B and LS258B are Quad 2-Input Mul | |||
| G-1 | (7) | DYTCOM | O7+ | Maxwell Technologies 28LV010 high density, 3.3V, 1 Megabit EEPROM microci | |
| G1- | (4) | ZILOG | SOP | 03+ | Notes * Indicates JEDEC registered data. 1. The current transfer ratio |
| G10 | (64) | n/a | N/A | The Read operation outputs the data in order from the initial accessed add | |
| G11 | (28) | QFN | n Efficiency up to 92% n Simple and easy to design with (using off-the- | ||
| G12 | (69) | GMT | SOP-8L | 04+ | • High-speed access time: 55, 70, 100 ns • CMOS low power o |
| G13 | (23) | NEC | MSOP-8 | Reliability Developed and manufactured in Germany guaranteeing & | |
| G14 | (25) | SSOP-3.9-20P | 6+ | (2) Those contemplating using the products covered herein for the followi | |
| G15 | (34) | MARVEL | 05+ | Output Features: •3 - 14.318 MHz REF clocks •1 - USB_48MHz | |
| G16 | (15) | MARVEL | 05+ | VID0-VID4 (DAC Digital Input Code Control) Pins 15-11 - These are the DA | |
| G17 | (39) | TI | TSSOP | 05+ | Figure 18.TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Bottom View P |
| G18 | (15) | NEC | 652 | Complete PWM Power Control Circuitry Uncommitted Outputs for 200-mA Sink | |
| G19 | (14) | 04/ | Power Management The HOST_WAKEUP and EXT_WAKE signals are used for power | ||
| G1A | (5) | SAGAMI | 4D28 | The AT8xC5112 has 3 software-selectable modes of reduced activity for fur | |
| G1B | (2) | Test Conditions / Pins IL = 8 mA IL = 20 mA IL = 30 mA IL = 73 | |||
| G1C | (11) | N/A | Figure 2 shows a typical test circuit for evaluation of the LM2462. Thi | ||
| G1D | (2) | • 64 8 RAM • 16-bit auto reloadable counter/timer • 5-c | |||
| G1G | (3) | The TLC372C is characterized for operation from 0C to 70C. The TLC372I is | |||
| G1J | (1) | Undershoot Clamp Diodes Low Power Consumption (ICC = 0.25 mA Typical) V | |||
| G1L | (1) | This octal buffer or line driver is designed specifically to improve bo | |||
| G1Z | (5) | The 80C186EB can receive interrupts from a num- ber of sources both inte | |||
| G2- | (30) | CRYDOM | DIP-6 | 08+ | The 64-bit ID identifies each bq2022. The 48-bit serial number is unique |
| G2. | (1) | This block receives or sends samples from/to the serial interface block f | |||
| G20 | (44) | HARRIS | TO-247 | 04+ | With the circuit modification shown in Figure 2, the trailing black level |
| G21 | (15) | OKI | QFP- | 07+/08+ | Hynix HYMD564G726(L)8M-K/H/L series is Low Profile registered 184-pin doub |
| G22 | (13) | ST | SOP28 | 07+ | Performance warranty of products offered on this data sheet is limited to |
| G23 | (8) | GTM | SOT23 | 2007 | (8-2) Input Timing Digital audio signal data into DIN terminal is |
| G24 | (50) | TI | 00+ | SSOP20 | The leadless chip carrier (LCC) package represents the logical next ste |
| G25 | (14) | IR | TO-3P | If the cell voltage exceeds the overvoltage threshold for 1 second, charg | |
| G27 | (12) | 26 | INTEL | produces a positive output pulse with a duration ap- proximately equal | |
| G28 | (11) | 2000 | |||
| G29 | (10) | N/A | ST | 04+ | Hynix HYMD212G726(L)S4M-K/H/L series incorporates SPD(serial presence dete |
| G2A | (1) | The link power status (LPS) terminal works with the C/LKON terminal to ma | |||
| G2B | (1) | GERMANY, Langenhagen/ Hanover49(511)789911 GERMANY, Munich49 89 92103-0 | |||
| G2C | (1) | ||||
| G2D | (1) | Working Peak Reverse Voltage Range − 10 V to 78 V Standard Zener B | |||
| G2E | (13) | OMR | 07/08+ | The UCC1580-x is specified for operation over the mili- tary temperature | |
| G2G | (1) | 350 | IR | 02+ | The AM93LC86 is the 16384-bit non-volatile serial EEPROM. The AM93LC86 pr |
| G2L | (3) | Programs compiled natively on the host can not run on the target Program | |||
| G2M | (1) | The DLYBLK input can be used to halt address generation at the end of a | |||
| G2N | (3) | OMRON | DIP 5+4 | 08+ | This micropowered, low dropout voltage device will source or sink up to |
| G2Q | (1) | The FAN2500/01 allows the user to utilize a wide variety of capacitors c | |||
| G2R | (164) | OMRON | RELAY | 06+ | The voltage range of the CPU has shown a downwards trend for the past 5 |
| G2S | (4) | GS | 扁桥 | The big advantage of this approach compared to a single DAC running at ha | |
| G2T | (2) | OMRON | DIP-24 | 06+ | The DAB is a quad-word FIFO that enables loading of quad- word data from |
| G2V | (10) | OMRON | DIP 4+4 | 08+ | This single-pole, double-throw reflective switch consumes less than 50uA |
| G2Y | (1) | REFOUT is a 3.3V CMOS level non-modulated inverted copy of the clock at | |||
| G2Z | (1) | Note 2: CPD is defined as the value of the internal equivalent capacitance | |||
| G-3 | (4) | This document contains information on a product under development at Span | |||
| G30 | (18) | Infineon | 06+ | QFN | This low failure rate represents data collected from Maxims reliab |
| G31 | (25) | MARVEL | 05+ | BAT (Pin 5): Battery Voltage Sense Input. A precision internal resistor d | |
| G32 | (35) | SMD | TOCOS | 05+ | The Hitachi HM5112805F, HM5113805F are 128M-bit dynamic RAMs organized as |
| G33 | (6) | NA | 05+ | 19.44 Mbit/s inputs to a 155.52 Mbit/s OC3 serial data output Performs p | |
| G34 | (7) | HA | Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Inpu | ||
| G35 | (14) | N/A | Function Port 2, Bit 1-7 Analog In 1-7 Reset Oscillator Clock Osci | ||
| G36 | (10) | TOKO | 3225 | 04+ | *) The terminating impedances depend on parasitics and q-values of matchin |
| G37 | (17) | TI | TSSOP | 07+ | Notes: 1. See XPLA3 family data sheet (DS012) for recommended operating |
| G38 | (6) | MICROCHIP | QFN-16P | 6+ | The receive cell data to the ATM layer from the receive FIFO. This is upd |
| G39 | (9) | SIEMENS | SIP | SIP | The serializer accepts 10-bit transmission characters and converts them f |
| G3A | (23) | The ADSP-21365/6 is code compatible at the assembly level with the ADSP- | |||
| G3B | (11) | TOCOS | 3X3-100K | 05+ | The PEN (Power supply ENable) input, driven from an open- collector sou |
| G3D | (4) | OMRON | DIP 3+4 | 08+ | The HYM71V633201 H-Series are Dual In-line Memory Modules suitable for eas |
| G3F | (2) | ||||
| G3G | (1) | Description The HCPL-90xx and HCPL-09xx CMOS digital isolators feature | |||
| G3H | (3) | ANRITSU | This pin provides an access to the output current control loop for the NC | ||
| G3L | (7) | 99 | Each DS1225 is shipped from Dallas Semiconductor with the lithium energy | ||
| G3M | (39) | OMRON | (LX)high-frequency | † Stresses beyond those listed under absolute maximum ratings may c | |
| G3N | (26) | NEC | Building on experience gained from previous generations of FPGAs, the V | ||
| G3P | (9) | ||||
| G3R | (2) | ||||
| G3S | (9) | PROTECH | TSOP | 02+ | VCXO parts from ICS require that locations be provided to tune the load |
| G3T | (6) | JAT | SOT | 05+ | The Flash identification register is a register not mentioned in the data |
| G3V | (110) | OMRON | 原装 | 08+ | Input capacitance Output capacitance Reverse transfer capacitance Tota |
| G-4 | (2) | JAT | SOT | 05+ | Transmit Clock Tri-statable. This signal is used in synchronous DPSK/QAM |
| G40 | (36) | FSC | TO-3PL | 05+ | |
| G41 | (7) | N/A | SMD | 1994 | The DSP56F801 DSP controller includes 8K words (16-bit) of program Flash |
| G42 | (13) | 94 | The feedback bank has one pair of low-skew, high-fanout output buffers | ||
| G43 | (9) | NS | 04+ | The MT8985 device provides both functions and allows existing systems base | |
| G45 | (3) | The HT82V16 is a complete analog signal pro- cessor for CCD imaging appl | |||
| G46 | (1) | 00+ | SUPPLY VOLTAGE, +VS to CVS BOOST VOLTAGE, +Vb to -Vb OUTPUT CURRENT, | ||
| G47 | (1) | HI | TO-247 | 05+ | IDENTIFICATION INPUTS: These four pins are part of the mechanism that all |
| G48 | (1) | Notes: 1. The algebraic convention, where the most negative value is a m | |||
| G49 | (3) | To accommodate split-band and filtering, the PCS VGA drives two output a | |||
| G4A | (47) | TOCOS | 5X5-50K | 05+ | Reading from the device is accomplished by taking Chip En- able (CE) an |
| G4B | (50) | IR | 04+ | TO220 | Maxims MAX312/MAX313/MAX314 analog switches feature low on-resistance (10 |
| G4D | (2) | NOTES: 1. See Test Conditions under TEST CIRCUITS AND WAVEFORMS. 2. Thi | |||
| G4E | (1) | q Electrical characteristics of power circuit (Tc=Tj=25˚C, Vcc=15V) | |||
| G4F | (4) | mitsumi | (1) Includes effects of amplifier input bias and offset currents. (2) Re | ||
| G4G | (1) | • Isolated Input Line Receiver • EIA RS-232-C Line Receiver | |||
| G4H | (1) | The AP1187 is specifically designed to meet the fast current transient ne | |||
| G4I | (2) | IR | TO-220F | 01+ | Bits D5 through D0 contain the counters programmed Mode. Output bit D7 con |
| G4J | (1) | SHARP | 0403+ | In order to saturate the power switch and reduce conduction losses, ade | |
| G4K | (1) | Please be aware that an important notice concerning availability, | |||
| G4L | (1) | ||||
| G4N | (1) | The SLC90E66 supports comprehensive power management, including full clock | |||
| G4P | (41) | IR | TO-247 | 05+ | Optimized for 2.5V LVTTL Guaranteed Low Skew < 25ps (max) Very low d |
| G4Q | (1) | ||||
| G4R | (6) | IR | TO-252 | 06+ | The MAX1536 constant-off-time, pulse-width-modulated (PWM) step-down DC-t |
| G4S | (15) | TOCOS | 5X5-100K | 04+ | Notes: 1. Typical specifications are not guaranteed 2. Offset an |
| G4U | (2) | OMRON | Relay | 0206+ | |
| G4W | (7) | pacasonic | relay | 08+ | CMOS I/O port or Timer Y input pin for pulse period measurement mode, pul |
| G4Y | (2) | The G4Y-152P9VDC high current Schottky rectifier module series has been o | |||
| G5- | (2) | The CM3016-48 is a CMOS linear voltage regulator with low quiescent cur | |||
| G5. | (3) | TOS | DIP-4 | 08+ | The AD581 represents an alternative to current limiter diodes which requ |
| G50 | (22) | NETVOX | TQFP | 05+ | Password Protection Configuration Portions of the memory array may be lo |
| G51 | (27) | GMT | SOT153 | 04+ | To 0.1% of full scale, data cycles from zero scale to full scale to zero |
| G52 | (15) | N/A | N/A | N/A | The 17550 operates from 2.5 V to 5.5 V, with independent control o |
| G53 | (5) | The ZL40518 is a laser diode driver for high speed operation of a grounded | |||
| G54 | (17) | Unknown | The LM74s 3.0V to 5.5V supply voltage range, low supply current and sim | ||
| G55 | (10) | Collector power dissipation Junction temperature Input voltage of pow | |||
| G56 | (2) | CMT | SOP | N/A | 1.4 PACKAGING/PIN EFFICIENCY Real estate and board configuration conside |
| G57 | (11) | SSOP/32 | 04+ | DSP Functions for CCD/CMOS Image Processing Video Encoder, Including Line | |
| G58 | (4) | NETVOX | TQFP | 05+ | Cell phones, for example, often face ASIC functionality limitations. Th |
| G59 | (3) | NETVOX | TQFP | 05+ | DESCRIPTION The 74AC138 is an advanced high-speed CMOS 3 TO 8 LINE DEC |
| G5A | (33) | OMRON | DIP8 | Second-generation HOTLink® technology AMD™ AM7968/7969 TAXIchip | |
| G5B | (24) | OMRON | 04+ | TAOperating free-air temperature−4085C † Defined by th | |
| G5C | (17) | OMRON | DIP | 2001 | Note: 1. This input level is calculated from the input power delivered t |
| G5D | (4) | N/A | NOTES: 1. Chip Enable references are shown above with the actual CE0 and | ||
| G5G | (1) | OMRON | 2006 | Two package styles are available. HOA0901- 011 is primarily intended for | |
| G5J | (1) | Notes: 1. See test circuit and wave forms. 2. This parameter is guaran | |||
| G5L | (41) | OMRON | RELAY | 06+ | The ADSP-21365/6 contains three megabits of internal SRAM and four megab |
| G5N | (17) | 仙童 | 06+ | TO-3P | The MC623 consists of a positive temperature coefficient (PTC) te |
| G5P | (6) | OMRON | 04+ | NOTES 1See Figure 1. 2Guaranteed by design and characterization; not pr | |
| G5Q | (9) | Serial data output, 5-V CMOS logic level tristate output for output (stat | |||
| G5R | (6) | OMRON | Relay(new original) | LATCHED ADDRESS BUS: Low-order bits of the system's 24-bit address bus. | |
| G5S | (11) | OMRON | 04+ | W83877ATF is made to fully comply with MicrosoftTM PC97 Hardware Design Gu | |
| G5V | (93) | OMRON | RELAY | 06+ | • Miniature package C Height: 3.90 mm C Width: 9.80 |
| G5Y | (7) | OMRON | 04+ | Low Loss Replacement for ORing Diode in Multiple Sourced Power Supplies | |
| G-6 | (5) | SUPERTEX | SMD | 05+ | The Link Fault Indicator (LFI) output is a TTL-level output that indicat |
| G60 | (29) | BGA | 08+ | *Settable gain dynamics (25 or 50dB) *Low power consumption, totally 1.0m | |
| G61 | (5) | NOT | N/A | 2006 | Fixed Closed-Loop Gain Amplifier C 10 V/V (20 dB) Wide Bandwidth: 1.8 GH |
| G62 | (1) | Low Loss Replacement for ORing Diode in Multiple Sourced Power Supplies | |||
| G63 | (8) | • Asynchronous/Isosynchronous Modes C Standard CAN Controller | |||
| G64 | (36) | RAYTHEON | SOIC28 | 07+ | TTL/CMOS Compatible Synchronous Enable: When EN goes LOW, Q outputs will |
| G65 | (182) | This DAC utilizes a double-buffered 3-wire serial interface that is comp | |||
| G66 | (2) | DIP-16 | 03 04 | detection, and an FSK voltage comparator which provides FSK demodulatio | |
| G67 | (23) | N/A | N/A | N/A | Most Significant Data Bit (MSB) Data Bits 6-1 Least Significant Data Bit |
| G68 | (11) | FUJ | DIP-40 | 08+ | The XC5200 Field-Programmable Gate Array Family is engineered to delive |
| G69 | (59) | GMT | 03+ | tLOW Low Period of SCL Clock tHIGH High Period of SCL Clock tSU;STA Setu | |
| G6A | (142) | OMRON | 原装 | 08+ | 12-Bit Dual Transmit DAC 200 MSPS Update Rate Single Supply: 3.0 V - 3.6 |
| G6B | (106) | OMRON | 03+ | 1.) When operated within the SAFE OPERATING AREA as defined by th | |
| G6C | (39) | OMRON | RELAY | 06+ | NOTES: 1 Production testing of the device is performed at 25C. Functiona |
| G6D | (18) | OMRON | DIP-4 | N/A | The FAN7382 is a monolithic half-bridge gate driver IC for driving MOSFE |
| G6E | (50) | omron | omron | dc00 | High Power Switching Regulator Controller for DDR Memory Termination VOU |
| G6G | (6) | omron | omron | dc96 | Note 5: Each digital input includes a small positive or negative current |
| G6H | (59) | ISOLATION Input-Output Surge Withstand Voltage (8, 9), (In accor | |||
| G6J | (10) | OMRON | RELAY | 06+ | Note: 1. Enhancement mode technology employs a single positive Vg |
| G6K | (70) | FUJITSU | 2006Pb | ||
| G6L | (5) | The MCS 96 microcontroller family members are all high-performance microc | |||
| G6M | (10) | MM1231, and BA7602 VCC Operating Range From 4.5 V to 9 V Wide Frequency | |||
| G6N | (9) | OMRON | DIP | 1997 | The RC2211 is a monolithic phase-locked loop (PLL) system especially des |
| G6P | (3) | C 4-MHz Crystal Oscillator C 32-kHz Crystal Oscillator &nb | |||
| G6R | (28) | OMRON | RELAY | 06+ | Surface mount board layout is a critical portion of the total des |
| G6S | (64) | omron | 08+ | The IC G6S-2-12V is a 300-MHz quadrature modulator that uses Atmels advan | |
| G6W | (1) | 2-bit bidirectional input/output lines with pull-high resis- Wake | |||
| G6Y | (11) | pacasonic | relay | 08+ | NOTES: 1. Duplicated per port. 2. Each bank has an input pin assigned th |
| G6Z | (3) | The receive section consists of an expanding DAC which drives a fifth o | |||
| G-7 | (2) | Test Condition Vss < VIN < Vcc Vss < VOUT < Vcc, /CS | |||
| G70 | (20) | 08+ | CASE: Hermetically sealed axial-lead glass DO-35 (DO-204AH) package TERM | ||
| G71 | (8) | 3 | 04+ | TI | The G710805 and G710805 are 75,497,472-bits QDR(Quad Data Rate) Synchronou |
| G73 | (17) | OKI | 03+ | PBGA | • Ensure that the control loop has enough phase margin at t |
| G74 | (16) | STR | TO220-5P | 07+ | The PI90LV047A/PI90LVB047A are quad flow-through differential line drive |
| G75 | (11) | N/A | • JEDEC standard 3.3V power supply • LVTTL compatible with mu | ||
| G76 | (12) | SOP | Ausgabe 01.2001 Herausgegeben von Infineon AG , Marketing-Kommunikation, | ||
| G77 | (5) | 06+ | QFN-16 | When the enable input is high, all four analog switches are off. The su | |
| G78 | (16) | USOP-8P | 6+ | The 320VC33 contains a JTAG port for CPU emulation within a chain of any | |
| G79 | (5) | VLSI | PLCC52 | 03/+04+ | Features • High sensitivity (+5dB compared with the ICX059CL) R |
| G7B | (2) | NOTES: 1. Dimensions are in inches. 2. Metric equivalents | |||
| G7F | (16) | Sampling clock rates can be programmed to 16, 32 or 64K bits/second from | |||
| G7G | (2) | Zener Voltage (VZ) is measured with junction in thermal equilibrium with | |||
| G7J | (12) | OMRON | 2.36E+10 | One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and seven 64 Kbyte secto | |
| G7K | (1) | PHILIPS | SOP8 | 04+ | RF C, RF+ (Pins 10, 11): Differential RF Outputs. One pin may be DC conne |
| G7L | (27) | OMRON | RELAY | 06+ | The HC4066 and CD74HCT4066 contain four independent digitally controlle |
| G7N | (10) | TO-220 | Note 5: Limits are 100% production tested at 25˚C. Limits over the o | ||
| G7S | (4) | ||||
| G7T | (4) | OMRON | RELAY | 06+ | Semelab Plc reserves the right to change test conditions, parameter limits |
| G-8 | (2) | MOTOR LOADS Motor loads can be tricky to evaluate. They are like a reac | |||
| G8- | (1) | GHA/GHB/GHC High-side, gate-drive outputs for external NMOS drivers. Ex | |||
| G80 | (22) | 08+ | Storage temperature range, TstgC 65C to 150C (1) Stresses beyond those | ||
| G81 | (27) | G8124 | 2005+ | Notes: 1. Minimum DC input is C0.3V. During transactions, input ma | |
| G82 | (15) | Low power, high speed CMOS FLASH technology Fully static design Wide o | |||
| G83 | (2) | DIP | CAUTION: These devices are sensitive to electrostatic discharge; f | ||
| G84 | (8) | 40 | 2005 | Full-Featured Evaluation Board for the AD7472 EVAL-CONTROL BOARD Compati | |
| G85 | (10) | ST | DIP8 | accompanying wiring and circuits must be kept insulated and dry to avoid | |
| G86 | (5) | BGA镜 | |||
| G88 | (14) | PANASIONIC | TQFP-48 | 97+ | Due to technical requirements components may contain dangerous substances |
| G89 | (6) | Digital | 98 | 6.7MHz Y and C filters, with CV out for NTSC or PAL 75Ω cabl | |
| G8C | (1) | 8 times faster than the shift frequency of the input registers the most | |||
| G8J | (5) | The TP3070 and TP3071 are second-generation combined PCM CODEC and Filt | |||
| G8N | (2) | The instruction and data caches operate independently from the rest of th | |||
| G8P | (24) | Widebus Family Undershoot Protection for Off-Isolation on A and | |||
| G8S | (1) | This small, power-efficient PA has a full 1700 to 2200 MHz bandwidth cove | |||
| G8W | (1) | Information furnished by Analog Devices is believed to be accurate and re | |||
| G8X | (2) | In-Circuit Serial Programming (ICSP™) Power-on Reset (POR) Devic | |||
| G8Y | (1) | NEC | BGA | CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic ch | |
| G90 | (22) | N/A | 05+ | The G90051 is a precision trimmed 2.5 V 5.0 mV shunt regulator di | |
| G91 | (61) | GMT | 00+ | After the Master sends a START condition and the slave address byte, th | |
| G92 | (14) | TO220 | O3 | as Coss while VDS is rising from 0 to 80% VDSS. † Coss eff. | |
| G93 | (12) | GMT | SOT-89 | 05+ | s Anyone purchasing any products described or contained herein for an abo |
| G94 | (8) | GMT | SOT-89 | This center tap Schottky rectifier has been optimized for very low forwa | |
| G95 | (35) | GMT | 2008 | Prescaler provides additional divide-by-4 function Fast databus access | |
| G96 | (31) | GAMMA | Once the chemistry is determined, the bq2000 completes the fast charge wi | ||
| G97 | (3) | SOP8 | WST | 08+PB | Ground. Oscillator input. Oscillator output. Active high reset. (with i |
| G99 | (14) | GMT | 07+ | The MAX9315 low-skew, 1-to-5 differential driver is designed for clock an | |
| G9S | (1) | ||||
| GA- | (15) | 99 | Note 2 Do not design with these parameters unless CKI is driven with an a | ||
| GA0 | (11) | N/A | DIP | 07+ | Simple programming interface On-chip tunable RC oscillator, 10% On-ch |
| GA1 | (175) | IR | SOP | International Rectifier's FRED.. series are the state of the art Ultra fas | |
| GA2 | (55) | IR | SOP | ||
| GA3 | (60) | MURATA | 06+ | SMD | Notes: 1. Insulation characteristics are guaranteed only within the safet |
| GA4 | (35) | CONEXANT | QFP1420-100 | 00+ | The SY89222L is a dual TTL-to-differential LVPECL translator wit |
| GA5 | (18) | IR | SOP | The MC100EPT622 is a 10- Bit LVTTL/LVCMOS to LVPECL translator. B | |
| GA6 | (15) | IR | SOP | Parameter Positive Supply Voltage (VCC to GND) Negative Supply Voltage | |
| GA7 | (14) | IR | SOP | (4) The products and product specifications described in this book are su | |
| GA8 | (12) | IR | SOP | Features q Few external components q Frequency and amplitude-stable unb | |
| GA9 | (18) | GLOBESPA | QFP | Single Supply for Read and Write: 2.7V to 3.6 (BV), 3.0 to 3.6V (LV) Fast | |
| GAA | (9) | DAL | SOP | The AT91X40 Series Microcontrollers embed up to 256K bytes of internal SR | |
| GAB | (1) | KYO | QFP- | 07+/08+ | • PNP Silicon Epitaxial Planar Transistors • Suited for low |
| GAC | (3) | LAT | PLCC | The MC623 is a 3.0 V solid-state, programmable temperature sensor | |
| GAD | (1) | RQFP-64 | 98 | ||
| GAE | (10) | OPTEC | The AMC7123/4 is member of ADDM North Star White/Blue LED driver | ||
| GAG | (1) | H2 The second harmonic arises from the input stage, and the lower the ap | |||
| GAI | (3) | The interface between the IOBs and core logic has been redesigned in th | |||
| GAJ | (1) | JAT | SOT-252 | 05+ | VCC, GND - DC power is provided to the device on these pins. VCC is the |
| GAK | (3) | GAL | DIP | A SCx/SDx downstream pair, or channel, is selected by the contents of th | |
| GAL | (1505) | nsc | nsc | dc92 | Logic Output Terminal O1 Resistor Terminal A1 Wiper Terminal W1 Resisto |
| GAM | (4) | QFP | 9604+ | up to 133 MHz in .25µ (173 Dhrystone MIPS) 1.3 Dhrystone MIPS per | |
| GAN | (5) | Function Amplifier 1 - Input 2 Amplifier 1 - Input 1 Analog gro | |||
| GAO | (2) | MEDL | CDIP | CDIP | Clock. The chip operates from a single-phase master clock, to whose risin |
| GAP | (4) | PMI | CDIP | Note 1: Measurements are made with the device in thermal equilibrium. Not | |
| GAR | (2) | Note 1: The SOIC and MSOP packages are thermally enhanced through the use | |||
| GAS | (3) | MINI | 08+ | Notes: 1. Please do not use the soldering iron due to avoid high stress t | |
| GAT | (18) | MINI | 08+ | After the CMX866 has been successfully powered up, both the CMX866 Receive | |
| GAW | (3) | TI | QFP | 00+ | |
| GAX | (2) | IR | The SY89328L is a differential LVPECL-to-LVTTL translator and an | ||
| GAZ | (3) | FAIRCHIL | QFP | 07+ | The leading-edge 0.15 µm / 0.12 µm CMOS 8-layer metal proces |
| GB- | (5) | 1SSR: 240V10A 5VDC | The Freescale manuals are available on the Freescale Semiconductors Web s | ||
| GB0 | (8) | LS CABLE | 05+ | • 1.25 (31.75mm) PCB Height • 168-Pin Unbuffered DIMM with Si | |
| GB1 | (30) | N/A | True Dual-Ported memory cells which allow simultaneous reads of the same | ||
| GB2 | (8) | N/A | THERMAL EFFECTS Internal heating can have a significant effect on curren | ||
| GB3 | (13) | IR | SOP | Fault protection is provided by internal foldback current limiting, an ou | |
| GB4 | (26) | 2008 | Each port has independent control pins: chip enable (CE), read or write | ||
| GB5 | (7) | CSBS | 95+ | Note 1: Specifications are 100% production tested at TA = +25C. Maximum an | |
| GB6 | (4) | WINBOND | QFP128 | For safety, the bq24400 inhibits fast charge until the battery voltage | |
| GB7 | (4) | IR | SOP | SUMMARY DESCRIPTION The M41ST85Y/W Serial TIMEKEEPER®/Con- troller | |
| GB9 | (1) | 90 | The circuit functionality is guaranteed within operation of ambien | ||
| GBA | (14) | 13 | CGRIX | Description The ACMD-7401 is a miniaturized duplexer designed using Agil | |
| GBB | (20) | Micrel | SOT-23- | 2005 | Figure 1 shows a typical battery pack application of the bq2014 using the |
| GBC | (2) | S3067 has the ability to bypass the internal VCO with an external sourc | |||
| GBD | (6) | N/A | 0805BEAD | The ispClock5500s PLL and divider systems supports the synthesis of clock | |
| GBE | (2) | NS | DIP-20 | 84-87+/CB | The CDC7005 is a high-performance, low-phase noise, and low-skew clock sy |
| GBF | (5) | ir | ir | dc94 | Notes: 1. TC is defined as case temperature, the temperature of the under |
| GBG | (1) | 2002 | With the integration of voice, video and data services into the same netwo | ||
| GBH | (1) | AI | SOT-323-6 | 04+ | † Stresses beyond those listed under absolute maximum ratings may c |
| GBI | (12) | GORDOS | 2007 | Pb−Free Packages are Available No Auxiliary Winding Operation Auto | |
| GBJ | (88) | PJ/LT | 07+ | RSL (Pin 4): The slew control resistor sets the maximum current and volta | |
| GBK | (4) | PWM current drive is integrated with 8 bits of control. Four bits are glo | |||
| GBL | (53) | N/A | 1206L | Bottom of DAC reference ladder. Normally bypassed with a 0.1µF capac | |
| GBP | (195) | Vishay | GBPC12W | 08+ | The FMS6346 provides an internal diode clamp to support AC- coupled inpu |
| GBR | (3) | CENTRAL | 04+/05+ | Inputs Are TTL-Voltage Compatible Provide Bus Interface From Multiple So | |
| GBS | (3) | NOTES: 1. For a loaded output the measurements are observed after | |||
| GBU | (131) | DIO | 1 | A 1.5 MΩ value of RREF from log average to C15 V will establish a 1 | |
| GBW | (1) | PHILIPS | SOIC-14 | 07+/08+ | A proper value of feed forward capacitor parallel with R1 can impr |
| GBX | (1) | Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V | |||
| GBY | (1) | DIODE | The bq2050H measures the voltage differential between the SR and VSS pins | ||
| G-C | (1) | AGERE | 2006Pb | The ballast control section is built around the IR21592 Dimming Ballast C | |
| GC- | (12) | PBF | This is the forward transconductance of the device at a specified value o | ||
| GC0 | (5) | N/A | N/A | 00+ | Digital Filter, DAC and Analog Low-Pass Filter Blocks • Digital de |
| GC1 | (36) | TI | 256BGA | 06+ | 9. PRESET MEMORY BUTTONS (1, 2, 3, 4, 5, 6) These buttons are used |
| GC2 | (13) | MOTOROLA | 06+ | replacement; Electrically Erasable (EE) technology allows reprogrammabili | |
| GC3 | (8) | TI | 07+ | Like XC3000A, the XC4000E family has Soft Startup. When the configuratio | |
| GC4 | (16) | GRAYCHIP | 00+ | Upon applying a reverse-polarity voltage to the DC/DC converter, an intern | |
| GC5 | (21) | TI | 07+ | The ADS8509 is a complete 16-bit sampling analog-to-digital (A/D) conve | |
| GC6 | (13) | DIP | The TLC372C is characterized for operation from 0C to 70C. The TLC372I is | ||
| GC7 | (9) | GC | SMD | 99+ | The boost-converter operating frequency can be set at 16, 24, or 32 times |
| GC8 | (119) | INTEL | BGA | Dimensions in mm. The components are situated on one side of the Rogers | |
| GC9 | (17) | FEVSY | PDIP64宽 | 244 | Figure 1 shows the timing of the encoder data clock (EDC), the e |
| GCA | (38) | LGS | CDIP16 | 2007+ | LoDCR mΩ DCR mΩ HEAT RATING INDUCTANCE TYPICALM |
| GCB | (14) | N/A | 0603B | Note: 1. All input pulses are supplied by a generator having the followi | |
| GCC | (2) | H-L | 06+ | The ISL6537A provides a complete ACPI compliant power solution for up to | |
| GCD | (10) | LGS | O7+ | Beneficial comments (recommendations, additions, deletions) and any perti | |
| GCE | (5) | The TMS41x809 series is a set of high-speed, 16 777 216-bit dynamic ran | |||
| GCF | (55) | NIEC | TO | The PT6360 Excalibur™ series of integrated switching regulat | |
| GCG | (6) | MURATA | The performance of the XA architecture supports the comprehensive bit-o | ||
| GCH | (3) | Figure 8 shows the connections for producing a C 10.24 V full- scale swi | |||
| GCI | (42) | CURRENT COMMAND (+,-) - are differential inputs for con- trolling the mod | |||
| GCM | (120) | MURATA | . | 09+ | The 74LVC(H)16244A is a 16-bit non-inverting buffer/line driver with 3- |
| GCN | (1) | The K9K1208U0A are a 64M(67,108,864)x8bit NAND Flash Memory with a spare | |||
| GCO | (3) | ||||
| GCQ | (3) | TO-220 | The communications interface allows the host to observe and control the c | ||
| GCR | (11) | GCRL | 04+ | required. The HSMP-48XX series are special products featuring ultra low | |
| GCT | (4) | SINKA | 02+ | SOP | Center tap chip resistors allow for greater flexibility of hybrid layout |
| GCU | (4) | 1735 | The HYM72V32656AT8 Series are 32Mx64bits Synchronous DRAM Modules. The mod | ||
| GCW | (1) | TTL/CMOS Reference input pre-scalar and Zero Delay MUX divider select inpu | |||
| GCX | (1) | N/A | 05+ | The HS I2C™-compatible module is a reference solution for implement | |
| GD- | (5) | INTEL | BGA PB | 05+ | NOTEGD-GM410GD08: (1) Input is less than 1% of full scale. (2) CGD-GM410G |
| GD1 | (87) | GIGA/INTEL | 04+ | ESD damage can range from subtle performance degrada- tion to complete d | |
| GD2 | (13) | INTEL | Port 3 Port 3 is an 8-bit bidirectional I O port with internal pullups Th | ||
| GD3 | (14) | INTEL | P | BGA | NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATI |
| GD4 | (136) | LG | DIP | 9606 | The Hynix 8Mx16 DDR SDRAMs offer fully synchronous operations referenced |
| GD5 | (25) | GS | DIP-16 | 87 | Sector data protection is afforded by methods that can disable any combin |
| GD6 | (22) | cirrus | cirrus | dc91 | CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic ch |
| GD7 | (502) | GS | DIP | 08+ | |
| GD8 | (69) | INTEL | BGA | Information furnished by Analog Devices is believed to be accurate and r | |
| GD9 | (3) | The receive (D/A) filter provides interpolation filtering on the 8 kHz sam | |||
| GDA | (8) | DAEWOO | 2008 | Internal synchronous rectification greatly improves efficiency and elimina | |
| GDB | (8) | MOTOROLA | 03+ | The power supply operating range of the EL2245 and EL2445 is from 18V d | |
| GDC | (23) | GIGA | BGA | 01 | The GDC16584 is a single-chip audio digital signal processor incorporati |
| GDD | (2) | INTEL | 05+ | BGA | DESCRIPTION Input reference frequency, 5V tolerant input Buffered clock |
| GDE | (5) | NOTES: (1) Includes the effects of amplifiers input bias and offset curre | |||
| GDF | (1) | ||||
| GDG | (2) | The 33099 uses a feedback voltage to establish an alternator field | |||
| GDH | (18) | Parameter SUPPLY VOLTAGES AVDD CLKVDD DVDD | |||
| GDL | (15) | PHILIPS | 2008 | Each DS1270 device is shipped from Dallas Semiconductor with its lithium | |
| GDM | (28) | PRX | SOP | To allow for convenient reading of blocks of contiguous data, the devic | |
| GDO | (1) | N/A | NOTES: 1. For conditions shown as Min. or Max., use the appropriate valu | ||
| GDP | (29) | ALCOSWIT.. | N/A | 06+ | The RAC pin remains HIGH for 109.38 µsec and stays LOW for 15.63 & |
| GDR | (8) | ALCOSWITCH/TYCO | N/A | The MAX4729/MAX4730 are available in small 6-pin SC70 and 6-pin µDF | |
| GDS | (44) | N/A | Parameter Forward Voltage Terminal Capacitance Collector Dark Curren | ||
| GDT | (2) | G-DESIGN | 04+ | QFP/48 | This register configures the directions of the I/O pins. If a bit in this |
| GDV | (1) | SOSHIN | 4532-5点 | 05+ | The ATGDVC02-254M features DATA polling to indicate the end of a program |
| GDX | (5) | N/A | QFP | Introduced in 1987/88, XC3000 is the industrys most successful family o | |
| GDZ | (81) | VISHAY /SI | 805 | 135-mΩ -Maximum (5-V Input) High-Side MOSFET Switch 500 mA Continu | |
| GE- | (5) | MOT | CAN3 | 04+ | The MAX2601/MAX2602 are RF power transistors opti- mized for use in porta |
| GE1 | (28) | PHIL | 01+ | TO-3 | During power-on, RESET is asserted when the supply voltage VDD becomes hi |
| GE2 | (76) | SOT-23 | After the software chip erase has been initiated, the device will intern | ||
| GE3 | (8) | HARRIS | DIP | 00+ | Unless otherwise specified: -40C < TAMB < 85C, -40C< Tj< 125 |
| GE4 | (12) | N/A | N/A | N/A | The CH1817 is a Family of Low Profile Data Access Arrangement (DAA) Modul |
| GE5 | (7) | PHIL | 01+ | TO-3 | • Added Reverse Type Package in ODERING INFORMATION and PIN CONFIGUR |
| GE6 | (11) | PHIL | 01+ | TO-3 | • Moisture Resistance, steady state: MIL-STD-883, method 1004.7, 85% |
| GE7 | (2) | 01+ | BGA | 96 Outputs Plasma Display Driver 95V Absolute Maximum Rating Reduced E | |
| GE8 | (13) | GE | 07+ | Variable gain amplifier (MMIC-Amplifier) for mobile communication Typica | |
| GE9 | (4) | GE | 07+ | Each device requires only a single 3.0 volt power supply for read, progra | |
| GEA | (1) | MOT | Before valid data exchanges between the serializer and deserializer can r | ||
| GEB | (2) | MOTOROLA | 03+ | Available Capacity in Nicd or NiMH Batteries Measures a Wide Dynamic-Cur | |
| GEC | (25) | ST | TO-220-7H | Interrupts • 12 sources 8 vectored interrupts 1. External I | |
| GED | (3) | inmos | Note 3 The HALT mode will stop CKI from oscillating in the RC and the cry | ||
| GEE | (3) | AMI | DESCRIPTION The NJW1503A is a PLL frequency synthesizer es | ||
| GEF | (81) | ST | 05+ | SOP-20 | 1 Gbit/sec, 100 MBytes/sec, each direction with full duplex support Up |
| GEG | (2) | ||||
| GEI | (1) | During the turnCon and turnCoff delay times, gate current is not constan | |||
| GEM | (48) | TSSOP | Ripple and noise are defined as periodic or random signals over th | ||
| GEN | (33) | LAMBDA | Module | N/A | Power supply for PCI clocks, nominal 3.3V Ground pin. PCI clock output |
| GEO | (4) | rs | rs | dc74+ | Operating features include an on/off inhibit, output voltage adjus |
| GEP | (4) | • 1.5 Mbps data rate • On-chip 3.3V regulator • Endpoi | |||
| GEQ | (2) | ||||
| GER | (4) | ITT | NEW | 86+ | DESCRIPTION The 74AC138 is an advanced high-speed CMOS 3 TO 8 LINE DEC |
| GES | (10) | The Data ALU registers can be read or written over the X memory data bus | |||
| GEX | (3) | This block performs a parallel transfer to/from the internal memory for t | |||
| GF- | (33) | ELectroMed | SOP20 | 0502+ | Write Enable 1 (WEN1). If the FIFO is configured for program- mable flags |
| GF0 | (20) | NVIDIA | BGA | 04/05+ | Atmels AT77C105A fingerprint sensor is dedicated to PDA, cellular and sma |
| GF1 | (69) | GATEFIELD | 97+ | A sophisticated interrupt structure recognizes up to eight interrupt level | |
| GF2 | (20) | NSC | 2008 | No external component required. LED sink current 20 mA and 15mA Indivi | |
| GF3 | (11) | ZOWIE | 07+ | The decoders receive data that are transmitted by an encoder and interpr | |
| GF4 | (37) | SOP/8 | 93+ | POWER-UP When power is first applied, power-on reset circuitry initial- | |
| GF5 | (8) | NEC | SOT | 05+ | Absolute Maximum Ratings are stress ratings. Stresses in excess of thes |
| GF6 | (8) | GF | TSSOP | 05+ | The device that acknowledges, has to pull down the SDA line during the |
| GF7 | (2) | TI | BGA | 03+ | 22811-009-DTS Rev ADQ# 2010 All technical information is believed to be |
| GF8 | (1) | DIP-8 | 05+ | MRS initializes the read and write pointers to zero and sets the output re | |
| GF9 | (24) | SOSHIN | 4(1206) | 04+ | The third generation of LCA devices further extends this architecture w |
| GFB | (13) | TR3 | 01+ | - Suspends erase operations to allow programming in same bank Da | |
| GFD | (5) | GREYFIELO | DIP | The LMV791 provides optimal performance in low voltage and low noise sy | |
| GFF | (2) | 大铁帽 | 08+ | Ambient Temperature under Bias Storage Temperature Voltage on any Pin | |
| GFG | (1) | Source code: ◊ VHDL Source Code or/and ◊ VERILOG Source Code | |||
| GFH | (1) | HARRIS | DIP-6 | 91+ | Hynix HYMD116G725A(L)8M-K/H/L series incorporates SPD(serial presence dete |
| GFI | (1) | System Reliability: Battery-backed SRAM is inherently vulnerable to shock | |||
| GFM | (2) | SOSHIN | 1812-5脚 | 05+ | Differential current outputs are provided to support single- ended or di |
| GFO | (6) | NVIDIA | PBGA | The new low current, high speed AlGaAs emitter manufactured with a uniqu | |
| GFP | (12) | HITACHI | TO-220 | 99+ | If one of the battery voltages becomes higher than the over charge detecti |
| GFR | (1) | n Pin-to-pin compatible to DS90C383, DS90C383A and DS90C385 . n | |||
| GFS | (5) | NVIDIA | BGA | N/A | making it an Ideal Device for Applications where Board Space is at a Pre |
| GFU | (2) | Notes: 1. NC pins are not connected to the die. 2. E3 (DNU) | |||
| GFW | (6) | SOSHIN | SOT | When one of the cell voltages exceeds V(PROTECT), an internal current so | |
| G-G | (2) | The ICSI IC61S6432 is a high-speed, low-power synchronous static RAM des | |||
| GG- | (1) | The voltage drop (VSR) across the sense re- sistor RS is monitored and i | |||
| GG0 | (4) | TI | 97 | An additional ST ROM contains all ST provided functions and libraries. | |
| GG1 | (4) | FUJNSU | QFP | Supply current and output power are a function of the voltage input on th | |
| GG2 | (1) | SE: 1 W to 25 W, BTL: 4 W to 50 W operation possibility (2.1 system) Sof | |||
| GG3 | (1) | SOT-89 | GMT | 05+ | Each arbitrary length of data packet consists of 3 portions viz, Row addre |
| GG4 | (1) | 25 | INTERSIL | 200 | The PCA9548A is an octal bi-directional translating switch controlled via |
| GG9 | (1) | IR | 04+ | - changed multiplier table - faster operating frequencies | |
| GGA | (1) | MOT | TSOP8 | 05+ | The BCT8244A scan test devices with octal buffers are members of the Te |
| GGB | (1) | MOT | TSOP8 | High performance 32-bit/40-bit floating point processor optimized | |
| GGC | (2) | ROM-less product of the µ PD78078 Counter-measure against EMI noi | |||
| GGE | (1) | CYPRESS | 四面52P | Honeywell reserves the right to make changes to improve reliability, funct | |
| GGF | (1) | IDT | SOT23-5 | 1999+ | The RC32355 is a System on a Chip which contains a high perfor- m |
| GGG | (1) | TI | 00+ | Silicon chip on Direct-Copper-Bond substrate - High | |
| GGH | (1) | synchronously with the LOW-to-HIGH clock (CP) transition. When one or b | |||
| GGI | (1) | 06+ | PLCC-44 | NOTES 1. Operating temperature range is as follows: B Version: C40C to + | |
| GGK | (5) | Footnotes: 1) Standard frequency stability (20,25,50ppm & others avai | |||
| GGU | (1) | 99+ | 117 | BGA | 2.3 Order of precedence. In the event of a conflict between the te |
| GH- | (6) | 03+ | QFN/48 | Two Channels: Measures Both Remote and Local Temperatures No Calibratio | |
| GH0 | (28) | SHARP | 05+ | CHS=0,BAL=11111 Vin = 1Vrms Vo=0.5Vrms BW=400Hz to 30kHz Vin=1Vrms BW | |
| GH1 | (12) | Output noise can be reduced to 18µV (typical) by connecting an ext | |||
| GH2 | (3) | MITSUBSHI | 达林顿 | Reference Output Voltage: This output biases to VCC C1.2V. Connect to VT | |
| GH3 | (7) | GH | DIP6 | 0510+ | The SA2400A is a fully integrated single IC RF transceiver designed for |
| GH4 | (2) | A buffered Output Enable (OE) input can be used to place the nine outputs | |||
| GH5 | (2) | N/A | N/A | Dynamic Response (ýIO/ýt = 1 A/10 µs, VI = VI, | |
| GH6 | (8) | SHARP | O7+ | SRAM • Power dissipation Operating : 40 mA Max &n | |
| GH7 | (2) | SOP | 08+ | Notes: 1. Load and Line Regulation are specified at a constant junction | |
| GH8 | (3) | 2003 | DIP-18 | 1) CPD is defined as the value of the ICs internal equivalent capacitance | |
| GHA | (7) | ||||
| GHD | (6) | N/A | |||
| GHF | (4) | ST | 00+ | DIP-16 | DESCRIPTION This Power MOSFET series realized with STMicro- electronics |
| GHG | (1) | Figure 18.TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Bottom View P | |||
| GHM | (118) | N/A | 1812 | Fully operational to +500V or +600V Tolerant to negative transient voltag | |
| GHO | (1) | Offered in 128Mx8bit the K9F1G08X0A is 1G bit with spare 32M bit capacity. | |||
| GHP | (3) | N/A | QFP | If CS2 exceeds 0.5V the outputs will be disabled and a softstart commen | |
| GHR | (5) | JST | 07+ | 1550 | The UCC1800/1/2/3/4/5 family offers a variety of package options, tem- p |
| GHS | (1) | High Power Switching Regulator Controller for 3.3V-5V to 1.xV-3.xV Step-D | |||
| GHT | (2) | DESCRIPTION The STV5345 is a HCMOS integrated circuit which performs al | |||
| GHV | (4) | abb | abb | dc95 | XTAL1 and XTAL2 are input and output, respectively, of an inverting ampli |
| GI- | (3) | LATTICE | 00+ | PBGA | Hewlett-Packards HSMS-2850 family of zero bias Schottky detector diodes |
| GI1 | (10) | N/A | SOP5.2mm | 2006 | Each device requires only a single 3.0 volt power supply for read, progra |
| GI2 | (12) | VIS | TO- | Ruotare il selettore su OC . Quando lalimentazione a ON e si applica i | |
| GI3 | (5) | SOP16M | 2007+ | If necessary, a REF instruction can be circumvented by means of a skip ope | |
| GI4 | (2) | 1817 | COMP (pin 9) and FB (pin 10) COMP and FB are the accessiable pins of the | ||
| GI5 | (12) | The HYS64D128020GBDL are industry standard 200-pin 8-byte Small Outline D | |||
| GI6 | (1) | Junction temperature = ambient for +25C specifications. Ju | |||
| GI7 | (25) | Vishay | P600 | 08+ | The transceiver performs the data parallel-to-serial and serial-to-parall |
| GI8 | (28) | VIS | 07+ | 1.1 Scope. This specification covers the performance requirements | |
| GI9 | (58) | 97 | TAOperating free-air temperature−4085C NOTES: 4. VCCI is th | ||
| GIB | (8) | IR | TO-220 | 03+ | PROCESSOR RESET/INITIALIZE: The INIT pin is used as a second reset pin fo |
| GIC | (21) | ZILOG | DIP | 00+ | NOTES 1Oversampling disabled. Static DAC performance will be improved wi |
| GID | (3) | The TOSHIBA GID2, −2 and −4 consist of a photo−transist | |||
| GIG | (3) | Note 4: For a power supply of 5V r10% the worst-case output voltages (VOH | |||
| GII | (4) | sgs | sgs | dc82+ | The AC533 devices are octal transparent D-type latches with 3-state out |
| GIK | (1) | Internal High Voltage Startup Regulator Minimum Operating Voltage of 21. | |||
| GIL | (23) | LS?? | 2005 | Notes: 1. For codes not listed in the figure above, please refer to the | |
| GIM | (1) | XTAL1 and XTAL2 are the input and output respec- tively of a inverting a | |||
| GIP | (40) | N/A | SOP8 | N/A | The maximum power package dissipation is the power dissipation le |
| GIS | (2) | Access to the user zones occurs only through the control logic built into | |||
| GIT | (2) | N/A | TSSOP-28 | NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. Minimums guaranteed but not p | |
| GIX | (1) | The bq2000 uses a peak-voltage detection (PVD) scheme to terminate fast c | |||
| GIZ | (2) | ROHM | SOP | Designed for ultraClinear amplifier applications in 50 ohm systems | |
| GJ2 | (11) | ＭＵＲＡＴＡ | • Synchronous Operation. • On-Chip Address Counter. • | ||
| GJ4 | (3) | Ceramic Capacitors Above 150 kHz the performance of aluminum electrolyti | |||
| GJ6 | (7) | Note: Some revisions of this device may incorporate deviations from publi | |||
| GJ7 | (4) | A write operation requires an 8-bit data word address following the devic | |||
| GJ8 | (1) | INTEL | |||
| GJ9 | (3) | GENJET | SOP | 9806 | o Powered Device Interface Fully Integrated IEEE 802.3af-Complian |
| GJA | (1) | MOT | TSOP8 | 05+ | The ZR78L Series show performance characteristics superior to other loca |
| GJC | (2) | SIP | GINJET | 92+ | The IRU431L keeps a constant voltage of 1.240V be- tween the Ref pin and |
| GJM | (60) | MURATA | 2007+PB | (1) The algebraic convention, whereby the most negative value is a minimu | |
| GJP | (2) | BGA | 07+ | The LM4980 is a stereo headphone audio amplifier, which when connected | |
| GK- | (7) | high-frequency tube | MITSUBISHI | 04+ | The MC10H/100H680 is a dual supply 4Cbit differential ECL bus to T |
| GK0 | (2) | GENNUM | DIP | The uA9636AC is a dual, single-ended line driver designed to meet ANSI St | |
| GK1 | (11) | WYC | DIP-4 | 08+ | A digital audio receiver (U002) is provided for easy connec- tion to S/P |
| GK2 | (2) | N/A | QFN | 07+ | (4) The products described in this material are intended to be used for s |
| GK5 | (2) | DIP-14 | 9701+ | 3.2 Design, construction, and physical dimensions. The design, con | |
| GK6 | (1) | SINO MATRIX | SSOP-20P | 2004 | Preliminary Information- These data sheets contain minimum and maximum sp |
| GK9 | (2) | Features • Integral Signal Conditioning • Linear Output | |||
| GKB | (3) | CISCO | PGA | 0144+ | Measurements are done with the 13 MHz oscillator in slave mode. Measurem |
| GKC | (2) | MOTO | TSSOP-8 | 2004 | The AD5399 is the industry-first dual 12-bit digital-to-analog converter |
| GKD | (4) | SP | 00+ | Note: Stresses greater than those listed under Absolute Maximum Ratings | |
| GKG | (11) | Panasonic | The addition of positive feedback (< 10 mV) is also recommende | ||
| GKH | (1) | MOT | 00+ | The Power Saving (PS) module implements the Idle Mode (ARM7TDMI core cloc | |
| GKM | (2) | SOP | The low-cost ADS-950 is an 18-bit, 500kHz sampling A/D converter. This | ||
| GKR | (2) | CDMA balanced input pin. This pin is internally DC-biased and should be | |||
| GKT | (1) | GENNUM | . | 100KEP circuits are designed to meet the DC specifications shown in the a | |
| GKU | (2) | The internal voltage regulator is temperature-compen- sated to assure pr | |||
| GKY | (1) | ADDRESS DATA BUS: These lines constitute the time multiplexed memory/IO a | |||
| GL- | (20) | SHARP | 2002+ | Even though absolute integral and differential linearity specs are not g | |
| GL0 | (6) | ITT | SOT-23 | N/A | The performance over temperature is achieved by inte- grating th |
| GL1 | (65) | N/A | 06+ | 500 | Economical surface mount design in both J-bend or Gull-wing terminations |
| GL2 | (24) | N/A | " Window structured high power laser diode ideal for high speed &nb | ||
| GL3 | (124) | SHARP | 04+ | The SONIC (Figure 1-1 ) consists of an encoder decoder (ENDEC) unit media | |
| GL4 | (76) | 台产 | 05+ | 4.3 Screening (JANTX, JANTXV, and JANS levels only). Screening sha | |
| GL5 | (64) | 03+ | The line on the graph shows the actual temperature that might be experie | ||
| GL6 | (62) | DIP | Through in-system programming, connections between I/O pins and archite | ||
| GL7 | (32) | GL | QFP | 01+ | Pad size in PCB Pad Shape Pad Definition Solder Mask Opening Solder St |
| GL8 | (62) | 04+ | QFP | CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active | |
| GL9 | (42) | SHARP | 05+ | Note 1: BYP internally connects to the active power input (DCLV or USB). D | |
| GLA | (12) | GPS | PLCC | 93 | A start may be issued to terminate the input of a control byte or the i |
| GLB | (6) | GIGALINK | SOP | C Random Access Time C 70 ns C Page Mode Read Time C 20 ns | |
| GLC | (53) | N/A | 06+ | 500 | OE controls the impedance of the output buffers. While CAS and RAS are lo |
| GLD | (15) | PARAMETER Frequency Range Frequency Tolerance Frequency Coefficient | |||
| GLE | (13) | NS | DIP | 2006 | The ICL7136 is an improved version of the ICL7126, eliminating the overra |
| GLF | (33) | N/A | 0603L | UL recognition2500 Vrms for 1 minute per UL 1577 CSA Compon | |
| GLG | (2) | MOT | QFP | ||
| GLI | (3) | CARRY | QFP | 05/06+ | (VCC = +2.7V to +3.3V, RRBIAS = RRLNA = 24kΩ, BUFFEN = LOW, all RF a |
| GLJ | (1) | ||||
| GLK | (7) | NOTES: 1. EVB555 boards (revision 1.1/1.2) can be modified by conn | |||
| GLL | (60) | Vishay | 08+ | 2. The ALD1704 has complementary p-channel and n-channel input di | |
| GLM | (15) | If during any pushbutton activity the STR input is activated, pushbutton | |||
| GLO | (1) | SAMSUNG | 07+/08+ | The VHC164 is an advanced high-speed CMOS device fabricated with silico | |
| GLP | (15) | SOSHIN | CHRG (Pin 3): Open-Drain Charge Status Output. When a depleted battery is | ||
| GLR | (1) | ||||
| GLS | (7) | TARNSFER/MARNUAL | These 8-bit registers feature 3-state outputs designed specifically for | ||
| GLT | (164) | G-LINK | SOJ | 1996 | CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL |
| GLU | (5) | 01 | Writing to the control register address with bit 7 set is the mode defini | ||
| GLX | (3) | JAT | 05+ | A microcontroller can be monitored by a digital window watchdog which acc | |
| GLZ | (28) | GS | 0805-12V | Support Mode 3 (11 MB s) timing proposal on en- hanced IDE (IDE-2 or ATA | |
| GM- | (9) | Low Cost Complete H-Bridge 8 Amp Capability, 75 Volt Maximum Rating Sel | |||
| GM/ | (1) | AMIS | SOP28 | To successfully enter the low-power mode, the MC68SEC000 must first be in | |
| GM0 | (15) | LGS | (2) JC data values stated are derived from MIL-STD-1835B which states the | ||
| GM1 | (110) | GENESIS | 0427+ | ||
| GM2 | (120) | G | . | The VHC132 is an advanced high speed CMOS 2-input NAND Schmitt Trigger | |
| GM3 | (49) | N/A | N/A | N/A | • Best in class in DIP7, DIP8, TO220, I2Pak packages • Leadfr |
| GM4 | (20) | 1735 | Undershoot Clamp Diodes Low Power Consumption (ICC = 0.25 mA Typical) V | ||
| GM5 | (77) | GENESIS | TDIR Direction Control TTL Levels EDIR Direction Control ECL Levels | ||
| GM6 | (107) | GENESIS | MQFP | 0529+PB | The VP-1000A is an advanced CMOS LSI chip for general purpose voice/soun |
| GM7 | (764) | 4911 | Input Voltage • 10 to 16 VDC HR15X-12XX • 18 | ||
| GM8 | (48) | SEMA | QFN-28 | 04+ | The light beam projected by the LED, passing through the condensing len |
| GM9 | (28) | LGS | TOSHIBA is continually working to improve the quality and reliability of | ||
| GMA | (80) | ROHM | LU applies between LL1 and LL2 LD applies between LL2 and LL minimum. Di | ||
| GMB | (20) | G.P | SOT23 | 05+ | 60/120- is a pin for selecting the orientation of the commutation scheme |
| GMC | (337) | 08+ | 1000:1 Dimming Range: The DIG_DIM input accepts a TTL or CMOS lo | ||
| GMD | (7) | N/A | BGA | 07+ | Notes: 1. The luminous intensity, I v, is measured at the peak of the s |
| GME | (2) | QLOGIC | 03+04 | TQFP2020-144 | The MITSUBISHI M5M28F101A is high-speed 1048576-bit CMOS Flash Memories. |
| GMF | (17) | 07+/08+ | Feedback Reference Voltage Switching Frequency Maximum Duty LX ON Resis | ||
| GMG | (1) | HYUPJIN | Care must be taken when attaching this product, whether it is done manual | ||
| GMH | (1) | Fully Integrated VCC and Vpp Switching for Dual Slot PC CardTM Interface | |||
| GMI | (2) | N/A | PLCC | 07+ | DATA MEMORY Data memory consists of a 512-bit RAM organized as 8 data r |
| GMK | (24) | TAIYO | . | 09+ | The Hynix HYM7V73AC801B H-Series are 8Mx72bits ECC Synchronous DRAM Module |
| GML | (2) | NS | SOP-28 | 01+/SX | Notes: 1. Repetitive Rating : Pulse width limited by maximum junction tem |
| GMM | (45) | HYNIX | 00+ | The AWT6135 meets the increasing demands for higher efficiency and line | |
| GMN | (3) | OKI | QFP128 | 00+ | C No HSYNC Jitter Anomaly C Negligible Data-Dependent Jitter Programmabl |
| GMP | (3) | DSI | n/a | Data output to Serial port Data Terminal Ready, active low Request To Se | |
| GMQ | (1) | Every manufacturing lot is tested in a low dose rate (total dose) envir | |||
| GMR | (27) | GMAMA | TO-220AB | 06+ | The TxDAC+ uses a digital 2 interpolation low-pass filter to oversample |
| GMS | (454) | LGS | SOP7.2mm | 2006 | This MOSFET is an enhancement-mode silicon-gate power field effect |
| GMT | (29) | UBKOM | N/A | Synchronization and shutdown pin. This pin may be used to synchronize the | |
| GMV | (10) | 98+ | 720 | TSSOP-44 | The Terminal Count (TC) output is HIGH when CET is HIGH and the counter |
| GMX | (3) | † All typical values are at VCC = 5 V. ‡ The parameters IOZ | |||
| GMZ | (45) | GENESIS | 35 | ||
| GN- | (1) | FURUNO | 02+ | The 74HC/HCT85 are 4-bit magnitude comparators that can be expanded to | |
| GN0 | (124) | PAN | SOT-363 | 05+ | Notes: 1. For codes not listed in the figure above, please refer to the |
| GN1 | (92) | NEC | SOT-323 | If the magnetic field exceeds the threshold levels, the current source | |
| GN2 | (16) | HITACHI | DIP | A typical communication on the Microwire bus is made through the CS, SK, | |
| GN3 | (1) | ||||
| GN4 | (25) | PANASONIC | SOT163 | Addresses, data I/Os, chip enables (E1, E2, E3), address burst control i | |
| GN5 | (2) | Panasonic | 96+ | SOP-5.2-10P | 5V CMOS and TTL Compatible Fast Switching Single Ev |
| GN6 | (8) | N | TO | Common I O for reduced pin count Four operation modes shift left shift r | |
| GN7 | (2) | HYNIX | 04+ | The LT6011/LT6012 work on any power supply voltage from 2.7V to 36V and d | |
| GN8 | (7) | Panasonic | 06+ | Current limit is trimmed to ensure specified output current and co | |
| GNB | (2) | Note 1: Absolute Maximum Ratings indicate limits beyond which damage to t | |||
| GNC | (1) | N/A | DIP | 90 | Read the contents of the Data Register pointed to by R1CR0 |
| GNI | (11) | ||||
| GNJ | (2) | N/A | 0402X2 | Operating from a wide-input voltage range of 7 V to 36 V, the PTN78000 pr | |
| GNK | (1) | Stresses beyond those listed under Absolute Maximum Ratings may cause per | |||
| GNL | (1) | GOTREND | 2520-2R2K | 04+ | Note1: The maximum rating means the limitation over which the laser shoul |
| GNM | (43) | MURATA | The K9F6408U0C is a 8M(8,388,608)x8bit NAND Flash Memory with a spare 256K | ||
| GNN | (1) | 2) Verify that a shunt is installed on jumper JU3 (SYNC). 3) Connect a +2 | |||
| GNO | (2) | PANASONIC | The TPS203x family of power distribution switches is intended for applica | ||
| GNR | (2) | Output Current of 3.0 A 1.25 V Maximum Dropout Voltage at 3.0 A Over Tem | |||
| GNS | (3) | Pin 1 VCC1 ( a 5V) The logic and clock power supply pin Pin 2 DIRECTION | |||
| GNT | (26) | GAON | 05+ | The TLV320AIC2x is a low-cost, low-power, highly-integrated, high-perform | |
| GO1 | (2) | 7500 | 06+ | The J-Series DC tachometer generators are low ripple units possessing a | |
| GO2 | (3) | SIG | DIP-24 | 08+ | All functions of this device are fully controllable by management through |
| GO3 | (1) | ACEX 1K device package types include thin quad flat pack (TQFP), plastic | |||
| GO5 | (4) | NVIDIA | BGA | 04+ | COMP and FB are the available external pins of the PWM converter error |
| GO6 | (6) | NVD | BGA | 05+ | POWER MOS power supply voltage POWER MOS power supply voltage Internal |
| GO7 | (4) | WIS | 06+ | Six of the 32 registers can be used as three 16-bit indirect address regi | |
| GO9 | (1) | Port 3, I/O. Port 3 functions as both an 8-bit, bidirectional I/O port an | |||
| GOC | (1) | • Low On-Resistance (16Ω typ) Minimizes Distortion an | |||
| GOF | (10) | NVIDIA | BGA | 2006 | The AD7734 analog front end features four single-ended input channels wi |
| GOL | (4) | SMC | The PWR_DWN# signal is an asynchronous, active-low LVTTL input that place | ||
| GOO | (1) | SOP14 | 06+ | SENSE (Pin 1): Maximum Overcurrent Sense Input. A sense resistor (RSENSE) | |
| GOP | (5) | N/A | SOP8 | N/A | The ADM2486 driver has an active-high enable feature. The driver differe |
| GOT | (1) | MAL | Clocks in the ispLSI 1048 device are selected using the Clock Distributi | ||
| GOU | (1) | MN | CDIP34 | CLKDs output originates from the cross point switch and goes through a pr | |
| GP- | (9) | N/A | Receiver Detection Single 3.3-V Supply Operation 64-Pin TQFP Using TIs P | ||
| GP/ | (1) | These Schottky diodes are specifically designed for both analog and digi | |||
| GP0 | (25) | 06+ | DIP-40 | The MAX1589A low-dropout linear regulator operates from a +1.62V to +3.6V | |
| GP1 | (456) | SHARP | 05+ | In-band Interference Rejection 20dB max. 2103dBm Sensitivit | |
| GP2 | (167) | GULF | DO-15 | 2007 | • 35 I/O pins, including nine high-current pins (15 mA, max.), eight |
| GP3 | (46) | GP | ORG PACKING | 08+ | Soldering (10 seconds)+260˚C ESD Susceptibility Human |
| GP4 | (19) | MITEL | TQFP1414-100 | 00+/01+ | Transmit Ready A-B (active low) - This function is associ- ated with 44 |
| GP5 | (41) | gepe | gepe | dc92+ | This active input determines the cycle type when ADV is LOW. This is the |
| GP6 | (32) | SOP16M | 2007+ | Byte 0: Frequency, Function Select Register Bit @Pup Pin# Descripti | |
| GP7 | (10) | Note 1: Absolute Maximum Ratings are those values beyond which the life | |||
| GP8 | (6) | SHARP | 03+ | DIP | The capacitance (Ciss) is read from the capacitance curve at a voltage co |
| GP9 | (2) | GP | SOT23 | 2007 | The HIP6601B drives the lower gate in a synchronous rectifier to 12V, w |
| GPA | (13) | TSC | TO | Pin Description Address 0-2. These pins are used to select one of up to | |
| GPB | (2) | MOT | TSOP8 | 05+ | Write cycle time Write pulse width Address setup time Address setup tim |
| GPC | (27) | evx | evx | dc00 | The CY7C1380D/CY7C1382D SRAM integrates 524,288 x 36 and 1,048,576 x 18 S |
| GPD | (44) | PLUA | QFN | 04 | 4. Parameters listed in Table 3 are controlled via design or process and |
| GPE | (5) | PLUA | QFP | 04 | TEMP: This is the output voltage produced by the modules internal temper |
| GPF | (31) | Package[1] A: 7.6 mm (0.3 inch) Single Digit Seven Segment Display F: | |||
| GPG | (1) | GPG | 01+ | SOP-8 | (1) Lead Forming When forming leads, the leads should be bent at |
| GPH | (2) | 2000 | Overtemperature Detect The overtemperature detect circuit switches the l | ||
| GPI | (6) | SHARP | 光电 | 04+ | Lead Temperature (1.6mm or 1/16 from case for 10s)+260C (1) Stresses be |
| GPL | (13) | Generalpuls | QFP-80P | 0733+(PB) | Data sheet information is generally presented in the following sequence |
| GPM | (30) | JAT | 05+ | This advanced technology has been especially tailored to mini- mize on-st | |
| GPO | (1) | 05+ | PLCC | The control signals for the configuration memory device (CE, RESET/OE and | |
| GPP | (10) | Vishay | DO-204AL | 08+ | The primary color output (pins 29, 31, 33) and COMMON output (pin 27) are |
| GPR | (2) | TEMIC | 99 | minal voltage is buffered internally and also applied to the lSET termin | |
| GPS | (57) | N/A | SMD | N/A | Direct interface to TRIPLEX LCD Low power dissipation (100 mW typ ) Low |
| GPT | (6) | N/A | FEATURES ・High Output Power: 34.0dBm(typ.) ・High Linear | ||
| GPV | (5) | LG INNOTEK | 05+ | or Powered Down Low and Flat ON-State Resistance (ron) Characteristics O | |
| GPX | (1) | Capacitor mounted close to the power module helps ensure stabilit | |||
| GPY | (1) | The DS1225AB provides full functional capability for VCC greater than 4. | |||
| GPZ | (3) | fci | fci | dc98 | I²C uses a two-wire serial interface, comprising a bi-directional |
| GQ8 | (2) | INTEL | 06+ | Thermal Protection The FAN2502/03 is designed to supply high peak output | |
| GQB | (1) | MICROCHIP | SOP-8P | 2002 | INPUT LO: Direct output mode where CE/LD, HBEN, MBEN and LBEN act as inpu |
| GQE | (1) | In DPSK mode the 73K322L modulates a serial bit stream into di-bit pairs | |||
| GQM | (24) | MURATA | 04+ | 5mV/sec Analog: Up to 4x Digital: 1/256 to 64x for individual Bayer pat | |
| GQN | (1) | 99+ | Figure 2 illustrates the logic block architecture. Each logic block cont | ||
| GR- | (1) | The GR-318/GR-318/GR-318 quad analog switches feature low on-resistance o | |||
| GR. | (1) | ||||
| GR0 | (7) | LOGIC | QFP | 07+ | The bq4802Y/bq4802LY real-time clock is a low-power microprocessor peri |
| GR1 | (20) | DIPPER | SMA | 05+ | • Fast Page Mode Access Cycle • TTL compatible inputs and o |
| GR2 | (14) | N/A | 1210 | C One Assembly/Test Site, One Fabrication Site Enhanced Diminishi | |
| GR3 | (6) | High current sink/source 25 mA/25 mA Four external interrupt pins Time | |||
| GR4 | (34) | MURATA | 805 | 07+ | NOTES: (1) Stresses above these ratings may cause permanent damage. Expo |
| GR5 | (6) | N/A | 1812 | TOSHIBA is continually working to improve the quality and reliability of | |
| GR6 | (1) | SONY | 06+ | Re a dy / Bus y St a t us . I nd ic a t e s w he t he r a w r it e o r e | |
| GR7 | (2) | N/A | 1206 | Note 4: When the input voltage VIN at any pin exceeds the power supplies | |
| GR8 | (1) | N/A | N/A | 00+ | (6) When designing your equipment, comply with the guaranteed values, in |
| GR9 | (1) | STM1403C. VOUT is driven to Ground when SAL is activated (may be used w | |||
| GRA | (4) | SANYO | DIP-30 | 04+ | The SN65LV1224A has an input threshold sensitivity of 50 mV. This allows |
| GRB | (1) | • International standard package • Moderate frequency IGBT | |||
| GRC | (7) | GRAPHTEC | This Application Note describes the operation of the OTA and features v | ||
| GRD | (3) | 505µA supply current 75MHz bandwidth Power down to Is = 33µA | |||
| GRE | (9) | TI | DIP-40 | 07+/08+ | |
| GRF | (47) | SiRF | QFP32 | 00+ | (Unless otherwise specified, all typical values are for 25C ambient tempe |
| GRG | (1) | The TLV2352 is designed using the Texas Instruments LinCMOS™ techno | |||
| GRH | (34) | N/A | 1206 | Device operation. The GRH1030COG331J1K is a complete stepper-motor driver | |
| GRK | (19) | 0805c | • 0.17 µm Process Technology • Simultaneous Read/Write | ||
| GRM | (8082) | MURATA | The LPC2210/2220 microcontrollers are based on a 32/16 bit ARM7TDMI-S CPU | ||
| GRN | (7) | The CA3080 and CA3080A are similar in generic form to conventional oper | |||
| GRO | (7) | N/A | TSOP20 | 07+ | VINMAX = Maximum input voltage (V) VOUT = Output Voltage (V) VDSQP = V |
| GRP | (203) | MURADA | 2003+ | The CD4011B, CD4012B, and CD4023B types are supplied in 14-lead hermetic | |
| GRQ | (4) | ||||
| GRR | (1) | The voltage at the TOVER pin is equal to a logic-low level if the sensor | |||
| GRS | (3) | MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to th | |||
| GRU | (1) | DIODE | During reference input rearrangement, such as during a switch from the pri | ||
| GRX | (6) | XICOR | DIP-8 | 08+ | The analog input pin transfers its signal to the chip for recording. For |
| GRY | (2) | The DDX-2100 Power Device is a dual channel H-Bridge that can deliver ove | |||
| G-S | (1) | • Suppresses low-frequency noise, which output from CCD by the corre | |||
| GS- | (48) | ST | MODULE | N/A | LSB means least significant bit. With the 5 V input range, one LSB |
| GS0 | (24) | NS | 03+ | This application note presents the design of a temperature display LIN sl | |
| GS1 | (201) | TAIWAN | N/A | In XC4000E, the H function generator is more versatile. Its inputs can | |
| GS2 | (77) | GULF | SMB | 2007 | Hynix HYMD18M725A(L)6-K/H/L series is unbuffered 200-pin double data rate |
| GS3 | (108) | globe | globe | dc0402 | • as a function of the output voltage. Full current limit of 500 m |
| GS4 | (60) | SEM | SOT-23 | 05+ | † Stresses beyond those listed under absolute maximum ratings may c |
| GS5 | (16) | BOTHHAND | The light beam projected by the LED, passing through the condensing len | ||
| GS6 | (13) | stock | • Learn C Learning involves the receiver calculating the tra | ||
| GS7 | (304) | GSI | TSOP | 03+ | Stresses above these ratings may cause permanent damage. Exposure to abso |
| GS8 | (326) | SANYO | DIP | 1995 | Turbo codes improves a transmission link by an additional gain of 2 to 3 |
| GS9 | (138) | GENNUM | SOP-8 | 04 | In addition, the temperature compensation of the Hall IC can be fit to |
| GSA | (22) | SanRex | IGBT | Stereo ∆ ADC On-Chip Digital Anti-Alias Filtering Single-ended Inp | |
| GSB | (7) | N/A | This register configures the directions of the I/O pins. If a bit in this | ||
| GSC | (120) | The Read Status Register instruction provides access to the status regi | |||
| GSD | (21) | VISHAY | SOT-23 | ||
| GSE | (32) | SIEMENS | QFP | • Up to 10-A Output Current • 5-V Input Voltage • Wide | |
| GSF | (6) | SOSHIN | 05+ | SMD | |
| GSG | (4) | GSG | DIP8 | 0506+ | 1. VCC and GND This IC has two VCC terminals and three GND termina |
| GSH | (14) | The devices can also be used without a back-biasing magnet. In th | |||
| GSI | (27) | Vishay | GBU | 2007 | This document is a general product description and is subject to change wi |
| GSJ | (2) | TOSHIBA | QFP | If an ADJ-bypass capacitor is use, the amplitude of the output ripple w | |
| GSK | (4) | *1. AC for 1 minute, R.H. = 40 ~ 60% Isolation voltage shall be m | |||
| GSL | (11) | LATT | 99+ | Multi-purpose input / output pin (Figure 2-2). • Button input pin | |
| GSM | (39) | Xtal/Clock: The input to the on-chip clock oscillator. A Xtal or externall | |||
| GSN | (3) | This device contains six independent gates each of which performs | |||
| GSO | (14) | VISHAY | 07+/08+ | In addition, each material offers a specific reliability rating. It is | |
| GSP | (29) | 98 | The ISL6118 has two shutdown modes. When disabled with a load current les | ||
| GSQ | (8) | memory system applications results in full-speed, error-free operation wi | |||
| GSR | (25) | N/A | The first members of TIs new BiMOS general-purpose operational amplifier | ||
| GSS | (3) | MICROCHIP | DIP-8 | 98+ | The ISSI IS62LV5128LL is a low voltage, 524,288 words by 8 bits, CMOS SR |
| GST | (8) | Murata | 3p | 2001 | Method 1 In military standard (1131 A-2204B), the distortion pr |
| GSV | (1) | Asynchronous mode. XASY = 0 Asynchronous transmission, XASY = 1 Synchrono | |||
| GSW | (5) | MINI | PLCC | 04+ | The wide operating supply range and high accuracy make the LTC6101 ideal |
| GSX | (10) | golledge | golledge | dc04 | The MLX90247DSG sensor IC is integrated together with a PTC thermistor. |
| GT- | (206) | GT | 07+/08+ | The Hitachi HN58V1001 is a electrically erasable and programmable ROM org | |
| GT0 | (28) | FAIRCHILD | 01+ | SOP-3.9-14P | Hynix HYMD232646(L)8-K/H/L series is designed for high speed of up to 133M |
| GT1 | (51) | TOS | 04+ | SOP-8 | Ž An 80ns wide start convert pulse is used for all production testin |
| GT2 | (128) | GLOBESPA | BQFP132 | The bq2063 works with an external EEPROM. The EEPROM stores the configura | |
| GT3 | (49) | PLCC68 | Notes; (1) Repetitive Rating: Pulse Width Limited by Maximum Junction Te | ||
| GT4 | (132) | GALLEO | BGA | N/A | The CMOS bq3285E/L is a low- power microprocessor peripheral providing a |
| GT5 | (39) | LG | 04+ | Note 6: Load and line regulation are measured at constant junction temper | |
| GT6 | (69) | 06+ | The ALD1704 is a CMOS monolithic operational amplifier with MOSFET input | ||
| GT7 | (2) | SHARP | DIP-16 | This product has been designed to meet the extreme test conditions and env | |
| GT8 | (35) | TOSHIBA | 00+ | FUNCTION SWITCHING The device provides functions switching pins for both | |
| GT9 | (12) | CASIO | QFP | 9946 | Seven npn Darlington pairs -55C to 125C ambient operating temperature ran |
| GTA | (1) | N/A | NSC | 04+ | The MC74HC1G02 is a high−speed CMOS 2−input NOR gate |
| GTB | (2) | ALCATEL | PLCC84 | 06+ | The device integrates complete interfaces to mono microphones. External c |
| GTC | (44) | sharp | sharp | dc03 | The X1 and X2 pins are the input and output, respec- tively, of an inve |
| GTE | (9) | LGS | 08+ | The MM54C151 multiplexer is a monolithic complementary MOS (CMOS) integra | |
| GTG | (3) | Note: Stresses greater than those listed under MAXIMUM RATINGS may cau | |||
| GTH | (14) | N/A | ROW/COLUMN ADDRESS SELECT: In the A/A Mux interface, the R/C pin is used | ||
| GTI | (1) | SMD | |||
| GTJ | (3) | In many applications, the card or tag manufacturer may choose to overwr | |||
| GTK | (2) | The LM74As 4.5V to 5.5V or 3.0V to 3.6V supply voltage range, low suppl | |||
| GTL | (191) | SIEMSENS | 03+ | TSOP-28P | 1 For normal continuous operation. A higher Tj is allowed as an overload |
| GTM | (11) | N/A | 0805L | 1) Skew is defined as the absolute value of the difference between the ac | |
| GTN | (3) | FLEXTRONICS | 03+ | (1) Electrical characteristics for "L" suffix devices are ident | |
| GTO | (2) | NS | SMD | 91 | result in significant injury to the user. 2. A critical component is any |
| GTP | (4) | 220 | Both the twisted pair A (TPA) and the twisted pair B (TPB) cable interfac | ||
| GTR | (34) | The information, diagrams, and other data in this manual are correct and | |||
| GTS | (13) | N/A | Gain Bandwidth Product (G +20) Gain Peaking 0.1dB Gain Flatness Bandw | ||
| GTT | (2) | GOTOP TECHNOLOGY | SOP-16 | 08+ | Differential or single-ended clock input signal. For differential, LVPECL |
| GTV | (5) | N/A | The HYM71V8M755HCFU6 Series are Dual In-line Memory Modules suitable for | ||
| GTW | (4) | GOTREND | 04+ | 300 mA/1.9V/2.5V DC to DC for Co-processor Core 80 mA/2.8V Dual-mode LDO | |
| GTX | (5) | 16 | MICROCHIP | 97+ | 64-Bit SDRAM interface 66 MHz to 100 MHz frequency range Direct inte |
| GU- | (3) | SANKEN | ICCSupply currentVCC = MAX,All outputs disabled5270mA † All | ||
| GU1 | (21) | NORITAKE | 08+ | 5000 | Note 1: All parameters specified over standard operating conditions unles |
| GU2 | (13) | NORITAKE | 08+ | 5000 | Control signals for the I/O cell registers are generated using an extra |
| GU3 | (2) | Note 8: Care should be taken to include the effects of self heating when | |||
| GU4 | (1) | Notes: 3. VIL(min.) = −2.0V for pulse durations less than 2 | |||
| GUB | (1) | GSI | 03+ | The CY62137CV18 is a high-performance CMOS static RAM organized as 128K | |
| GUC | (1) | 93 | DAC full scale current control. A resistor connected between this pin and | ||
| GUD | (1) | The SN54LVC04A hex inverter contains six independent inverters designed f | |||
| GUF | (15) | GULF | DO-41 | 2007 | A single-ended reference clock on the unselected reference input can caus |
| GUL | (1) | EPSON | QFP | or bidirectional data flow in bursts. An automatic power down feature, c | |
| GUM | (3) | QUALCOMM | 06+ | QFP | Notes: 1. Permanent device damage may occur if the above Absolute |
| GUR | (5) | GS | High CTRCE(SAT) comparable to Darlingtons CTR guaranteed 0C to 70C Hig | ||
| GUS | (31) | 2008 | Building on experience gained from Virtex FPGAs, the Virtex-E family is | ||
| GUV | (1) | Genicom | 05+ | This is an input pin to the device and is generated by the master that i | |
| GV1 | (2) | JAT | 6.3X5.4 | 05+ | Begin analysis at the VOL (quiescent) point. This is the intersection of |
| GV2 | (4) | A range of surface mount, chip LEDs with a white diffused lens, available | |||
| GV4 | (3) | TOCOS | 03+ | SMD | The device offers complete compatibility with the JEDEC single-power-sup |
| GV6 | (1) | DELTA | TSOP48 | 07+ | The HA-5020 is a wide bandwidth, high slew rate amplifier optimized for v |
| GV7 | (3) | N/A | N/A | N/A | The SPT1018 has 10 KH and 100K ECL logic level compat- ible video contr |
| GV8 | (1) | AMS | Stresses beyond those listed under "absolute maximum ratings" m | ||
| GV9 | (4) | ||||
| GVA | (1) | MINI | 08+ | High surge capacity. For use in low voltage, high frequency inverters, f | |
| GVB | (1) | IBM | 00 | Stability The IRU431L has many different domains of stability as a funct | |
| GVC | (15) | LG | The speed and density of the CY7C344 makes it a natural for all types of | ||
| GVD | (1) | These devices can be used as two 8-bit transceivers or one 16-bit transce | |||
| GVM | (3) | Texas Instruments reserves the right to change its products and services | |||
| GVN | (2) | This document contains proprietary and confidential information of Perfor | |||
| GVP | (1) | N/A | BGA | * 1.1 Scope. This specification covers the performance requirements for N | |
| GVS | (28) | 3 | QFP | The amplifier works on any total power supply voltage between 2.7V and 36 | |
| GVT | (227) | SUMMARY DESCRIPTION The M68AW128ML is a 2 Mbit (2,097,152 bit) CMOS SRA | |||
| GVX | (1) | SNT-4A S-817A11APF-CUATFG S-817A12APF-CUBTFG S-817A13APF-CUCTFG | |||
| GW0 | (4) | KET | 04+ | VBIAS (VCC, VBS) = 15V, VSS = COM and TA = 25C unless otherwise specified. | |
| GW1 | (12) | 1808 | When 16/68# pin is at logic 1, this input is chip select C (active low) | ||
| GW2 | (3) | ST | TO-247 | 06+ | Note 1: Absolute Maximum Ratings indicate limits beyond which damage to t |
| GW3 | (14) | CONEXANT | 07+/08+ | The main purpose of this bipolar transistor is broad- band amplification | |
| GW4 | (2) | JAT | SMA | 05+ | The Texas Instruments MSP430 family of ultralow-power microcontrollers co |
| GW5 | (7) | INTEL | SOP | 05+ | The PIC14000 is supported by a full-featured macro assembler, a softwar |
| GW6 | (1) | DIP-20 | The products of the ELD series were newly developed to serve as drivers f | ||
| GW7 | (8) | GW | PLCC68 | N/A | R2 = (FSI x R1) / ( |Vin| - FSI) Where: FSI = The attenuated voltage bet |
| GW8 | (2) | N/A | SSOP-24 | 08+ | 4. Power amplifier It is necessary to insert the coupling capacit |
| GW9 | (5) | GW | No part of this publication may be reproduced or transmitted in any form | ||
| GWA | (1) | • Power-save pull-up resistor built-in (AL series) Frequency divid | |||
| GWC | (2) | PHILIPS | TSSOP14 | 07+ | SUMMARY DESCRIPTION The M68AF511AL is a 4 Mbit (4,194,304 bit) CMOS SRA |
| GWF | (1) | JAT | SMA | 05+ | advanced circuit design to provide ultra-low active current. This is ide |
| GWI | (17) | INTEL | BGA | The Intel 87C54 is a single-chip control-oriented microcontroller which i | |
| GWK | (1) | The OPA820 provides a wideband, unity-gain stable, voltage-feedback amp | |||
| GWL | (1) | BROADCOM | BGA | 0321+ | ‡ Stresses beyond those listed under absolute maximum ratings may c |
| GWM | (5) | IXYS | CAPACITOR SELECTION To minimize ripple voltage, output capacitors | ||
| GWR | (1) | Junction-to-case thermal resistance is specified from the IC junct | |||
| GWS | (7) | GW | 3000 | 07+ | The oscillators are available with SC or AT cut crystals and provide an |
| GWT | (2) | SIEMENS | 96/97+ | PLCC68 | Device bus operations are initiated through the internal command regist |
| GWY | (1) | SMD | GOTREND | 05+ | This monolithic Transil Array is based on 6 unidirectional Transils wit |
| GX- | (10) | CYRIX | 95 | The FM25L16 is a serial FRAM memory. The memory array is logically orga | |
| GX0 | (4) | ||||
| GX1 | (29) | N | PLCC | ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications | |
| GX2 | (8) | GX | DIP | Guard Outputs for Ion Detector Input +/-0.75pA Detect Input Current Inte | |
| GX3 | (2) | 40 | 2005 | Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserv | |
| GX4 | (16) | N/A | N/A | N/A | When the asynchronous initialize input, INIT, is LOW, the data in the ini |
| GX5 | (1) | Widebus Family D A-Port Outputs Have Equivalent 25-Ω | |||
| GX6 | (1) | DESCRIPTION The VN750, VN750S, VN750PT, VN750-B5 are a monolithic devi | |||
| GX7 | (1) | Multi-purpose input / output pin (Figure 2-2). • Button input pin | |||
| GX9 | (7) | CHINA | DIP | O3 | The AP436 is a high-speed controller designed to drive N-channel power MO |
| GXA | (1) | The 256/288-Mbit RDRAM devices are extremely high- speed CMOS DRAMs org | |||
| GXB | (2) | sie | sie | dc82 | The MHF Series provides full power operation at case temperatures from C |
| GXC | (4) | MOTO | 93+ | Power conversion gain from 2nd LNA/mixer to 1st IF, PRFin = -50 dBm No | |
| GXE | (1) | The ISL43140/ISL43141/ISL43142 are quad single-pole/ single-throw (SPST | |||
| GXI | (11) | 118 | CYRIX | 97+ | The DS1642 is a 2K x 8 nonvolatile static RAM and a full-function real tim |
| GXL | (15) | NS | BGA | AØ, BØ & CØ- are the connections to the motor ph | |
| GXM | (30) | CYRIX | BGA | The HC688 and HCT688 are 8-bit magnitude comparators designed for use i | |
| GXO | (13) | ||||
| GXP | (1) | HP | PLCC | 94+ | MCHS = # macrocells used in high speed mode MCLP = #macrocells used in |
| GXX | (1) | SAM | 4139 | 95+ | • Low profile <Height> PC board terminal type: 9.5 mm |
| GY1 | (1) | rft | n/a | Features l Advanced process technology l Key parameters optimized for P | |
| GY2 | (3) | 13 | RICOH | 215 | Specified for 79C, 112C and 132CChannel Loading Excellent Distortion Pe |
| GY3 | (1) | The W256 is a 3.3V/2.5V buffer designed to distribute high-speed clocks i | |||
| GY4 | (9) | The 74HC/HCT299 contain eight edge-triggered D-type flip-flops and the | |||
| GY5 | (1) | N/A | N/A | 500 | n 1 µs instruction cycle time n Three multi-source interrupts ser |
| GYA | (2) | The HYM72V32736T8 Series are Dual In-line Memory Modules suitable f | |||
| GYB | (1) | MOT | The HYM7V73AC1601B N-Series are Dual In-line Memory Modules suitable for | ||
| GYG | (1) | Address Inputs Byte Enable Data In / Out Data In / Out (word-wide mo | |||
| GYM | (1) | PHILIPS | SOP08 | 06+ | Edition 07.96 This edition was realized using the software system FrameMa |
| GYR | (1) | N/A | 06+ | QFN | To 0.1% of full scale, data cycles from zero scale to full scale to zero |
| GYT | (1) | GAL | TQFP/100 | 00+ | AP1128 is a linear regulator designed as a cost-effective solution for ac |
| GZ- | (6) | FUJITSU | 01+ | QFP | Please be aware that an important notice concerning availability, |
| GZ1 | (11) | vishay | vishay | dc03 | This EOL notification announces the cessation of manufacture of the device |
| GZ2 | (2) | The LTC®3717 is a synchronous step-down switching regulator controlle | |||
| GZ3 | (3) | N/A | 1206L | (1) An export permit needs to be obtained from the competent authorities | |
| GZ5 | (7) | vishay | vishay | dc01 | Enhanced Word Spotting capability (10 SI or 4 SD words) in parallel Nois |
| GZ6 | (4) | vishay | vishay | dc02 | The attached data sheets are provided by SAMSUNG Electronics. SAMSUNG Elec |
| GZ7 | (3) | me | me | dc78 | The READ command selects the bank from BA0, BA1 inputs and starts a bur |
| GZ8 | (5) | TSSOP20 | 98+ | Transfect cells at high cell density. 90-95% confluence at the time of t | |
| GZA | (3) | PHILIPS | DIP | 95+ | The receive section of the CYP15G0401DXA Quad HOTLink II consists of fo |
| GZB | (9) | Maximum power dissipation with no heat sink used. Lead soldering temperat | |||
| GZF | (4) | vishay | vishay | dc01 | The transmitters are inverting level translators that con- vert CMOS-logi |
| GZH | (10) | GT | 03+ | BGA | Note 2: All characteristics are measured with capacitor across the input |
| GZS | (1) | The oscillator is programmed with two resistors and a capacitor to set s | |||
| GZT | (1) | Please be aware that an important notice concerning availability, | |||
| GZZ | (6) | CONEXANT | BGA | 07+ | eight CAT24FC02 may be individually addressed by the system. The last b |
About Seekchip- Services - Comments - Contact us - Links - Map
© 2008 China Electronics Market,License 浙ICP备10014259号