| Mfg | pack | D/C | Descrpion | ||
| H.D | (1) | N/A | Controller (host) sends a start bit. Controller (host) send | ||
| H.F | (1) | Thermal Resistance, Junction-to-Case - IGBT Thermal Resistance, Junctio | |||
| H-0 | (2) | N/A | 865 | To program a Leading Edge Blanking period, connect a capacitor, C, to C | |
| H0- | (1) | HOSONIC | SOP | Figure 2 shows the typical Insertion Loss graphs of the PACSZ1284 for D | |
| H00 | (63) | Pulse | A | A | The RF5189 is a linear, medium-power, high-efficiency amplifier IC desi |
| H01 | (14) | NICHICON | SOP | • Linear Regulator − 3.3 V 2% Output Voltage & | |
| H02 | (12) | 25 | LT | Positive analog supply pin. This pin should be connected to a quiet volt | |
| H03 | (18) | N/A | 3X3可调电阻 | ANALOG I/O 8-Channel, 400kSPS High Accuracy, 12-Bit ADC O | |
| H04 | (19) | HARRZS | 05+ | No warranty is made with respect to uses, operating conditions, or combin | |
| H05 | (16) | MORNSUN | 08+ | Play In: The input via SW2 from a voice storage device such as the MX812. | |
| H06 | (5) | N/A | MQFP | 07+ | Industry's first TotalCMOS™ SPLD - both CMOS design and process t |
| H07 | (2) | M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on S | |||
| H08 | (8) | SEC | TO-92 C档 | N/A | The FM25L16 provides substantial benefits to users of serial EEPROM as |
| H09 | (4) | HAR | SOP-20 | Bluetooth is a registered trademark of Bluetooth SIG, Inc. and is used un | |
| H0A | (2) | MOT | Notes: 1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Dont | ||
| H0D | (1) | Hynix HYMD212G726A(L)S4-M/K/H/L series incorporates SPD(serial presence de | |||
| H0J | (6) | SMD | RIVER | 05+ | Atmel can accept Register Transfer level (RTL) designs for VHDL (MIL-STD |
| H0T | (1) | The LPC47M14x* is a 3.3V (5V tolerant) PC99 compliant Super I/O controller | |||
| H-1 | (4) | N/A | 05+ | The power dissipation of the SOTC23 is a function of the drain pa | |
| H1- | (8) | HARRIS | 228 | ＤＩＰ | Description Luminous Intensity per LED (Digit Average)[3,4] Pe |
| H10 | (131) | 00+ | SSOP-3.9-16P | This family is a 16M bit dynamic RAM organized 2,097,152 x 8-bit configura | |
| H11 | (1230) | HAR | 95+ | This is a diagram of a typical application of the MSK 4221. The d | |
| H12 | (85) | N/A | 02+ | PLCC-68 | The H-Bridge contains integrated free-wheel di- odes. In case of free-w |
| H13 | (76) | HARRIS | DIP-40 | 9810 | The ILD610 series is a dual channel optocoupler series for high density |
| H14 | (11) | MOTOROLA | SOP | 06+ | The transmission data is input from TX+/- pins differentially. In general |
| H15 | (39) | INFINEON | TO3P | POWER SUPPLY Supply Voltages AVDD5 DVDD Anal | |
| H16 | (66) | MTEK VISION | 5 | An external voltage must be supplied to the VRef pin which provides the r | |
| H17 | (25) | 95 | VCC1 is the positive supply voltage pin for the transmitter output amplifi | ||
| H18 | (17) | 06+ | DIP-28 | • HIGH PERFORMANCE E2CMOS® TECHNOLOGY fmax = 300 MHz Ma | |
| H19 | (9) | 01+ | QFP | The bq2000 detects the battery chemistry by monitoring the battery-voltag | |
| H1A | (6) | HYUNDAI | 00+ | The AD8353 provides linear output power of 9 dBm with 20 dB of gain at 9 | |
| H1B | (2) | Furthermore, this circuit block compares the input signal to a threshold, | |||
| H1C | (1) | Screen tested 100% on each device at -55C, +25C & +125C temperature, | |||
| H1F | (1) | SOP | 506 | LCD BIAS Output Voltage Range FB Threshold Voltage FB Input Current LC | |
| H1I | (12) | DIP | Although TX and RX cores are physically separate, each channel can | ||
| H1M | (3) | The software Flash Bank Erase mode is initiated by issuing the specific s | |||
| H1N | (4) | The XC9500XV architectural features address the require- ments of in-sys | |||
| H1P | (3) | HARRIS | SOP | 99+ | Depending on the type of information to be switched, the MT8985 device can |
| H-2 | (5) | Agilent | DIP | 04+ | For the most current package and ordering information, see the Package Op |
| H2- | (3) | 98 | Provides various voltages for DDR-STR applications Provide a swit | ||
| H20 | (80) | M-TEK | 03+ | • Linear Regulator − 3.3 V 2% Output Voltage & | |
| H21 | (48) | HARRIS | SOP | 00+ | † Pulsed-output patterns are tested during AC switching at 2 |
| H22 | (41) | N/A | N/A | N/A | This device is a 6 channel EMI filter array for data lines. Greate |
| H23 | (35) | HARRIS | SOP | The uncommitted output transistors provide either common-emitter or emitt | |
| H24 | (18) | INTERSIL | 00+ | This data sheet has been carefully CORPORATION • 5980 NORTH SHANN | |
| H25 | (29) | HARRIS | SOP-8 | 05+ | The RS-232 line driver circuits convert TTL logic level inputs into inv |
| H26 | (6) | SOT-153 | The upper and lower gates are held low until the driver is initialized. | ||
| H27 | (13) | IR | 04+ | USOP-8P | Low stand-by current 0.1µA (typ.) Directly TTL compatible : All i |
| H28 | (16) | N/A | N/A | N/A | All local logic block outputs are brought back into the GRP so they can |
| H29 | (5) | HAR | SOP | The Hynix H2902 Series are 8Mx64bits Synchronous DRAM Modules. The module | |
| H2A | (4) | TELIAN | QFP | 1999 | The IGBT is ideal for many high voltage switching applications operating |
| H2B | (1) | Head-of-line blocking prevents switch performance, and operation defectiv | |||
| H2C | (1) | Square waves contain only odd harmonics, so the lowest frequency componen | |||
| H2D | (3) | 04+ | C Glueless Interface to Synchronous Memories: SDRAM or SBSRAM C G | ||
| H2K | (3) | 96 | STATUS REGISTER READ: The status register can be used to determine the de | ||
| H2M | (9) | Efficient 16-bit 56800E family hybrid controller engine with dual Harvard | |||
| H2N | (12) | 华昕 | 排带 | Maximum Input Voltage Power Dissipation Thermal Resistance Junction t | |
| H2R | (9) | Notes to the characteristics 1. The unweighted RMS noise output v | |||
| H2T | (1) | NEC | 02+ | The Active Scan Chain refers to the scan chain configuration as seen by t | |
| H2U | (1) | No Auxiliary Winding Operation Internal Output Short−Circuit Prote | |||
| H2Y | (2) | The ICL7104, combined with the ICL8052 or ICL8068, forms a member of In | |||
| H-3 | (3) | As shown in Figure 4, the VSENSE input is connected to the collector of | |||
| H3- | (1) | INTERSIL | DIP | 00+ | (VDD = 2.7V to 3.6V (H3-5033-5/H3-5033-5), VDD = 4.5V to 5.5V (H3-5033-5/H |
| H30 | (56) | INF | TO-3P | Standard SDRAM Protocol Internal 4bank operation Voltage : VDD = 2.5V, V | |
| H31 | (55) | HARRIS | SOP | 07+ | The IS93C46A/56A/66A are controlled by a set of instructions which are |
| H32 | (20) | IR | DIP16 | 2005 | Thermistor : Temperature dependant resistor. Basically there are 2 types |
| H33 | (4) | 95+ | SOP | temperature variations. Simply tying the biasing diode to the supply thro | |
| H34 | (25) | N/A | SMD | 4 | Pin 13 (VSEN) can be used to modify the internal set point for the smoke |
| H35 | (39) | ST | 06+ | 3800 | The CBT6832D is a 16-bit controlled enable rate 1-of-2 multiplexer/demul |
| H36 | (1) | MICROCHIP | TSSOP-8 | 02+ | @ Digital power output 824-849 MHz Over supply voltage Over temperature |
| H37 | (4) | SSOP16 | This is a dual-purpose input. In the single device configuration (XI grou | ||
| H38 | (7) | AD | TQFP1010-64 | Description This family of SMT LEDs is packaged in the industry standa | |
| H39 | (7) | PHILIPS | CDIP | 06+ | The SecSi™ (Secured Silicon) Sector is an extra 256 byte sector ca |
| H3A | (4) | MAXTOR | QFP100 | We Listen to Your Comments Any information within this document that you | |
| H3B | (6) | HY | PLCC | 07+ | (2) The technical information described in this book is limited to showin |
| H3C | (12) | MAXTOR | QFP100 | This is the gate-source voltage which produces 250 microA of drain curren | |
| H3M | (3) | The Electrical Sub-Assembly (ESA) consists of a double-sided printed | |||
| H3P | (1) | The Media Access Control function, provided by the Ethernet Network Con | |||
| H3R | (6) | The entry of sections for each group is truly random and without limitat | |||
| H3S | (2) | ST | 06+ | 3650 | 0-0 - Not to be used 0-1 - Data Memory (read only from the microprocess |
| H3Y | (29) | OMRON | Relay(DZ) | 02460N+ | The EL8300 represents a triple rail-to-rail amplifier with a - 3dB bandwi |
| H-4 | (2) | TOSHIBA is continually working to improve the quality and reliability of | |||
| H4- | (1) | ST | DIP42 | ENA (Pin 10) (enable): ENA is a logic input that will en- able the PWM o | |
| H40 | (32) | INTERSIL | SOP-8P | 07+ | Asynchronous signals include output enable (OE), sleep mode input (ZZ), |
| H41 | (2) | SOP | Valid combinations list configurations planned to be sup- ported i | ||
| H42 | (10) | HARRIS | SOP-8 | N/A | THE HUF76009 is an application-specific MOSFET optimized for switching |
| H43 | (19) | N/A | N/A | 2004 | Programmable options include the length of pipeline (Read latency of 2 or |
| H44 | (2) | HARRIS | 8P | The thermal protection circuit shuts off the amplifier when the s | |
| H45 | (3) | HARRIS | 05+ | The HAL 805 is programmable by modulating the sup- ply voltage. No addi | |
| H46 | (12) | HARRIS | 06+ | The MARC4 microcontroller consists of an advanced stack-based 4-bit CPU c | |
| H47 | (2) | IR | USOP-8P | 6+ | Notes: 8. Per TTL driven input (VIN=3.4V); all other inputs at VCC |
| H48 | (29) | IR | 04+ | USOP-8P | The video decoder, a 9-bit video input processor, is a combination of a |
| H49 | (18) | SOP-8 | Semelab Plc reserves the right to change test conditions, parameter limits | ||
| H4M | (8) | The product information and the selection guides facilitate selection of | |||
| H4P | (1) | HARRIS | PLCC | Load Mux. RRE = "1" and MSE = "1": LDM is an output te | |
| H4R | (26) | Two non-inverting buffers are also included in this IC for buffering th | |||
| H4S | (1) | N/A | Measuring Diode Parameters The measurement of the five elements which ma | ||
| H-5 | (3) | The HIP6601 drives the lower gate in a synchronous-rectifier bridg | |||
| H5- | (2) | ISSI reserves the right to make changes to its products at any time witho | |||
| H50 | (58) | Pulse | A | A | MAX 3000A devices provide programmable speed/power optimization. SpeedCc |
| H51 | (12) | PULSE | 08+ | SMD24 | Table 2 shows the interrupt vector and DSP-to-DSP semaphores at reset of |
| H52 | (23) | HAR | 92+ | SMD | The sensors include a temperature-compensated Hall plate with active of |
| H53 | (10) | hengstler | hengstler | dc92 | Consult factory for available frequencies and specs. Not all options avai |
| H54 | (12) | 三极 | A 5% resistor value is recommended. In the OOK mode, this pin is usually | ||
| H55 | (10) | HAR | DIP | 05+ | The BALBSG (the indicates the output voltage value) is a low-saturation |
| H56 | (6) | TO-92L | 07+ | VERTICAL SYNC OUTPUT A vertical sync output is derived by internally int | |
| H57 | (3) | AMIS | 04+ | MQFP144 | −I2S, Left, Right Justified or DSP −16/20/24/32 bit Word Len |
| H58 | (2) | PHILIPS | PLCC44 | The CMOS bq3287E/bq3287EA is a low-power microprocessor periph- eral pro | |
| H59 | (2) | INTERSIL | 06+ | Collector C Emitter Saturation Voltage, IC=-300mA, IB=-30mA Base C Emit | |
| H5A | (1) | s Low-power dissipation s Complies with JEDEC standard no. 7A s ESD pro | |||
| H5C | (13) | *1. AC for 1 minute, R.H. = 40 ~ 60% Isolation voltage shall be m | |||
| H5D | (3) | N/A | QFP-48 | AP1604 can be soft-start with a proper capacitor connected between CE/SS | |
| H5I | (2) | HARRIS | SOP | 99+ | Fully compliant with the Universal Serial Bus Specification, version 1.1 |
| H5L | (2) | B4-pin serial interface BKey scanning (6 4 matrices) BProgramming dis | |||
| H5M | (6) | The PSD3XX I/O ports can be used for: • Standard I/O ports | |||
| H5N | (21) | HITACHI | SOT-523 | 05+ | The rated contact capacity and life are typical values. Since contact p |
| H5P | (1) | HYNIX | FBGA | Command Line Format Command lines issued to the modem follow a strict fo | |
| H5R | (16) | Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V | |||
| H5V | (1) | A transaction is a collection of packets needed to complete a memory acc | |||
| H5Y | (1) | • Low forward voltage VF and good wave detection efficiency ç | |||
| H60 | (56) | HARRIS | 99+ | SOP-8 | Data Line Pulsing: USB20H04 turns on its data line pull-up resistor (eithe |
| H61 | (8) | N/A | DIP-28 | 08+ | • Three video anti-aliasing or reconstruction filters • |
| H62 | (5) | N/A | SMD | 2001 | |
| H63 | (8) | HITACHI | DIP | JITO -2 represents the latest Fox response to urgent marketplace pressur | |
| H64 | (10) | ROHM | QFN | The asterisk ( ) indicates that the power supply voltage detection unit ch | |
| H65 | (9) | HARRIS | SOP8 | Notes: 1. Test conditions assume signal transition times of 5 ns or less | |
| H66 | (12) | INTERSIL | 08+ | • Viewing Angles Match Traffic Management Sign Requ | |
| H67 | (1) | PHILIPS | PLCC68 | Push-button Reset Input (MR). A logic low on MR asserts the reset output | |
| H68 | (6) | HARRIS | SOP-8 | The receive filter is a digital filter that meets CCITT G.714 requirement | |
| H69 | (12) | ST | 06+ | Maximum Reverse Voltage: Maximum Reverse Current @ VR = 5V: Peak Wavelen | |
| H6A | (3) | Address inputs Bank select address Data-input/output Chip select Row | |||
| H6C | (1) | BUFFALO | QFP | 00+ | Refer to the MSM9888L/MSM9889L Data Sheet. If the timing diagrams descride |
| H6D | (2) | N/A | QFP-48 | In order to reduce lock times and prevent erroneous data from being loade | |
| H6E | (1) | N/A | 3P | 08+ | Note : 1. * : These pins are not used in this module. 2. Pins 111, 158 a |
| H6N | (3) | Infineon | TO-252 | 05+ | PARAMETERSYMBOL MIN. Average Luminous IntensityIV870 Peak Emiss |
| H6R | (1) | Performance Motion Devices, Inc. (PMD) warrants performance of its produc | |||
| H6Z | (1) | Over & under voltage sense input dedicated to the 12V line Over & | |||
| H-7 | (2) | HARRIS | DIP | 07+ | The NUP1105L provides a transient voltage suppression solution fo |
| H70 | (14) | 9715 | Active low signal from ATM signifying that data will be sampled on RDAT[7 | ||
| H71 | (13) | 06+ | SOP-24 | Note 2: Limits are 100% production tested at TA = +25C. Limits over operat | |
| H72 | (17) | HARRIS | DIP-8 | 90+ | The UCC5630A is used in multi-mode active termination applications, whe |
| H73 | (1) | The H7320D416125185X1992361 detects the audible tone signals used by most | |||
| H74 | (26) | ZARLINK | TQFP | 03+ | The EL5420 is available in the space-saving 14-pin TSSOP package, the ind |
| H75 | (15) | SOP18 | 98 | The information provided herein is believed to be reliable at press time. | |
| H76 | (84) | HARRIS | SENSE (Pin 1): Maximum Overcurrent Sense Input. A sense resistor (RSENSE) | ||
| H77 | (4) | 71 | HARRIS | Hynix HYMD116725B(L)8J-J series is unbuffered 184-pin double data rate Syn | |
| H78 | (35) | HARRIS | . | The P/R input is latched by the falling edge of the CE pin. A HIGH level | |
| H79 | (6) | 220 | The 18TQ Schottky rectifier series has been optimized for low reverse lea | ||
| H7B | (2) | Note: (1) This parameter is tested initially and after a design or proce | |||
| H7C | (2) | Eleven years of experience have enabled ST to develop a chipset that offe | |||
| H7E | (7) | OMRON | All linear dimensions are in inches (millimeters). This drawing is subj | ||
| H7N | (8) | ||||
| H7P | (2) | RENESAS | SOT-252 | 05+ | |
| H-8 | (5) | H | 92 | Note 3: An internal Zener at the GATE pin clamps the charge pump voltage | |
| H8/ | (19) | HIT | QFP | 05+ | Programmable LVDS amplitude (VOD) and LVDS offset volt- age (VOS) of th |
| H80 | (19) | HARRIS | SOP | The ULN2001A, ULN2002A, ULN2003 and ULN2004Aare high voltage, high curr | |
| H81 | (5) | 2007 | *FDD: Supports up to two floppy disk drives *Parallel: One enhanced bi-di | ||
| H82 | (19) | HARRIS | SOP-8 | 00+ | For applications requiring output voltage On/Off control, the 12pin ISR |
| H83 | (18) | HP | SSOP | SSOP | V+ - Is the power connection for the top of the output bridge. These pin |
| H84 | (8) | ASLLIC | SOP | 06+ | In order for Xinger surface mount components to work optimally, there mus |
| H85 | (13) | SAMSUNG | 04+ | LCC | The look-ahead carry feature simplifies serial cascading of the co |
| H86 | (4) | HARRIS | SOP-8 | A bypass capacitor (0.1µF) should be placed as close as possible to | |
| H87 | (3) | VDE = Differential Error Voltage = Common-Mode Error Voltage. See | |||
| H88 | (4) | SAMSUNG | * This is a stress rating only and functional operation of the device at | ||
| H89 | (7) | 05+ | The SN65LVDS151 consists of a 10-bit parallel-in/serial-out shift registe | ||
| H8A | (2) | FRANCE | QFP | 07+ | FUNCTIONAL DESCRIPTION The H8AD10SHAN is a power comparator with full- |
| H8B | (1) | ||||
| H8C | (1) | The STK12C68-20 requires VCC = 5.0V 5% supply to operate at specified sp | |||
| H8D | (18) | Murata | 01+ | ZIP/19 | |
| H8F | (5) | API8208A is a high quality voice synthesizer capable of varying playback | |||
| H8N | (1) | TI is not confident of the operation of the DLL in this product at this t | |||
| H8P | (1) | MURATA | 2008 | The device is entirely command set compatible with the JEDEC single-power | |
| H8R | (1) | 6. Solder Gap Identification (See Figure 2): Each solder gaps respective | |||
| H8S | (8) | HIT | 1512 | 02+ | TMS320C67x and C67x are trademarks of Texas Instruments. Motorola is a |
| H8W | (1) | The LM34910 Step Down Switching Regulator features all of the functions | |||
| H-9 | (1) | compatibility table). Active current limitation combined with thermal s | |||
| H9- | (1) | 03+ | BGA | The PCA9544A provides four interrupt inputs (one for each channel) and on | |
| H90 | (30) | 日立 | TO-92 | Input and output interface capability to systems at 5V VCC Bus-Hold dat | |
| H91 | (7) | HAR | SOP-14 | Hardware Reset, active Low. Provides a hardware method of resetting the | |
| H92 | (21) | HARRIS | SOP | Differential reference clock input. The reference clock input is used as | |
| H93 | (6) | HST | SOP | These devices feature 3-state outputs designed specifically for driving h | |
| H94 | (16) | ST | SOP | This pin is internally connected to the inverting input of the PWM compara | |
| H95 | (7) | ST | 05+ | SOP-16 | FEATURES Allows Safe Board Insertion and Removal from a Live C48 |
| H96 | (7) | In a /WE-controlled write, the memory cycle begins on the falling edge | |||
| H97 | (62) | AGILENT | 2007 | Accuron, Application Maestro, dsPICDEM, dsPICDEM.net, ECAN, ECONOMONITOR | |
| H98 | (10) | HARRIS | SOP-20 | These devices are controlled through a 20MHz SPI™/QSPI™/MICRO | |
| H99 | (9) | KENWOOD | 28脚 | 05+ | 6.45...7.14 *) 7.13...7.88 *) 7.79...8.61 *) 8.65...9.55 &nbs |
| H9A | (1) | SOT23-5 | 04+ | NOTES 1Typicals represent average readings at 25C, VDD = 5 V, VSS | |
| H9D | (1) | OE controls the impedance of the output buffers. When OE is high, the buf | |||
| H9G | (1) | ST | 96+ | SMD | In addition, the TSC80C31/80C51 has two software-selectable modes of red |
| H9N | (1) | These N-Channel enhancement mode power field effect transistors are produ | |||
| H9P | (1) | DALLAS | N/A | 583 | Typical active current 400 mA Typical standby current 25 mA Reliable CMO |
| H9R | (7) | 100 year message retention (typical) • 100K analog record cy | |||
| H-A | (2) | NANA | Input Frequency Output Clock Rise Time Output Clock Fall Time Output Cl | ||
| HA- | (12) | 99+ | • This product function as level shift transceiver that change VCCA | ||
| HA0 | (18) | SOP14 | 06+ | Built-in power save circuit Built-in current limit circuit Built-in th | |
| HA1 | (2372) | HITACHI | SOP8 | 07+ | |
| HA2 | (605) | INTERSIL | CAN | CAN | Adjustage of stand-by SW (1) Since VCC can directly be controlled to ON o |
| HA3 | (167) | INTERSIL | DIP | 00+ | Figure 6. Block diagram of the 2 GHz production test board used for NF, G |
| HA4 | (118) | 04+ | SOP | The MK1491-06 is a low cost, low jitter, high performance clock synthes | |
| HA5 | (84) | © Cypress Semiconductor Corporation, 2004. The information contained | |||
| HA6 | (39) | HIT | N/A | 1752 | The SPI interface can communicate at a maximum of 5Mbps data rate with a |
| HA7 | (281) | N/A | N/A | N/A | Notes: 1. For Max. or Min. conditions, use appropriate value specified u |
| HA8 | (13) | CHINA | TO-92 | 99 | The RF front end of the receiver is a heterodyne configuration that conve |
| HA9 | (124) | Erase/write enable (EWEN) Before any device programming (WRITE, WRAL, ER | |||
| HAA | (81) | HAR | PLCC20 | 03/+04+ | The TMS320C67x DSPs are the floating-point DSP family in the TMS320C6000& |
| HAB | (10) | 249 | Whether the flag offset registers are programmed as described in Table | ||
| HAC | (12) | SSOP20M | 2007+ | Vishay Siliconix maintains worldwide manufacturing capability. Products ma | |
| HAD | (25) | POWER-ONE | SOP | Normally, capacitor values on the order of several hundred microfarads ar | |
| HAE | (1) | MOT | PLCC52 | 06+ | INTRODUCTION National Semiconductor (NSC) is committed to provide ap- p |
| HAF | (46) | Hynix HYMD116645A(L)8-K/H/L series is designed for high speed of up to 133 | |||
| HAG | (11) | ST | BGA | 99 | Notes: 1. Operation of this device in excess of any of these limi |
| HAI | (58) | SANYO | 652 | Signal input pin. A internal matching circuit, configured with resisto | |
| HAK | (2) | HITACHI | LL34-6V | The tag requires no internal power supply. Its contactless interface gener | |
| HAL | (75) | itt | itt | dc94 | These solid state display devices are designed and tested for use in a |
| HAM | (5) | AT | SOT-23 | s Three-Terminal Adjustable Or Fixed Output Voltage s Guaranteed | |
| HAN | (26) | N/A | N/A | 200 | |
| HAO | (1) | The 24XX128 supports a bidirectional 2-wire bus and data transmission p | |||
| HAP | (4) | ORIGIN | 05+ | 1.) When operated within the SAFE OPERATING AREA as defined by th | |
| HAR | (12) | HAR | dip/sop | 0728vgc+ | The HAR-506-2 is a high current, fast response regulator which can maint |
| HAS | (55) | AD | DIP32 | 3Msps Sampling ADC with Two Simultaneous Differential Inputs 1.5Msps Thr | |
| HAT | (606) | HIT | SMD-8 | 05+ | The transponder is the mobile part of the closed coupled identification s |
| HAU | (5) | origin | SOT-23 | LDQM and UDQM control the lower and upper bytes of the I/O buffers. In re | |
| HAW | (2) | HITACHI | DIP | A customized leadframe has been incorporated into the standard SOT-23 pa | |
| HAX | (9) | SAN-O | SOP | 411 | It is possible to choose from the four different modulation schemes: Bin |
| HAY | (4) | MICROCHIP | PLCC | Sirenza Microdevices SBB-5089 is a high performance InGaP HBT MMIC amplif | |
| HAZ | (14) | The PCM58P is a complete, precision 18-bit digital- to-analog converter | |||
| HB- | (115) | CERATECH | 0805BEAD | The SNAP! Pulse programming algorithm uses initial pulses of 100 microsec | |
| HB/ | (3) | 05+ | QFP-80 | The serial interface sends out the conversion results during the 16 clock | |
| HB0 | (21) | SOP14 | 06+ | Except the build-in USB 1.1 interface, the capability of cooperating with | |
| HB1 | (62) | MODEL | SINKA | 05+ | Other features include low quiescent current, typical- ly 70µA, and |
| HB2 | (42) | NAIS | Relay(new original) | These signal conditioners are designed to provide an easy and convenient | |
| HB3 | (39) | DIP | 04/05+ | Stability The IRU1261 requires the use of an output capacitor as part of | |
| HB4 | (21) | SOP-14 | The LPC47M14x* is a 3.3V (5V tolerant) PC99 compliant Super I/O controller | ||
| HB5 | (53) | HBO | SOP-24 | 0123+ | Note 1: Limits are 100% production tested at TA = +25C. Limits over the op |
| HB6 | (13) | NA | NA | Xtal/Clock: The input to the on-chip Xtal oscillator. A Xtal, or externall | |
| HB7 | (23) | TI | QFP/瓷 | 07+/08+ | |
| HB8 | (5) | TRANSPOW | SOP-40 | 02+ | VelociTI is a trademark of Texas Instruments Incorporated. Motorola is |
| HB9 | (3) | HOWA | DIP | 00+ | Unused product terms are automatically disabled by the compiler to decrea |
| HBA | (47) | MICCROSEMI | SOT-23 | • Function entry/exit instructions, multi load/store instruction fo | |
| HBB | (17) | COEV | SOP-12 | 05+ | Members of the Texas Instruments SCOPE ™ Family of Testability Produ |
| HBC | (44) | HERMAT | TSSOP | 0316+ | |
| HBD | (25) | POWER-ONE | SOP | Low ON resistance: rDS(ON) = 5ΩΩ Wide bandwidth: 1.3GHz (-3 | |
| HBE | (6) | JAPAN | SSOP-M36P | 6+ | The INFINEON Direct RDRAM is a general purpose high-performance m |
| HBF | (45) | ST | DIP-14 | 08+ | Resale of TI products or services with statements different from or beyon |
| HBG | (6) | N/A | ST | 04+ | Each device includes on a single silicon chip a voltage regulator, |
| HBH | (2) | RFT6120 Device Features • CDMA2000 1X Mobile Station Modem chipset | |||
| HBI | (5) | HINT | QFP-160 | 06+ | Notes: 2. The voltage on any input or I/O pin cannot exceed the po |
| HBL | (47) | tamu | tamu | dc03 | • high frequency rectifiers, output rectifiers of switched |
| HBM | (6) | QUICKLOGIC | N/A | N/A | Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Co |
| HBN | (2) | This circuit demonstrates the operation of a stepper motor, and | |||
| HBP | (1) | DIP | Complete UHF receiver on a monolithic chip 300MHz Data Rates up to 2.1 | ||
| HBR | (7) | FDK | ZIP-18P | Attention please! The information herein is given to describe certain co | |
| HBS | (75) | POWER-ONE | SOP | A flexible, thick-wall, heat- shrinkable tubing to be used in conjunctio | |
| HBT | (13) | high-frequency tube | IR | 04+ | The CY7C436X3AV is a synchronous (clocked) FIFO, meaning each port empl |
| HBU | (1) | The HBU100KBBCF0K architecture is illustrated in the block diagram of Fig | |||
| HBV | (1) | Electrical characteristics are guaranteed over full junction temperature | |||
| HBW | (1) | HBW | SOP-28P | 05+ | 8 Independent, Full-Featured T1/E1/J1 Framers/Formatters Independent Tra |
| HBX | (1) | vishay | vishay | dc0621 | After the Master sends a START condition and the slave address byte, th |
| HBZ | (2) | high-frequency tube | IR | 04+ | NOTES: 1. In order to initialize the circuit, an initialize pause of 100 |
| H-C | (1) | SOP20 | 06+ | ||
| HC- | (114) | NA | 00+ | Calibrated directly in Kelvin Linear 10 mV/¡C scale f | |
| HC/ | (1) | 1. H = HIGH voltage level L = LOW voltage level X = dont | |||
| HC0 | (64) | SOP14 | ©Atmel Corporation 2004. All rights reserved. Atmel® and combinat | ||
| HC1 | (360) | MOT | PLCC52 | 05+ | In the above figure, the transmitter should be set so that the output V o |
| HC2 | (205) | SOP20 | 06+ | Complete closed loop current control based on Synchronously Rotating Fram | |
| HC3 | (136) | HMS | Another key feature of the C67x CPU is the load/store architecture, where | ||
| HC4 | (551) | HIT | 97 | BiFET operational amplifiers offer the inherently-higher input impedance | |
| HC5 | (321) | INTERSIL | Note 1 Absolute Maximum Rating are those values beyond which the safety o | ||
| HC6 | (40) | PANASONIC | The C515 is an upward compatible version of the SAB 80C515A 8-bit microco | ||
| HC7 | (59) | MT | 01+ | SSOP-20 | n Generates all clock frequencies for Pentium (II), AMD and Cyrix |
| HC8 | (15) | HARRIS | SMD | 03+ | HT1626 is a peripheral device specially designed for I/O type MCU used to |
| HC9 | (64) | STM | 04+ | 22 | Note: Stresses greater than those listed under MAXIMUM RATINGS may caus |
| HCA | (26) | INTERSIL | SOP-20 | 98+ | The interconnect structure (GRP) is very similar to Lattices existing is |
| HCB | (52) | N/A | Notes: 1. Repetitive Rating : Pulse width limited by maximum junction tem | ||
| HCC | (111) | ST | CDIP16 | 9322 | The byte pointer bit must be toggled to the correct value before operatin |
| HCD | (40) | 98+ | SSOP16脚 | ||
| HCE | (1) | After the software chip erase has been initiated, the device will interna | |||
| HCF | (852) | 92 | s 16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package. s 8 | ||
| HCG | (3) | DIP/18 | The UC1842A/3A/4A/5A family of control ICs is a pin for pin compati- ble | ||
| HCH | (6) | 2000 | Pericom Semiconductors PI74AVC+16820, a 10-bit flip-flop designed for 1 | ||
| HCI | (23) | HARRIS | DIP | 1. H = HIGH voltage level h = HIGH voltage level one set-up time | |
| HCJ | (3) | This new generation of trench MOSFETs from Zetex utilizes a unique structu | |||
| HCL | (10) | DIP | 07+ | During normal operation, power consumption may be minimized by disabling | |
| HCM | (145) | SPT | PLCC | PLCC | V+ - Is the power connection for the top of the output bridge. These pin |
| HCN | (215) | AGILENT | 08+ | For applications requiring powerful I/O capabilities, the Z86319 provide | |
| HCO | (11) | Note 1. 100KEP circuits are designed to meet the DC specifications shown | |||
| HCP | (3819) | 安捷伦 | SOP | SOP | The 33981 can be controlled by pulse-width modulation (PWM) with a |
| HCQ | (4) | Integrated tracking capacitor Senses motion of ring magnet or ferrous t | |||
| HCR | (4) | 2001 | • 18V to 36V Input Voltage Range • Programmable Output Volta | ||
| HCS | (232) | 6.55 | PRECAUTIONS • The exterior of this product can melt since due to t | ||
| HCT | (308) | DIP | DIP | Two different interfaces are supported on the network side. The first is | |
| HCU | (6) | FDS | TSSOP-14 | 04+ | The VCXH16244 contains sixteen non-inverting buffers with 3-STATE outpu |
| HCV | (3) | TI | SOP14 | MOSFET gates can be efficiently switched up to 2MHz using the ISL6208. Ea | |
| HCW | (2) | A | DIP | The application circuit examples are only to explain the representative a | |
| HCX | (3) | Used as external reference input when internal reference is disabled (i.e | |||
| HCY | (8) | ST | DIP | 07+ | TAOperating free-air temperatureC 55125C 4085C NOTE 3: All unused |
| H-D | (3) | TOKIN | DESCRIPTION The 74LCX05 is a low voltage CMOS OPEN DRAIN HEX INVERTER | ||
| HD- | (15) | HIROSE ELECTRIC | SMD | 07+ | The AD7683 is a 16-bit, charge redistribution, successive approximation, |
| HD/ | (1) | The HD/MC14014BP provides an economic stand-alone solution for 4 : 2 : | |||
| HD0 | (21) | HB | MDS | 05+ | The 3803/3804 group is the 8-bit microcomputer based on the 740 family c |
| HD1 | (847) | HIT | QFP | 01+ | DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. |
| HD2 | (229) | HIT | DIP | 06+ | • Single +5V supply • 24-pin SOIC • Compatible with fi |
| HD3 | (176) | For optimum thermal performance in a natural convection application, the | |||
| HD4 | (1235) | HIT | DIP | Master mode and snapshot mode output signal. Active HIGH during readout. | |
| HD5 | (25) | HITCHIA | 00+ | 600-kHz Sample Rate 2 LSB Typ, 4 LSB Max INL 18-Bit NMC Ensured Over Tem | |
| HD6 | (5366) | HIT | SMD | 94 | The TS80C54/58X2 has 2 software-selectable modes of reduced activity for |
| HD7 | (2891) | HIT | DIP | The ceramic resonator of the stereo decoder PLL circuit is used as a sto | |
| HD8 | (69) | Hitachi | Evaluating the accuracy of Maxim real-time clocks (RTCs) can be simplified | ||
| HD9 | (27) | HIT | DIP | MATERIAL: Units are encap- sulated in a low thermal resis- tance moldi | |
| HDA | (35) | SPT | CDIP | CDIP | Chip Enable to output in Low-Z Chip disable to output in High-Z Chip E |
| HDB | (9) | HIT | QFP-44 | 6. As it might be a cause of degradation of destruction to apply static el | |
| HDC | (61) | HANDO | PLCC | 07+ | Note 4: For single supply operation, the following conditions apply: V+ = |
| HDD | (16) | AD | AUCDIP | These N-Channel power MOSFETs are manufactured using the | |
| HDE | (9) | vishay | vishay | dc04 | Information at the D input is transferred to the Q, Q outputs on the pos |
| HDF | (35) | 01 | When EBEN is high and EA is low all program mem- ory operations take pla | ||
| HDG | (18) | AD | new | The PI6C918 and PI6C919 are high-precision, low-voltage general-purpose | |
| HDH | (5) | ADI | DIP | 8429 | Operating voltage range Current consumption during standby Built-in 2.2V |
| HDI | (20) | NEC | 05+ | The CP3BT10 connectivity processor combines high perfor- mance with the | |
| HDJ | (7) | Agilent | SOP24 | International Rectifier Radiation Hardened MOSFETs are tested to verify th | |
| HDK | (1) | Lead Temperature 1.6mm (1/16 inch) from case for 10s260C (1) Stres | |||
| HDL | (499) | N/A | N/A | 205 | The EL5120, EL5220, and EL5420 also feature fast slewing and settling tim |
| HDM | (164) | HDMP | QFP84 | 08+ | Unusual current waveforms can be estimated with an ap- proximation to a |
| HDN | (16) | Addresses and chip enables are registered at rising edge of clock when ei | |||
| HDO | (2) | The RESET pin is connected to the RST pin on the register and to the OE pi | |||
| HDP | (16) | HDK | Accuracy (each DAC) Integral linearity error Diffential l | ||
| HDR | (19) | div | div | dc80+ | (1)Consult factory for test procedure. The reed switch shall be pl |
| HDS | (1140) | N/A | N/A | N/A | 2. The inhibit control input is Not compatible with TTL devices |
| HDT | (8) | C&K | 0623+ | Notes: 1. For Max. or Min. conditions, use appropriate value specified u | |
| HDU | (3) | FAIRCHILD | EWC: Event and Waveform Controller • Compatible with Intels Programm | ||
| HDV | (3) | HAR | SMD | Eleven years of experience have enabled ST to develop a chipset that offe | |
| HDW | (9) | SAMTEC | 08+ | Digital End-of-Charge Output: N-Ch open drain output. Low indicates char | |
| HDX | (2) | -12V TCK GND TDO VCC VCC INTB- INTD- PRSNT1- RSVD PRSNT2- GND | |||
| HE- | (32) | 02+ | The base part, PI6C2308A-1, provides output clocks in sync with a referen | ||
| HE0 | (3) | Logic and internal gate drive supply voltage Oscillator timing resistor | |||
| HE1 | (40) | AVASEM | PLCC28 | Note 3: : The maximum power dissipation must be derated at elevated tempe | |
| HE2 | (17) | TI | TVSOP-48 | 00+ | ©2002 by ZiLOG, Inc. All rights reserved. Information in this publica |
| HE3 | (25) | TI | 00+ | Note: 1. Multiple Supplies: The Voltage on any input or I/O pin can | |
| HE4 | (9) | SOP20 | 03+ | NOTES: 1. Minimums are guaranteed but not production tested. 2. This pa | |
| HE5 | (11) | TI | TSOP48 | 07+ | and XACT are registered trademarks of Xilinx. All XC- prefi |
| HE6 | (23) | EPSON | QFP-208 | 2001 | • Avalanche rated parts available • Package with DCB cerami |
| HE7 | (33) | DIP | floating gate technology and byte wide in telligent programming algorithm | ||
| HE8 | (30) | connetral | connetral | dc78+ | For the device-specific interrupt priority configurations, see the " |
| HE9 | (22) | 97 | This document is a general product description and is subject to change wi | ||
| HEA | (19) | HAR | QFP | AL,BL,CL - Are the lowside logic level digital inputs. These three input | |
| HEB | (2) | Transmitter Differential Variable Swing Output. Output is CML compatible. | |||
| HEC | (49) | PHILIPS | 98+ | SOP16 | Built-in VCO coil for intermediate frequency signal processing AFT adjus |
| HED | (996) | AGILENT | 08+ | A buffered output-enable (OE) input can be used to place the eight output | |
| HEE | (4) | PHILIPS | SMD16 | 1) CPD is defined as the value of the ICs internal equivalent capacitance | |
| HEF | (1448) | Upon power-up, the FIFO must be reset with a Reset (RS) cycle. This cau | |||
| HEH | (2) | Reset input. Active Low Schmitt-Trigger input. The Schmitt-Trigger input | |||
| HEI | (4) | HITACHI | PLCC | 03+ | Notes: 6. For I/O ports, Input Leakage Current (II) includes the 3-state |
| HEJ | (1) | The NCP631 is a low dropout positive voltage regulator that is ca | |||
| HEK | (2) | Latch storage of input data Blanking input Lamp test input Low power co | |||
| HEL | (71) | N/A | N/A | N/A | The input/output pins (I/O1 through I/O16) are placed in a high-impedan |
| HEM | (13) | HITACHI | SOT-23 | Output Voltage Amplitude and Serial Interface Clock. Tie this pin high | |
| HEN | (1) | ONSEMI | SOP | 506 | This input coupling capacitor blocks DC voltage at the amplifiers termina |
| HEP | (33) | ON | The EC000 core is completely upward user code-compatible with all other m | ||
| HER | (129) | HER | 07/08+ | Deadtime High-Current Totem-Pole Dual Output Stage Drives Push-Pull Conf | |
| HES | (31) | POWER-ONE | SOP | This is the drain-source resistance at 25C with VGS = 10V. Since RDS(on) | |
| HET | (13) | PHILIPS | Specifications Outline Dimensions Pin Connections and Short Description | ||
| HEW | (2) | 00 | ISSI reserves the right to make changes to its products at any time witho | ||
| HEX | (1) | IOR | DIP-8P | 06+ | Note: Stresses greater than those listed under MAXIMUM RATINGS may cause |
| HF- | (7) | 2008 | Enhanced PCI South Bridge for Desktop, Mobile and Embedded Applications | ||
| HF0 | (17) | N/A | N/A | 211 | The A1421, A1422, and A1423 are ac-coupled Hall-effect sensors which incl |
| HF1 | (10) | ASI | (LX)high-frequency | Designers must have two documents to fully use all the features of this de | |
| HF2 | (11) | TI | 00+ | The sensor turns to high current consumption with the magnetic south po | |
| HF3 | (41) | ASI | (LX)high-frequency | Beneficial comments (recommendations, additions, deletions) and any perti | |
| HF4 | (8) | HIT | SOP-8 | 0236+ | Product reliability information can be found at http://www.mtp.int |
| HF5 | (58) | N/A | TrenchMOS output stage Current limiting Overload protection Overtemper | ||
| HF6 | (6) | HIT | 01+ | QFP | Maximum ratings are those values beyond which device damage can occur. Ma |
| HF7 | (43) | The DDX-2000 converts serial I2S digital audio signals into pulse-width-m | |||
| HF8 | (1) | Maximum power dissipation with no heat sink used. Lead soldering temperat | |||
| HF9 | (5) | HIT | SIZEB determines the bus width of Port B. A HIGH on this pin selects byte | ||
| HFA | (616) | POWER-ONE | SOP | Load Regulation Since the IRU1010 is only a three-terminal device, it is | |
| HFB | (677) | AGILENT | 08+ | 10 years minimum data retention in the absence of external power Data is | |
| HFC | (270) | 2520 | The HY62K(U,V)T08081E is a high-speed, low power and 32,786 X 8-bits CMOS | ||
| HFD | (10) | 05+ | Brooktree products are not designed or intended for use in life support a | ||
| HFE | (22) | honey | honey | dc91 | Master/Slave Synchronization. When it is open, a signal synchronous with |
| HFF | (2) | PHI | SOP | 07+ | • Function, pinout, and drive compatible with FCT and F logi |
| HFI | (26) | 0402L | Single supply: 1.8 V to 5.5 V Two-wire serial interface (I2CTM serial | ||
| HFJ | (5) | HALO | 06+ | The circuits and measurements contained in this document are given | |
| HFL | (1) | Inside the SPT1175, reference resistors are placed between AVDD and VRTS | |||
| HFM | (64) | SAFECOM | 98+ | SOP | Figure 1 shows the main screen of typical Maxim RTC evaluation software. |
| HFP | (7) | The LED oscillator with the NL27WZ04 duel gate inverter and the g | |||
| HFQ | (20) | murata | SMD | 2004 | Channel 0 Red (V) Video Input. Input for Red component video channel or |
| HFR | (15) | DIODES | SDO | 99 | a. DC characteristics are design targets and pending characterization. b |
| HFS | (8) | SEMIHOW | TO-220F | The Hynix HYM71V32655AT8 Series are 32Mx64bits Synchronous DRAM Modules. | |
| HFT | (18) | ASI | (LX)high-frequency | The amplifier works on any total power supply voltage between 2.7V and 36 | |
| HFV | (1) | ||||
| HFW | (27) | FCI | 08+ | Section 3.4, VPP Program and Erase Voltages, added Updated Figure 9: Au | |
| HFX | (6) | MURATA | Input Capacitance VT+1 VTC1 VT+ C VTC1 &nb | ||
| HG- | (20) | AKE | 08+ | The product information and the selection guides facilitate selection of | |
| HG0 | (2) | FAIRCHILD | N/A | 04+ | The error amplifier compares a sample of the dc-to-dc converter output vo |
| HG1 | (33) | N/A | One of the benefits of ISDs ChipCorder technology is the use of on-chip n | ||
| HG2 | (65) | HARRIS | TO-3P | 05+ | The UCC3808 dual output drive stages are arranged in a push-pull configur |
| HG3 | (10) | HUAWEI | 模块 | 08+ | Corona C Corona is the ionization of air or other vapors which causes the |
| HG4 | (15) | SOP | ³7KLV GRFXPHQW VWDWHV WKH FXUUHQW WHFKQLFDO VSHFLILFDWLRQV UHJDUGLQJ | ||
| HG5 | (67) | 03+ | Data on the A or B data bus, or both, can be stored in the inter- nal D | ||
| HG6 | (250) | 45 | HITACHI | 99+ | Reduced Conducted and Radiated EMI Single Resistor Control of Output Swit |
| HG7 | (103) | RENESAS | 05+ | In nibble interface mode, data is input most-significant nibble first, al | |
| HG8 | (3) | ZIP | ZIP | The ZL5011x is capable of assembling user-defined packets of TDM traffic | |
| HGA | (3) | MOT | |||
| HGB | (1) | MOT | This method fails if a user applies RESET during the FPGA configuration | ||
| HGC | (1) | HONGO | QFP60 | This INFINEON modules are industry standard 144 pin 8-byte Synchronous DR | |
| HGE | (3) | N/A | |||
| HGF | (7) | N/A | Trigger Voltage: The measured peak voltage across the ESD suppressor bef | ||
| HGG | (6) | ST | DIP-14P | 07+ | Strap:see Note 4 Notes: 1. DQ-to-I/O wiring may be changed |
| HGH | (1) | VCC2 is the positive supply voltage pin for the transmitter oscillator. Pi | |||
| HGJ | (4) | CLARE | stock | Elantec, Inc. products are not authorized for and should not be used wit | |
| HGL | (3) | NOTE: EP circuits are designed to meet the DC specifications shown in the | |||
| HGM | (2) | Each 6B Series module and board is a complete microcontroller-based proc | |||
| HGN | (1) | HITACHI | DIP | 07+ | This IC is intended for two-way asynchronous communication between data |
| HGP | (1) | The voltage regulator circuitry (bandgap reference and class AB power a | |||
| HGR | (7) | Sampling of the analog input starts on the falling edge of the fourth I/O | |||
| HGS | (8) | AD | AUCDIP | The MK3725 is a low cost, high-performance, two output 3.3 Volt VCXO an | |
| HGT | (385) | Intersil | TO-252 | 08+ | NOTES 1Measured at IOUTA, driving a virtual ground. 2Nominal full-scale |
| HGW | (1) | -1600.00 -1558.30 -1600.00 -1600.00 -1600.00 -1600.00 -1600.00 -160 | |||
| HGZ | (3) | N/A | • External components • External host for initialization | ||
| HH- | (32) | Amplifier noise performance is outstanding with a noise density of 8.5 nV | |||
| HH0 | (6) | ALLE | 07/08+ | Maximum switching frequency for control input (VO > VCC, VI = 5 V, RL | |
| HH1 | (3) | The LVTH162245 data inputs include bushold, eliminating the need for ex | |||
| HH2 | (7) | ST | TQFP48 | 10-Bit Resolution Non-Linearity: 1/2 LSB to 2 LSB Nonlinearity Tempco: 0 | |
| HH3 | (4) | ALLE | 07+ | NOTES: 1. All typical values are at VCC = 5 V, Tamb = +25C ambient and | |
| HH4 | (23) | CANON | DIP-40 | 07+/08+ | ILatchCUp LatchCUp PerformanceAbove VCC and Below GND at 125C (Note |
| HH5 | (2) | LIERD | Relay(new original) | Ratiometricity simply means that the output offset voltage and se | |
| HH6 | (3) | PANASONIC | BGA | 04+ | SPI Serial Memory The memory portion of the device is a CMOS Serial EEP |
| HH7 | (2) | MM1207 is described here as the representative model. MM1207 is a wideban | |||
| HH8 | (27) | INTEL | O7+ | The interrupt controller unit (ICU) provides a flexible means for reque | |
| HHA | (2) | N/A | 00+ | PLCC44 | overvoltages below this level will not cause any damage. The extinction |
| HHB | (14) | Information at the data (D) inputs meeting the setup time requirements is | |||
| HHC | (3) | TDK | ZIP | 99+ | ELECTRICAL CHARACTERISTICS Operating conditions T amb = C40C to + 85C, V |
| HHD | (4) | POWER ONE | SOP | 321 | s Complies with the ACPI™, OnNow™ and USB power management re |
| HHE | (2) | and Extends Battery Life RDS(on) = 0.180 W, VGS = −10 | |||
| HHF | (7) | SHINDENGEN | DIP | 07+ | Ring Indicator (Active-LOW). These inputs are associated with individual |
| HHI | (1) | This integrated circuits is manufactured on a CMOS process. It can be dama | |||
| HHM | (63) | N/A | Notes: 1. The Standby input must be controlled using an open- co | ||
| HHN | (1) | MOT | SOP/28 | 02+ | The ADV7183A integrated video decoder automatically detects and converts |
| HHP | (2) | JAT | 3225 | 05+ | • Supply of instruction fetch memory addresses; the sequenc |
| HHS | (10) | SOP | The internal reverse bias protection eliminates the require- ment for a | ||
| HHT | (6) | PLCC | The ISP1521 has seven downstream facing ports. If not used, ports 3 to 7 | ||
| HHU | (2) | SMD-8 | 04+ | The ADM70x family of products is guaranteed to provide a valid reset lev | |
| HHV | (6) | ST | TQFP48 | • Two potentiometers in one package • 2-wire serial interface | |
| HHW | (1) | PHI | SSOP24 | 07+ | 8. Guaranteed by Design. 9. This parameter is guaranteed by design but |
| HHY | (2) | 5V TOLERANT INPUTS HIGH SPEED: tPD = 6.3ns (MAX.) at VCC = 3V POWER DO | |||
| H-I | (1) | Minimum Quiet Time Required between CS Rising Edge and Start of Next Con | |||
| HI- | (109) | 2008 | The accumulator closely relates to ALU operations. It is also mapped to l | ||
| HI/ | (1) | ||||
| HI0 | (15) | HYUPJIN | The main purpose of this bipolar transistor is broad- band amplification | ||
| HI1 | (862) | HAR | DIP | 04+ | The LM1881 Video sync separator extracts timing informa- tion including |
| HI2 | (106) | INTERSIL | CAN10 | † Stresses beyond those listed under absolute maximum ratings may c | |
| HI3 | (228) | HAR | DIP | 07+ | The intended application of these devices and signaling technique is for |
| HI4 | (104) | HAR | LCC28 | 87/88 | Intel® 82551ER [Intel® 82551QM optional] (PCM-9577F) Intel® 8 |
| HI5 | (257) | HARRIS | SOP | 07+ | The DS89C430, DS89C440, and DS89C450 offer the highest performance availa |
| HI6 | (16) | 2007 | Shunt protection devices clamp voltage peaks at the Output-Pin and VDD- | ||
| HI7 | (28) | HAR | Integration of the TT allows connection to full-speed and low-speed devic | ||
| HI8 | (72) | har | har | dc90 | The Multimode terminator contains all functions required to terminate and |
| HI9 | (153) | HARRIS | SOP-16 | 98+ | The HI99201HS-5 is a video amplifier with differential input and output |
| HIA | (2) | HARRIS | DIP | s Flyback Operation with Quasi-Resonant Soft Switching for Low Po | |
| HIB | (1) | INTERSIL | SOP-8P | 07+ | One way to measure micro-fluidic flow is by measuring the pressure differe |
| HIC | (24) | MURATA | 13脚 | 98+ | Therefore it should be no problem to achieve the recommended values of r |
| HID | (5) | 95-96+ | In burst mode the A/D converter does repeated conversions at the rate sele | ||
| HIE | (1) | JEDEC compatible LVTTL level inputs and outputs 10 output, low skew clock | |||
| HIF | (69) | HIR | 07/08+ | „ Mounting surface must be smooth, flat, free or burrs or other &n | |
| HIG | (4) | HT | 裸片 | 2001 | The signal on the current sense input pin is also connected to the input |
| HIH | (9) | DESCRIPTION Dual center tap rectifier suited for Switch Mode Power Supp | |||
| HII | (21) | INTERSIL/HAR | 1678 | The total power dissipated by the HVDD supply may be approximated using t | |
| HIJ | (1) | KUNMING | 07+ | The HIJ-035-35HB supports multiple CPUs, all LCD panel types, CRT, and ad | |
| HIL | (4) | INTER | CDIP | 0301+ | State-of-the-Art BiCMOS Design Significantly Reduces ICCZ ESD Protection |
| HIM | (12) | HARRIS | SOP28W | 07+ | Note: ww represents the date code and pls refer to Date Code Rule before |
| HIN | (518) | DIP16 | 00 | The standby function is provided by the STBY* control, pin 2. If pin 2 | |
| HIO | (2) | Intersil | SOP16 | 02+ | |
| HIP | (953) | 1 | ZIP | There are no user serviceable parts nor any maintenance required for | |
| HIQ | (1) | The IC provides 12 key inputs (KEY1~KEY12). Of the 12 keys, KEY1 can be | |||
| HIR | (8) | 9613 | Similarly, an ideal 3.3V capacitive tripler generates 9.9V. The desired o | ||
| HIS | (27) | orga | orga | dc01 | The attached data sheets are prepared and approved by SAMSUNG Elec |
| HIT | (47) | HIT | TO-92 | 07+ | 1.) When operated within the SAFE OPERATING AREA as defined by th |
| HIV | (1) | N/A | TO-11P | 07+ | This familiy is a 64Mbit dynamic RAM organized 4,194,304 x 16bit configura |
| HJ- | (1) | N/A | N/A | N/A | Note 7: Because the Bus LVDS serial data stream is not decoded, the maxim |
| HJ0 | (2) | The functions for this block are: 1. Decode the internal address bus to | |||
| HJ1 | (10) | TI | TSSOP | 07+ | Over the years, the performances of the SLICs considerably increased an |
| HJ2 | (4) | AEC-Q100† Qualified for Automotive Applications Customer-Specific | |||
| HJ3 | (4) | HI-SINCERITY | 2. Guaranteed by design. Resistance measurements do not include test circ | ||
| HJ4 | (17) | SOP16 | 06+ | Temperature range is −15C to +105C, typical at 25C. | |
| HJ5 | (1) | SOP14 | 06+ | • Ampelanwendung • Hinterleuchtung (LCD, Schalter, Tasten, | |
| HJ6 | (2) | TI | TSSOP20 | Designed for DDR200/266/333/400 PC mother board clock buffering Supports | |
| HJ7 | (9) | HSMS | TO-252 | 04+ | The quad consists of eight differential low noise (0.65nVHz) voltage pre |
| HJ8 | (3) | TAIWEN | TO-252 | Indicates that a DRAM/SDRAM memory refresh cycle is in progress. To be u | |
| HJ9 | (16) | BGA | BGA | Organized as 2M x 8 bits Single 3.3V Power Supply Stacks of 16 SRAM 128K | |
| HJA | (2) | MOT | The power dissipation of the SOTC23 is a function of the drain pa | ||
| HJB | (1) | NA | NA | Miniature,cost-effective switching solution. Molded construction for comp | |
| HJC | (18) | Serial Data. SDA is a bidirectional pin used to transfer data into and ou | |||
| HJF | (1) | HAR | 220 | 9944 | High speed output rise and fall (20 ns typ) at load capacitance (CL) of |
| HJK | (21) | N/A | The popular 1N5985 thru 1N6031 series of 0.5 watt Zener Voltage Regulators | ||
| HJM | (3) | JRC | SUPPLY VOLTAGE C VCC = 3V to 3.6V for Program, Erase and Read Op | ||
| HJR | (1) | The CN8223 ATM Transmitter/Receiver with UTOPIA Level 1 interface provides | |||
| HJS | (4) | TX voice (Mic.) inputs, selectable by SW1 available for handsfree mic./ha | |||
| HJW | (4) | low, total supply current will be higher, depending on OUT current. Tot | |||
| HK- | (32) | TAIMIC | SOP | This hermetically packaged QPL product features the latest advanced silic | |
| HK0 | (28) | N/A | 0201L | Signal input pin. A internal matching circuit, configured with resisto | |
| HK1 | (213) | TAIYO YUDEN | 2007+PB | Reset Input: Schmitt trigger reset input. If 0, sets all control registers | |
| HK2 | (41) | TAIYO | 07+ | Device Protocol The X76F102 supports a bidirectional bus oriented pro- | |
| HK3 | (10) | Description The HEDS-974x series is a high performance, low cost, opti | |||
| HK4 | (3) | TI | TSSOP | 99+ | † Stresses beyond those listed under absolute maximum ratings may c |
| HK5 | (8) | LAMBDA | Module | N/A | High current sink/source 25 mA/25 mA Up to 47 I/O pins with individual |
| ＨＫ６ | (2) | Writing of memory data is performed in either byte or word increm | |||
| HK7 | (2) | 92 | DIP | There is no provision to abort an Erase or Program operation, once initia | |
| HK8 | (5) | HARRIS | SOP-8 | Semelab Plc reserves the right to change test conditions, parameter limits | |
| HK9 | (3) | 0330+ | 1. Users should independently evaluate the suitability of and test each p | ||
| HKA | (8) | hot sell | DIP | og stock | The TLV3011 and TLV3012 are available in the tiny SOT23-6 package for s |
| HKB | (3) | MOT | NOTES: 1. Dimensions are in inches. 2. Metric equivalents are given fo | ||
| HKC | (1) | The DS90C385A is a pin to pin compatible replacement for DS90C383, DS90 | |||
| HKD | (3) | HAR | 95 | DIP | The most common application for charge pump devices is the invert |
| HKE | (23) | ST | 05+ | SOP-16 | 1. Test conditions: T = 25º C, Supply Voltage = +6 V, Device Voltage |
| HKG | (4) | MOTO | DIP | 1993 | Figure 4 is the complete schematic diagram of the OTA. The OTA employs |
| HKJ | (1) | HUAHANG | DIP | 06+ | Serial Interface The HKJTB3-A supports a bidirectional bus oriented pro |
| HKL | (2) | HD | QFP2828-208 | 1. Place series resistors and CI capacitors as close as possible to the re | |
| HKN | (2) | dc | Notes: 5. LL disables outputs if TEST = MID and sOE# = HIGH. &nbs | ||
| HKP | (3) | HANDKEY | DIP | 06+ | The references for the eight DACs are derived from two reference pins (o |
| HKR | (3) | ST | SOP16 | 07+ | 1. StarTech PPI Card memiliki konektor DB25 Female yang berisi 24 port eks |
| HKS | (4) | IPD | SOP | For the purposes of simplification, the following descrip- tions will ass | |
| HKT | (15) | LAMBDA | Module | N/A | Hardware data protection measures include a low V CC detector that autom |
| HKV | (6) | Strap:see Note 4 Notes: 1. DQ-to-I/O wiring may be changed withi | |||
| HKW | (4) | These three inputs establish a code defining one of eight possibl | |||
| HKX | (6) | The power good signal generator is to monitor the voltage level of power | |||
| H-L | (1) | JAT | 5650 | 05+ | 3. AGC (AGC, pixel mixing, mirror reversal, and OB clamping functions) & |
| HL- | (25) | high-frequency tube | HITACHI | 04+ | |
| HL0 | (56) | NS | DIP28 | 98+ | The READ instruction will stream out data at a specified address on the D |
| HL1 | (41) | N/A | 100KEP PECL/ECL compatible differential output. PECL/ECL termination is w | ||
| HL2 | (31) | 3,060 | This low failure rate represents data collected from Maxims reliab | ||
| HL3 | (18) | N/A | SOP8 | The clock is generated by a phase-locked oscillator (PLO). The PLO is loc | |
| HL4 | (6) | FAIRCHILD | DIP（陶瓷） | 7827 | All the 80C186XL integrated peripherals are con- trolled by 16-bit regis |
| HL5 | (12) | N/A | 7.9X5.0 | Timer counter 3 : 8-bit 1 (square-wave output, event count, generation o | |
| HL6 | (28) | HL | 1600/box,160/tray | 0601+ | be accessed in less than 70ns/90ns with respect to Spec. This eliminates |
| HL7 | (7) | 裸片 | 99+ | Device erasure occurs by executing the erase command sequence. This initi | |
| HL8 | (9) | INTEL | |||
| HL9 | (13) | ROHM | TSSOP-3.9-20P | 6+ | The capacitance (Ciss) is read from the capacitance curve at a voltage c |
| HLA | (8) | 98 | In the normal mode, these devices are functionally equivalent to the F245 | ||
| HLB | (12) | HSM | TO-252 | 04+ | Supports automatic programming, Embedded AlgorithmTM*3 Write/Erase/Erase |
| HLC | (50) | 02+ | UV/OV PINCCUNDERVOLTAGE AND OVERVOLTAGE DETECTION Undervoltage Fal | ||
| HLD | (14) | SHINDENGEN | SIP10 | 04+ | ADPCM bit rate select inputs. The QSEL0 and QSE1 signals are strobed in |
| HLE | (62) | samtec | samtec | dc99 | The ADS5553 is a high-performance, dual channel, 14 bit, 65 MSPS analog-t |
| HLF | (2) | The HEF4094B is an 8-stage serial shift register having a storage latch | |||
| HLG | (4) | NanoStar and NanoFree Packages Low Static-Power Consumpti | |||
| HLI | (2) | JAT | 05+ | The VP-1000A is totally self-contained. It can access the external memor | |
| HLJ | (1) | The Simultaneous Read/Write architecture provides simul- taneous operati | |||
| HLK | (3) | TMIN = −40C, TMAX = +85C. Typical values are at TA = 25C, clock fre | |||
| HLL | (1) | ST | DIP8 | Bidirectional Data Bus. This bidirectional bus is used as the entire data | |
| HLM | (3357) | hp | hp | dc99 | The LIN driver function LIN_IdleClock can check whether or not there is a |
| HLN | (330) | —— | CDIP28 | —— | Here we see a data line and the clock of a standard SDRAM isolated in a |
| HLP | (3) | IR | 98+ | The HYM72V64736B(L)T8 Series are 64Mx72bits ECC Synchronous DRAM Modules. | |
| HLQ | (2) | The GS4882 and GS4982 feature an internal color burst filter for minimiza | |||
| HLS | (27) | RU | 08+ | Special Function Registers The special function registers (directly addr | |
| HLT | (22) | MOT | SOP8 | N/A N/A | 1. Required LO level is a function of the LO frequency. 2. The LO input |
| HLU | (4) | NA | NA | • Superior Performance in Outdoor Environments • Wa | |
| HLV | (1) | 2008 | Tutte le informazioni contenute nel presente manuale sono state accuratam | ||
| HLW | (14) | fci | fci | dc04 | PCM INTERFACE The FSX and FSR frame sync inputs determine the begin- ni |
| HLX | (7) | HLX | N/A | Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type. | |
| HLY | (1) | ON | • Fully asynchronous operation • Automatic power-down • | ||
| H-M | (1) | NIHON | SMB | 05+ | Dimensions in mm. The components are situated on one side of the Rogers |
| HM- | (6) | HIT | RF input pin. This pin is NOT internally DC blocked. A DC blocking capac | ||
| HM0 | (45) | N/A | Designing for Very Fast Load Transients The transient response of the DC | ||
| HM1 | (671) | HIT | CDIP22 | 9603+ | Hynix HYMD232646(L)8-K/H/L series incorporates SPD(serial presence detect) |
| HM2 | (230) | Hitachi | The LS160 and LS162 count modulo-10 in the BCD (8421) sequence From stat | ||
| HM3 | (216) | TEMIC | 00+ | DIP20 | All Typical Values are at VCC = 5 V, Ta = 25C The algebraic convention is |
| HM4 | (138) | Hitachi | Power mode: Normal, Slow, Idle, Stop mode and SL_IDLE mode. Normal mode: | ||
| HM5 | (1345) | HIT | SOZ | 94+ | Notes: 1. For conditions show as Max. or Min., use appropriate value spe |
| HM6 | (1780) | The Hitachi HN29W25611S Series is CMOS Flash Memory with AND type memory | |||
| HM7 | (54) | N/A | SOT-89 | 05+ | All devices present a 1/8 unit load to the RS-485 bus, which allows up to |
| HM8 | (78) | HMC | DIP | 07+ | All voltages are referenced to V SS = 0 V (ground). All characteristics |
| HM9 | (208) | 华斑 | q Electrical characteristics of power circuit (Tc=Tj=25˚C, Vcc=15V) | ||
| HMA | (129) | FAIRCHILD | 05/06+ | .OperatingVoltage Range of Drive Circuitry: 4.5 to 5.5 V .OperatingJunct | |
| HMB | (124) | 华昕 | SOT23 | Note: (1) This parameter is tested initially and after a design or proce | |
| HMC | (866) | Hittite | 05+ | LCD panel VCOM adjustment LCD panel brightness and contrast control Mec | |
| HMD | (13) | N/A | The AD5305/AD5315/AD5325 are quad 8-, 10-, and 12-bit buffered voltage o | ||
| HME | (3) | • Untinted non diffused lens • Utilizing ultrabright AllnGa | |||
| HMF | (22) | dale | dale | dc72+ | † Pulse-testing techniques maintain the junction temperature as clo |
| HMG | (1) | HP | SSOP | 99+ | Notes: 1. Repetitive Rating : Pulse width limited by maximum junction tem |
| HMH | (54) | Fairchi | 05+ | NOTES: 1. For conditions shown as Min. or Max., use appropriate value sp | |
| HMI | (31) | HARRIS | CDIP | The power input pin of the regulator. Typically a large storage capacitor | |
| HMJ | (7) | WJ | Notes: 5. Distribution data sample size is 500 samples taken from 5 diffe | ||
| HMK | (12) | TAIYO | . | 09+ | The 33099 uses a feedback voltage to establish an alternator field |
| HML | (39) | put, namely; mechanical and optomechanical. It re- quires minimal externa | |||
| HMM | (35) | Data/Address Transfer All data transfers (including addresses) take plac | |||
| HMN | (10) | 03+ | BACKPLANE TEST DATA OUTPUT: This output drives test data from the STA111 | ||
| HMO | (1) | The TMS28F400BZx is a 524 288 by 8-bit / 262 144 by 16-bit (4 194 304-bit | |||
| HMP | (68) | 华晰 | 袋装 | The internal PFD, a high-speed rising edge triggered type, has an interna | |
| HMR | (23) | 1600 | 7.4.3 DHCP RFC 2131, 2132 Dynamic Host Control Protocol (DHCP) provides | ||
| HMS | (105) | HYNIX | 00+ | Flame-resistant Suppress combustion and smoking after a malfuncti | |
| HMT | (74) | TEMIC | 2008 | Notes: 5. VIL(min.) = −2.0V for pulse durations less than 2 | |
| HMU | (54) | HOSICEN | SOP | 00+ | Notes:3. Pulsed measurement, PW 350 µs, duty cycle 2%. 1. Precau |
| HMV | (6) | TOS | 00P3 | 6520 | • Fast Page Mode Access Cycle • TTL compatible inputs and o |
| HMW | (2) | HANLIM | 00+ | In such cases a mechanical shutter is needed to shield the array from inc | |
| HMX | (2) | N/A | SOT-89 | 05+ | (2) Storage The LEDs should be stored at 30C or less and 70%RH or |
| HMZ | (20) | N/A | The MAX1533/MAX1537 are dual step-down, switch- mode power-supply (SMPS) | ||
| HN- | (7) | HYUNDAI | PQFP-208P | 03+ | ‡ Stresses beyond those listed under absolute maximum ratings may c |
| HN0 | (3) | 模块 | 03+ | An on-chip PWM dimming circuit enables and disables the current mode regu | |
| HN1 | (163) | N/A | N/A | 04+ | Glass passivated die construction Ideal for printed circuit boards Plast |
| HN2 | (332) | Hitachi | At 333 MHz (3.0 ns) core instruction rate, the ADSP-21365/6 perfo | ||
| HN3 | (32) | Continuous Drain Current, VGS @ 4.5V Continuous Drain Current, VGS @ 4. | |||
| HN4 | (64) | HITACHI | DIP | Hynix HYMP112S64MP8 series is unbuffered 200-pin double data rate 2 Synchr | |
| HN5 | (187) | HIT | 00+ | The MSM7702 is a single-channel CODEC CMOS IC for voice signals ranging fr | |
| HN6 | (389) | HITACHI | SOP | 00+ | Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Forward |
| HN7 | (14) | PAN | DIP-24 | 04+ | MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to th |
| HN8 | (5) | N/A | N/A | N/A | SIZEB determines the bus width of Port B. A HIGH on this pin selects byte |
| HN9 | (10) | DIP20 | 07+ | HN91610A is a 6-channel video driver IC developed for progressive DVD play | |
| HNA | (4) | SAMSUNG | The HN29V1G91 series achieves a write speed of 10 Mbytes/sec, which is 5 | ||
| HNB | (2) | HT-SINCERITY | Maximum ratings are those values beyond which device damage can occur. Ma | ||
| HNC | (9) | LA | MODULE | The NCP1501 is a dual mode regulator that operates either as a PW | |
| HND | (2) | HND | 3225 | 05+ | The ICL8038 waveform generator is a monolithic integrated circuit capabl |
| HNG | (2) | 01 | Widebus Family Output Ports Have Equivalent 22-Ω Series R | ||
| HNI | (3) | HITACHI | SOT-163 | 07+/08+ | Provide a very well decoupled 5V bias supply for the IC to this pin by co |
| HNK | (1) | Two communication ports are provided, a 1-Wire and a 3-wire port. The adva | |||
| HNL | (12) | YAGEO | 3225 | When power is applied to VDD, an internal Power On Reset holds the PCA95 | |
| HNM | (3) | N/A | N/A | N/A | SINGLE CHIP MPEG2 LAYER 3 DECODER SUPPORTING: - All features specified |
| HNR | (1) | ||||
| HNS | (3) | N/A | SOP | 07+ | The feature set of the 80C186EB meets the needs of low power space criti |
| HNT | (7) | HITACHI/TOSHIBA | 2500 | 1. Charge qualification 2. Trickle charge, if required 3. Fast charge (c | |
| HNV | (1) | CAUTION: THIS IS AN ESD SENSITIVE DEVICE. Chip carrier material should be | |||
| HNZ | (1) | At a gain of +2, the EL2245 and EL2445 have a -3dB bandwidth of 100MHz | |||
| HO- | (17) | HOSONIC | SOP | 650 | Motorola reserves the right to make changes without further notice to any |
| HO1 | (3) | SWIRE | PLCC | 03+/04+ | DISP high disables the LED display. DISP tied to VCC allows PROGX to conn |
| HO2 | (2) | HOSONIC | SOP | 314 | The PGA and black level auto-calibration are con- trolled through a sim |
| HO3 | (2) | TOS | QFP-44 | 1. 4-channel(4 Form A) of RF Photo- MOS Relays 2. SO package 16-pin type | |
| HO5 | (1) | tmc | tmc | dc00+ | Note 6: Load and line regulation are measured at constant junction temper |
| HO6 | (2) | N/A | MQFP | 07+ | Refer to the RC5051 Block Diagram illustrated in Figure 2. The control l |
| HO9 | (2) | HOSONIC | SOP | 607 | This publication is issued to provide outline information only which (unl |
| HOA | (83) | honeywell | 0 | 0 | Even the most conservative heat-sink design will not save the MOSFET. T |
| HOC | (4) | S3 | PLCC28 | Programmable Output Voltage to 36 Volts Low Dynamic Output | |
| HOF | (2) | SCS | 陶DIP | 88+ | In addition to the data sheet changes made above due to product enhanceme |
| HOH | (1) | Note 1 Absolute Maximum Ratings indicate limits beyond which damage to th | |||
| HOJ | (1) | RIVER | Note 1: Relative accuracy is the deviation of the analog value at any code | ||
| HOL | (1) | ||||
| HOM | (4) | AGERE | BGA | This pin is the positive supply pin, and should always be the most posi | |
| HON | (3) | AMIS | O7+ | The SoftStart charge eases batteries into the fast charge stage by gradual | |
| HOO | (3) | ZILOG | SMD18 | NOTES: (1) Standard test timing: 1ms integration, 200µs hold, 100&m | |
| HOP | (6) | (LX)high-frequency | - On chip Hall sensor - Rotor-locked shutdown - Automatically restart - | ||
| HOR | (4) | SYMBIOS | QFP | 95 | |
| HOS | (45) | ADI | |||
| HOT | (5) | NCR | 93 | Dual axis accelerometer on a single IC chip 5 mm 5 mm 2 mm LCC package | |
| HOW | (1) | HOWAY | 1998 | QFP | The designer can choose the internally generated reference voltages by c |
| HOY | (1) | The sensor array is composed of 300 rows and 300 columns of sensor plates | |||
| H-P | (1) | MB90895 series devices are 16-bit micro general-purpose controller | |||
| HP- | (29) | HYPHI ELECTRONICS | 4 | Both the TPA and TPB cable interfaces incorporate differential comparator | |
| HP0 | (27) | The high-side driver is designed to drive low rDS(on) N-channel MOSFETs. | |||
| HP1 | (82) | HP | 2007 | address spaces, and I/O control registers, occupy separate sections of t | |
| HP2 | (117) | N/A | QFP-48 | Regulates voltage over a broad operating current and temperature range E | |
| HP3 | (53) | HEWLETT | DIP8 | A 0.1 µF capacitor is placed between this pin and ground to provi | |
| HP4 | (102) | Note: (1) The minimum DC input voltage is C0.5 V. During transitions, in | |||
| HP5 | (64) | 06+ | |||
| HP6 | (26) | HP | 04+ | SOP8 | The output and reset of the integrators is controlled by a 128-bit shift |
| HP7 | (53) | HP | SMD-8 | The RHL package is available taped and reeled only in quantities of 3,000 | |
| HP8 | (17) | HP | 00+ | Input-Output Enable, asynchronous input, active LOW. Controls the | |
| HP9 | (19) | HEWLETT | SOP8 | 2.Controlling dimension : millimeters. 3.Maximum lead thickness includes | |
| HPA | (28) | 07+ | NOTE:2679 tbl 01 1. Stresses greater than those listed under ABSOLUTE MA | ||
| HPB | (2) | N/A | negative transition of each input pulse; a high level on the RESET line | ||
| HPC | (222) | 8906+ | High-performance, EEPROM-based programmable logic devices (PLDs) based o | ||
| HPD | (26) | HP | An analog overcurrent detection circuitry is built into the ISP1521, whic | ||
| HPE | (2) | HP | QFP | 2002 | Hynix HYMD232726A(L)8J-J series incorporates SPD(serial presence detect). |
| HPF | (97) | Agilent | CQFP2828 | The Hynix HYM72V32M636T6M Series are 32Mx64bits Synchronous DRAM Modules. | |
| HPG | (3) | system clocks (At a SCLK of 66Mhz and TCK of 1MHz this allows for 66 TC | |||
| HPH | (6) | DIP(DC-DC) | 00+ | SW (Pin 1): Switch Pin. This is the collector of the internal NPN Power s | |
| HPI | (21) | INTEL | BGA | 06+ | Internal Memory Restores Volume Setting After Shutdown or Power Down Dig |
| HPJ | (3) | HP | Drain-Source Breakdown Voltage Breakdown Voltage Temperature Coefficient | ||
| HPK | (6) | The HPK1063-02 is a monolithic CMOS integrated circuit that includes st | |||
| HPL | (33) | SUSUMU | 0201L | International Rectifier radiation hardened HEXFETs have been characteri | |
| HPM | (73) | HP | 99+ | 1. Typical characteristics are at TA = 25oC.2. Fmax = 1/tRC. 3. These | |
| HPN | (8) | 华晰 | 排带 | The AT8xC5111 has 3 software-selectable modes of reduced activity for fur | |
| HPP | (1) | EXPANSION OUT/HALF-FULL FLAG (XO/HF) This is a dual-purpose output | |||
| HPQ | (17) | MINI | 08+ | 2. Span (Gain) and Zero (Offset) Adjustments (See Figure 3): DATEL | |
| HPR | (73) | Module | BB | 93+ | The receiver senses signals through the RXI input, which minimizes refl |
| HPS | (7) | To aid equipment management and maintenance, the HPS0256 passes an embe | |||
| HPT | (14) | MOT | SOP8 | Connect control terminal to VIN terminal The quiescent current ca | |
| HPV | (6) | HEWLETT | SOP8 | The I/O port of this device has a pullup current source that maintains th | |
| HPW | (32) | HEWLETT | 06+ | 500 | The ADM2486 driver has an active-high enable feature. The driver differe |
| HPX | (5) | 1230 | The gain error in the HPX050GD ADCs, is defined as the difference betwee | ||
| HPY | (4) | N/A | 1206LED | ESD (electrostatic discharge) sensitive device. Electrostatic charges as | |
| HPZ | (25) | N/A | The HPZ181210-D can be configured for automatic power saving Burst Mode o | ||
| HQ- | (1) | Magnitude of Common Emitter Small-Signal Short-Circuit Forward Current | |||
| HQ1 | (25) | NEC | SOT-89 | 04+ | With a 16-bit CPU core that enables high-speed arithmetic computations an |
| HQ2 | (7) | NEC | SOT89 | Virtex-E devices provide better performance than previous generations o | |
| HQ3 | (2) | C Read, program and erase operations from 2.7 to 3.6 volts C Ide | |||
| HQ4 | (1) | Passivated high commutation triac in a SOT78 (TO-220AB) plastic package. | |||
| HQ5 | (2) | SL | SOP24 | 0305+ | The 78253 series of converter transformers are specifically designed for |
| HQF | (1) | Information contained in this publication regarding device applications | |||
| HQM | (1) | 97+ | The ZREF25 design provides a stable voltage without an external capacito | ||
| HQP | (2) | RECEIVE CHANNEL Number of Inputs Input Voltage Range Common-Mode Vol | |||
| HR- | (58) | LAMBDA | Module | N/A | Test Condition Vss < VIN < Vcc Vss < VOUT < Vcc, /CS |
| HR0 | (2) | LB | SOP16 | 01+ | Renesas Technologys HN58V65A series and HN58V66A series are electrically |
| HR1 | (40) | HOMERUN | 400 | QFP | * Antiparallel diode for high frequency switching devices * Antis |
| HR2 | (12) | LB | The HR2002 includes a POK output to indicate when input power is present | ||
| HR3 | (9) | 模块 | BCT | 00+ | A Frequency Control pin (BOOST/FC) is provided to select either a high |
| HR4 | (8) | INSTERSIL | 03+ | Margin Dn*: When this open-collector (open-drain) input is asserted to GN | |
| HR5 | (6) | semicond | An inhibit/sync pin is standard on all models of the HR700 Series conver | ||
| HR6 | (39) | HanRun | Note: 1. Load and line regulation are specified at constant junction temp | ||
| HR7 | (7) | HARR | DIP | 94+ | CAUTION: Stresses above those listed in Absolute Maximum Ratings may caus |
| HR8 | (3) | HP | 04+ | Hynix HYMD532M646(L)6-K/H/L series incorporates SPD(serial presence detect | |
| HR9 | (14) | HR | a/n | 746 | To have a good approximation of the remaining voltages at both Vin and Vo |
| HRA | (7) | MOT | TIs new, small geometry, state-of-the-art, analog CMOS process allows t | ||
| HRB | (18) | Hitachi | Circuits for safe protective separation against electri- cal shock acco | ||
| HRC | (19) | Hitachi | Updated part listing on first page and in Table A. Table AAdded 266 MHz | ||
| HRD | (10) | SHINDENGEN | MODULE | 03+ | VBIAS (VCC, V BS1,2,3) = 15V, VS0,1,2,3 = VSS and TA = 25C unless otherw |
| HRE | (1) | 80C51 based architecture 4K x 8 ROM (IC80C51 only) 128 x 8 RAM Two 16 | |||
| HRF | (61) | N/A | 0807+ | 97+ | In the application shown in Figure 1, the STROBE signal is provided by th |
| HRG | (1) | 1 ms instruction cycle time Three multi-source vectored interrupts servi | |||
| HRH | (3) | SMD-8 | 04+ | FEATURES • Dual Channel (LH1540) • Current Limit Protection | |
| HRI | (1) | ALCATEL | 06+ | PLCC84 | 2.0V to 6.3V operation Three switch inputs: S2, S1, S0 C seven function |
| HRL | (37) | sovcor | sovcor | dc80+ | The ISP1521 is a stand-alone Universal Serial Bus (USB) hub controller IC |
| HRM | (16) | HITACHI | SOT-23 | IF Port. This pin is DC coupled. For applications not requ | |
| HRN | (21) | CMD | SOP | CS to WR Setup time WR to Status delay WR pulse width CS to WR Hold | |
| HRP | (104) | AGILENT | 08+ | The LM45 series are precision integrated-circuit temperature sensors, w | |
| HRR | (5) | 2002 | The output data consists of 128 bits of analog data from a charge mode li | ||
| HRS | (20) | HKE | Relay(new original) | The module may be disabled by pulling PC below 2.3V with respect to the | |
| HRT | (2) | All voltages are measured with respect to GND, unless otherwise sp | |||
| HRU | (16) | HITACHI/RENESAS | 805 | Note 1: Absolute Maximum Ratings indicate limits beyond which damage to t | |
| HRV | (3) | RENESAS | SOD-323 | 05NOPB | Common-Mode Leakage DIGITAL INPUTS Input Logic High (SDA a |
| HRW | (53) | HITACHI | TO- | The sensor consists of a precision linear Hall IC, which is optimized to | |
| HS- | (26) | N/A | N/A | N/A | Notes: 1. RJA is determined with the device mounted on a 1 in2 2 oz. cop |
| HS0 | (43) | NS | SOP | The M51132 is a VCA (Voltage Controlled Amplifier) IC developed as an ele | |
| HS1 | (104) | 406 | MICROCHIP | 99+ | An obvious approach is to include a timer that shuts down the IC after a |
| HS2 | (48) | MAGCOM | In the graph below the transfer function of the HS2001 is given. •T | ||
| HS3 | (47) | SIPEX | 00+ | Hynix HYMD132645B(L)8-M/K/H/L series is designed for high speed of up to | |
| HS4 | (21) | 1. Test conditions unless otherwise noted: 25º C, Supply Voltage = + | |||
| HS5 | (22) | DIP | N/A | internal current-control circuitry (or by the PHASE or ENABLE inputs). | |
| HS6 | (20) | IC | SOP | GATE (Pin 7): Gate Drive Output Pin for Internal and External Pass Transi | |
| HS7 | (6) | SIPEX | CDIP40 | 9421 | Notes: 6. Test conditions assume signal transition time of 5 ns or |
| HS8 | (12) | 4 | 华昕 | DIP | Filter Characteristic Select (Input). In Hardware Control, FCS selects the |
| HS9 | (81) | SIPEX | DIP | N/A | The customer¢s voice sources are recorded sec- tion by section into |
| HSA | (11) | HS | These N-Channel power MOSFETs are manufactured using the | ||
| HSB | (56) | HITACHI | 06+ | SOT-323 | The main counter, Nominal Available Charge (NAC), represents the availabl |
| HSC | (110) | AVAGO | The ICS660 provides clock generation and conversion for clock rates com | ||
| HSD | (297) | agi | agi | dc0422 | The isolation voltage is a galvanic isolation and is verified in an elect |
| HSE | (8) | HITACHI/RENESAS | DIP | Data is clocked on the negative transition of the CLOCK waveform. If less | |
| HSG | (8) | HOLD is used in conjunction with the CS pin to select the device. Once | |||
| HSH | (3) | HITACHI | SOT-34 | N/A | Note: All information contained in this data sheet has been carefully che |
| HSI | (7) | INTERSIL | 07+ | UART channel A Receive Data or infrared receive data. Normal receive data | |
| HSJ | (29) | N/A | Hosiden | 05+ | Vcc = 2.7V~3.3V, TA = 0C to 70C/ -40C to 85C unless otherwise specified & |
| HSK | (24) | Hitachi | Note: Stresses greater than those listed under MAXIMUM RATI | ||
| HSL | (2) | TB6549F/P is a full-bridge driver IC for DC motor which uses LDMOS for o | |||
| HSM | (2218) | AGILENT | 08+ | TMS320C62x, VelociTI, and C62x are trademarks of Texas Instruments. Moto | |
| HSN | (5) | BOSE | SOP- | 03+ | |
| HSO | (4) | Note 5: Dynamic supply current is higher due to the gate charge being de | |||
| HSP | (247) | The HYM72V64736(L)T8 Series are 64Mx72bits ECC Synchronous DRAM Modules. | |||
| HSR | (42) | DIP | CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic ch | ||
| HSS | (47) | 99/00+ | Drain-to-Source Breakdown Voltage Gate Threshold Voltage Gate-to-Sourc | ||
| HST | (30) | GROUP | SOP | 06+ | • Compatible with Popular Fiber Optic Module Specifications |
| HSU | (41) | RENESAS | 2008 | Care must also be taken to minimize the capacitance to ground seen by t | |
| HSV | (2) | 142 | PHILIPS | 99+ | • ML22Q54 The ML22Q54 is a speech synthesis device with a 4- |
| HSW | (10) | HOSIDEN | 00+ | !Features 1) Built-in bias resistors enable the configuration of an inver | |
| HSX | (3) | Note 3: The Absolute Maximum Ratings are those values beyond which the sa | |||
| HSY | (2) | HITACHI | 厚膜 | Use the typical performance graphs as a guide for expected variat | |
| HSZ | (2) | the device has a Sector Protect function which hardware write protects | |||
| H-T | (2) | BGA | 91 | The TC55VEM416AXBN is a 16,777,216-bit static random access memory | |
| HT- | (117) | HARVATEK | SOD-523 | The new package that consists of OSAs and ESA with the combination of | |
| HT0 | (22) | SOP14 | 06+ | Operating Voltage, VDD Input High Voltage, VIH Input Mid-Level Voltage, | |
| HT1 | (193) | HOLTEK | TO-92 | 05+ | PRODUCTION DATA information is current as of publication date. Products c |
| HT2 | (200) | TI | TSOP20 | 2007+ | The enhanced configuration device features multiple configuration scheme |
| HT3 | (61) | SOP14 | 06+ | CAUTION: These devices are sensitive to electrostatic discharge. F | |
| HT4 | (211) | The RDRAM architecture enables the highest sustained bandwidth for multip | |||
| HT5 | (19) | SOJ | 97+ | Erase (ERASE) After the erase instruction is entered, CS must be brought | |
| HT6 | (159) | HOLTEK | CRC-6 | 08+ | Unless otherwise specified: -40C < TAMB < 85C, -40C< Tj< 125 |
| HT7 | (218) | HOLTEK | 03+ | Storage Temperature−40C to +150C (1) Stresses above those listed | |
| HT8 | (144) | HOLTEK | DIP-18 | 08+ | The GS9068 inputs are self-biased, allowing for simple AC coupling to the |
| HT9 | (261) | HOL | HIGH SPEED: tPD = 4.3 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC | ||
| HTA | (3) | 88 | As shown in the Block Diagram, the circuit is comprised of four function | ||
| HTB | (12) | ||||
| HTC | (60) | KAWASAKI | MODULE | N/A | The AP1501 series are monolithic IC that design for a step-down DC/DC con |
| HTD | (88) | Eupec | Differential clock input. The TFP513 supports both single-ended and fully | ||
| HTE | (2) | Hitachi | 2699 | The 320VC33 contains a JTAG port for CPU emulation within a chain of any | |
| HTF | (7) | N/A | The Fairchild Switch FST34170 is a 17-bit to 34-bit high- speed CMOS TT | ||
| HTG | (7) | HT | Bongding | 01+ | The bq4802Y/bq4802LY provides direct connections for a 32.768-kHz quart |
| HTH | (3) | Input capacitance Output capacitance Reverse transfer capacitance Tota | |||
| HTI | (7) | 1996+ | The bq2050 determines battery capacity by monitor- ing the amount of curr | ||
| HTJ | (9) | KUNMING | 04+ | Ausgabe 01.2001 Herausgegeben von Infineon AG , Marketing-Kommunikation, | |
| HTK | (1) | N/A | These devices operate from a 2.5-V to 5.5-V single supply voltage and are | ||
| HTL | (6) | Programmable undervoltage and overvoltage detectors disconnect the load w | |||
| HTM | (24) | TxD = logic 1 (or floating) on this pin produce an undriven or recessive | |||
| HTN | (8) | HTNV | 123 | 04+ | Chip select. A high-to-low transition on CS resets the internal counters |
| HTP | (34) | LA | MODULE | The CMX866 has the capability to generate single or dual user-defined tone | |
| HTQ | (1) | N/A | TQFP80 | 07+ | • VDD : 2.5V 0.2V, VDDQ : 2.5V 0.2V for DDR266, 333 • VDD : |
| HTR | (52) | SIEMENS | To set the new VTRIP voltage, apply the desired VTRIP threshold voltage | ||
| HTS | (87) | AD | AUCDIP | The customer¢s voice sources are recorded sec- tion by section into | |
| HTT | (182) | Eupec | Output resistanceDifferential, HB C VDD = 1.3 V20 or 40Ω (1) | ||
| HTV | (8) | A write operation requires an 8-bit data word address following the devic | |||
| HTW | (1) | Port 0 is also the multiplexed low-order address and data bus during acc | |||
| HTX | (1) | † Stresses beyond those listed under absolute maximum ratings may c | |||
| HTY | (2) | Thermal Data - Thermal Resistances Some thermal data (e.g., junction tem | |||
| HTZ | (5) | Modem Control Output For external modem, these pins are bit7~4 of the mo | |||
| HU- | (8) | N/A | 4516 | High speed 190 MHz, C3 dB bandwidth (G = +1) 100 V/µ | |
| HU0 | (5) | TI | TSOP14 | 07+ | The HU04 microcontroller features a direct connection to off-chip memory, |
| HU1 | (6) | TO-263 | 07+ | The device features single 3.0 V power supply operation for both read and | |
| HU2 | (8) | Multi-Input Wake Up (on the 8-bit Port L) Brown out detector Analog com | |||
| HU3 | (2) | SOP32 | Note 14: A 40% to 60% duty cycle range insures proper operation at all cl | ||
| HU4 | (9) | HYUNDAI | TQFP | 1999 | The information provided herein is believed to be reliable; however, C&am |
| HU5 | (2) | Bursts can be initiated with either ADSP (Address Status Processor) or | |||
| HU6 | (2) | HSMC | 04+ | Operational Bandwidth Test Frequency Gain Input Return Loss Output | |
| HU7 | (1) | Hynix HYMD564G726(L)8-K/H/L series incorporates SPD(serial presence detect | |||
| HU8 | (11) | HY | PLCC | 99+ | The bq2000 uses a peak-voltage detection (PVD) scheme to terminate fast c |
| HU9 | (1) | N/A | SOP14S | 07+ | The LVTH18512 and LVTH182512 scan test devices with 18-bit universal bus |
| HUA | (4) | N/A | N/A | N/A | Pin-compatible upgrade of TMC2242B User-selectable interpolate d.c. gain |
| HUB | (5) | This IC provides protection for lithium ion batteries in the event of over | |||
| HUC | (9) | RENESAS | SOD523 | Note 2: This IC contains a zener clamp structure between the chip VCC and | |
| HUD | (1) | The IC provides three universally applicable 40-mA open-collector buffers | |||
| HUE | (16) | IOR | 2008 | Absolute linearity is utilized to determine actual wiper voltage versus e | |
| HUF | (642) | KA/INF | TO | ||
| HUG | (2) | Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., | |||
| HUL | (18) | 96+ | Must be chosen from an inspection lot that has been submitted to and pass | ||
| HUM | (6) | HITACHI/RENESAS | SOT23 | The demo boards are designed to verify different features easily and qu | |
| HUN | (5) | STT | SOT-23 | Note 3: When the input voltage at any pin exceeds the power supply (that | |
| HUP | (2) | PCM input C 102 dB of Stopband Attenuation C Supports Sample Rates up to | |||
| HUR | (1) | ZILOG | SOP | 03+ | The 16-bit synchronization counter is the basis behind the transmitted |
| HUS | (5) | FUNJIN | 9911 | The push-pull clock output drives a load to within 400mV of either supply | |
| ＨＵＴ | (3) | NOTES: 1. All typical values are at VCC = 5 V, unless otherwise noted. T | |||
| HV- | (5) | 9619 | Package drawings, standard packing quantities, thermal data, symbolizatio | ||
| HV0 | (14) | DIODE | Throughout this document, the term 2.7 V refers to the full voltage ran | ||
| HV1 | (19) | NI | TO223-3P | 6+ | These lamps are made with an advanced optical grade epoxy, offering supe |
| HV2 | (43) | INTERSL | STK | 2005+ | * NOTE : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cyc |
| HV3 | (33) | 43 | HI | O3 | Hardware data protection measures include a low V CC detector that autom |
| HV4 | (17) | 96 | • True dual-ported memory cells which allow simultaneous re | ||
| HV5 | (70) | Supertex | QFP | 05+ | These N-Channel enhancement mode power field effect transistors are produ |
| HV6 | (21) | HV | 00+ | These pins are connected internally to the DMOS output transistors which | |
| HV7 | (31) | SUPERTEX | 06+ | The TO-220 is offered in a 3-pin is universally preferred for all commer | |
| HV8 | (72) | hp | SMD | SMD | 32 Mbit Am29DL32x devices had a larger SecSi Sector. Factory locked parts |
| HV9 | (67) | Supertex | PLCC | 07+ | VCE=(--)5V, IC=(--)1A VCE=(--)5V, IC=(--)6A VCE=(--)5V, IC=(--)1A VC |
| HVA | (1) | TI | SSOP | 07+ | Notes: (1) RMA flux is recommended. Duration can be extended to 10 sec. m |
| HVB | (5) | HITACHI | 2008 | The CCFL regulator drives an inductor that acts as a switch-mode current | |
| HVC | (218) | HITACHI | 二极 0603 | • Frequency Output (SW Selectable: Off, 1Hz, 100Hz, or 32.76 | |
| HVD | (40) | HITACHI | 06+ | Clock: CK and CK are differential clock inputs. All address and control i | |
| HVE | (20) | HITACHI | 603 | † Stresses beyond those listed under absolute maximum ratings may c | |
| HVF | (1) | The Samsung M464S3254DTS is a 32M bit x 64 Synchronous Dynamic RA | |||
| HVH | (1) | MICRO | SSOP | 05+ | Drain-to-Source Breakdown Voltage Gate Threshold Voltage Gate-t |
| HVJ | (1) | The SN74CB3T16211 is organized as two 12-bit bus switches with separate o | |||
| HVK | (8) | Hitachi | Test conditions at IO = 3.5mA, RLOAD = 100Ω, and CLOAD = 9pF. IO re | ||
| HVL | (21) | renesas/Hitachi | SOD323 | 06+ | Dropout Voltage C The input/output voltage differential at which t |
| HVM | (78) | Hitachi | These N-Channel power MOSFETs are manufactured using the | ||
| HVN | (22) | HVN | 95+ | DIP- | The data of Figure 13 is based on TJ(pk) = 150C; TC is variable d |
| HVP | (3) | ON | SOP-8 | See the Texas Instruments document, PowerPAD Thermally Enhanced Package A | |
| HVR | (27) | Hitachi | The ispLSI 2128VE is a High Density Programmable Logic Device available | ||
| HVS | (3) | 05+ | 2 | QFN | The block diagram of the HVS0N72 series sensor is shown in Figure |
| HVT | (3) | sanken | sanken | dc83 | † Stresses beyond those listed under absolute maximum ratings may c |
| HVU | (212) | HITACHI | 08+ | † Notice: Stresses above those listed under "Maximum Ratings&q | |
| HVV | (1) | REF (Pin 9) (voltage reference output): REF is the output of an accurate | |||
| HVX | (2) | ||||
| HVY | (1) | The M5M51016BTP, RT are a 1048576-bit CMOS static RAM organized as 6553 | |||
| HW- | (88) | * | * | * | BURST CONFIGURATION COMMAND: The Program Burst Configuration Register com |
| HW. | (1) | 50 | ZILOG | 99+ | A general-purpose data register file is contained in each processing ele |
| HW0 | (10) | SOP | Link Fault Indicator. This output indicates the status of the input data | ||
| HW1 | (40) | ASAHIKASEI | The IA186ES/188ES is a form, fit, and function replacement for the origin | ||
| HW2 | (18) | HOME | QFP | The HW20001 microcontroller embeds 136K bytes of internal SRAM. The inter | |
| HW3 | (13) | N/A | N/A | N/A | are included on the CY7C138/9 to handle situations when mul- tiple proce |
| HW4 | (10) | HITACHI | 03+ | CAN | The BTS 781 GP is part of the TrilithIC family containing three dies in |
| HW6 | (1) | ST | SNR = 90 dB in 150 kHz bandwidth (to Nyquist @ 61.44 MSPS) Worst | ||
| HW7 | (1) | HX | TO220 | 98 | The HT6026 encoder begins a one-word transmission cycle upon receipt of a |
| HW8 | (1) | HW | DIP | 93+ | The SN74CBT3125C is a high-speed TTL-compatible FET bus switch with low O |
| HW9 | (6) | N/A | TO8 | 06+ | implement logic functions in the 500- to 800-gate-array complexity. Since |
| HWA | (1) | Eighteen configurable outputs each drive terminated trans- mission lines | |||
| HWB | (2) | The M68300 family of integrated processors and controllers is built on an | |||
| HWC | (13) | HITACHI | TB1208 | Signal input pin. A internal matching circuit, configured with resisto | |
| HWD | (83) | HWD | TSSOP16/SOP16/DIP16 | 05+ | • Integrated Pulse Shaping Circuit. • Built-in B3ZS/HDB3 Encod |
| HWE | (4) | RXCLK is the clock output bit clock. This clock is used to transfer Heade | |||
| HWF | (1) | Thermal Design The IRU1050 incorporates an internal thermal shutdown tha | |||
| HWG | (2) | N/A | The conditioning of the pressure signal begins with a capacitance | ||
| HWI | (1) | N/A | 25201008 | range of input supply voltage. The lower current limit rating and 7V maxi | |
| HWL | (6) | N/A | 25201008 | Data Inputs/Outputs: Inputs array data during program operation, when CE | |
| HWM | (1) | MOT | The device can accommodate astigmatic, single foucault and double fouca | ||
| HWP | (2) | spect | spect | dc94 | Hynix HYMD216M726A(L)6-J/M/K/H/L series is designed for high speed of up |
| HWS | (28) | N/A | SOP8 | 07+ | DESCRIPTION This power MOSFET is designed using the compa- nys consolid |
| HWT | (2) | 日立 | The READ instruction is the only instruction that outputs serial data o | ||
| HWX | (41) | TQFP100 | 05+ | READY/BUSY: The RDY/BSY pin provides the devices ready/busy status when | |
| HWY | (7) | hit | hit | dc00 | Lead temperature, Tsol, 1,6 mm (1/16 inch) from case for 10 seconds |
| HX0 | (6) | HAR | 9621 | 1250 | The 256Mb SDRAM is a high-speed CMOS, dynamic random-access memor |
| HX1 | (30) | RFMD | MuxIt is a family of general-purpose, multiple-chip building blocks for i | ||
| HX2 | (19) | Pulse | A | A | When power is applied to VDD, an internal Power On Reset holds the HX201 |
| HX3 | (3) | CAUTION: These devices are sensitive to electrostatic discharge; follow p | |||
| HX4 | (1) | The 2 series of decoders are capable of decod- ing informations that con | |||
| HX5 | (9) | Pulse | A | A | • Platinum Tri-Metal System High Temperature Stability R |
| HX6 | (1) | HIMAX | 2006 | These high speed synchronous counters utilize advanced silicon-gate CMOS | |
| HX8 | (34) | HIMOX | QFP-48 | 05+ | The SPI protocol is controlled by op-codes. These op-codes specify the |
| HXA | (1) | A reduction in video noise is achieved by correlating the picture content | |||
| HXC | (2) | DDC | 90 | f Video and snapshot operation f Progressive scan read out with horizonta | |
| HXD | (1) | SmartVoltage technology provides a choice of VDD and VPP combinations, as | |||
| HXF | (1) | ST | N/A | Port 2 Port 2 is an 8-bit bidirectional I O port with internal pullups Po | |
| HXL | (6) | HSMC | The basic unit of logic on the ispLSI 2096VL device is the Generic Logic | ||
| HXO | (16) | dsl | dsl | dc00 | The Fairchild Power Switch(FPS) product family is specially designed for |
| HXT | (11) | HSMC | 04+ | outdoor displays optical indicators signal and symbol luminaire marker | |
| HXV | (2) | DIP40 | 2007+ | The HXV3000-3L is a technological upgrade with ESD protection for the ori | |
| HXW | (5) | HOSIDEN | 01+ | presented in straight binary or twos complement formats. An out-of-range | |
| HXX | (2) | SOP | Low End of Resistor High End of Resistor Wiper Terminal of Resistor Sub | ||
| HY- | (12) | 800 mA Continuous Output Current Rating 30 V Output Voltage Rating Int | |||
| HY0 | (2) | When VCC is greater than 1V and less than the UVLO threshold, REF is pu | |||
| HY1 | (39) | DIP-28 百瓷 | Mono-BTL Output Power (RL = 8Ω, VDD = 3.0V, THD+N = 1%)410 | ||
| HY2 | (235) | HYNIX | 03+ | 36 macrocells with 800 usable gates Available in small footprint packages | |
| HY3 | (14) | HY | 2007+ | ||
| HY4 | (8) | N/A | DIP | 06+ | Reference level for the relative attenuation arel of the TFS 282 A is the |
| HY5 | (1232) | HYNIX | 03+ | The MAX3738 accepts differential data input signals. The wide 5mA to 60mA | |
| HY6 | (655) | STOP condition at the end of a Write command triggers the internal EEPR | |||
| HY7 | (48) | HY | SOJ | 94+/99+ | • 1.25 (31.75mm) PCB Height • 168-Pin Unbuffered DIMM with Do |
| HY8 | (42) | HYUNDAI | SOP32W | 2007+ | ISENSE: This is the input to the X10 wide bandwidth current-sense amplifi |
| HY9 | (16) | N/A | N/A | N/A | The value of the capacitor is recommended to be the line length (time) |
| HYA | (1) | MOTO | TSSOP-8 | 2004 | Proper operation requires the use of two current limit resistors, |
| HYB | (464) | INF | 06+ | • ML22Q54 The ML22Q54 is a speech synthesis device with a 4- | |
| HYC | (12) | HYNIX | 08+ | The device includes an 8x digital interpolation filter for PCM signals. | |
| HYD | (3) | Pixelworks | BGA- | 03+ | READY: is the acknowledgment from the addressed memory or I/O device that |
| HYE | (10) | QI | The AHC244 devices are organized as two 4-bit buffers/line drivers with | ||
| HYF | (9) | SIEMENS | SOJ-28 | The device incorporates auto-calibration and built-in self-test (BIST) ro | |
| HYG | (4) | HYNIX | 2007 | efficiency of the HPR1XX Series means the series is able to offer greate | |
| HYI | (7) | HYNIX | 2006 | RESET: A RESET input pin is provided to ease some system applications. Wh | |
| HYL | (11) | HYUNDAI | DIP | 07+ | A Command User Interface (CUI) serves as the interface between the syst |
| HYM | (85) | To enhance device driver efficiency and reduce interrupt latency, intern | |||
| HYN | (5) | The TC58DxM72x1xxxx is a 128-Mbit (138,412,032) bit NAND Electrica | |||
| HYP | (9) | CISCO SYSTEMS | BGA | Beneficial comments (recommendations, additions, deletions) and any perti | |
| HYQ | (1) | OUTPUT VOLTAGE LIMITERS Default Limit Voltage Minimum Limiter Separati | |||
| HYR | (4) | ALEPH | N/A | 01+ | VFB (Pin 7): Error Amplifier Inverting Input. The noninvert- ing input of |
| HYS | (82) | Infineon | Note 3: Absolute Maximum continuous ratings are those values beyond which | ||
| HYU | (30) | HY | BGA | 00+ | |
| HYV | (1) | BGA | N/A | The Fairchild Semiconductor HYVF643AL is a high efficiency driver ampli | |
| HYW | (1) | ZILOG | 2007 | The Bay Linear B3800 series is monolithic control circuit containing th | |
| HYZ | (6) | sie | sie | dc94+ | Note 4: The maximum allowable power dissipation is a function of the maxi |
| HZ- | (1) | (i.e. Ground) output voltage. In contrast, an unbuffered inverter such a | |||
| HZ0 | (17) | STEW | 1707 | Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed- | |
| HZ1 | (89) | Hitachi | † Stresses beyond those listed under absolute maximum ratings may c | ||
| HZ2 | (56) | Renesas | Operating voltage range: 4.5V to 5.5V CMOS technology for | ||
| HZ3 | (48) | Hitachi | The UC62LV2008 is a high performance, very low power CMOS Static | ||
| HZ4 | (29) | Hitachi | pre-filter, followed by an eighth order switched-capacitor bandpass fil | ||
| HZ5 | (29) | SOD-323 | 03+ | The SSTV16857 is a 14-bit registered buffer designed for 2.3V-2.7V | |
| HZ6 | (30) | REN | DO-35 | 5 | where TJ(max) is the maximum allowable junction tempera- ture of the die |
| HZ7 | (27) | Renesas | 10-Year Minimum Data Retention in the Absence of External Power Data is | ||
| HZ8 | (2) | Hitachi | The CY7C107B and CY7C1007B are high-performance CMOS static RAMs organi | ||
| HZ9 | (29) | Hitachi | In addition, each material offers a specific reliability rating. It is | ||
| HZB | (6) | HITACHI | NOTES: 1. Dimensions are in inches. Metric equivalents are given | ||
| HZC | (3) | Hitachi | The HYM71V653201 H-Series are Dual In-line Memory Modules suitable for eas | ||
| HZD | (4) | HUIZHONG | stock | The BH616UV8010 is a high performance, ultra low power CMOS Static Random | |
| HZF | (32) | HITACHI | 04+ | These counters are fully programmable; that is, they can be preset to any | |
| HZH | (1) | N\A | QFP | 95+ | The inductor L and Schottky barrier diode SBD should be connected close t |
| HZK | (103) | N/A | N/A | Maximum ratings are those values beyond which device damage can occ | |
| HZL | (1) | The UCC3941 family of low input voltage single inductor boost converters | |||
| HZM | (274) | NEC | SOT23 | 07+ | Permanent device damage may occur if Absolute Maximum Ratings are exceede |
| HZN | (2) | JAT | 05+ | The M divider divides the VCSO output frequency, feeding the result int | |
| HZP | (1) | DIP | Notes: (1) As measured in ANADIGICS test fixture with single-ended RF in | ||
| HZS | (164) | RENESAS /日立 | In an M68300 family component, the major functions and glue logic are all | ||
| HZT | (5) | HIT | 03 | 8. The HZT33-02TA and HZT33-02TAA have RSET/RSET input pins. An i | |
| HZU | (197) | RENESAS | 0805_ | 2004 | odcOutput Duty Cycle4753 All parameters measured at fMAX unless noted o |
| HZV | (3) | HITACHI | SOD-323 | 06+ | This material and the information herein is the property ofFuji Electric |
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