| Mfg | pack | D/C | Descrpion | ||
| M.S | (1) | 08+ | Hynix HYMD564726(L)8-K/H/L series is unbuffered 184-pin double data rate | ||
| M/2 | (1) | ||||
| M/I | (1) | ||||
| M/L | (1) | ||||
| M/V | (2) | ||||
| M-0 | (1) | The HMS30C7202 is a highly integrated low power microprocessor for persona | |||
| M00 | (21) | MOT | TSSOP20 | 00+ | Clocks in the ispLSI 2064 and 2064A devices are se- lected using the de |
| M01 | (30) | AD | 07+ | Single supply: 1.8 V to 5.5 V Two-wire serial interface (I2CTM serial bus | |
| M02 | (40) | SUPPLY VOLTAGE, +VS to -VS SUPPLY VOLTAGE, +VB SUPPLY VOLTAGE, -VB OUTP | |||
| M03 | (23) | ACTARIS | 04+ | TQFP-64P | VB: Supplies power to all circuits of the regulator except the collector |
| M04 | (20) | 台产 /红 | SMD1206 | eight CAT24FC02 may be individually addressed by the system. The last b | |
| M05 | (16) | NEC | 06+ | 1123 | Schematic capture, automatic place and route Logic and timing simulatio |
| M06 | (11) | N/A | 0603L | Reset Input: Schmitt trigger reset input. If 0, sets all control registers | |
| M07 | (6) | SOP8S | 2007+ | 4ž_ÞÐW FUNC [1]‘ôDÈ Aœ Ah FUNC | |
| M08 | (16) | OKI | QFP100 | rising edge of the CLK pin. On the falling edge of the 8th clock the da | |
| M09 | (10) | MOTOROLA | NOTES: 1. Inputs are capable of translating the following interface stan | ||
| M0C | (30) | BGA | COMPRESSED GCI MODE In GCI compressed mode, one GCI frame consists | ||
| M0G | (1) | Notes: 1. Measurements at 900MHz were made using an ICM fixture with a do | |||
| M0K | (1) | A 2.85V output version is suitable for SCSI-2 active termination. Unlik | |||
| M0L | (3) | Analog output. The output signal has a maximum amplitude of 2.0 VPP above | |||
| M0R | (2) | The M0R1WB0001/20/40 is a 1K/2K/4K Bit SPI Serial CMOS EEPROM internall | |||
| M0S | (10) | Standard Microsystems is a registered trademark of Standard Microsystems | |||
| M1 | (1) | The ADS5542 is a high-performance, 14-bit, 80MSPS analog-to-digital conve | |||
| M-1 | (85) | AT&T | 9612 | TAOperating free-air temperature−40125C NOTE 4: All unused c | |
| M1- | (122) | HAR | DIP | 04+ | REF is 5V tolerant 4 pairs of programmable skew outputs Low skew: 200ps |
| M1( | (1) | The HA-5020 features low differential gain and phase and will drive two d | |||
| M1. | (1) | High-speed consumer electronic ports ESD protection of PC ports, includ | |||
| M10 | (145) | OKI | PLCC68 | 03/+04+ | Drain-to-Source Breakdown Voltage Gate Threshold Voltage Gate-to-Source |
| M11 | (137) | ESMT | 00+ | TSOP40 | The DS1554 also contains its own power-fail circuitry which automatically |
| M12 | (167) | 600 | NULL | 95+ | WRITE PROTECT: When the WP pin is low, program and erase operations to al |
| M13 | (52) | ON | 02+ | 1. Serial control by I2C bus. 2. 5-inputs, 2-outputs. 3. Video and audio | |
| M14 | (104) | QFP160 | 08+ | Advanced 0.5µ E2CMOS process 1000 erase/program cycles guaranteed | |
| M15 | (175) | TI | SOP | n Variable power management n Packaged in 6-lead SOT-23 (ADC081S101 als | |
| M16 | (205) | ALI | (SX)computer IC | 05+ | Sector data protection is afforded by methods that can disable any combin |
| M17 | (18) | AUO | 07+ | Parameter Power Supply, Input/Output Voltage Operating Temperatu | |
| M18 | (50) | IC | SOP | A range of surface mount, chip LEDs with a white diffused lens, available | |
| M19 | (49) | MOTOROLA | ZIP | 00+ | 5% tolerance of output voltage Wide input range Internal thermal overloa |
| M1A | (2) | PT | Description BD52XXG/FVE, BD53XXG/FVE are series of high-accuracy detect | ||
| M1B | (7) | Relay(DZ) | 93+ | 4. Design your application so that the product is used within the ranges | |
| M1C | (5) | The On/Off Control (pin 3) may be used for remote on/off operation. As sho | |||
| M1D | (3) | Figure 1 shows the timing of the encoder data clock (EDC), the e | |||
| M1E | (3) | QFP-44 | |||
| M1F | (31) | Three Phase 16-Bit Center Based PWM Generation Unit with 12.5 ns | |||
| M1G | (1) | TOS | TO-92 | The UCC28510 family also features leading-edge modulation for the PFC sta | |
| M1J | (1) | The clock driver serial protocol accepts byte write, byte read, block wri | |||
| M1K | (1) | codestrip. These detectors are also spaced such that a light period on | |||
| M1M | (74) | ONS | 06+ | SOT323 | (DVDD1.8 = AVDD1.8 = 1.8V, AVCLK = AVDD3.3 = DVDD3.3 = 3.3V, modulator off |
| M1N | (3) | Panasonic | LL-34 | Note: These are stress ratings only. Stresses exceeding the range specifie | |
| M1P | (2) | ||||
| M1S | (5) | The IS41LV32256 is compatible with JEDEC standard SGRAMs. This 8-Mbit E | |||
| M1T | (2) | • Link aggregation and load balancing - Switch dependent & | |||
| M1V | (1) | The OXCF950 is a low cost asynchronous 16-bit PC card (henceforth referr | |||
| M2 | (1) | The ACPF- 7002 is a high rejection full band transmit filter designed fo | |||
| M-2 | (31) | QFP | 98 | AMDs Flash technology combines years of Flash memory manufacturing expe | |
| M2- | (4) | SOP20 | 2005 | This model provides a more precise description of the thermal charac- ter | |
| M2. | (3) | PARAMETER Reference Voltage Section Fb Voltage Fb Voltage Line Regulati | |||
| M20 | (157) | MOT | 99 | SOP-8 | Left channel positive output in BTL mode and SE mode. Supply voltage Lef |
| M21 | (132) | MINDSPEED | BGA | 07+ | Two Channels: Measures Both Remote and Local Temperatures No Calibratio |
| M22 | (95) | ST | DIP24 | 04+ | Power Diode Module FDF60BA is designed for single phase full wave rectifi |
| M23 | (76) | MOT | TSSOP16 | APPLICATIONS Automotive Applications Automatic Test Equipment Data Acqu | |
| M24 | (741) | STM | In ringing mode (Ring relay in position 2), the only protection device | ||
| M25 | (384) | LASER | 01+ | DIP-8 | The M252501 is designed to convert three lines of input data to a |
| M26 | (13) | 00+ | The Timing and Watchdog Module (TWM) contains a Real- Time timer and a | ||
| M27 | (1581) | ST | 96 | TA = 0C to 70C / -40C to 85C (I), unless otherwise specified 85ns | |
| M28 | (684) | OKI | TSOP-24 | 1997+ | • Wide supply voltage range of 1.2V to 3.6V • Complies with JE |
| M29 | (1471) | ST | DIP/28 | 92+ | 5.2.4 Control of Transceiver Chip The ST20196 runs the firmware controll |
| M2A | (2) | MOT | TO-252 | The internal microprocessor is an enhanced version of the industry-standa | |
| M2B | (3) | ||||
| M2C | (3) | MICREL | PDIP | 06+ | Analog signals at the input (Vx) are firstly bandlimited to 508 kHz by an |
| M2D | (1) | NS | 07+ | 5V TOLERANT INPUTS HIGH SPEED : tPD = 5.0ns (MAX.) at VCC = 3V POWER | |
| M2E | (1) | HIT | BGA | 0149+ | If two or more UC1524 regulators are to operated synchro- nously, all o |
| M2F | (7) | SHINDENGEN | Reference voltage input. This pin should be driven from an accurate, st | ||
| M2G | (1) | TEMIC | MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to th | ||
| M2I | (1) | - 10, 8, 6 or 4bit up/down counting - Parallel load - 8 different inp | |||
| M2K | (3) | 18-36 Vdc and 36-75 Vdc Input Models Continuous Short Circuit Protectio | |||
| M2L | (2) | E1, T1, AND SUBRATE OPERATION COMPLIES WITH G.SHDSL AND HDSL2 16-BIT, DE | |||
| M2M | (6) | Stresses beyond those listed under absolute maximum ratings may cause pe | |||
| M2N | (1) | Fast, High-Density 1.8 V FPGA Family - Densities from 58 k to 4 M syste | |||
| M2P | (3) | SHARP | 06+ | The DS1668/DS1669 Dallastats are controlled through a contact closure i | |
| M2S | (7) | MIT | TSOP | 02+ | I2C or MPU control interface selection. If MODE is logic high, the chip i |
| M2T | (3) | The standby function is provided by the STBY* control, pin 2. If pin 2 | |||
| M2V | (72) | PLCC62 | Should the Buyer purchase or use a Samsung product for any such unintende | ||
| M2X | (4) | Level-triggered control input (active LOW). This is the frame synchroniza | |||
| M2Y | (1) | SENTAOL | SOP16S | 2007+ | The gain of each amplifier channel is controlled by the DC voltage level |
| M2Z | (1) | 99 | The IDTQS74FCT2827T is a 10-bit buffer with 3-state outputs and a | ||
| M-3 | (4) | QFP | 99 | The 16-bit digital output is multiplexed into an 8-bit out- put word that | |
| M3- | (42) | HARRIS | DIP | The Evaluation System is the most convenient environment for the develo | |
| M3. | (1) | MITSUBISHI | BGA | 07+/08+ | The I2S-compatible audio data interface allows the device to connect with |
| M30 | (1590) | MIT | SOP8 | Jitter-free operation is maintained over the full temperature and VCC ran | |
| M31 | (78) | Maximum ratings are those values beyond which device damage can occur. M | |||
| M32 | (144) | EPSON | 98+ | SSOP-L70P | Differential output for the synthesizer. LVPECL interface levels. Active |
| M33 | (79) | ALI | 03+ | QFP | • DLL aligns DQ and DQS transitions with CK transitions |
| M34 | (1271) | MITSUBISHI | SOP | 1995 | FEATURES Precision 1.200 V Voltage Reference Ultracompact 3 mm 3 mm SOT- |
| M35 | (354) | MITSUBISHI | DIP | 1998 | Note: 5. This input level is calculated from the input power delivered t |
| M36 | (198) | ST | 07+ | The circuit is centered around the IR51H420 Ballast Driver Hybrid | |
| M37 | (2260) | MITSUBISHI | DIP64 | 97+ | Four package terminals are used as inputs to set the default value for fo |
| M38 | (1432) | MIT | 99+ | QFP/64 | 1. Pappenfus, Brueue & Schoenike, Single-Sideband Prin- ciple |
| M39 | (797) | kemet | kemet | dc92+ | Fault protection is provided by internal foldback current limiting, an ou |
| M3A | (5) | NEC's NE6510179A is a GaAs HJ-FET designed for medium power mobile comm | |||
| M3C | (2) | M3C51E050M DUAL CORE DSP FEATURES 320 MIPS ADSP-219x DSP in a 144-Lead L | |||
| M3D | (6) | RICOH | SOT-23 | Addresses, data I/Os, chip enables (E1, E2, E3), address burst control i | |
| M3E | (4) | SHMC | QFP | Chip Enable input. Used for device selection. A Low level on both CE and | |
| M3F | (2) | This device has built-in protection against high static voltages or elec | |||
| M3G | (1) | TO220-3 | 00+ | TOSHIBA | The XC73144 features a power-management scheme which permits non-speed- |
| M3H | (6) | Note 8: Skew is defined as the absolute value of the difference between t | |||
| M3L | (4) | EQUATOR | BGA | As your new, mixed-logic (5V and 3.3V) design evolves and your cur | |
| M3P | (1) | MOT | SOP/8 | 95+ | DESCRIPTION The STV5348 decoder is a computer-controlled teletext devic |
| M3Q | (1) | 01+ | multiplexer. When the ENABLE INPUT is held "High", all output | ||
| M3R | (2) | The M3R14TAJ50 has CMOS standby mode which re- duces the maximum VCC curr | |||
| M3S | (4) | MEISEI | A programmable signal-detect level set pin (SDLVL) sets the thres | ||
| M3T | (1) | The Hynix HYM7V631601B F-Series are 16Mx64bits Synchronous DRAM Modules. | |||
| M3X | (4) | SB: The voltage on SB sets the output current level at which standby mod | |||
| M4 | (1) | Voltage-feed-forward ramp modulation, current mode control, and internal | |||
| M-4 | (10) | LUCENT | O7+ | The INT5130 implements Intellons patented PowerPacket OFDM technology and | |
| M4- | (86) | LATTICE | QFP | s 16/32-bit ARM7TDMI-S microcontroller in a LQFP144 and TFBGA144 package. | |
| M4( | (1) | As an alternative, consider an AC-coupled approach to reduce the power di | |||
| M4. | (1) | ||||
| M40 | (217) | EPSON | TSOP48 | 2007+ | execute the command. The contents of the register serve as inputs to the |
| M41 | (209) | ST | 07+ | • High-performance, low-cost solution to switch between vid | |
| M42 | (31) | AMD | BGA | 03+ | Power Control (SO-14 only) Maximum Logic 0 Minimum Logic 1 Logic Inpu |
| M43 | (111) | TI | 07+ | causes the DQ pins to tri-state. Crystal Connection, drives crystal on st | |
| M44 | (67) | MITSUBISHI | DIP | 00+ | |
| M45 | (90) | STMICRO | D/S | 07/08+ | The audio DAC uses Micronas proprietary multibit sigma-delta technique. |
| M46 | (50) | SOP | 03/+04+ | provided. TI bases its knowledge and belief on information provided by th | |
| M47 | (42) | T | SOP | 03/+04+ | Embedded MPC8xx core up to 133 MHz Maximum frequency operation of the e |
| M48 | (598) | HIGH SPEED: fMAX = 180MHz (TYP.) at VCC = 5V tCK-Q = 3.9ns (TYP.) at V | |||
| M49 | (34) | AMD | BGA | 02+ | C Thirty 32K word (64K byte) Sectors with Individual Write Lockout |
| M4A | (341) | 3.0 Device Specifications 3.1 DC Electrical Specifications 5V 5% 3.1. | |||
| M4C | (2) | MITSUBISHI | 2007 | Note: Stresses greater than those listed under MAXIMUM RATINGS may cause | |
| M4E | (1) | This IC functions in a variety of CPU systems and other logic systems to | |||
| M4F | (1) | The HC164 and HCT164 are 8-bit serial-in parallel-out shift registers w | |||
| M4G | (1) | • Dual Logic On/Off Control • Over-Temperature Shutdown R | |||
| M4H | (1) | <1mV/mA (see Figure 1) Low Crosstalk Between Switches Pin Compatible | |||
| M4L | (86) | ST | 06+ | • FCT-C speed at 5.5 ns (FCT16841T Coml) • Power-off disable | |
| M4N | (4) | N/A | DIP | 07+ | NOTE: 1. AVSS (reference ground) must be connected to 0V (ground). AVCC |
| M4S | (1) | SEMTECH | 2007 | • Single 3.3V0.3V power supply • All device pins are LVTTL co | |
| M4T | (18) | AISIN | 04+ | 1.2MHz Switching Frequency Low VCESAT Switches: 330mV at 1.3A High Outpu | |
| M4V | (1) | Testing of the switching parameters is modeled after testing methods spec | |||
| M4X | (2) | 97 | The DC/DC power module shall be installed in an end-use equipment and con | ||
| M4Z | (6) | sgs | sgs | dc0641 | External Memory Interface The SiW3500 does not require additional memory |
| M-5 | (18) | TOKIN | SOP | 05+ | Specifications are production tested at TA =25C. Specifications over the - |
| M5- | (80) | LATTICE | QFP-100 | 06 | The transmission cycle begins when the chip is selected with the CSN inpu |
| M50 | (1829) | CRYDOM | MODULE | N/A | When the device is disabled, via the ENABLE input, CT is discharg |
| M51 | (1785) | MIT | QFP | • Three-phase, full-wave, linear BLDC motor driver • Commuta | |
| M52 | (1101) | MITSUBISHI | 2007 | Note 3. Operation at high input voltages is dependent upon load current. | |
| M53 | (331) | MIT | DIP | The BCT543 octal transceiver contains two sets of D-type latches for te | |
| M54 | (719) | MIT | QFP | 01+ | 32-bit non-multiplexed address and data bus High-speed interruptible DMA |
| M55 | (308) | 98+ | SOP-8 | 1. Typical characteristics are at TA = 25oC.2. Fmax = 1/tRC. 3. These | |
| M56 | (247) | MIT | 1: Care should be taken so as to not exceed the thermal dissipation capab | ||
| M57 | (288) | MIT | 03+ | The program cycle has addresses latched on the falling edge of WE or CE | |
| M58 | (385) | ST | 07+ | • Clock frequency: 166, 143, 100 MHz • Fully synchronous; a | |
| M59 | (135) | ST | . | The MAX1533/MAX1537 include on-board power-up sequencing, a power-good (P | |
| M5A | (13) | MITSUBISHI | 95 | NOTE: The inhibit function of the zero or carry outputs does not end wh | |
| M5B | (1) | This low skew clock driver offers 1:10 fan-out. The large fan out from a | |||
| M5C | (3) | TEMC | 1598 | 98+ | Notes: 1. CL = Load capacitance: includes jig and probe capacitance. |
| M5D | (1) | MITSUBISHI | N/A | N/A | ENCV Variable clock enable (TTL compatible input) - This input directly c |
| M5E | (2) | MOS | SOP14 | 03+/04 | A single-ended clock input is used to control all internal con- version |
| M5F | (8) | 三凌 | TO-220 | The Timing and Watchdog Module (TWM) contains a Real- Time timer and a | |
| M5G | (2) | MITSUBIS | DIP | Fifth Generation HEXFETs from International Rectifier utilize advanced p | |
| M5H | (2) | Reliable CMOS with MNOS cell technology 105 erase/write cycles (in page m | |||
| M5I | (6) | 07+ | Technology: high performance SiGe Bandwidth: 9 GHz Input noise current | ||
| M5K | (41) | MIT | DIP16 | 2007+ | This device is intended to be used only in a half-bridge which drives in |
| M5L | (268) | N/A | N/A | N/A | The Z86319 is a member of the Z8 family of CMOS micro- controllers arch |
| M5M | (2884) | The CPU provides fast instruction (up to 10 MHz clock speed) execution | |||
| M5N | (7) | MITSUBISHI | DIP | 2001 | SOP 2.5.9Process critical and key parameters 0076604 Process Qualificatio |
| M5P | (2) | ST | 03 | ACK Polling Once a stop condition is issued to indicate the end of the | |
| M5R | (2) | Fault Flag FLG is an N-channel, open-drain MOSFET output. The fault-flag | |||
| M5S | (2) | The processor communicates with these modules over the on-chip intermodul | |||
| M5T | (7) | Drain-to-Source Breakdown Voltage Gate Threshold Voltage# ➃ Gate- | |||
| M5W | (2) | MIT | The HT99C410 is an 8-bit high performance RISC-like microcontroller whi | ||
| M5X | (1) | ||||
| M5Z | (2) | QFP | MIT | 98+ | The amplitude demodulator of the transceiver detects the AM signal genera |
| M-6 | (4) | TOKIN | To lower power dissipation in the regulator, a dropping resistor can be | ||
| M6- | (19) | HAR | CDDIP20 | The IA186ES/188ES microcontrollers are an upgrade for the 80C186/188 micr | |
| M60 | (209) | 三凌 | 711 | Data Registers (DR) The potentiometer has four 10-bit non-volatile Data | |
| M61 | (199) | MIT | SOP | 0105+ | As judged from expression (1), the turn-off time toff is affected by coll |
| M62 | (583) | RENESAS | SOP-8P | 04+ | Stresses beyond those listed under absolute maximum ratings may cause per |
| M63 | (278) | MIT | QFP | 2000 | Device Description The following information is provided: part number, |
| M64 | (180) | N/A | OKI | 04+ | process, the THAT 1510 and 1512 improve on existing integrated microphon |
| M65 | (400) | MIT | 96+ | QFP/100 | The ASH transceivers unique feature set is made possible by its system ar |
| M66 | (550) | MITSUBISHI | 98+00+ | QFP | HEXFET technology is the key to International Rectifiers advanced line |
| M67 | (261) | MITSUBISHI | N/A | 1999 | The PIC12C67X devices have special features to reduce external componen |
| M68 | (509) | 1850 | The memory, internal to the device, is organized as 32 pages of eight byte | ||
| M69 | (106) | ＳＴ | over 2000 volts can accumulate on the human body or asso- ciated test eq | ||
| M6A | (3) | 97 | When MULTIPLEX is low, this is DB0. When MULTIPLEX is high this is the | ||
| M6B | (1) | ST | SOP | 04+ | Programmable option for internal pull-up resistor on each input pi |
| M6C | (1) | 03 | Address Latch Enable output for latching the low byte of the address dur | ||
| M6E | (1) | 99+ | |||
| M6L | (1) | MIT | 0303+ | 288 | The LMH6560 is a high speed, closed-loop buffer designed for application |
| M6M | (126) | MITSUBESHI | Maximum Repetitive Reverse Voltage Average Rectified Forward Current, & | ||
| M6O | (1) | No license is granted, implied or otherwise, under any patent or patent ri | |||
| M6P | (1) | WIZNET | TQFP | 07+ | +53 ppm -30 ppm/C from + 25C to - 55C, 60 ppm below 10 pF. X7R & Z5 |
| M6X | (3) | − Active Mode: 200 µA at 1 MHz, 2.2 V − Standby Mode: 0 | |||
| M7 | (1) | The Firmware Hub (FWH) is a flash memory device for BIOS storage, based | |||
| M-7 | (3) | TOKIN | WFP14W | 2007+ | 2.88MB Super I/O Floppy Disk Controller − Relocatable to 480 Diffe |
| M7- | (10) | ATI | BGA | 02/03+ | • Plastic package has Underwriters Laboratory Flammability |
| M7( | (1) | All four clock outputs of the FS6011 may be tristated to facilitate cir | |||
| M70 | (50) | HP | SMD5 | 06+ | ADC Output (LSB) ADC Output ADC Output ADC Output ADC Output ADC Out |
| M71 | (22) | Information furnished is believed to be accurate and reliable. However, S | |||
| M72 | (30) | OKI | QFP | 97 | 3-phase rectifier bridge 3-phase short circuit rated, ultrafast IGBT in |
| M73 | (17) | OKI | 98 | The FSK modulator/demodulator produces a frequency modulated analog outpu | |
| M74 | (2087) | 97 | DIP | Description MULT0 (Pin 43) Value. This bit is Read Only. Reserved Contr | |
| M75 | (111) | OKI | QFP80 | Caution: Stresses beyond those listed under Absolute Maximum Ratings may | |
| M76 | (58) | OKI | QFP | 05+ | Note 17: This describes the difference between the delay of the LOW-to-HIG |
| M77 | (41) | MOTOROLA | 15 | The bq2083−V1P2 SBS-compliant gas gauge IC for battery pack or in | |
| M78 | (25) | MITSUBISHI | DIP-40 | 00+ | Addressing The UD61256 is a dynamic Write- Read-memory with random acc |
| M79 | (28) | OKI | 02+ | QFP/100 | |
| M7A | (1) | OSC1, OSC2 are connected to an RC network or Crystal (determined b | |||
| M7B | (5) | SHARP | QFP | 07+ | Use the typical performance graphs as a guide for expected variat |
| M7C | (3) | ATI | 05+ | The EM78M612 is a series of Universal Serial Bus 8-bit RISC Multi-Time Pro | |
| M7E | (25) | BGA | 05+ | ||
| M7G | (14) | RENESAS | QFP-44 | 2004 | PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFER |
| M7H | (2) | OKI | 02+ | QFP | The FCT373T and FCT573T consist of eight latches with three-state outpu |
| M7L | (1) | 5.1 In consideration of the materials provided as part of the Voice Codec | |||
| M7N | (1) | N/A | N/A | N/A | FEATURES 225 ps Propagation Delay through the Switch 4.5 Switch Connect |
| M7P | (1) | 1. Special use of 2 coil latching types: 2 ways can be considered if 2 | |||
| M7S | (1) | Areas where care in design must be observed are thermal ground, RF groun | |||
| M7T | (2) | MIYOSHI | PQFP48 | 2007+ | NOTE: The die and wire bonds are exposed on the front side of the |
| M7U | (7) | EPSON | 97+ | QFP | Available in the Texas Instruments NanoStar and NanoFree |
| M7W | (1) | MOSART | TQFP | A read cycle is initiated by the falling edge of CAS or OE, whichever o | |
| M-8 | (23) | TELTONE | DIP18 | 2000 | All thermal impedance data is approximate for static air conditions at 1 |
| M8- | (25) | 02+ | BGA | spikes (see ISO7637 transient compatibility table). Active current limi | |
| M80 | (212) | 90 | Notes: 1. Test conditions assume signal transition times of 2 ns or less | ||
| M81 | (55) | Serial Data (SDA). SDA is a bidirectional pin used to transfer data into | |||
| M82 | (151) | MICROCHIP | SOP8 | N/A | The MAX8546 has a wide 2.7V to 28V input range, and does not need any addi |
| M83 | (366) | dale | dale | dc81+ | This document contains detailed information on power considerations, DC/A |
| M84 | (18) | The standard PC chipset functions (DMA, interrupt controller, timers, p | |||
| M85 | (58) | GLENAIR | SOP | 06+ | FLASH MODE The Flash logic pin (Flash) controls the internal FET con- n |
| M86 | (10) | PANASONIC | The M860BM system integration module (SIM49) handles a wide array of func | ||
| M87 | (44) | NS | DIP | 06+ | The interrupt controller lets the DSP respond to 13 interrupts with mini |
| M88 | (62) | MIT | STK | 2004+ | FEATURES lOptions :- 10mm lead spread - add G after part no. &n |
| M89 | (25) | C&K | DIP64 | 07+ | PMD assumes no liability for applications assistance or customer product |
| M8A | (2) | 96 | The IDT70V9279/69 is a high-speed 32/16K x 16 bit synchronous Dua | ||
| M8D | (1) | JAT | 04+ | The following discussion refers to the schematic in figure 2 belo | |
| M8G | (2) | TOSHIBA | TO-220 | 00+ | Power Thyristor/Diode Module PK40FG series are designed for various recti |
| M8H | (1) | M/A-COM | Disclaimer: The contents of this document are subject to change without n | ||
| M8J | (2) | TOSHIBA | TO-220 | 06+ | Asynchronous mode. XASY = 0 Asynchronous transmission, XASY = 1 Synchrono |
| M8M | (1) | The 79L00A Series of three terminal negative voltage regulators is | |||
| M8R | (1) | • 3V to 40V Input Voltage Operation • Internal 1.6A Peak Curr | |||
| M8S | (2) | N/A | SMI | 04+ | Low voltage noise density of 2.1nV/Hz and -88dBc spurious-free dynamic ra |
| M8T | (4) | S | DIP16 | 2007+ | Unless otherwise specified, the typical specification value applies over |
| M8V | (1) | N/A | The product term allocator is a dynamic, configurable resource that shift | ||
| M8X | (1) | TRIBENTT | QFP | 07+/08+ | OUTPUT DRIVE ENABLE (ODE) The ODE pin is the master output three-s |
| M-9 | (33) | ALPHA | DIP | DIP | Notes: 1. PD indicates an internal pull-down and PU indicates an i |
| M9- | (25) | 电阻排 | with Intels Pentium II Processor. The PT6700 includes a di | ||
| M90 | (18) | MITSUBISHI | QFP | 07+ | - Wide supply Voltage range: 2.0V to 36V Single or dual s |
| M91 | (44) | MIT | 97 | The parameter tOH indicates the system compatibility of this device when | |
| M92 | (39) | TELTONE | DIP-8 | 00+ | |
| M93 | (334) | ST | 05 | The read transaction shows a request packet at clock edge T0 containing | |
| M94 | (27) | MIC | 08+ | In addition, the temperature compensation of the Hall IC can be fit to | |
| M95 | (405) | ST | SOP8 | 0626+PB-FREE | The HYM72V64C756K8M H-Series are gold plated socket type Dual In-line Memo |
| M96 | (46) | N/A | ATMEL | 04+ | The conversion process and data acquisition are controlled using CS and |
| M97 | (32) | MOTOROLA | 04+ | The COP424C COP425C COP426C COP444C and COP445C fully static Single-Chip | |
| M98 | (96) | N/A | OKI | 04+ | Low profile (5.0mm max. height), high current (6.8A, 1uH) SMD type. Unshi |
| M99 | (25) | MOTOROLA | N/A | 00+ | Maximum ratings are those values beyond which device damage can occur. M |
| M9C | (1) | The added enhancement known as the Glitch Eater is used to minimize effec | |||
| M9Q | (1) | LT | 04+ | G5131-25T11U G5131-26T11U G5131-27T11U G5131-28T11U G5131-29T11U G513 | |
| M9R | (2) | MOT | DIP | 07+ | This pin is the positive supply pin, and should always be the most posi |
| M9S | (5) | MOT | 04+ | MLP-M48P | The MAX1124 is a monolithic 10-bit, 250Msps analog- to-digital converter |
| M-A | (6) | LUCENT | QFP | 1997 | Note 5 The shortest allowable SK clock period e 1 fSK (as shown under the |
| MA- | (87) | SIRENZA | 厚膜50脚 | 94+ | The test set described in this paper allows complete quanti- tative char |
| MA0 | (123) | AT&T | 07+ | The FDC05 (W) series required a minimum 10% loading on the output t | |
| MA1 | (707) | 2:1 Mux inputs for YPbPr and RGB inputs Supports D1, D2, D3 and D4 vid | |||
| MA2 | (522) | NSC | 97 | Brooktree reserves the right to make changes to its products or speci@ | |
| MA3 | (783) | Panasonic | 12000 | Forward voltage(typ.) IF=20mA Forward voltage(max.) IF=20 | |
| MA4 | (507) | M/A-COM | The accelerated program (ACC) feature allows the system to program the d | ||
| MA5 | (211) | seiko | seiko | dc95 | (1) Package drawings, standard packing quantities, thermal data, symboliz |
| MA6 | (152) | TESLA | DIP | ESD damage can range from subtle performance degradation to complete dev | |
| MA7 | (380) | PANASONIC 94+ | SOT-323 | 06+ | In addition, the temperature compensation of the Hall IC can be fit to |
| MA8 | (463) | PAN | 04+ | To program a Leading Edge Blanking period, connect a capacitor, C, to C | |
| MA9 | (18) | 9 | 97+ | NON-HERMETIC LOW COST CERAMIC 70mil PACKAGE +21.5dBm TYPICAL OUTPUT POWE | |
| MAA | (269) | M/A-COM | Maximum Recurrent Peak Reverse Voltage Maximum RMS Voltage Maximum DC | ||
| MAB | (297) | M/A-COM | controller/timers, a message unit with an Intelligent Input/Output (I2O) | ||
| MAC | (1154) | ON | 04+ | to 30 Mbps Bus-Pin ESD Protection Exceeds 12 kV HBM Compatible With ANS | |
| MAD | (44) | MOT | DIP | Maximum ratings are those values beyond which device damage can occur. Ma | |
| MAE | (1) | N/A | N/A | N/A | To reset the VTRIP voltage, apply a voltage between 2.7 and 5.5V to the |
| MAF | (75) | M/A-COM | Pulse-testing techniques are used to maintain the junction temperature as | ||
| MAG | (32) | SOP | The CDCLVP110 clock driver distributes one differential clock pair of e | ||
| MAH | (16) | QFP | -12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# RESVD PRSNT2# GND | ||
| MAI | (9) | N/A | N/A | N/A | The product information and the selection guides facilitate selection of |
| MAJ | (2) | 1 | electrical characteristics over recommended operating conditions, AVDD = D | ||
| MAK | (1) | N/A | NSC | 04+ | All protective features of thermal shutdown, current limiting, and safe-a |
| MAL | (175) | N/A | 05+ | Fully compliant with the Universal Serial Bus Specification, version 1.1 | |
| MAM | (36) | MAXIM | 07+ | Advanced circuit design achieves 85 ns settling times with very low glit | |
| MAN | (395) | FAIRCHILD | 05/06+ | The second generation CoolSET™-F2 provides several special enhance | |
| MAO | (8) | N/A | 2001 | SSOP | This chip, when properly assembled, displays characteristics similar to T |
| MAP | (123) | 2008 | HyperPHY channels can be used as the serial backplane interface b | ||
| MAR | (97) | 3COM | BQFP100 | /EOP /End of Process (Input, active Low). To terminate a DMA transfer, th | |
| MAS | (421) | MICRON | QFP | 02+ | |
| MAT | (142) | NRS | 03+ | During packet reception the serial data bits are split into 2-, 4-, or 8- | |
| MAU | (3) | HIT | QFP | 05+ | The PWM signal is the control input for the driver. The PWM signal can en |
| MAV | (20) | DIP-4 | Total Gate Charge (turn-on) Gate-to-Emitter Charge (turn-on) Gate-to-C | ||
| MAW | (9) | 07+ | • Fault Protected 16-Channel 12-Bit A/D Converter with Sampl | ||
| MAX | (40546) | MAX | SOP | • JEDEC registered 1N5985 to 1N6031 • Similar to operating | |
| MAY | (33) | HAR | DIP | Notes: 1Stresses above those listed under Absolute Maximum Ratings may c | |
| MAZ | (529) | Panasonic | 2008 | prevent output pulses when power is turned on. An unused RESET input sh | |
| M-B | (2) | AGERE | 02+03+ | (8) Typical value for minimum intermessage gap time. Under software &nbs | |
| MB- | (15) | 9706 | System Characteristics The following spec table entries are guaranteed by | ||
| MB. | (5) | N/A | The Allegro ACS750 family of current sensors provides economical and preci | ||
| MB0 | (17) | FUJ | TSSOP-20 | 02+ | Two external precision resistors (RUP and RDN ) per VCCIO bank are used |
| MB1 | (736) | N/A | N/A | N/A | The second is the programmable 16- or 32-bit-wide SDRAM interface that a |
| MB2 | (295) | FUJITSU | 2007 | The XC95144 is a high-performance CPLD providing advanced in-system pro | |
| MB3 | (792) | FUJ | 9511 | constructed in eight-pin, hermetic, dual-in-line, ceramic packages. T | |
| MB4 | (689) | 94 | SOP | The CY7C235A replaces bipolar devices pin for pin and offers the advantag | |
| MB5 | (188) | 97 | The EB-2100x is an evaluation amplifier that showcases Apogees all-digita | ||
| MB6 | (1124) | FUJ | QFP100 | s Intended for Radio Frequency (RF) front end applications in the GHz ran | |
| MB7 | (499) | FUJ | DIP | 04+ | Sample tested during initial release and after any redesign or pro |
| MB8 | (3937) | FUJITSU | SOJ | 99+ | To protect against load faults, the PT4470/80 series of DC/DC converters |
| MB9 | (771) | FUJ | SOP/28 | 99+ | The external resistors allow the user to accurately and independently se |
| MBA | (128) | vishay-gro | n/a | The accelerated program (ACC) feature allows the system to program the d | |
| MBB | (315) | HITACHI | SOP | 2. Low capacitance between output terminals ensure high response speed: | |
| MBC | (362) | The MBCG31423-2517APFV-G/MBCG31423-2517APFV-GE require 7.5V to 12V dual s | |||
| MBD | (28) | ON | 07+ | SNR = 90 dB in 150 kHz bandwidth (to Nyquist @ 61.44 MSPS) Worst | |
| MBE | (16) | DIP8 | 07+ | SPI Serial Memory The memory portion of the device is a CMOS Serial EEP | |
| MBF | (27) | HITACHI | 100A600V | With the circuit modification shown in Figure 2, the trailing black level | |
| MBG | (24) | FUJITSU | QFP | 00+ | The MC74AC646/74ACT646 consist of registered bus transceiver circ |
| MBH | (3) | and Chip Erase, Erase Suspend and Resume are written to the device in c | |||
| MBI | (33) | SSOP | Designers are strongly encouraged to provide three kinds of power pairs f | ||
| MBK | (9) | HIT | 04+ | Maximum ratings are those values beyond which device damage can occ | |
| MBL | (177) | FUJ | PLCC44 | 03/+04+ | B. Failure Rate Prediction The failure rate will depend on the junction |
| MBM | (1458) | FUJITSU | DIP-28 | 02+ | Output (Pulse Out). Output connected to inductor. Power Supply (5.5V-22V) |
| MBN | (112) | HITACHI | 600A600V | Integrated analog features consist of stereo line inputs with an analog b | |
| MBP | (12) | EPSON/SHARP | SMD | 99 | NOTES: 1. See Test Conditions under TEST CIRCUITS AND WAVEFORMS. 2. Thi |
| MBR | (1626) | MCC | ITO-220AB | 05+ | The standard MBM29DL16XTE/BE offer access times 70 ns, 90 ns and 120 ns, |
| MBS | (39) | TSC | 07+ | Information in this document is provided in connection with Intel product | |
| MBT | (56) | MOT | The IDT5T929 generates a high precision FEC (Forward Error Cor- r | ||
| MBU | (9) | N/A | N/A | N/A | • MPEG 1 system and MPEG2 program/audio/video decoding and s |
| MBV | (1) | ONS | 06+ | SOT23 | The MAX3320 combines a microprocessor (µP) super- visory circuit wi |
| MBW | (8) | N/A | 0805BEAD | VCC = Max. VIN VHC; V IN VLC VCC = Max. VIN = 3.4V(3) VCC = Max. Ou | |
| MBY | (1) | The bq4847 Real-Time Clock Mod- ule is a low-power microprocessor periph | |||
| M-C | (16) | AGERE | LLP-48 | 2001+ | Analog output. The output signal has a maximum amplitude of 2.4 VPP above |
| MC- | (231) | 94+ | Notes: 4. Not 100% tested, guaranteed by design. 5. IVDD c | ||
| MC( | (1) | Motorola（HITACHI） | DIP | Using an n-channel MOSFET in this way simplifies the gate drive for a h | |
| MC. | (2) | MOT | SOP16W | 2007+ | Œ120 V AC resistive load (CHB type) 30 V DC resistive load (C |
| MC/ | (7) | MOT | SOP14S | 2007+ | The MC/3346/DCMC/3346/D have internal termination resistors for use with |
| MC0 | (252) | MOT | Supply of this implementation of Dolby Technology does not convey a licen | ||
| MC1 | (11282) | MOTO | PLCC | PLCC | The output stages switch at half the oscillator frequency, in a push/pull |
| MC2 | (504) | MOT | SOP | If the accumulated value exceeds 1/3200 kWh, an external signal is gene | |
| MC3 | (3814) | MOTOROLA | DIP | Power down control. When PD is LOW, the inputs are disabled and internal | |
| MC4 | (621) | MOT | DIP | These multiplexers are monolithic complementary MOS (CMOS) integrated ci | |
| MC5 | (690) | MOT | FDIP | 8120+ | The A8430 uses a constant-frequency, current-mode control scheme to reg |
| MC6 | (4435) | Freescale | 04+ | The device comes with extensive serial communication capabilities. On-ch | |
| MC7 | (8171) | 00+ | Detailed Description Digitally Controlled Impedance (DCI) Configurable | ||
| MC8 | (443) | N/A | Regular supply bypassing techniques are recommended. A 10µF capaci | ||
| MC9 | (1679) | MOT | QFP | 05+ | 4.4.2 Group B inspection. Group B inspection shall be conducted in |
| MCA | (96) | MINI | 08+ | The TTL parallel I/O interface may be configured as either a FIFO (confi | |
| MCB | (78) | QFP-48P | 6+ | Command Line Editing - The backspace can be used to edit a command line b | |
| MCC | (568) | IXYS | SOP | Features • Three Functions in One Package • Small 16 Pin SO | |
| MCD | (341) | IXYS | 04+ | The ABT162244 contains sixteen non-inverting buffers with 3-STATE output | |
| MCE | (12) | MOT | BGA | The Contek LM79XX series of three-terminal negative regulators ar | |
| MCF | (245) | The 80C186EB Timer Counter Unit (TCU) provides three 16-bit programmable | |||
| MCG | (2) | mhs | mhs | dc95 | The bq2050H Lithium Ion Power Gauge™ IC is intended for battery- p |
| MCH | (838) | ROHM | N/A | Reading from the device is accomplished by taking Chip Enable (CE) and | |
| MCI | (61) | ETRON | 4 | The HYM7V73A801B F-Series are Dual In-line Memory Modules suitable for eas | |
| MCJ | (4) | MOTO | DIP | N/A | • High-Performance Phase-Locked-Loop Clock Distribution for N |
| MCK | (20) | N/A | 1812 | The UT28F256 PROM incorporates special design and layout features which | |
| MCL | (88) | MITSUMI | 08+ | Moreover, the output swing for an ideal RS-232 transceiver would be 5V wi | |
| MCM | (1557) | MOTOROLA | CDIP | CDIP | October 10, 2001: Revised AC timing characteristics in Tables 5, 6 |
| MCN | (6) | MOT | PLCC68 | The SSTs ATA-Disk Module (ADM) contains a controller, embedded firmware, | |
| MCO | (44) | IXYS | SOP | Compared to the AM26LS32 and the AM26LS33, the AM26LS32A and AM26LS33A in | |
| MCP | (2685) | MICROCHIP | 08+PBF | Transmit Clock Tri-statable. This signal is used in synchronous DPSK/QAM | |
| MCQ | (15) | The LPS (link power status) terminal works with the S5_LKON_DS2 terminal | |||
| MCR | (4575) | This family is a 16M bit dynamic RAM organized 1,048,576 x 16-bit configur | |||
| MCS | (139) | TEMIC | O7+ | Any semiconductor devices have inherently a certain rate of failure. You | |
| MCT | (403) | QTC | 04+ | ||
| MCU | (51) | SHAMROCK | The SD1010A implements four advanced display technologies: 1. Advanced mo | ||
| MCV | (39) | MOTOROLA | DIP | 00+ | Regulates voltage over a broad operating current and temperature range S |
| MCW | (7) | MOTO | 9822 | Enhanced Parallel Port (EPP) Compatible - EPP 1.7 and EPP 1.9 (IEEE 1284 | |
| MCX | (24) | MOT | SMD | 07+/08+ | The voltage direction is given • by an arrow which points from th |
| MCY | (11) | FAIRCHILD | DIP | 429 | 2. Regularly and continuously improve the performance of our products, pr |
| MCZ | (101) | The Si9986 is available in both standard and lead (Pb)-free, 8-pin SOIC | |||
| M-D | (11) | LUCENT | 05+ | DESCRIPTION The M74HC4316 is an high speed CMOS QUAD BILATERAL SWITCH | |
| MD- | (91) | M-SYETOM | TSOP | 04+ | The device is available with access times as fast as 70 ns. The devices a |
| MD. | (1) | † The TPS75x01 is programmable using an external resistor divider ( | |||
| MD0 | (107) | ＡＶＸ ＣＯＲＰ | The clear function is synchronous. A low level at the clear (CLR) input s | ||
| MD1 | (154) | CIRRUSLOGIC | 03+ | ||
| MD2 | (568) | INTEL | DIP | 03+ | Lead free product Leadless chip form , no lead damage Lead-free solder j |
| MD3 | (71) | N/A | MOT | 05+ | Cell balancing of each cell is performed via a cell bypass path, which is |
| MD4 | (37) | AIX is a trademark of IBM Corporation. DOS, OS/2, Windows NT, and | |||
| MD5 | (136) | INTEL | DIP | Higher Efficiency and Extends Battery Life − RDS(on) | |
| MD6 | (35) | Sitonix | QFN-48P | 6+ | The Bluetooth controller consists of a number of functional blocks that o |
| MD7 | (54) | *Stresses greater than those listed under "Absolute Maximum Ratings | |||
| MD8 | (680) | T | 08+ | Two-byte instruction can be referenced by using a REF instruction (An exce | |
| MD9 | (36) | MDRAM | PLCC | 1996 | The Am186TMED/EDLV microcontrollers are part of the AMD E86TM family of |
| MDA | (101) | N/A | SOP16S | 93+ | XTAL1 and XTAL2 are the input and output respec- tively of a inverting a |
| MDB | (22) | GENERAL | 4-DIP | As VCE is increased, the power dissipation of the transistor increases un | |
| MDC | (98) | IXYS | SOP | The first stage (the data encoder) implements Manchester (BiPhase) or M | |
| MDD | (238) | 1850 | The MPC7455 is the third implementation of the fourth generation (G4) mi | ||
| MDE | (13) | N/A | N/A | N/A | Information present at any register is transferred to the respect |
| MDF | (62) | SanRex | SOP | Package Description 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead | |
| MDG | (11) | NULL | SOP16 | 03+/04+ | Output clock. This pin is selectable under processor control to be either |
| MDH | (4) | 99 | MINATO | 8 | As shown in the functional block diagram on Page 1, the ADSP- 21262 uses |
| MDI | (31) | N/A | QFP | 06+ | Cin = Required 1000µF electrolytic Cout= Required 330µF elect |
| MDJ | (22) | AD | 06+/07+ | EDO page mode operation permits all 1,024 columns within a selected row | |
| MDK | (18) | The CPU features two sets of functional units. Each set contains four uni | |||
| MDL | (92) | ROHM | 08+ | The oscillator may be replaced by an external clock signal at input X1. | |
| MDM | (40) | JAPAN | DIP8 | CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic ch | |
| MDN | (15) | HITACHI | MODULE | Clocks in the ispLSI 2096VL device are selected using the dedicated clo | |
| MDO | (11) | APPLIED | DIP-2 | 9746+ | The SC5388 is a 2-channel digital preset equalizer utilizing CMOS |
| MDP | (294) | DLE | CAUTION: These devices are sensitive to electrostatic discharge; f | ||
| MDQ | (29) | CATELEC | MODULE | The combination of the MDQ100A12/16 and the MAX3744/ MAX3724 allows for t | |
| MDR | (118) | brentek | brentek | dc02+ | As with all shunt voltage references, an external bias resistor (RBIAS) |
| MDS | (110) | The MDSM-15PE-Z10-VR22C is a high performance, low skew, low jitter cloc | |||
| MDT | (145) | MDT | The product term allocator is a dynamic, configurable resource that shif | ||
| MDU | (7) | DL | 05+ | Notes: 1. Please do not use the soldering iron due to avoid high stress t | |
| MDV | (12) | ST | The UCC3808A family offers a variety of package options, temperature rang | ||
| MDW | (1) | Wait or Transfer Acknowledge. When configured as wait, this signal is as | |||
| MDX | (17) | STRATOS | 07+ | The W83877ATF is an enhanced version from Winbond's most popular I/O chip | |
| MDY | (8) | 0 | 0 | Single chip teletext IC Analog CVBS-input with onchip clamp | |
| MDZ | (5) | The JTAG translator ability to interface JTAG to non-JTAG devices is idea | |||
| M-E | (2) | The device supports low-power standby operation. When RESET is low, the d | |||
| ME- | (10) | ||||
| ME0 | (16) | SANYO | DIP | 90+ | The ME00006-3 center tap Schottky rectifier module series has been optim |
| ME1 | (23) | MATSUKI | 06+ | Notes: 5. Test conditions assume signal transition time of 3 ns or | |
| ME2 | (91) | 微盟 | SOT89 | 08+ | During packet reception the serial data bits are split into 2-, 4-, or 8- |
| ME3 | (40) | Microne ? | 08+? | There are two limitations on the power handling ability of a tran | |
| ME4 | (32) | N/A | The output stage of most power amplifiers has three distinct limitations | ||
| ME5 | (28) | PRX | 100A/400V/DIODE/6U | • Two potentiometers in one package • 2-wire serial interface | |
| ME6 | (49) | MICRONE | 00+ | ||
| ME7 | (32) | MICRO | SOP-8 | 08+ | Eight GLBs, 32 I/O cells, two dedicated inputs and two ORPs are connecte |
| ME8 | (7) | N/A | N/A | N/A | NOTE: Intersil Pb-free plus anneal products employ special Pb-free materia |
| ME9 | (5) | MATSUKI | 06+ | The Texas Instruments ME9926 and ME9926A are TI PanelBus flat pan | |
| MEA | (59) | MAXIM | 06+ | 500 | Any integrated circuit can be damaged by ESD. Burr-Brown recommends that |
| MEB | (21) | PRX | SOP | Supply voltage for LCD driver: 15.0 to 30.0 V Number of LCD driver output | |
| MEC | (45) | JS | 05+ | 5V power supply 5V power supply 5V LNA power supply RF input LNA grou | |
| MED | (17) | MOT | 2008 | The Texas Instruments (TI) translation voltage-clamp (TVC) family | |
| MEE | (8) | IXYS | SOP | When the output load exceeds the current-limit threshold or a short is pr | |
| MEF | (19) | JS | 05+ | DESCRIPTION The M27W201 is a low voltage 2 Mbit EPROM of- fered in the | |
| MEG | (63) | SMD | 03/+04+ | High Efficiency: Up to 95% Very Low Quiescent Current: Only 10µA D | |
| MEH | (1) | 234 | MX | 87+ | The MC623 consists of a positive temperature coefficient (PTC) te |
| MEI | (2) | With every advance of this magnitude, there arise new considerations th | |||
| MEJ | (1) | FAIRCHILD | 04+ | 3P | Command Line - A command line may include a series of commands. The mode |
| MEK | (16) | IXYS | 06+ | IGBT模块 | MECHANICAL INFORMATION Electrical connection to the SOIC is made through |
| MEL | (10) | JAPAN | MSOP | H = Input Voltage High Level, h = Input voltage high one set-up timer pri | |
| MEM | (144) | MOT | CAN | The DPL 4519G processor is designed as part of the Micronas chip set fo | |
| MEN | (1) | ||||
| MEO | (6) | IXYS | SOP | If the command byte is a MUX command byte, any additional data bytes sent | |
| MEP | (12) | N/A | N/A | N/A | Digital Signal Processor (DSP) Block • Playback mode which support |
| MEQ | (1) | 模块 | 03+ | 1. Hitachi neither warrants nor grants licenses of any rights of Hitachis | |
| MER | (17) | JAT | 05+ | HIGH SPEED: tPD =5.8 ns (TYP.) at VCC = 3.3 V COMPATIBLE WITH TTL OUTP | |
| MES | (28) | N/A | DIP | 03+ | The STK11C88-20 requires VCC = 5.0V 5% supply to operate at specified sp |
| MET | (54) | JS | 05+ | NOTES: 1. W is high for read cycle. 2. All timings are refer | |
| MEU | (4) | The averaging ADC integrates over a 40ms period (typ) with excellent nois | |||
| MEV | (1) | VISHAY | 04+ | At both ends of each array and between each resistor segment is a CMOS | |
| MEW | (4) | The VCXH16244 contains sixteen non-inverting buffers with 3-STATE outpu | |||
| MEX | (5) | AMD | SMD | 98 | The MAX4223CMAX4228 current-feedback amplifiers combine ultra-high-speed |
| MEY | (2) | N/A | SMD | 98+ | The page read operation of the device is controlled by CE and OE inputs. |
| M-F | (37) | Hardware data protection measures include a low V CC detector that autom | |||
| MF- | (150) | N/A | 1210 | Tantalum capacitors are recommended on the output bus but only the AVX T | |
| MF0 | (70) | The MBM29DL16XTE/BE are pin and command set compatible with JEDEC standar | |||
| MF1 | (258) | NSC | CDIP | CDIP | Fully Integrated xVCC and xVPP Switching xVPP Programmed Independent of x |
| MF2 | (149) | MJ | TSOP | 96+ | The SN65176B and SN75176B differential bus transceivers are integrated ci |
| MF3 | (45) | JAT | 05+ | Designed for PCN and PCS base station applications with frequencie | |
| MF4 | (30) | MF | 00+ | The C6203 device program memory consists of two blocks, with a 256K-byte | |
| MF5 | (134) | ASJ | Note 5: Set FB to C0.3V, 2.5V and insure that COMP does not phase invert | ||
| MF6 | (61) | epcos | epcos | dc98 | Feedback. Input to the error amplifier. For the Adjustable option, connect |
| MF7 | (7) | 05+ | NOTES: 1. Designators in TYPE: P: power supply and ground, DI: digital in | ||
| MF8 | (6) | Note 1: VINPP is the signal swing before the external capacitor tied to th | |||
| MF9 | (5) | NS | 04+ | The PT7700 is a new series of high- performance, 15 Amp Integrate | |
| MFA | (24) | 2001 | SMD | Specifically designed for Automotive applications, this HEXFET® Powe | |
| MFB | (2) | OKI | 04+ | Triple-channel video amplifier Supply voltage up to 115 V 80V Output | |
| MFC | (89) | QFP44 | The ICS728 VCXO function consists of the external crystal and the integ | ||
| MFD | (2) | MYSOY | QFP | 98+ | The compensation capacitor is connected between pins 1 and 3 and |
| MFE | (73) | N/A | CAN4 | N/A | The Hynix HYM71V32635AT8 Series are Dual In-line Memory Modules sui |
| MFF | (4) | PHI | 92+ | DIP-L40P | Under-Voltage Lockout An Under-Voltage Lock-Out (UVLO) inhibits the ope |
| MFG | (2) | TCS | TSOP28 | 97/98 | C 1.5ns setup to clock and 0.5ns hold on all control, data, and a |
| MFI | (9) | TEW | 5*7 | The A29DL16x family consists of 16 megabit, 3.0 volt-only flash memory de | |
| MFK | (19) | ntk | ntk | dc96 | remains on until either the high-side switch turns on again or the induct |
| MFL | (7) | NTK | The MOC810X and CNY17F-X devices consist of a gallium arsenide LED optica | ||
| MFM | (28) | N/A | 1812 | Output clock data format C Controls the output clock (ODCK) format for ei | |
| MFO | (5) | MOT | 2脚 | 07+/08+ | Available in the Texas Instruments NanoStar™ and NanoFree™ Pa |
| MFP | (35) | TQFP | 2006 | Theseversatile devices are usefulfor driving a wide range of loads incl | |
| MFQ | (12) | MOT | 182 | • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) | |
| MFR | (500) | is available from the falling edge of Serial Clock (C). The difference | |||
| MFS | (61) | bourns | bourns | dc02 | The EM39LV040 provides Chip-Erase feature, which allows the entire memory |
| MFT | (4) | SMD | TDK | 05+ | The NE251 is a dual gate GaAs FET designed to provide flexibility in it |
| MFU | (8) | FAI | TO263 | 04+ | LOW BATTERY THRESHOLD The low battery voltage level is set intern |
| MFW | (2) | Input Capacitance VT+1 VTC1 VT+ C VTC1 &nb | |||
| MFX | (3) | NTK | 02+ | SOP | 1) CPD is defined as the value of the ICs internal equivalent capacitance |
| MFZ | (2) | SOP | SUPPLY VOLTAGE, +VS to CVS BOOST VOLTAGE, +Vb to -Vb OUTPUT CURRENT, wit | ||
| M-G | (7) | TOS | 9814 | FEATURES lOptions :- 10mm lead spread - add G after part no. &n | |
| MG- | (16) | DIP | 02+ | Note 1 Output voltage is set to be 2.5V. Note 2: Line and load regulati | |
| MG/ | (2) | † Stresses beyond those listed under absolute maximum ratings may c | |||
| MG0 | (58) | AVX | 07+ | Silicon implementations are much more cost effective than multi-wire cabl | |
| MG1 | (373) | TOSHIBA | SOP | (IBAT = 375/RPROG). This pin also allows for the charge current to be mon | |
| MG2 | (223) | TOSHIBA | MODULE | N/A | 10 Sec. Pulsed Drain Current, V GS @ -4.5V Continuous Drain Current, V G |
| MG3 | (214) | TOSHIBA | SOP | For each bridge, the user selects an external resistor (RT) and c | |
| MG4 | (114) | 1850 | The CY7C245A is a CMOS electrically programmable read only memory organ | ||
| MG5 | (203) | The circuits and measurements contained in this document are given only i | |||
| MG6 | (51) | N/A | Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock | ||
| MG7 | (170) | 99+ | 42 | Disable mode places the device in a sleep state, where quiescent current | |
| MG8 | (199) | INT | PGA132金面 | 9444+ | The 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O incorporates a n |
| MG9 | (31) | 07+ | The power management control facilities include socket power control, i | ||
| MGA | (305) | AGILENT | SOT23-6 | 2000 | Outputs of the analog signal ground voltage. SGT outputs the analog signa |
| MGB | (27) | ON | 00+ | Note: Stresses greater than those listed under MAXIMUM RATINGS may cause | |
| MGC | (40) | 22 | 93+ | Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS | |
| MGD | (30) | N/A | VICOR | 04+ | All devices are manufactured and tested on a MIL-PRF-38534 certi- fied |
| MGE | (4) | 132 | 03+ | Wide frequency range Ð 0.01 Hz to 300 kHz Wide supply voltage range | |
| MGF | (250) | 三菱 | Frequency Range824849 Gain (Small Signal)30 Gain Variation vs Temp-0.02 | ||
| MGG | (1) | N/A | The internal decoupling capacitors help prevent high frequency i | ||
| MGH | (1) | COEV/TYCO | Passivated guaranteed commutation triacs in a plastic envelope suitable | ||
| MGI | (1) | DIP32 | 96 | On Board 24Mhz Crystal Driver Circuit Can be clocked by an external 24MHz | |
| MGL | (18) | N/A | 1206 | (MGLB3216-030T6/MGLB3216-030T8/MGLB3216-030T9 EV kits, VCC = +2.75V, regis | |
| MGM | (9) | N/A | N/A | N/A | The DM9601 provides USB transceiver which is compliant with USB1.1, 10/10 |
| MGN | (7) | N/A | RELATIVE ACCURACY This term, also known as end point linearity or integr | ||
| MGP | (39) | ON | TO | VIN = 2V VIN = 2V VFBx = 1.4V, VLFB > VBRT C 0.1V VFBx = 1.4V, VLF | |
| MGR | (3) | 100 | 天龙伟业 | 靳先生 | The TLC3541 and TLC3545 are designed to operate with low power consumpt |
| MGS | (71) | ON | SOT-23 | 07+（ROHS） | Two clock sources are used to drive the microcontroller, a main clock dri |
| MGT | (7) | N/A | N/A | N/A | slope going through 0 at the sampling point. This, expanded out gives u |
| MGV | (1) | NOTES: 1. tPLH and tPHL are production tested. All other parameters guar | |||
| MGW | (7) | ON | TO | CAUTION: These devices are sensitive to electrostatic discharge; follow p | |
| MGY | (6) | 03+/04+ | TO3PL | The LM3310 is a step-up DC/DC converter integrated with an Operational | |
| M-H | (1) | QFP | 2001 | Note 2: At elevated temperatures, device power dissipation must be derate | |
| MH- | (3) | MST | 07+ | SOT23 | Transmitter Differential Input. Input accepts AC- or DC-coupled differenti |
| MH0 | (41) | HAR | CAN | The electrical characteristic data has been developed from actual product | |
| MH1 | (113) | WJ | SOP8 | 03+ | Hynix HYMD264G726B(L)8-M/K/H/L series incorporates SPD(serial presence det |
| MH2 | (40) | 3.9mm | 01+ | To guarantee the Table 1 delay accuracy for input frequencies higher than | |
| MH3 | (70) | TAZYO | This pin establishes the reference current for the internal current steeri | ||
| MH4 | (19) | ID | DIP | Notes: 1. Repetitive Rating : Pulse width limited by maximum junction tem | |
| MH5 | (22) | 1000 | The device has a software lockout feature to pre- vent the data | ||
| MH6 | (89) | MOT | QFP/64 | 03+ | The Flash devices contain two separate banks of memory (bank a an |
| MH7 | (43) | Note 5: In applications where high power dissipation and/or poor package | |||
| MH8 | (94) | MIT | DIP | DIP | Stresses beyond those listed under absolute maximum ratings may cause per |
| MH9 | (11) | DENSO | DIP16 | 91+ | The chip embeds IEEE 802.3 MAC functions for each port and these function |
| MHA | (15) | MAGICTEC | 0205 | Chapter 6, "Instruction Set," describes the features and convent | |
| MHB | (5) | N/A | DIP | 06+ | Optional data flow resume by Xon any character DMA signalling cap |
| MHC | (38) | 0603-600 | The ADSP-21365/6 includes an on-chip instruction cache that enables thre | ||
| MHD | (7) | GPS | DIP | NOTES: 1. These power consumption characteristics are for all the valid | |
| MHE | (4) | INTERPOINT | 模块10 | 9426 | State-of-the-Art EPIC-B ™ BiCMOS Design Significantly Reduces Power |
| MHF | (16) | N/A | Ready/Busy status is indicated using bit 7 of the status register. If bit | ||
| MHG | (1) | MHG | 94+ | The HT815D0 is a single chip LOG-PCM voice synthesizer LSI with 11.2-sec | |
| MHI | (3) | AEM INC | N/A | Data stored in data memory can be manipulated by 1-, 4-, and 8-bit | |
| MHK | (11) | The bq4802Y/bq4802LY provides direct connections for a 32.768-kHz quart | |||
| MHL | (32) | N/A | N/A | N/A | Flash Architecture Multiple 4-Mbit Partitions Dua |
| MHM | (16) | OKI | 04+ | The maximum allowable power dissipation, as shown in Equation (2), is a | |
| MHN | (1) | HARRIS | STK | 01# | |
| MHO | (33) | When used alone, the CLP30-200B1 acts at the internal overvoltage refer | |||
| MHP | (44) | MOTOROLA | MOUDLE | N/A | Rectifiers advanced line of power MOSFET transistors. The efficient geo |
| MHQ | (27) | MOTOROLA | CDIP | CDIP | Notes: 1. No permanent damage with only one parameter set at maximum limi |
| MHR | (9) | * Output current rating may be limited by duty cycle, ambient temperatur | |||
| MHS | (31) | MHS | 04+ | AMD MirrorBit flash technology combines years of Flash memory manufactu | |
| MHT | (10) | solitron | solitron | dc72 | RSENSE - This is the common connection for the bot- tom of the bridge. Th |
| MHV | (16) | FSL | 07+ | − Conforms to USB specification Rev. 1.1 − Supports 1 devic | |
| MHW | (271) | MOTOROLA | (LX)high-frequency | A range of silicon varactor diodes for use in frequency control and filt | |
| MHY | (8) | TOSHIBA | SOT | 05+ | By means of an external distance resistor on the oscillator (pin RDi) it i |
| MHZ | (2) | DIP-40 | 458 | Three-phase bipolar drive Direct PWM drive Built-in | |
| M-I | (1) | The CMX866 Programming Register should only be written to when the Progra | |||
| MI- | (828) | N/A | The ADSP-BF535 Blackfin processor contains a rich set of peripherals con | ||
| MI0 | (17) | Instruction Structure The byte following the address contains the instru | |||
| MI1 | (26) | MITSUBISHI? | Available in the Texas Instruments NanoStar™ and NanoFree™ Pa | ||
| MI2 | (16) | N/A | DIP | 96+ | n Floating channel designed for bootstrap operation Fully operati |
| MI3 | (24) | MIT | 01+ | Fifth Generation HEXFETs from International Rectifier utilize advanced p | |
| MI4 | (40) | HARRIS | SMD | 9804+ | Maxim evaluates pressure pot stress from every assembly process du |
| MI5 | (5) | 2003 | An excitation voltage is applied to the thermistor (RTHERM) and precisio | ||
| MI6 | (12) | HAR | PLCC | The FM1233A features a highly accurate voltage reference to which VCC is | |
| MI7 | (10) | INTEL | 02+ | Fluid analysis is essential in a wide range of current applications. Biol | |
| MI8 | (8) | MITSUBISHI | 06+ | NOTE: All input pulses are supplied by a generator having the following c | |
| MI9 | (26) | OKI | PLCC84 | 03/+04+ | PRODUCT PREVIEW information concerns products in the formative or desig |
| MIA | (8) | MAXIM | 06+ | 500 | DIGITAL INPUT CURRENT Input High Current, IIH Input Low Cu |
| MIB | (4) | DIP | 98 | All voltages are referenced to V SS = 0 V (ground). All characteristics | |
| MIC | (7732) | MICREL | SSOP-20 | 06+ | Teccor Electronics reserves the right to make changes at any time in order |
| MID | (62) | IXYS | VS = 5V, TA = 25˚C, RL = 100Ω (Typical values unless specifie | ||
| MIE | (21) | UNi | The LM193 is characterized for operation from −55C to 125C. The LM2 | ||
| MIF | (13) | N/A | Still picture of 800 600 pixel uncompressed Video of VGA resolution (640 | ||
| MIG | (318) | TOSHIBA | PIM | Quick Reference Slim profile, (0.6-2.0mm thick light guide), and u | |
| MII | (14) | IXYS | IGBT | N/A | Typical Data is at TA = +25C and VCC = 5 V and is for design information o |
| MIK | (24) | 2003 | DIP-8 | The RC5051 contains two identical high current output drivers that utili | |
| MIL | (37) | digi | digi | dc97+ | After the CMX866 has been successfully powered up, both the CMX866 Receive |
| MIM | (16) | 4000 | MOT | 0150+ | Notes: 1 Monitoring time is the time from the last pulse (negative |
| MIN | (149) | RAYCHEM | RAYCHEM | 08+ | The CS4398 also has an proprietary DSD processor that allows for volume c |
| MIO | (19) | IXYS | SOP | NOTE : 1. Samsung are not designed or manufactured for use in a device or | |
| MIP | (264) | FDKK | This series of silicon tuning varactors have an epitaxial mesa design wit | ||
| MIQ | (27) | MINI | 08+ | The Hynix HYM71V8M635HC(L)T6 Series are Dual In-line Memory Modules | |
| MIR | (5) | 07+ | Maximum / minimum signal levels The following table gives the transmitte | ||
| MIS | (35) | TI | CFP | 9839 | The MAX1698 EV kit contains a switching-regulator cur- rent-source circui |
| MIT | (44) | N/A | The HY62LF16404D is a high speed, super low power and 4Mbit full C | ||
| MIU | (2) | 00+ | intersil | 800 | 3.4.1 Lead finish. Unless otherwise specified, lead finish shall b |
| MIV | (3) | micropac | micropac | dc86 | The PCD6003 integrates all the digital and analog speech management and |
| MIW | (1) | TOSHIBA | MODULE | N/A | The standard device offers access times of 70, 90, and 120 ns, allowing h |
| MIX | (5) | TEMIC | 2008 | ||
| MJ- | (8) | N/A | Six channels of EMI filtering for data ports Pi-style EMI filters in a | ||
| MJ0 | (7) | DENSO | The pin function index is similar to the explanation of the pin function | ||
| MJ1 | (253) | N/A | *Notice: Stresses above those listed under Maximum ratings may cause per | ||
| MJ2 | (58) | MOTOROLA | SOP | HighCperformance, lowCcost CMOS EEPROMCbased programmable logic devices | |
| MJ3 | (52) | MOT/ON | TO-3 | The MJ3772 is a general purpose gain block that offers good dynamic rang | |
| MJ4 | (52) | N/A | N/A | N/A | ESD damage can range from subtle performance degradation to complete dev |
| MJ5 | (17) | MITSUBISHI | DIP | 95 | of a program or erase operation can be detected and any error condition |
| MJ6 | (7) | TO-3 | 08+ | Load current passes through the external current sense resistor. When the | |
| MJ7 | (11) | MOT/ON | TO-3 | Byte loads are used to enter the 128 bytes of a sector to be programmed o | |
| MJ8 | (13) | MOT/0N | TO-3 | 04+ | • Two processing elements, each made up of an ALU, Mul- tip |
| MJ9 | (6) | ON | TO-3 | 04+ | 100% production tested at the specified temperature. 100% production te |
| MJA | (13) | ATI | 00+ | BGA | Hynix HYMD232726A(L)8J-J series is unbuffered 184-pin double data rate Syn |
| MJB | (17) | MOTOROLA | TO-263 | The bar antenna is a very critical device of the complete clock receiver | |
| MJC | (4) | 1. A 0.1 µF low frequency tantalum bypass capacitor in parallel with | |||
| MJD | (323) | ON | TO-252 | 04+ | A LOW on both pins initializes the FIFO read and write pointers to the fir |
| MJE | (459) | ON | TO-220 | 06+ | Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceede |
| MJF | (48) | MOT/0N | TO-220 | 04+ | The LM393 series are dual independent precision voltage comparator |
| MJH | (52) | ON | TO-3P | 06+ | Notes 1. Test voltage must be applied within dv/dt rating. 2. All devic |
| MJJ | (3) | MOTOROLA | 826 | A zero crossing output (ZX) produces an output that is synchro- nized to | |
| MJK | (3) | Notes: 1. See test circuit and waveforms. 2. This parameter is guarant | |||
| MJL | (29) | ON | 06+ | When calculating synchronous frequencies, use tS1 if all inputs are on t | |
| MJM | (8) | JRC | STK | 2005+ | These dual beam leads are intended for use in balanced mixers and in eve |
| MJN | (26) | 08+ | These three functional blocks are identical in operation, so only a single | ||
| MJP | (4) | MAC8 | † Typical values are at VCC = 5 V, TA = 25C. ‡ Not more tha | ||
| MJS | (5) | CHINA | 0403+ | PGA 478 for Intel Pentium 4 CPU with Hyper-Threading Technology up | |
| MJT | (2) | Tiny SOT−353 and SOT−553 Packages Extremely High Speed: tPD 2 | |||
| MJU | (3) | 723 | Allows Safe Board Insertion and Removal from a Live Backplane Controls S | ||
| MJW | (32) | N/A | DIP | 93 | Drain-to-Source Breakdown Voltage Gate Threshold Voltage Ga |
| MJY | (55) | 1850 | The Samsung M464S1724CT1 is a 16M bit x 64 Synchronous Dynamic RA | ||
| MK- | (17) | MINI | 08+ | † For simplicity, routing of complementary signals LD and CK is not | |
| MK0 | (23) | 99 | Diode protected input stage for power OFF condition 17 ns typ high speed | ||
| MK1 | (292) | MK | SMD16 | 9552+ | When the voltage drop to the positive input of the com- parator (i,e,VB) |
| MK2 | (307) | MICREL | QFN | 04+ | The ISL6537A provides a complete ACPI compliant power solution for up to |
| MK3 | (227) | ICS | SOP-8 | FEATURES 40 MSPS Correlated Double Sampler (CDS) 4 dB 6 dB Variable CDS | |
| MK4 | (396) | Toshiba | 8000 | ||
| MK5 | (196) | MOSTEK | DIP | The input capacitor CI is necessary for compensation of line influences. | |
| MK6 | (78) | ST | DIP | 06+ | ICC and ICC are dependent on output loading and cycle rate. The specifie |
| MK7 | (50) | ICS | 07+ | Differential PECL compatible outputs 700 ps propagation delay input to | |
| MK8 | (5) | vishay | vishay | dc0511 | The TLV246x is a family of low-power rail-to-rail input/output operationa |
| MK9 | (36) | mci | mci | dc96 | Enable EN (enable) is a CMOS compatible input. EN enables or disables a |
| MKA | (15) | ZHANGDE | SOP | • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V p | |
| MKB | (17) | N/A | N/A | N/A | TAOperating free-air temperature−55125−4085C NOTE 3: A |
| MKC | (53) | The MAX2601/MAX2602 are high-performance silicon bipolar transistors in p | |||
| MKD | (27) | phoenix | phoenix | dc02 | NOTE: All input pulses are supplied by a generator having the following c |
| MKF | (9) | NTK | only, and functional operation of the device at these or any other conditi | ||
| MKG | (20) | MOSTEK | 4 | The MSK 4351 is a 50 Amp, 3 Phase Isolated Bridge Smart Power Moto | |
| MKH | (4) | AGL | 00+ | The HY64UD16322M is a 32Mbit 1T/1C SRAM featured by high-speed operation | |
| MKI | (17) | Read the contents of the Data Register pointed to by R1CR0 | |||
| MKJ | (13) | ST | PGA181 | 8434 | No External Programming Voltage Needed Programmable Code Protection by S |
| MKK | (21) | QFP | 01+ | The TMS320C62x DSPs include an on-chip memory, with the C6203 device offe | |
| MKL | (1) | The HYS64(72)16300GU and HYS64(72)32220 are industry standard 168-pin 8-b | |||
| MKM | (2) | Broad Support Program: A BSP layer is provided to allow easy porting of p | |||
| MKO | (2) | PHILIPS | SSOP/TSSOP | 03+ | Motorola reserves the right to make changes without further notice to any |
| MKP | (197) | VISHAY | 256-byte SecSi™ (Secured Silicon) Sector Factory locked and | ||
| MKQ | (3) | 01+ | Dimensions InchesMillimeters MinMaxMinMax .046.056 | ||
| MKR | (2) | When 16/68# pin is at logic 1 for Intel bus interface, this output become | |||
| MKS | (284) | wima | wima | dc99 | This information is believed to be accurate and reliable, however no resp |
| MKT | (278) | PHI | 07+ | *1 If the switching voltage exceeds the rated contact voltage, reduce the | |
| MKX | (1) | Note 2: The maximum power dissipation is dictated by TJMAX, JA, and the a | |||
| MKY | (7) | STEP | QFP64 | 2.1. General. The documents listed in this section are specified i | |
| MKZ | (1) | ZIRCON | TQFP80 | Low power RS-485 systems Network hubs, bridges, and routers Point of | |
| M-L | (41) | Reference inputs The voltage differential between the VREFL and VREFH i | |||
| ML- | (12) | ML | QFP | 03+ | * Equipped with all stages of a mono receiver from antenna to aud |
| ML0 | (36) | N/A | 04+ | TI warrants performance of its semiconductor products to the specificatio | |
| ML1 | (69) | TQFP-144 | 99 | Input/Output Capacitors: The PT6440 regulator series requires a 100µ | |
| ML2 | (283) | The ispLEVER® design tool from Lattice allows large complex designs t | |||
| ML3 | (22) | ML | 00+ | TO78 | Each Address ALU can update one address register from its respective addr |
| ML4 | (444) | MICROLINEAR | TSSOP-20 | The National Semiconductor® PC87431x family of mini- Baseboard Mana | |
| ML5 | (48) | FAIR | TSSOP-28 | 01+ | • Low voltage operation • Low saturation voltage (<500mV, |
| ML6 | (435) | MICROLIN | 711 | AD5383-5 is calibrated using an external 2.5 V reference. Temperat | |
| ML7 | (109) | OKI | 0251+ | This datasheet contains new product information. Analog Corp. reserves the | |
| ML8 | (45) | ML | 06+ | The FIFO has a combined Empty/Output Ready flag (EF/OR) and a combined | |
| ML9 | (53) | LUCENT | PLCC28P | 00+ | Note 2: The maximum power dissipation is dictated by TJMAX, JA, and the a |
| MLA | (35) | TI | SOP/8 | 00/P | Phase compensation is used to ensure stable operation even if load curre |
| MLB | (203) | N/A | 0805BEAD | If the port is left in a forced 1394b beta only (B1, B2, or B4) mode, the | |
| MLC | (49) | Two serial outputs (Os and Os) are available for cascading a number of | |||
| MLD | (9) | Pin Definitions Pinout Tables - CS144 Chip-Scale BGA Package - FG256 F | |||
| MLE | (12) | FSC | 02+ | T0-3P | - Ideal for DDR-I and DDR-II applications - Capable of sourcing and sinki |
| MLF | (623) | TDK | 0603 | 07/环保 | The Rambus Direct RDRAM™ is a general purpose high-performance mem |
| MLG | (218) | TDK | 2007+PB | When a sync pulse is detected on channel A (CVBS), the DC restore loop is | |
| MLH | (91) | MINSATO | 98 | sFEATURES qOperating Voltage4.7 to 13V qWOW Function | |
| MLI | (58) | 0805L | Performance Latest processor technology, Intel® Penti | ||
| MLK | (124) | TDK | 0603 | 07/环保 | BVDSSDrain-to-Source Breakdown Voltage100 ∆BV DSS/∆T J Tempe |
| MLL | (45) | MIROSEMI | 1WR | 05+ | † The bus-hold circuit can sink at least the minimum low sustaining |
| MLM | (44) | MOT | 2008 | NOTES: A. CL includes probe and test-fixture capacitance. B. Wave | |
| MLN | (3) | ASI | (LX)high-frequency | • Solid-state Relay (Equivalent to AQW210S) - Typical RON 2 | |
| MLO | (21) | M/A-COM | Notes: 1: VC1 2.4 ,VC2 2.4, VM 2.4, VC1 5.0, VC2 5.0, VC3 5.0, VM13 5.0, | ||
| MLP | (26) | ON | TO-220 | 08+ | (1) The algebraic convention, in which the least positive (most negative) |
| MLR | (92) | TDK | 1608 | q LOW NOISE PREAMP: Low Input Noise: 1.0nV/Hz Active Termi | |
| MLS | (79) | ferroxcube | ferroxcube | dc04 | The DSP is a 20x20 bit core audio processor performing several user contr |
| MLT | (19) | ADI | 07+ | Maximum ratings are those values beyond which device damage can occur. Ma | |
| MLU | (9) | TDK | • Data mask (DM) for write data • DLL aligns DQ and DQS tra | ||
| MLV | (24) | MAG LAYERS | 2002+ | Fast, high-density Field-Programmable Gate Arrays - Densities from 50k | |
| MLX | (253) | MELEXIS | SOP | 06+ | Notes: *All PIO signals are shared with other physical pins. See t |
| MLZ | (18) | TDK | 0603L | Source current: In stand-by condition Source current: While detecting l | |
| M-M | (10) | 2007 | (4) The products described in this material are intended to be used for s | ||
| MM- | (14) | functional operation of the device at these or any other condition | |||
| MM. | (1) | NS | SOP14S | 2007+ | Notes: 1. ∆VF for diodes in pairs and quads in 15 mV maximum at 1 |
| MM/ | (9) | NSC | n/a | 89 | The MM/MC74HC132N has a 2Vp-p differential input range (1Vp-p • 2 |
| MM0 | (34) | N/A | NSC | 04+ | Input & output negative-voltage ratings may be exceeded if the input |
| MM1 | (1254) | MITSUMI ELECTRIC CO.LTD | 97 | *Stresses above those listed under Absolute Maximum Ratings may cause per | |
| MM2 | (218) | ST | 00+ | Supply Voltage (V+ − V−) Differential Input Voltage | |
| MM3 | (350) | 美芝美 | SOT-23-5P | 6+ | 62 powerful instructions Up to 1ms instruction cycle with 4MHz system c |
| MM4 | (104) | MOT | 2008 | Hynix HYMD132G725A(L)8M-K/H/L series is Low Profile registered 184-pin dou | |
| MM5 | (963) | NS | DIP8 | 04+ | SWITCHING PARAMETERS QgTotal Gate Charge QgsGate Source Charge QgdGate |
| MM6 | (26) | MIT | 06+ | Active low signal from ATM signifying that data will be sampled on RDAT[7 | |
| MM7 | (1718) | FSC | SOP | 00+98 | The Honeywell HRF-ROC093XC is a half-duplex transceiver for use in wirele |
| MM8 | (75) | MOTOROLA | TO-3 | This device contains two independent positive pulse trig- gered J-K flip | |
| MM9 | (144) | N/A | N/A | N/A | The switch is turned on by a single enable (OE) input. When OE is LOW, th |
| MMA | (1363) | N/A | N/A | N/A | Collector-to-Emitter Voltage Continuous Collector Current Continuous |
| MMB | (2611) | bey | bey | dc00 | Stresses beyond those listed under "absolute maximum ratings" m |
| MMC | (158) | MOTOROLA | 04+ | ||
| MMD | (202) | SOT-89 | 06+ | ||
| MME | (8) | MIT | QFP | 04++ | Notes: 1. All timing is referenced to the CPUCLK. 2. The Internal label |
| MMF | (91) | MOT | SOT223 | 00+ | No Auxiliary Winding Operation Internal Output Short−Circuit Prote |
| MMG | (21) | MMG | N/A | • Power supply : Vdd: 2.6V 0.1V, Vddq: 2.6V 0.1V • Double-d | |
| MMH | (20) | Panasonic | DIP8 | 9038 | Features • Wide frequency rangeC15.0MHz to 250.0MHz • User s |
| MMI | (69) | mmi | mmi | dc81 | In addition, the MMI63S140N can be configured to support two different |
| MMJ | (19) | ON | 05+ | The TFP401/401A supports display resolutions up to UXGA in 24-bit true co | |
| MMK | (150) | evx | evx | dc01 | The converter can be disabled to minimize battery drain. During shutdow |
| MML | (7) | HIT | SMD | Data bits to be transmitted through the cable ports are received from the | |
| MMM | (29) | MOTOROLA | 06+ | QFN | TOUT C This pin is the buffered output of the temperature sensor. The an |
| MMN | (2) | This pin is capable of driving a standard CMOS or TTL load. No external | |||
| MMO | (15) | N/A | Flexible control options for power management are available when the seri | ||
| MMP | (87) | 2008 | If the external master has initiated a register read request, the SX2 wi | ||
| MMQ | (54) | ON | SOT-163 | 07+ | NOTES: 1. All voltage values, except differential voltages, are with resp |
| MMS | (1209) | N/A | ON | 04+ | Fully Integrated VCC and Vpp Switching for Dual Slot PC CardTM Interface |
| MMT | (118) | ON Semiconductor | 05+ | 10EP circuits are designed to meet the DC specifications shown in the abo | |
| MMU | (212) | ON | 07+ | Note) *1: Except for the operating ambient temperature and storage temper | |
| MMV | (24) | ZILOG | QFP | 03+ | • AGC PIN diode drive circuit for FM RF AGC; AGC detection a |
| MMW | (3) | High-drive GTLP backplane interface devices feature adjustable edge-rate | |||
| MMX | (63) | HITACHI | 1812 | 05+ | The SN74GTLP22034 is a high-drive, 8-bit, three-wire registered transceiv |
| MMY | (1) | Note 9: The 1µA limit is based on a testing limitation and does not | |||
| MMZ | (290) | N/A | Note 4: The Absolute Maximum Ratings are those values beyond which the sa | ||
| M-N | (3) | AGERE | 03/04+ | The MAX1661/MAX1662/MAX1663 serial-to-parallel/ parallel-to-serial conver | |
| MN- | (1) | LSI | QFP | 98 | Differential analog input pins. With a 1.0V reference voltage the differ |
| MN0 | (6) | PANASONIC | DIP42 | 47 | RESET is an active low output that provides a RESET signal to the Microp |
| MN1 | (2545) | PANASONIC | The device is programmed on a word-by-word basis. Programming is accompli | ||
| MN2 | (96) | 173 | PANASONIC | ‡ Stresses beyond those listed under absolute maximum ratings may c | |
| MN3 | (346) | PAN | DIP8 | First of all, use the largest supply voltage available (15V or +30V is c | |
| MN4 | (296) | PANASON | If you have any questions or comments regarding this publication, please | ||
| MN5 | (208) | PANASONIC | Unless specifically noted all references to the 80C186EB apply to the 80 | ||
| MN6 | (725) | MIT | DIP | The TLE 5206-2 is an integrated power H-bridge with DMOS output stages | |
| MN7 | (170) | ＰＡＮＡＳＯＮＩＣ | Unlike the other two modes that accept only a single specified input freq | ||
| MN8 | (136) | 2000 | Hynix HYMD232726B(L)8-M/K/H/L series incorporates SPD(serial presence dete | ||
| MN9 | (83) | 664 | LSI | 99+ | Magnetic offset caused by mechanical stress is com- pensated for by usi |
| MNA | (26) | ROHM | 01+ | ||
| MNB | (13) | WOOJU | 04+ | NOTES: 1. Dimensions are in inches. 2. Metric equivalents ar | |
| MNC | (8) | 2003 | The W681511 includes an on-chip precision voltage reference and an additi | ||
| MND | (2) | MN | AUCDIP | The REG103 is a family of low-noise, low-dropout, linear regulators with | |
| MNE | (2) | OKI | (1) Maximum voltage between transistors shall be 500 V dc. (2) Derate | ||
| MNG | (5) | NS | PQFP-160 | 01 | A word-width-select option is provided on Port B for 36-bit, 18-b |
| MNI | (2) | ||||
| MNK | (2) | The ZL30414 accepts a CMOS compatible reference at 19.44 MHz and generate | |||
| MNL | (3) | N/A | Horizontal This output produces only true H pulses of nominal width | ||
| MNM | (12) | NEC | QFP | s Up to forty-six 5 V tolerant general purpose I/O pins. Up to nine edge | |
| MNO | (3) | ST | SMD | Current-mode PWM Controller High-current output drive suitable for Power | |
| MNP | (10) | METANETICS | Sensitivity can often be increased by using a bigger electrode, reducing | ||
| MNR | (447) | N/A | 1206X5 | This series includes Auto-Track™ sequencing. Auto-Track sequencing | |
| MNS | (3) | EAGLEMOSS | SMD | 1 | This latched Schmitt input signal is inverted and routed to D7 of the dat |
| MNT | (22) | 1 | ALCATEL | 05+ | The receive path consists of a programmable amplifier (RxPGA), a tunable |
| MNU | (2) | NOTES: 1. Stresses beyond those listed may cause permanent damage to the | |||
| MNV | (2) | MAXIM | • Operating temperature from - 55 C to + 110 C • No Base Te | ||
| MNZ | (4) | PANASONIC | 06+ | Power-On Reset Generator with Adjustable Delay Time: 1.25ms to 10s Very | |
| M-O | (3) | N/A | N/A | 2003 | Unless otherwise specified, these specifications apply over V12=12V, V5=5V |
| MO- | (16) | 457 | INTERDESIGN | TSStorage temperature-65125C Absolute maximum continuous ratings are th | |
| MO1 | (28) | SAGEM | Input Voltage Range: 8V to 75V Valley Current Limit At 1.25A | ||
| MO2 | (35) | 06+ | SSOP/16 | The SDA is a Bi-directional pin used to transfer addresses and data int | |
| MO3 | (7) | Fairchild | TO-220 | 05+ | The ISL6527 makes simple work out of implementing a complete control and |
| MO4 | (1) | SMD | QTC | 05+ | These flip-flops have independent J, K, Set, Reset, and Cloc |
| MO6 | (3) | MOTOROLA | 07+/08+ | The Flash program memory supports both parallel programming and in serial | |
| MO7 | (1) | © 1997 MX•COM Inc.www.mxcom.com Tele: 800 638-5577 910 744-5050 | |||
| MO9 | (9) | 04+ | MEASUREMENT TIPS This demonstration board and the component values shown | ||
| MOA | (1) | The device also features Personal Video Recording capabilities. It has a | |||
| MOB | (21) | HYUPJIN | The thermally efficient package mea- sures only 2mm x 2mm x 0.75mm. Its | ||
| MOC | (1407) | Fairchi | 05+ | The RC2207 is a monolithic voltage-controlled oscillator (VCO) integrate | |
| MOD | (58) | 395 | ST | 00+ | Note 1: All units are 100% production tested at TA = +25C. Limits over the |
| MOE | (5) | megatron | megatron | dc97 | 1.2.3 Device class designator. The device class designator is a si |
| MOF | (5) | GPS | 07+ | The MOF3495/1226/1227 performs voltage conversions but does not | |
| MOG | (7) | GPS | 07+ | The combination of narrow nonlinear range and low limiting offset allows | |
| MOH | (14) | GPS | CDIP | CDIP | ISSI reserves the right to make changes to its products at any time witho |
| MOI | (3) | INFINEON | PLCC68 | INVALID OP-CODE: If an invalid op-code is received, no data will be shift | |
| MOJ | (10) | GPS | CDIP | CDIP | : the number for special module.: the number of CR (Control Regist |
| MOL | (21) | FERRANTI | CDIP | N/A | The input/output pins (I/O 0 through I/O15) are placed in a high-impeda |
| MOM | (27) | GPS | PLCC-28 | 07+ | Notes: 1. Measurements obtained from a fixed narrow band tuning describe |
| MON | (16) | SMSC | SOP24 | 07+/08+ | The MON35W82 is a P-Channel Power MOS FET with low on-state resistance |
| MOO | (5) | RKC | 86 | NOTES: 1. Designators in TYPE: P: power supply and ground, DI: digital in | |
| MOP | (5) | DIP | 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers pnp I | ||
| MOQ | (1) | ||||
| MOR | (27) | GPS | 07+ | • Operating temperature from - 55 C to + 110 C • No Base Te | |
| MOS | (79) | MINI | 08+ | • SuperWIDE HIGH-DENSITY IN-SYSTEM PROGRAMMABLE LOGIC | |
| MOT | (58) | MOT | 96+ | SOP-8 | FEATURES Ultrahigh Speed: Current Settling to 1 LSB in 35 ns High Stabi |
| MOU | (3) | ||||
| MOV | (1) | Note that still image decompression can also be accomplished by configur | |||
| MOX | (11) | victoreen | victoreen | dc83+ | NanoStar and NanoFree Packages Low Static-Power Consumpti |
| MOZ | (1) | The HT24LC02 is a 2K-bit serial read/write non-volatile memory device usi | |||
| M-P | (8) | NOT | 04+ | a: Stresses greater than those listed under „Absolute Maximum Ratin | |
| MP- | (33) | MP | ＢＧＡ | • JEDEC registered 1N5333 to 1N5388B • Zener voltage availa | |
| MP/ | (1) | Values shown in this table are design targets and are subject to change be | |||
| MP0 | (67) | CTS | 2007+PB | In designing a crystal oscillator, the values of C1 and C2 as shown in th | |
| MP1 | (477) | MPS | SSOP20 | 3月4日 | BOOT is the floating bootstrap supply pin for the upper gate drive. Conne |
| MP2 | (192) | TI | . | The Am79C961A PCnet-ISA II Ethernet controller, a single-chip Ethernet | |
| MP3 | (122) | MP | CAN6 | • 1.27 mm (0.050 in.) pitch contact arrangement in two rows | |
| MP4 | (130) | 98 | Inhibit: The Inhibit pin is an open-collector/drain negative logic input | ||
| MP5 | (88) | ROHM | 00+ | Eight 8-bit registers are provided for control, option select, and status | |
| MP6 | (102) | 91 | PMD warrants performance of its products to the specifications applicable | ||
| MP7 | (609) | TI | DIP | 2000 | ALERT alarm is an open drain, active-LOW output which requires an exter |
| MP8 | (221) | EXAR | SOP | 1998 | In single pushbutton mode or when using the digital source input, as th |
| MP9 | (102) | 93 | As load current is reduced, the energy required in the inductor diminis | ||
| MPA | (68) | TI | 07+ | Notes: 1. For Max. or Min. conditions, use appropriate value specified u | |
| MPB | (29) | The noise of Q1A and Q1B would normally be quite signifi- cant about 6 n | |||
| MPC | (1366) | NOTES 1Input bias current is specified for two different conditions. The | |||
| MPD | (130) | MINI | 08+ | deasserted. Data will be read out of the FIFO on both rising and falling | |
| MPE | (36) | 96 | Each device includes on a single silicon chip a voltage regulator, | ||
| MPF | (119) | CAN | 99+ | NOTES: (1) Junction Temperature = Ambient Temperature for low temperature | |
| MPG | (41) | Vishay | MPG06 | 08+ | I 32-level Low Voltage Detection I Brown-out Reset I Software selectabl |
| MPH | (1) | 04 | This hybrid integrated circuit is housed in a hermeti- cally sealed TO-3 | ||
| MPI | (22) | OUTPUT VOLTAGE LIMITERS Default Limiter Voltage Minimum Limiter Separa | |||
| MPJ | (1) | The S1M8821/22/23 is a high performance dual frequency synthesizer with i | |||
| MPK | (3) | MB90895 series devices are 16-bit micro general-purpose controller | |||
| MPL | (23) | ROHM | SOT-89 | 04+ | A buffered output-enable (OE) input can be used to place the eight outp |
| MPM | (74) | ALTERA | QFP | 2006 | 3.3V 10% Receive Input Power Supply. Bypass with 0.1µF//0.01µF |
| MPN | (10) | Motorola | n/a | The Codec controller supports any AC97 compliant CODEC. The functionality | |
| MPO | (19) | DELTA | An unused RESET input should be tied to VDD . However, if an entire sec | ||
| MPP | (13) | JS | 05+ | The LTC®3803 is a constant frequency current mode flyback controller | |
| MPQ | (57) | DIP | DIP | The device supports low-power standby operation. When the reset input (RS | |
| MPR | (192) | SONY | 1900 | DIP | Multiplexed PCI address/data bus. A bus transaction consists of an addres |
| MPS | (1018) | ON | 07+ | Moreover, the output swing for an ideal RS-232 transceiver would be 5V wi | |
| MPT | (28) | JS | 05+ | Note 3: The shortest allowable SK clock period = 1/fSK (as shown under th | |
| MPU | (17) | 07+ | The LX8385/8385A/8385B series ICs are positive regulators designed to p | ||
| MPV | (23) | N/A | N/A | 04+ | Notes: 1. For Max. or Min. conditions, use appropriate value specified u |
| MPX | (321) | N/A | N/A | 04+ | The pre-emphasis is used to compensate for long or lossy transmission m |
| MPY | (66) | - | SMD | 07+/08+ | 2.5V or 3.3V operation Split output bank power supplies Output frequency |
| MPZ | (42) | 0603B | This publication is issued to provide information only and (unless agreed | ||
| MQ- | (12) | Detect voltage range: 0.8V (N-ch open drain) Operating voltage range : 0. | |||
| MQ/ | (2) | HIROSE | 03+ | HY57V561620A is offering fully synchronous operation referenced to a posit | |
| MQ0 | (1) | Peak and hold mode with programmed peak time: When the channel is turned | |||
| MQ1 | (32) | Notes: 9. All typical values are measured at VCC = 3.3V, TA = 25C. 10. | |||
| MQ2 | (22) | NVIDIA | 03+ | For applications requiring output voltage On/Off control, the 12pin ISR | |
| MQ3 | (11) | mot | mot | dc81+ | When the IC is enabled (TXEN high) a phase locked loop locks the output |
| MQ4 | (1) | HY57V1294020 is offering fully synchronous operation referenced to a posit | |||
| MQ5 | (7) | N/A | The device also features split output bank power supplies which enable th | ||
| MQ6 | (1) | Specifications Outline Dimensions Dimensions of Sensitive Area Positio | |||
| MQ7 | (4) | PHILIPS | MP-56 | 07+ | 30 fully-programmable I/Os (5V tolerant) 4 external interrupts 8-bit p |
| MQ8 | (32) | ROCHESTER | CQFP68 | —— | 64Mbit of Flash Memory Page Program (up to 256 Bytes) in 1.4ms (typica |
| MQ9 | (2) | SEEQ | 99+ | PLCC | Note 2: At elevated temperatures, device power dissipation must be derate |
| MQA | (1) | The device can accommodate astigmatic, single foucault and double fouca | |||
| MQC | (18) | MCDIAQ | BGA | 04+ | FUNCTION Power Supply Ground Track Mode Select Analog Input An |
| MQD | (3) | N/A | † Stresses beyond those listed under absolute maximum ratings may c | ||
| MQE | (123) | N/A | N/A | 04+ | Note 1: Thermal resistance of the TO-3 package (K, KC) is typically 4I |
| MQF | (25) | 08+ | RESET The RESET input pin when pulled low initializes the micro- contro | ||
| MQG | (1) | N/A | Description Numeric, Right Hand DP Numeric, Left Hand DP Hexad | ||
| MQH | (6) | murata | murata | dc98 | The K1S1616B1A is fabricated by SAMSUNGs advanced CMOS technology |
| MQK | (13) | N/A | N/A | 04+ | Notes: 1. PD indicates an internal pull-down and PU indicates an i |
| MQL | (47) | MURATA | 00+ | Once activated, the link-on output will continue active until the LLC be | |
| MQP | (3) | USING THE SP304 POWER SUPPLIES The SP304 requires 12V and +5V for full | |||
| MQR | (5) | MURATA | 1. The collector of each transistor in the MQR002A1G06 is isolated from t | ||
| MQS | (1) | * All specs and applications shown above subject to change without prior | |||
| MQT | (4) | MURATA | The CE pin is taken LOW to enable all Playback and Record operations. The | ||
| MQW | (26) | N/A | N/A | N/A | DESCRIPTION Intended for analog and digital satellite STB receivers/Sat |
| MQX | (1) | MAX | SMD | State-of-the-Art Advanced BiCMOS Technology (ABT) Widebus ™ Design f | |
| MQY | (1) | 714 | Member of the Texas Instruments Widebus™ Family Ideal for Use in P | ||
| M-R | (3) | N/A | 25201008 | READ: The AT49BV/LV040 is accessed like an EPROM. When CE and OE are low | |
| MR- | (25) | 428 | ＤＩＰ | Stresses above those listed under Absolute Maximum Ratings may cause perm | |
| MR/ | (1) | The SPI interface can communicate at a maximum of 5Mbps data rate with a | |||
| MR0 | (99) | AVX | 0 | 5 | Very Low Dropout Voltage 800 mA Output Current High Output Voltage Ac |
| MR1 | (52) | MOT | 9518+ | Stresses beyond those listed under absolute maximum ratings may cause pe | |
| MR2 | (340) | N/A | 02+ | for reads or writes to any location in memory. An automatic power down f | |
| MR3 | (41) | FAIRCHILD | 05/06+ | Up to 97% Efficiency 2MHz PWM Switching 800mA Guaranteed Output Current | |
| MR4 | (23) | DENSO | DIP | Hynix HYMD564M646(L)6-K/H/L series incorporates SPD(serial presence detect | |
| MR5 | (53) | N/A | N/A | 04+ | Crystal input, has internal load cap (36pF) and feedback resistor from |
| MR6 | (82) | DIP | Isolation in Powered-Down Mode, V+ = 0 Low ON-State Resistance (0.9 ͐ | ||
| MR7 | (29) | ON | 07+ | Maximum Recurrent Peak Reverse Voltage Maximum RMS Bridge Input Voltage | |
| MR8 | (92) | ON | One 64 x 8 (512-bit) Configuration Zone Three 64 x 8 (512- | ||
| MR9 | (33) | ERICSSON | N/A | 2004 | Internal Power Dissipation JA (Exposed paddle soldered down) JA (Expose |
| MRA | (67) | MOTOROLA | MODULE | 00+ | "Advance" product information describes products that are in de |
| MRB | (12) | N/A | N/A | 04+ | State-of-the-Art EPIC-B™ BiCMOS Design Significantly Reduces Power |
| MRC | (88) | IR | 07+ | † Package drawings, standard packing quantities, thermal data | |
| MRD | (33) | 01+ | FEATURES 1 pC Charge Injection 2.7 V to 5.5 V Dual Supply +2.7 V | ||
| MRE | (2) | These devices are adjustable high-precision shunt regulators whose outpu | |||
| MRF | (1403) | MOTOROLA | high-frequency tube | of a program or erase operation can be detected and any error condition | |
| MRG | (32) | SOP/16 | 90+ | Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V | |
| MRH | (4) | Multifunction Instructions Pipelined Architecture Supports Efficient Cod | |||
| MRJ | (2) | The MAX4364/MAX4365 are bridged audio power amplifiers intended for porta | |||
| MRK | (3) | QFP | The L5970AD is a step down monolithic power switching regulator with a | ||
| MRL | (3) | 0805L | Leading-edge triggering (A) and trailing edge triggering (B) inputs are | ||
| MRM | (2) | ♦ Noise Spectral Density = -164dBFS/Hz at fOUT = 16MHz b | |||
| MRN | (15) | TOSHIBA | N/A | N/A | † All typical values are at VCC = 5 V, TA = 25C. ‡ Applies |
| MRO | (4) | SHARP | QFP | 96+ | - Low voltage low power architecture including internal voltage r |
| MRP | (13) | LGIC | 07+ | The floating-point unit operations set includes floating-point add | |
| MRR | (6) | The ISD5008 device is designed for use in a micro- processor- or microco | |||
| MRS | (181) | ON-SEMI SCG | 07+ | The lamp current is limited by a control amplifier that protects the exte | |
| MRT | (24) | 64 | INTERSIL | 03+ | PMC-2001514 (p2) © Copyright PMC-Sierra, Inc. 2001. All rights re |
| MRU | (10) | NEC | SOT-323 | • Double data rate architecture: two data transfers per clo | |
| MRV | (2) | ITU-T and ANSI Tone Detection per channel Per channel Power Down Functi | |||
| MRW | (26) | MOT | Note 4: For a power supply of 5V 10% the worst case output voltages (VOH, | ||
| MRX | (11) | The µPD75P316A is a product of the µPD75316 with on-chi | |||
| MRY | (1) | OKI | Received Data Output, push-pull CMOS driver output capable of driv | ||
| M-S | (5) | 1. Cost The cost of both the component and the manufacturing overhead | |||
| MS- | (192) | MSI | 00+ | QFP-S48P | Error Flag (FAN2503 only) To indicate conditions such as input voltage d |
| MS0 | (99) | TOSHIBA | TE25 | The TPS2490 and TPS2491 are easy-to-use, positive high voltage, 10-pin Hot | |
| MS1 | (390) | Notes: 1. The luminous intensity, I v, is measured at the peak of the s | |||
| MS2 | (262) | LEACH | (LX)high-frequency | The K4S560432E / K4S560832E / K4S561632E is 268,435,456 bits synch | |
| MS3 | (410) | LAMBDA | Module | N/A | The MSK 5115-00 is an adjustable version in the series of high performan |
| MS4 | (46) | 1 | QFP | Notes 1. Signals on NC, COM, or IN exceeding VCC or GND are clamped by | |
| MS5 | (53) | N/A | 2003 | Ground connection. For best performance, keep traces physically short an | |
| MS6 | (180) | MOSEL | DIP/28 | 07+ | Note) The PWM data set, the PWM Frequency set and the PWM phase set comma |
| MS7 | (57) | N/A | N/A | 04+ | The reverse current will not exceed 10 µA at the Reverse Voltage ra |
| MS8 | (48) | MX | QFP | 07+/08+ | The AC ACT843 bus interface latch is designed to elimi- nate the extra p |
| MS9 | (24) | JAT | SOT | 05+ | 30 fully-programmable I/Os (5V tolerant) 4 external interrupts 8-bit p |
| MSA | (500) | AGILENT | SMT-86 | 05+ | A customized leadframe has been incorporated into the standard SOT-23 pa |
| MSB | (89) | MORNSUN | 08+ | NOTE: 1. AVSS (reference ground) must be connected to 0V (ground). AVCC | |
| MSC | (555) | OKI | 07+ | Following the address and acknowledge bit with logic 0 in the read/write | |
| MSD | (147) | ONS | 06+ | SOT346 | The XR16C854/854D1 (854) is an enhanced quad Universal Asynchronous Rec |
| MSE | (9) | ITT | 0004 | Complies with USB Specification Rev 1.1 & 2.0 Supports Full Speed M | |
| MSF | (34) | 0 | 0 | The C6711/C6711B/C6711C/C6711D uses a two-level cache-based architecture | |
| MSG | (72) | N/A | The BIU uses a set of control registers to determine how many wait states | ||
| MSH | (7) | Parallel configuration control input. This input controls the loading of | |||
| MSI | (14) | Section is the basic element constituting the contents of the voice ROM. | |||
| MSJ | (25) | ALCATEL | PLCC68 | 06+ | FEATURES High Performance Member of Pin-Compatible TxDAC Product |
| MSK | (29) | MSK | 八脚铁帽 | 08+ | Table 1 provides an overview of the C6711/C6711B/C6711C/C6711D DSPs. The |
| MSL | (62) | N/A | 1206 | To minimize interrupt overhead an interrupt arbitration system is includ | |
| MSM | (3926) | OKI | 03+ | Also useful for RS-232 transceivers is the capability for switching betwe | |
| MSN | (8) | N/A | The MSN3010-153 is a member of the Atmel AT91 16/32-bit Microcontroller f | ||
| MSO | (14) | ST | QFP-80 | 03 | The 2-wire serial interface accepts standard System Management Bus (SMBus |
| MSP | (1717) | ITT | PLCC44 | SYMBOLFUNCTION BBE High switching noise rejection CapacitorCBH & | |
| MSQ | (82) | ittcann | ittcann | dc80+ | Notes: 1. Repetitive Rating : Pulse width limited by maximum junction tem |
| MSR | (23) | ON | 06+ | The block SelectRAM memory resources are 18 Kb of True Dual-Port RAM, p | |
| MSS | (143) | VISHAY | DO-220AA,T&R | 08+ | |
| MST | (394) | M | 04+ | TQFP-L176P | 1) CPD is defined as the value of the ICs internal equivalent capacitance |
| MSU | (19) | N/A | PLCC | 07+ | The error amplifier compares a sample of the dc-to-dc converter output vo |
| MSV | (14) | SOD-323 | 1. Required LO level is a function of the LO frequency. 2. The LO input | ||
| MSW | (15) | MCL | O7+ | The actual completion of the nonvolatile write is a synchro- nous with th | |
| MSX | (9) | TI | AUWCQFP1420-100 | 97+ | 2.1 General. The documents listed in this section are specified in |
| MSY | (1) | MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to th | |||
| MSZ | (22) | *Stress above the listed absolute maximum rating may cause permanent damag | |||
| M-T | (57) | AGERE | 2002 | BGA | This pin controls the transfer rate of transmit PCM data. In the |
| MT- | (25) | N/A | 06+ | 500 | temperature will exceed 125C when over-temperature protection is active. |
| MT0 | (78) | D | 00+ | 1450 | Specifications contained in this data sheet are in effect as of the publi |
| MT1 | (448) | N/A | N/A | N/A | VDDQ - I/O Power Supply This feature is available only on the SST39VF160 |
| MT2 | (515) | MSL | SSOP | 98 | It contains two groups of 2 bit latches controlled by an enable input ( |
| MT3 | (184) | MITEL | QFP1414-80 | 01+ | Radio frequency IC for analog cordless telephone application in 26/50 MHz |
| MT4 | (2098) | MICRON | FBGA60 | 06+ | To guarantee the Table 1 delay accuracy for input pulse width smaller tha |
| MT5 | (1271) | MICRON | Power Supply: 2.5 V to 5.25 V operation Normal mode: 75 &m | ||
| MT6 | (144) | MTK | BGA | 06+ | Inhibit: The Inhibit pin is an open-collector/drain negative logic input |
| MT7 | (56) | 13 | MT | 02+ | TURBOSWITCH 1200V drastically cuts losses in all high voltage operation |
| MT8 | (717) | 8 | Ordering Information continued on last page. † NOTE: Parts are offe | ||
| MT9 | (427) | ZARLINK | IC LSIM | Novel current mode design Virtual ground current summing &nb | |
| MTA | (105) | MOTO | TO-220 | 03+ | High performance 32-bit/40-bit floating-point processor optimized |
| MTB | (164) | MOT | D2PAK | 07+ | 1. Hitachi neither warrants nor grants licenses of any rights of Hitachis |
| MTC | (313) | ACATEL | QFP | 1/ Separate samples may be used for each step. In the event of a g | |
| MTD | (453) | 98 | Why Are Pulsed LEDs Brighter Than DC LEDs? There are two main reas | ||
| MTE | (18) | N/A | I.2 - Read Operation The address of the first register to read is progra | ||
| MTF | (12) | SEIKOEPSON | QFP | 1991 | |
| MTG | (8) | Reset will terminate any operation, e.g., Read, Erase and Program, in prog | |||
| MTH | (83) | The L Family is a Low Power version of the CH1817 DAA. When Off-Hook, thi | |||
| MTI | (10) | MTI | PLCC | 95+ | RFMs TX-series hybrid transmitters are specifically designed for short-ra |
| MTJ | (35) | AD | 06+/07+ | The TLC372 has internal electrostatic discharge (ESD) protection circuits | |
| MTK | (16) | MTK | 06+ | BGA | Notes: 1) Current CEPT/ETSI regulations: CEPT REC 70-03 Annex 1, ETSI EN |
| MTL | (54) | MYSON | . | The EM785830AA is an 8-bit RISC type microprocessor with low power | |
| MTM | (209) | MOT/ON | TO-3 | 07+ | DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . . -0.5V to + |
| MTN | (10) | LEDTECH | The AD581 can also be used in a two-terminal mode to develop a positive | ||
| MTO | (6) | VIKKO | 00+ | QFN吕波 | • High-speed access time: 10, 12, 15, and 20 ns • CMOS low p |
| MTP | (452) | ON | 06+ | †Purchase of I2C components from Maxim Integrated Products, Inc. or | |
| MTQ | (8) | Can Be Used in Three Combinations: C OR-AND Gate C OR Gate C AND Gate | |||
| MTR | (15) | AGERE | 02+ | BGA/9*9 | The devices accept 4- or 5-bit words at the data input (DI0 C DIn) under |
| MTS | (174) | LUCENT | BGA | N/A | Hynix HYMD216646(L)6-K/H/L series incorporates SPD(serial presence detect) |
| MTT | (24) | MYSON | QFP | 94 | Notes: 2. Multiple Supplies: The voltage on any input or I/O pin ca |
| MTU | (14) | 01 | 5V tolerant inputs and outputs 10 mA ICCQ max Power-down high impedance | ||
| MTV | (376) | N/A | N/A | N/A | Transmit Positive Data Input. TTL input for a positive polarity pulse (th |
| MTW | (45) | FRE | TO | ||
| MTX | (6) | LOGIC | QFP | 07+ | • IN-SYSTEM PROGRAMMABLE In-System Programmable (ISP™) |
| MTY | (14) | MOT | TO-3PL | 04+ | Secured Silicon Sector: Extra 256 Byte sector Factory locked and |
| MTZ | (346) | ROHM/00+ | N/A | 0 | The MAX5236/MAX5237 precision, dual, voltage-out- put, 10-bit digital-to- |
| M-U | (6) | Ultra Low Dropout300 mV at 300-mA Load Ultra Low Noise30 mVRMS (10-Hz t | |||
| MU- | (3) | ZILOG | DIP | 02+ | Erase (ERASE) After the erase instruction is entered, CS must be brought |
| MU0 | (33) | Stanley | 00+ | Input Voltage Range: 3.0V to 5.5V Regulated 5V Output | |
| MU1 | (14) | DSI | n/a | SAMPLE CLOCKS DATACLK, SHP, SHD Clock Period DATACLK High/ | |
| MU2 | (10) | MOT | 金属帽 | 8617 | 3-A Low-Dropout Voltage Regulator Available in 1.5-V, 1.8-V, 2.5-V, and 3 |
| MU3 | (12) | QFP | Bus Manager/Isochronous Resource Manager (IRM) Contender programming in | ||
| MU4 | (7) | ROHM | SOP | 02+ | Note 8: CPD is defined as the value of the internal equivalent capacitanc |
| MU5 | (13) | 07+ | Edition 1998-10-08 Published by Siemens AG, Bereich Halbleiter, Marketin | ||
| MU6 | (5) | *Absolute maximum ratings apply at 25C, unless otherwise noted. Stresses | |||
| MU8 | (7) | Panasonic | PLCC | When low, "A" & "B" data is present on its respec | |
| MU9 | (343) | MUSIC | 07+ | All 240xA devices offer at least one event manager module which has been | |
| MUA | (27) | MUSIC | 07+ | 4ž_ÞÐW FUNC [1]‘ôDÈ Aœ Ah FUNC | |
| MUB | (48) | 1850 | |||
| MUC | (2) | QFP | PANASONIC | 04+ | 2.2 Order of precedence. In the event of a conflict between the te |
| MUD | (1) | ON | SOT-23 | The command register itself does not occupy any addressable memory locatio | |
| MUF | (1) | ASIC | SOP | 07+ | the latches store information that was present on the D inputs a setup |
| MUG | (2) | SAMYOUNG | 06+ | The ISL6227 dual PWM controller delivers high efficiency precision voltag | |
| MUK | (2) | SAMYOUNG | 05+ | 1. MTTF calculator available at http://www.freescale.com/rf. Select Tools | |
| MUL | (12) | Dual axis accelerometer on a single IC chip 5 mm 5 mm 2 mm LCC package | |||
| MUM | (6) | MOTOROLA | SMD6 | O419 | improve its serial transmission characteristics. These encoded character |
| MUN | (379) | ON | SOT-23 | 05+ | Cases: TO-220 molded plastic Epoxy: UL 94V-0 rate flame retardant Term |
| MUO | (1) | These Darlington arrays are furnished in 16-pin dual in-line plast | |||
| MUP | (1) | 127 | ST | 03+ | NTSC-M, PAL-M/B/D/G/H/I Composite, S-Video & YCrCb component video ou |
| MUR | (736) | HARRIS | TO-220 | 02+ | Output Voltage Integral Color LEDs and Matching Color Filters on Sensors |
| MUS | (22) | crystal | crystal | dc96 | This Logic Level Insulated Gate Bipolar Transistor (IGBT) features |
| MUT | (5) | SMD | 01+ | Integral nonlinearity is the deviation of the analog value at any | |
| MUX | (114) | AD | DIP | 04+ | The SSM2165 is a complete and flexible solution for condition- ing micro |
| M-V | (1) | The information provided herein is believed to be reliable at press time. | |||
| MV- | (9) | DIP-28 | The 6N137, HCPL-2601/2611 single-channel and HCPL-2630/2631 dual-channel | ||
| MV0 | (14) | PS | DIP-08P | 8526 | The MSK 4220 is a complete H-Bridge circuit to be used for DC brus |
| MV1 | (107) | UCC | 07/08+ | The information provided herein is believed to be reliable; however, BURR | |
| MV2 | (54) | MIT | 511 | The open-collector outputs are connected to a 28-V Z-diode. The collector | |
| MV3 | (122) | MTEKVISION | BGA特价 | 07+ | V1: Minimum absolute applied voltage corresponding to maximum opt |
| MV4 | (19) | MITEL | N/A | 07+ | This active input determines the cycle type when ADV is LOW. This is the |
| MV5 | (287) | FAIRCHILD | 05/06+ | This family is a 64M bit dynamic RAM organized 4,194,304 x 16-bit configur | |
| MV6 | (155) | N/A | SOP-28 | • The products described in this document are subject to the foreign | |
| MV7 | (59) | ST | SOT-223 | 2004 | NOTES 1Oversampling disabled. Static DAC performance will be improved wi |
| MV8 | (187) | FAIRCHILD | 06+ | 发光管 | Output voltage amplitude at f=1 kHz such that total output harmonic distor |
| MV9 | (15) | FAIRCHILD | 05/06+ | Note 5: The maximum allowable power dissipation is a function of the maxi | |
| MVA | (83) | MITEL | SOP18 | 01+ | In burst mode the A/D converter does repeated conversions at the rate sele |
| MVB | (3) | 1850 | If the TO-263 package is used, the thermal resistance can be reduced by i | ||
| MVC | (7) | CDIP16 | 2007+ | The SSTV16857 is intended to be incorporated into standard DIMM (Dual In | |
| MVD | (19) | N/A | NOTE:2677 tbl 04 1. Stresses greater than those listed under ABSOLUTE MA | ||
| MVE | (8) | NA | 03+ | These edge-triggered multivibrators feature output pulse-duration contr | |
| MVF | (3) | ADVANIEK | 03+ | Miniature,cost-effective switching solution. Molded construction for comp | |
| MVG | (11) | SAMYOUNG | 06+ | Member of the Texas Instruments Widebus™ Family TI-OPC™ Circ | |
| MVH | (5) | The HYM72V32M656H(L)T6 Series are Dual In-line Memory Modules suitable for | |||
| MVI | (4) | WVI | The UCC3808A family offers a variety of package options, temperature rang | ||
| MVJ | (5) | 07+ | Note : 1. Load and line regulation are specified at constant junction tem | ||
| MVK | (52) | nic | nic | dc99 | Out (pin 7) This is the main timing chain output. It has a |
| MVL | (18) | LECROY | 00+ | Allows Safe Board Insertion and Removal from a Live Backplane Controls S | |
| MVM | (18) | MSI | SOLT40 | 94+ | Measurement place A place that is nothing of extreme light reflected in t |
| MVN | (5) | Bild/Fig. 5 Grenzstrom je Zweig IF(OV)M bei Luftselbstkhlung, tA=45C und | |||
| MVP | (20) | ccube | ccube | dc98 | Please be aware that an important notice concerning availability, |
| MVQ | (44) | ZARLINK | TQFP | ||
| MVR | (118) | ROHM | 3X3-4.7K | 05+ | Hynix HYMD264M646A(L)F8-J/M/K/H/L series is unbuffered 200-pin double data |
| MVS | (31) | ASTEC | 2007 | The EBD10RD4ADFA is 128M words 72 bits, 1 rank Double Data Rate (DDR) SD | |
| MVT | (60) | MITEL | 03/04+ | The ICS950703 is part of a whole new line of ICS clock generators and buf | |
| MVU | (3) | The MVU14-6FB/SK/MVU14-6FB/SK are dual precision, 16-/14-bit, multiplyin | |||
| MVV | (5) | ON | SOT323 | The MVVC403/MVVC403 are high speed comparators fabricated on Analog Devi | |
| MVW | (1) | The SN74GTLPH1645 is a high-drive (100-mA), 16-bit bus transceiver partit | |||
| MVX | (4) | PMI | 95+ | •Built-in DC-DC converter circuit for PWM function •Built-in | |
| MVY | (10) | nec | nec | dc02 | Communications Diversity radio systems Multimode digital receivers: &nb |
| MVZ | (6) | nec | nec | dc02 | Efficient 16-bit 56800E family engine with dual Harvard architecture Up |
| MW- | (7) | PHILIPS | SOIC-16 | 07+/08+ | (Unless otherwise indicated, copies of the above specifications, s |
| MW0 | (13) | LUCENT | 模块 | 02+ | The absolute maximum temperature under any condition is li |
| MW1 | (28) | NEC | 05+ | PLCC | The 20mA current source starts to charge up the exter- nal capacitor. In |
| MW2 | (9) | TAIWAN | SOT-323 | 05+ | 2.5V to 20V Step Down Achieved Using Dual Input Output Voltage down to |
| MW3 | (6) | AELTA | 04+/05+ | An electrical circuit model is shown in Figure 1-4. The coupling capacit | |
| MW4 | (36) | FREESCALE | 06+ | The Si91871 is a 300-mA CMOS LDO (low dropout) voltage regulator. It is | |
| MW5 | (14) | SMD | FREESCALE | 0502+ | Radial taping is applied to lead type and plastic taping to chip type. Wi |
| MW6 | (16) | Freescale/Motorola 07+ | Temperature Sensor Two Quadrature Decoders Optional | ||
| MW7 | (5) | TO-3P | The 256Mb DDR SDRAM uses a double-data-rate archi- tecture to achieve h | ||
| MW8 | (3) | MAXWELLS | TO-252 | 06+ | Buffered Reference Mode Unbuffered Reference Mode Buffered Reference Mod |
| MWA | (26) | ON | SOT143-0G | ||
| MWB | (1) | Soft Start The soft-start circuit limits inrush current when the device | |||
| MWC | (1) | N/A | N/A | 04+ | Synchronous circuitry allows for precise cycle control triggered |
| MWD | (7) | IPD | 2007 | * All specs and applications shown above subject to change without prior | |
| MWE | (3) | For A-to-B data flow, the device operates on the low-to-high transition o | |||
| MWH | (1) | N/A | N/A | 04+ | This CMOS device is designed for switching PCM-encoded voice or da |
| MWI | (42) | IXYS | The value of Ki may also be slightly different at the extremes of the | ||
| MWL | (2) | 3225 | The output stage of most power amplifiers has three distinct limitations | ||
| MWM | (6) | When valid data on the TX pins detected, the jabber timer is started. I | |||
| MWP | (4) | ON | SOT-323 | 05+ | The EL2244 and EL2444 also feature an extremely wide output voltage swi |
| MWS | (36) | N/A | dualoct received from the DQA/DQB data pins of the Channel to be loaded | ||
| MWX | (1) | The ADSP-TS202S processor has compute blocks that can exe- cute computat | |||
| MX- | (17) | DATEL | DIP | DIP | Collector-emitter voltage peak value Collector-Base voltage (open emitt |
| MX/ | (1) | N/A | N/A | N/A | Maximum Ratings are those values beyond which damage to the device may oc |
| MX0 | (93) | SK | 05+/06+ | † All characteristics are measured with zero common-mode input volt | |
| MX1 | (126) | MX | 88 | 2850 | In all modes, the output clocks are frequency-locked to the input. The ou |
| MX2 | (1219) | MX | 08+ | Many conditions affect the thermal performance of the power modul | |
| MX3 | (48) | N/A | QFP112 | The emulator consists of a base unit that connects to the PC by way of t | |
| MX4 | (35) | NVIDIA | BGA | 05+ | The DS1543 is in the read mode whenever CE (chip enable) is low and WE ( |
| MX5 | (143) | CAN | CAN | Notes: 1. NC pins are not connected to the die. 2. C2 (DNU) | |
| MX6 | (105) | MXIC | Note: 1) Inverter low-side is composed of three sense-IGBTs including fre | ||
| MX7 | (705) | AD | SOP | 04+ | When the ECU experiences a loss of ground condition, this pin switch to a |
| MX8 | (127) | MXIC | 07+ | The device includes an 8x digital interpolation filter for PCM signals. | |
| MX9 | (120) | Drain-to-Source Breakdown Voltage Gate Threshold Voltage Gate-to-Sourc | |||
| MXA | (13) | MAX | SOP-24 | 99 | 2.1.1 @cificatiom, standxds, and handhxwks. fie fcJlwing ~ificatio |
| MXB | (21) | 2000 | The MAX5069A evaluation kit (EV kit) is a fully assembled and tested circ | ||
| MXC | (13) | 04+ | NOTES: 1. Data inputs must be low a minimum time of tACT max., after RES | ||
| MXD | (52) | MAXIM | SC70-3 | 07+ | functional operation of the device at these or any other condition |
| MXE | (2) | 02+ | (*) Our SO-8 package used for Voltage Regulators is modified internally t | ||
| MXF | (52) | TDK | 3(1206) | 05+ | TapePak and TRI-STATE are registered trademarks of National Semiconductor |
| MXG | (1) | MURATA | © Siemens AG 1996. All Rights Reserved. As far as patents or other | ||
| MXH | (2) | TSINGHUA | 00+ | The HD404318 Series is 4-bit HMCS400-series microcomputer with large-capa | |
| MXI | (1) | MAX | SOP | Note: (1) This parameter is tested initially and after a design or proce | |
| MXJ | (6) | PREMIER | 02+ | Power247™ PowerEdge™ PowerSaver™ PowerTrench® QF | |
| MXK | (2) | DIP20 | Case: SC-59, Molded Plastic Case material - UL Flammability Rating 94V-0 | ||
| MXL | (120) | 50 | NULL | NULL | 3. Measured by the voltage drop between A and B pins at the indicated cur |
| MXM | (21) | MOT | 07+ | TXENABLE has two purposes. In all modes, TXENABLE must be high for the DA | |
| MXN | (2) | NOTES: 1. All VDD pins must be connected to 3.3V power supply. 2. All VD | |||
| MXO | (96) | CTS | SOP | 517 | These devices employ the Schottky Barrier principle in a metal |
| MXP | (3) | MEDIAXPRESS | 06-07+ | These power transistors are produced by PPC's DOUBLE DIFFUSED PLANAR pro | |
| MXQ | (1) | Normally the PWM comparator will sense a ramp crossing a control voltag | |||
| MXR | (6) | MEMSIC | 04+ | Functions To provide memory addresses. During sector erase A19-A11 addre | |
| MXS | (11) | N/A | SOP-28 | ** Required for stability. Must be rated for 10 µF minimum over int | |
| MXT | (43) | Thaler Corporation has developed a nonlinear compensation network of ther | |||
| MXU | (2) | SYNERGY | PLCC | Maximum ratings are those values beyond which device damage can occur. M | |
| MXW | (1) | Port 0 (AD0C7), I/O. Port 0 is an open-drain, 8-bit, bidirectional I/O p | |||
| MXZ | (1) | n Clock recovery from PLL lock to random data patterns. n Guaranteed tr | |||
| MY- | (11) | OMRON | 04+ | The CS4344 family is based on a fourth order multi-bit delta-sigma modula | |
| MY1 | (2) | N/A | SOP-10 | The DS2745 provides current-flow, voltage, and temperature measurement da | |
| MY2 | (41) | mot | mot | dc92 | Cin = Required 1000µF electrolytic Cout= Required 330µF elect |
| MY3 | (4) | The operation of these three multifunction inputs depends on the setting | |||
| MY4 | (37) | OMRON | Relay(DZ) | 00+ | The Intersil HSP45240 is a high speed Address Sequencer which provides |
| MY5 | (5) | M/A-COM | Limits in standard typeface are for TJ = 25˚C, bold typeface applies | ||
| MY6 | (4) | TAOperating free-air temperature−4085C NOTE 3: All unused in | |||
| MY7 | (5) | M/A-COM | 1. Specifications typical at Ta=+25],resistive load,nominal input voltage | ||
| MY8 | (18) | MOSART | 04 | Note 2: Operating Ratings indicate conditions for which the device is fun | |
| MY9 | (2) | M/A-COM | NOTES 1NSV features enabled. 2DNL measures the deviation of the actual D | ||
| MYB | (5) | Guaranteed Logic HIGH Level Guaranteed Logic LOW Level Standard Input(4) | |||
| MYC | (1) | ST | TQFP-176 | The Am29F016 is a 16 Mbit, 5.0 Volt-only Flash memory organized as 2 Me | |
| MYK | (1) | The AT49BV16X4(T) is 2.7 to 3.6 volt 16-megabit Flash memory organized as | |||
| MYL | (11) | MYLEX | QFP160 | LCD Segment output terminal / LCD Common output terminal SEG40 in 1/3Duty | |
| MYM | (2) | LG | 06+ | where frequency is in hertz, resistance in ohms, and capacitance in farad | |
| MYR | (2) | ROHM | 2X2-200R | Parameter AVDD to GND1 AVDD to DVDD VP to GND VP to AVDD Digital I/O | |
| MYS | (8) | D | SOP10 | The TAR5SBxx Series is comprised of general-purpose bipolar singl | |
| MYU | (2) | ||||
| MYV | (1) | Pb−Free Package is Available Small Compact Surface Mountable Packa | |||
| MYW | (2) | LAMBDA | The HS-800/810 Series of quartz crystal oscillators provide MECL 10K and | ||
| MZ- | (9) | PH | 08+ | Note: Fix all unused input pins to high or low level. Generally, | |
| MZ0 | (8) | TOYODA | DIP | Features 1) The built-in bias resistors consist of thin-film resis | |
| MZ1 | (11) | N/A | N/A | N/A | There are two kinds of logic blocks, the Programmable Functional Unit (PF |
| MZ2 | (10) | TDK | Short Circuit Withstand: Suitable for use on a circuit capable of delive | ||
| MZ3 | (19) | DSI | n/a | The functions of the device include analog input multiplexing, on-chip | |
| MZ4 | (29) | Motorola | 92 | So, with RSET = 4.7kΩ, ICPmax = 2.5mA. This multiplexer output allo | |
| MZ5 | (8) | PHILIPS | SMD | 99+ | TRI-STATE is a registered trademark of National Semiconductor Corporation |
| MZ6 | (2) | The LH1526 relay is two SPST normally open switches that can replace el | |||
| MZ7 | (8) | M/A-COM | The HD404849 series of HMCS400-series microcomputers is designed to incre | ||
| MZ8 | (5) | M/A-COM | On the next clock rise the data presented to DQs and DQP[A:B] (or a subse | ||
| MZ9 | (4) | The TC650/TC651 acquire and convert their junction temperature (TJ) inf | |||
| MZA | (49) | N/A | 0402X2 | Recordings are stored in on-chip nonvolatile memory cells, providing zer | |
| MZB | (1) | Mini Small Outline Package (MSOP) Mini Small Outline Package (MSOP) Mini | |||
| MZC | (26) | MODULE | Hynix HYMD512G726(L)4-K/H/L series is designed for high speed of up to 133 | ||
| MZD | (5) | N/A | N/A | 04+ | Guaranteed 1% output voltage tolerance (LM317A) Guaranteed max. 0.01%/V |
| MZE | (2) | QFP | 1999 | The MAX422_EUT is 100% production tested at TA = +25C. Specificati | |
| MZF | (2) | Used as input or output fuses for surge-sensitive compo- nents, such as | |||
| MZG | (2) | TEMIC | Note: Agilent Technologies encoders are not recommended for use in safet | ||
| MZJ | (1) | Single supply: 1.8 V to 5.5 V Two-wire serial interface (I2CTM serial bus | |||
| MZK | (25) | MODULE | (5) Capacitor Selection A low ESR (Equivalent Series Resistance) | ||
| MZM | (8) | ON | 23-3V | Complete PWM Power Control 3.6-V to 40-V Operation Internal Undervoltage | |
| MZP | (34) | N/A | N/A | 04+ | Note: (1) The minimum DC input voltage is C0.5 V. During transitions, in |
| MZQ | (1) | TEMIC | All part numbers end with a place code, designating the silicon-die revis | ||
| MZS | (6) | PH | 07+ | NOTES: 1. Dimensions are in inches. 2. Metric equivalents | |
| MZT | (4) | DENSO | • 16-bit I/O timer 16-bit free-run timer : 1 channel | ||
| MZU | (1) | ABC | 00+ | The LM45 series are precision integrated-circuit temperature sensors, w | |
| MZV | (3) | The EP111 is specifically designed, modeled and produced with low | |||
| MZW | (3) | QTC | 05+ | SOP-8 | The output stage of the MD1811 has separate power connections enabling th |
| MZX | (3) | OKI | Direction of Rotation: When the codewheel rotates in a counter- clockw |
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