| Mfg | pack | D/C | Descrpion | ||
| N/E | (1) | ||||
| N/N | (1) | ||||
| N/P | (39) | ||||
| N/R | (1) | ||||
| N/S | (3) | ||||
| N-0 | (1) | NEC | 94 | Applications • Mobile telecommunication C Cellular phone & | |
| N0. | (2) | JAT | SOT | 05+ | ANALOG-TO-DIGITAL CONVERTER (INCLUDING MUX AND ATTENUATORS) Total |
| N00 | (85) | NEC | 94 | • Hole-less clip/pressure mount package compatible with TO- | |
| N01 | (33) | SAMSUNG | QFP | OO | register, the IDT70V7519 has been optimized for applications having unidi |
| N02 | (28) | DSI | n/a | The TP3054, TP3057 family consists of µ-law and A-law monolithic | |
| N03 | (6) | N/A | N/A | N/A | DESCRIPTION The HOA0901 sensor consists of a dual channel IC detector a |
| N04 | (17) | NEC | 98+ | 35000 | The PCF84C12A, PCF84C22A and PCF84C42A are general purpose CMOS microco |
| N05 | (2) | 34 | MICROCHIP | 99+ | The ROHM Diode Manufacturing Department has developed PIN diodes optimiz |
| N06 | (13) | DSI | n/a | Notes: 1. IDD Dynamic is the IC current while clocking column data throug | |
| N07 | (2) | 71 | FAIRCHIL | 04+ | The result of the coercive field of the magnetic circuit With a di/dt of |
| N08 | (39) | Signal data can be accepted at rates up to rxclk in UMTS mode for either | |||
| N09 | (5) | QFN | 06+ | The HEF4094B is an 8-stage serial shift register having a storage latch | |
| N0G | (1) | WRITE PROTECT: The write protect pin (WP) will allow normal read/write op | |||
| N0J | (3) | To lower power dissipation in the regulator, a dropping resistor can be | |||
| N0L | (1) | Unlike the other two modes that accept only a single specified input freq | |||
| N0R | (1) | Note 10: The given JA is for an HWD2119 package in an LDA08B with the Expo | |||
| N0X | (1) | 1. The ICS clock generator is a slave/receiver, I2C component. It can re | |||
| N-1 | (1) | a separate VCCIO reference input which is independent of the main VCC s | |||
| N1. | (1) | The availability of the amplifier bias current (IABC) terminal significa | |||
| N10 | (53) | VTI | DIP-8 | 04+ | • High-speed access time: 10, 12, 15, and 20 ns • CMOS low p |
| N11 | (13) | N/A | N/A | N/A | Analog output. The output signal has a maximum amplitude of 2.4 VPP above |
| N12 | (59) | CAN3 | The information contained in this document is being issued in advance of | ||
| N13 | (10) | MOTOROLA | The primary color output (pins 29, 31, 33) and COMMON output (pin 27) are | ||
| N14 | (24) | KYOCERA | MQFP | 2000 | 24421-009-DTS Rev ADQ# 2009 All technical information is believed to be |
| N15 | (88) | MOTOROLA | 2005 | Note 3: Without a heat sink, the thermal resistance of the TO-3 package i | |
| N16 | (42) | N/A | 0603B | The LVTH240 data inputs include bushold, eliminating the need for extern | |
| N17 | (25) | High Side Driver Output. This pin must be connected to the gate of the ha | |||
| N18 | (5) | The GS1545 is a high performance integrated Equalizing Receiver designed | |||
| N19 | (22) | EPCOS | ZIP-5 | 07+/08+ | The VCO accepts analog control inputs from the PLL filter block. The FS |
| N1A | (7) | NEC | TO-92S | 00+ | Initiating A Conversion Please refer to Figure 4. The SP8480 was de- si |
| N1E | (1) | Collector-to-Emitter Breakdown Voltage Continuous Collector Current (Fi | |||
| N1F | (4) | NEC | TO92S | NOTE: Device will meet the specifications after thermal equilibrium has b | |
| N1L | (6) | NEC | TO92S | Programmable 64-bit encoder crypt key Two 64-bit IFF keys Keys are rea | |
| N1N | (5) | ST | SOT-223 | Addresses and data needed for the programming and erase operations are | |
| N1X | (1) | VISHAY | 2008 | First ASIC replacement FPGA for high-volume production with on-chip RAM | |
| N20 | (42) | 0805BEAD | Notes : 1. * Checked No Connect(NC) pins are reserved for higher density a | ||
| N21 | (17) | NEC | SOT-23 | 05+ | • On-board single power supply (VCC): VCC = 2.7 V to 3.6 V • Or |
| N22 | (7) | TI | SOP8 | Select data in or data out on SDA or Measurement latching for transmissio | |
| N23 | (3) | FAIRCHILD | SSOP8 | 01+ | 0 V dc Bias +0.5 V dc Bias DC to 100 MHz; VDD = 2.5 V 10% 500 MHz; VDD |
| N24 | (4) | PDIP48 | 00+ | Please be aware that an important notice concerning availability, | |
| N25 | (58) | SI | TO-92 | 04+ | The temperature of the lead should be measured using a thermocouple pla |
| N26 | (28) | wes | n/a | Address Inputs Byte/Word Enable Data In / Data out Data In/Out (Wor | |
| N27 | (56) | INTEL | PLCC32 | All MAX® II devices provide Joint Test Action Group (JTAG) boundary- | |
| N28 | (130) | INTEL | PLCC-32 | Table 1. Electrical Specifications ItemSpec. Input and Output Impedance5 | |
| N29 | (20) | PANASONIC | QFP | 95+ | The functions for this block are: 1. Decode the internal address bus to |
| N2C | (1) | − Active Mode: 200 µA at 1 MHz, 2.2 V − Standby Mode: 0 | |||
| N2D | (8) | Elixir | 07+ | Like all members of the FLASH370i family, the CY7C372i is rich in I/O res | |
| N2N | (5) | ST | 管 | The GS4882 and GS4982 differentiate between valid and in- valid input sig | |
| N2S | (3) | Elixir | 07+ | s Data Management Software (DMS) AMD-supplied software manages | |
| N3- | (1) | The Intel 80C186XL is a Modular Core re-implementation of the 80C186 micr | |||
| N30 | (27) | TOSHIBA | 07+/08+ | The circuit makes use of a peak hold capacitor, CHOLD, at the output of t | |
| N31 | (19) | S | 陶DIP16 | 99+ | 4. Slide the HEDS-8905 or HEDS- 8906 centering tool over |
| N32 | (49) | FSC | TO-220 | 07+ | The M28R400C is a 4 Mbit (256Kbit x 16) non-vol- atile Flash memory tha |
| N33 | (17) | IC | alpha/skyworks | 99+ | tLOW Low Period of SCL Clock tHIGH High Period of SCL Clock tSU;STA Setu |
| N34 | (84) | SAMSUNG | QFP | 01+ | NOTES 1Tester measures code transitions by dithering the voltage of the |
| N35 | (22) | SOT23-5 | 05+ | The tone controls, the essential elements of the feedback system, are l | |
| N36 | (9) | QFP | 05/06+ | The CY7C133/143 has a flow-through architecture that facili- tates repeat | |
| N37 | (35) | SSOP | alpha/skyworks | 99+ | |
| N38 | (14) | TSSOP | alpha/skyworks | 02+ | 90% of Vcc MIN.; 10% of Vcc MAX. 15 pF is standard. Contact factory for h |
| N39 | (14) | TSSOP | alpha/skyworks | 99+ | Operating temperature range is: C40C to +85C. Guaranteed b |
| N3A | (2) | NKK | MQFP | 1995 | PORT I is an 8-bit Hi-Z input port The 28-pin device does not have a ful |
| N3N | (3) | ST | SOT-223 | 04+ | Continuous Drain Current, VGS @ 10V (Silicon Limited) Continuous Drain |
| N3P | (1) | ST | TSO-223 | 05+ | Contains Eight D-Type Flip-Flops With Single-Rail Outputs Clock Enable L |
| N3R | (1) | NKK | 7210 | System Resources, some of which have been previously listed, provide add | |
| N4. | (1) | LNB selection and standby function Provides up to 500 mA load current | |||
| N40 | (31) | TQFP-100P | AGERE | 05+ | |
| N41 | (17) | NEC | FIG31 | The transceiver performs the data parallel-to-serial and serial-to-parall | |
| N42 | (5) | UART channel A Transmit Data or infrared encoder data. Standard transmit | |||
| N43 | (10) | Bild/Fig. 5 Grenzstrom je Zweig IF(OV)M bei Luftselbstkhlung, tA=45C und | |||
| N44 | (3) | 0 | 0 | Note 1) The specified condition Tj=25˚C means that the test should | |
| N45 | (21) | ST | * Antiparallel diode for high frequency switching devices * Antis | ||
| N46 | (10) | 07+ | The HY51V(S)17403HG/HGL is the new generation dynamic RAM organized 4,194, | ||
| N47 | (4) | 07+ | NOTES 1Measured single-ended into 50 W load. 2Output noise is measured w | ||
| N48 | (7) | 07+ | A four-wire (SCLK, MOSI, MISO, SS) SPI interface is provided for ISD5008 | ||
| N49 | (8) | The read or write mode is selected through W. A logic high on W selects t | |||
| N4C | (2) | All signals are TTL levels, including programming sig- nals. Bit locati | |||
| N4H | (2) | To retain data, 1,024 refresh cycles are required in each 16 ms period. | |||
| N4N | (2) | ST | TO-223 | Collector-to-Emitter Voltage Continuous Collector Current Continuous | |
| N5- | (1) | • Operating temperature from - 55 C to + 110 C • No Base Te | |||
| N50 | (20) | vac | 01+ | Precision Optical Performance AlInGaP II (aluminum indium gallium phosph | |
| N51 | (13) | CAUTION | SOJ | 07+ | 1. Controlling Unit: millimeter. 2. Tolerance on the true position of the |
| N52 | (23) | IC | SOP | − Active Mode: 160 µA at 1 MHz, 2.2 V − Standby Mode: 0 | |
| N53 | (13) | N/A | SMD | 95+ | This popular Transient Voltage Suppressor (TVS) series for 1N6036 thru 1N |
| N54 | (27) | ST | 06+ | 399 | This digital clock is designed for use with high-speed CPUs and communicat |
| N55 | (20) | 05+ | 514 | SOT-263 | The N550AD is a Silicon Microwave Monolithic Integrated Circuit designe |
| N56 | (7) | QFN | Skywoks | 01+ | Notes: Stresses greater than those listed under MAXIMUM RATINGS may cau |
| N57 | (8) | ALPHA | 02+ | The IGBT is ideal for many high voltage switching applications operatin | |
| N58 | (11) | BGA | 02+ | This device contains circuits to protect its inputs and outputs against d | |
| N59 | (9) | CAN3 | 1. Device mounted on FR-4 PCB, 1 inch x 0.85 inch x 0.062 inch; pad layout | ||
| N5A | (4) | NIPPON | (LX)high-frequency | CAP: A capacitor is normally connected between this pin and GND providin | |
| N5C | (15) | INTEL | PLCC44 | 03/+04+ | • High Reliability - NEL HALT/HASS qualified for crystal osc |
| N5D | (3) | N/A | N/A | N/A | The 16-bit synchronization counter is the basis behind the transmitted |
| N5M | (2) | MIT | TSOP | 00+ | The UC3854A/B products improve upon the UC3854 by offering a wide bandwid |
| N5N | (2) | N/A | N/A | Notes: 2. The voltage on any input or I/O pin cannot exceed the po | |
| N5S | (2) | SMD Low profile 5 pin package Isolation Test Voltage 5000 VRMS CTR fle | |||
| N5W | (1) | N/A | DIP2 | 06+ | The N5W562 is an audio power amplifier primarily designed for driving C |
| N-6 | (2) | TAMRA | 07+/08+ | Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output | |
| N6- | (1) | While the LM2936 maintains regulation to 60V, it will not withstand a s | |||
| N60 | (21) | QFN-12 | Skywoks | 01+ | The ZL5011x incur very low latency for the data flow, thereby increasing |
| N61 | (3) | PHILIPS | TSSOP20 | The 8-bit program status word (PSW) controls ALU operations and in | |
| N62 | (8) | MIT | SSOP36 | The Fairchild portfolio of Star*Power FETs includes a family of devices | |
| N63 | (10) | CRACK | . | 02+ | The VGA CMOS image sensor features DigitalClarity Microns breakthrough l |
| N64 | (10) | N/A | SMD | 99+ | The LC/LV/LD549 is an 8 pin, low voltage, push-pull audio frequency outpu |
| N65 | (9) | FAIRCHILD | 05/06+ | 1) Connect the electronic load (+) terminal to the VOUT banana jac | |
| N66 | (5) | ALPHA | 02+ | Three UART serial ports for data/testing/Bluetooth USB (version 1.1) Ana | |
| N67 | (3) | 00+ | 300 | One independent programmable bi-level 1D-resolution conversion block is | |
| N68 | (10) | . | 250 ps propagation delay input to output 50 ps propagation delay dispers | ||
| N69 | (4) | ALPHA | 02+ | 400 MSPS Internal Clock Speed Integrated 14-bit D/A Converter Programmab | |
| N6C | (1) | Thermal Design The IRU1261 incorporates an internal thermal shutdown tha | |||
| N6L | (3) | piher | piher | dc05 | BUS HIGH ENABLE/STATUS: During T1 the bus high enable signal (BHE) should |
| N6S | (4) | Note: Fix all unused input pins to high or low level. Generally, | |||
| N-7 | (1) | EPSON | 1996 | QFP | Note 3: Absolute Maximum Ratings indicate limits beyond which damage to t |
| N70 | (97) | SIEMENS | 07+ | The size and placement of the capacitors for the main voltage bus for th | |
| N71 | (79) | ST | SMD-20 | 0539+398PCS,0611+839PCS | When RST is driven high, the value on ROMA07 C ROMA00 is latched into the |
| N72 | (6) | N/A | SMD | 97+ | In addition to the data sheet changes made above due to product enhanceme |
| N73 | (4) | N/A | SMD | 89+ | Antiparallel diode for high frequency switching devices Antisaturation |
| N74 | (949) | 00 | Note 3 The SK frequency specification specifies a minimum SK clock period | ||
| N75 | (58) | IRELAND | The MC623 is a 3.0 V solid-state, programmable temperature sensor | ||
| N76 | (111) | N/A | PLCC | 98+ | The RC32355 contains an on-chip Ethernet MAC capable of 10 and 10 |
| N77 | (6) | MOTORO | 00+ | This device contains protection circuitry to guard against damage | |
| N78 | (7) | 98 | The N7841V3, N7841V3B, N7841V3, and N7841V3 devices are part of the TMS3 | ||
| N7C | (1) | MICROCOM | PLCC-44 | 04+ | The first six digits number shows lot number. The lot number is composed |
| N7E | (18) | 3m | 3m | dc02 | The SuperFlash technology provides fixed Erase and Program times, indep |
| N7G | (1) | CHIPEXPRESS | 9730 | at the transistor level and verified through measurements made on fabric | |
| N7M | (1) | JRC | DIP8 | 03+ | the device can work also with dynamic ones). Many of its electrical cha |
| N7N | (1) | ST | TO-223 | Motorola reserves the right to make changes without further notice to any | |
| N7R | (1) | N/A | SMD | 2000 | Der dargestellte Berechnungsmodus stellt eine Näherung der tatsä |
| N7S | (1) | N/A | NSC | 04+ | b: ICC1 and ICC3 are dependent on output loading and cycle rate. The spec |
| N-8 | (1) | CMD | SOP-18 | 97+ | This new generation of Trench MOSFETs from Zetex utilizes a unique structu |
| N8- | (1) | SOP-14 | 98+ | High performance and low cost solution Synchronous operation with high ef | |
| N80 | (642) | INTEL | PLCC-44 | 07+/08+ | The logic block is the basic building block of the Ultra37000 architectur |
| N81 | (19) | INTEL | PLCC44 | 05+ | If the N81C66 is in a nonvolatile write cycle a no ACK (SDA=High) respo |
| N82 | (518) | INTEL | 07+ | 6. Solder Gap Identification (See Figure 2): Each solder gaps respective | |
| N83 | (44) | INTEL | SOP | • Pout>13W, çT>40% @ VDD=12.5V, VGG=5V, Pin=50mW | |
| N84 | (1) | INTEL | PLCC | 07+ | 4.5.2 Group B inspection. Group B inspection shall be conducted in |
| N85 | (50) | 92 | 1. Renesas Technology Corp. puts the maximum effort into making semiconduc | ||
| N86 | (1) | The device is enabled when the EN pin is connected to a low-level input v | |||
| N87 | (180) | INTEL | 06+ | 397 | The inhibit function is provided by the Inhibit* control, pin 1. If pin |
| N88 | (19) | 97 | SOP | The devices described in this document are typically used as lowCp | |
| N89 | (34) | Xilinx introduces the XC1800 series of in-system program- mable configur | |||
| N8C | (1) | NS | PQFP-144 | 98 | FULL FLAG (FF) The Full Flag (FF) will go LOW, inhibiting further |
| N8G | (1) | These edge-triggered multivibrators feature output pulse-duration contr | |||
| N8H | (2) | SN | DIP | The TPS211xA family of power multiplexers enables seamless transition bet | |
| N8O | (1) | AMD | PLCC | 07+ | Note 10 For best long-term stability any precision circuit will give best |
| N8Q | (2) | INTEL | 96+ | PLCC/68 | JANS level Thermal impedance (see 4.3.4) hFE1 and ICEX hFE1 an |
| N8R | (1) | N/A | SMD | 2000 | Supports DVD format, Video CD 2.0 (White Book), & CD-DA (Red Book) Re |
| N8T | (74) | Sig | 8105 | perform serial to parallel conversion, SONET/SDH overhead processing an | |
| N8X | (28) | sig | sig | dc84 | High Speed Communication Line Protection USB 1.1 and 2.0 Power and Data |
| N90 | (5) | SAMSUNG | QFP | O1 | The common enable (EN) is synchronous so that the outputs will only be e |
| N91 | (8) | MOT | 00+ | This is a dual function pin. In the IDT Standard mode, the EFB function is | |
| N92 | (8) | N/A | • Cost optimized, full custom circuit design 10BASE-T/100BAS | ||
| N93 | (9) | OPTL | SOP-20P | 05+ | STANDARD DEFINITION MODE Hue Accuracy Color Saturation Acc |
| N94 | (7) | S | DIP | 06+ | Setting the VTRIP Voltage This procedure sets the VTRIP to a higher volt |
| N95 | (1) | PITTWAY | DIP | The FSK modulator/demodulator produces a frequency modulated analog outpu | |
| N96 | (6) | SIG | NOTES: 1. Dimensions are in inches. 2. Metric equivalents | ||
| N97 | (1) | TO78 | CD players read out the digital signal from the disc using a built-in p | ||
| N98 | (2) | ZILOG | SOP | 98+ | TI warrants pe rformance of its se miconductor products to the spe cifica |
| N99 | (9) | magne | magne | dc80+ | If high inductance values and low capacitor values are used, the additio |
| N9C | (1) | NSC | QFP | AS serves to demultiplex the address/data bus. The falling edge of AS lat | |
| N9H | (1) | PHI | 2007 | Bypass all power supplies, as well as the REFERENCE OUTPUT (pin 21), to | |
| N9K | (1) | PHOTOBIT | WCPGA1111 | INITIALIZATION During the microprocessor initialization routine, t | |
| NA- | (5) | Fujitsu 06+ | Ruotare il selettore su FL . Quando lalimentazione a ON e si applica i | ||
| NA0 | (8) | DIA | O7+ | Notes: 1. NC pins are not connected to the die. 2. C2 (DNU) | |
| NA1 | (13) | TAKAMISA | RELAY | 06+ | |
| NA2 | (3) | TAKAMISAWA | Relay(DZ) | *0004B8 | UART channel A Receive Data or infrared receive data. Normal receive data |
| NA3 | (14) | HAR | 06+ | 500 | Power On Reset: V CC Lock-Out Write Protect In order to prevent data cor |
| NA4 | (1) | ICCMaximum Quiescent Supply Current5.58.080µAVIN = VCC or GND | |||
| NA5 | (21) | Built-in Power Save Circuit Built-in Current Limit Circuit Built-in Th | |||
| NA6 | (2) | taka | taka | dc96 | Zener Breakdown Voltage: 6.2 − 47 Volts DC Power Diss |
| NA7 | (2) | MOT | 01+ | PLCC84 | The P87C51Mx2 provides greater functionality, increased performance and ov |
| NA8 | (1) | INTEL | 03+ | VDD to GNDC0.3 V to 7 V Analog Input Voltage to GNDC0.3 V to VDD + 0.3 V | |
| NA9 | (1) | TAKAMISA | RELAY | 06+ | This N-Channel power MOSFET is ® manufactured using t |
| NAA | (3) | 2007 | The LVDS388 and LVDT388 (T designates integrated termination) are eight | ||
| NAB | (2) | ON | 00+ | Power down protection is provided on all inputs and 0 to 7V can be acce | |
| NAC | (157) | 7. The NAC2470M6.6V56TR13 is put into shutdown by bringing RE high and DE | |||
| NAD | (3) | TI | DIP | 90 | Description SS1 Spread Spectrum control bit SS0 Spread Spectrum control |
| NAE | (9) | NA | 00+ | SOP16 | The in-Line Micro filter has been specifically designed to implement the |
| NAG | (9) | STANLEY | N/A | The UCC283−3/−5/−ADJ family of positive linear series | |
| NAH | (1) | CAN | CAN | The temperature of the case should be measured using a thermocou- ple pl | |
| NAI | (8) | NAIS | SOP-6 | The device contains an 8-bit instruction register that controls the ope | |
| NAJ | (1) | HITACHI | 06+ | 1039 | |
| NAK | (2) | • Categorized for Luminous Intensity Yellow and Gre | |||
| NAL | (13) | TAKAMISAWA | Relay(DZ) | *9533B8 | • Low Jitter • CMOS and TTL output levels • High Q Cry |
| NAM | (2) | SOT-363 | Broadcom®, the pulse logo, MIB AutocastTM and Connecting everything&re | ||
| NAN | (91) | 07+ | 27000 | The NANOSMDC012F-2/253T and NANOSMDC012F-2/2253T are high- speed dual 4- | |
| NAP | (6) | 430 | ZILOG | 00+ | 5V, 3V, and 3.3V versions available High accuracy output voltage Guara |
| NAR | (12) | STANLEY | N/A | 8. The minimum Full Scale Calibration Range (FSCR) is limited by the maxi | |
| NAS | (66) | 国产 | DIP | ||
| NAT | (13) | 2007 | NOTES: (1) For detailed drawing and dimension table, please see end of da | ||
| NAX | (19) | ALP | 07+/08+ | ||
| NAY | (2) | Thermocouple: 0.5% of indicated value or 1_C, whichever greater, 1 digit | |||
| NAZ | (3) | 98 | The HYM72V16M656B(L)T6 -Series are gold plated socket type Dual In-line Me | ||
| NB- | (3) | The Hynix NB-32B01 Series are 16Mx64bits Synchronous DRAM Modules. The mo | |||
| NB0 | (3) | APEX | 八脚铁帽 | 08+ | Hynix HYMD116645B(L)8-M/K/H/L series incorporates SPD(serial presence dete |
| NB1 | (65) | ON | 03+ | The DS2751 performs temperature, voltage, and current measurement to a res | |
| NB2 | (84) | N/A | 0603TEM | Xilinx development software (XEPLD) supports all mem- bers of XC7300 fa | |
| NB3 | (20) | SOPH | 95 | When VCC is between 0 and 1.5 V, the device is in the high-impedance stat | |
| NB4 | (33) | DIP-14 | 99+ | RF Integrated Corp. believes the information provided is reliable at pres | |
| NB6 | (40) | ON | QFN-16 | 06+ | Power Up and Down Requirements. There are no restrictions on the power-u |
| NB7 | (30) | SIEMENS | 05+ | The APA4863 also served well in low-voltage appli- cations , which provid | |
| NB8 | (3) | FUTITSU | QFP | 00+ | (5) The products and product specifications described in this material ar |
| NB9 | (1) | † Stresses beyond those listed under absolute maximum ratings may c | |||
| NBA | (1) | The UT51C164 is high speed 5V EDO DRAMs organized as 256K bit X 16 I/O and | |||
| NBB | (10) | RFMD | 2008 | The transmitter includes a PLL to multiply the reference clock to the tra | |
| NBC | (73) | ON | 07+ | The special detect circuitry monitors the received analog signal to deter | |
| NBD | (1) | PECL, LVPECL, ECL, LVECL, HSTL Clock or Data Inputs. Internal 75kΩ | |||
| NBE | (2) | JAT | • Plastic package has Underwriters Laboratory Flammability | ||
| NBL | (15) | BROADCOM | These amplifiers have a 360-µV input offset voltage, a 17 nV/Hz inp | ||
| NBM | (1) | ZILOG | DIP | 98+ | The ADS8509 is specified at a 250-kHz sampling rate over the full tempe |
| NBP | (7) | MINI | 08+ | The center tap Schottky rectifier module has been optimized for ultra l | |
| NBQ | (14) | Yageo | 2008+ | Basically an 8-bit DAC with input latches, the AD7524s load cycle is sim | |
| NBR | (8) | N/A | When a push-button is used to manually reset a µP, ringing from the | ||
| NBS | (82) | SI | 06+ | Figure 2: is a block diagram of the 256/288 Mbit Direct RDRAM. It consi | |
| NBT | (31) | N/A | SOP | 07+ | The IS41C4100 and IS41LV4100 is a CMOS DRAM optimized for high-speed ba |
| NBU | (1) | • High-speed access time: 35, 45, 55, 70 ns • Low active pow | |||
| NBX | (4) | When the ORG pin is connected to VCC, the (x16) orga- nization is selec | |||
| NC- | (27) | NANA | Mechanical Characteristics: • Case: Epoxy, Molded • Weight: 21 | ||
| NC. | (3) | ST | ZIP4 | Two power-saving features are embodied in the HY29DL16x. When addresses | |
| NC/ | (1) | Multi-Input Wake-Up (MIWU) Supports up to 32 wake-up or interrupt input | |||
| NC0 | (16) | N/A | Floating bootstrap supply pin for the upper gate drive. Connect a boots | ||
| NC1 | (35) | NETWORK | 0511+ | QFP | The LM32 is a digital temperature sensor that measures 3 temperature zo |
| NC2 | (45) | NAIS | Relay(new original) | (*) NOTE: SELF PROTECTING Stressed above those listed underAbsolute Max | |
| NC3 | (26) | 97+ | 58 | The NC311C is a field memory (FMEM) that is upwardly and pin-to-pin compa | |
| NC4 | (32) | SMD | • State-of-the-art architecture Non-volatile data storage | ||
| NC5 | (20) | SOP | 3.0 - 16A @ 125/250VAC 4.0 C 16A @ 125 (UL/CUL) 1500Vrms min > 100M& | ||
| NC6 | (6) | N/A | NEOPAC | 04+ | NOTES: 1. At f = fMAX, address and control lines (except Output Enable) a |
| NC7 | (1027) | FAIRCHILD | SOT-163 | Single supply: 1.8 V to 5.5 V Two-wire serial interface (I2CTM serial b | |
| NC8 | (12) | Information Storage Devices ISD1000A Chip- Corder® Series provides hi | |||
| NC9 | (2) | motola | 2007 | The bq3285E/L bus cycle consists of two phases: the address phase and the | |
| NCA | (9) | The capacitor connected to this pin sets the Cycle Skip period. Once a cy | |||
| NCB | (9) | N/A | Port 0 is also the multiplexed low-order address and data bus during acc | ||
| NCC | (13) | NETSWARP | The IDTQS74FCT2244T is an 8-bit buffer/line driver with three-stat | ||
| NCD | (24) | JAT | 05+ | • Any System Requiring RS-232 Communication Ports - Battery | |
| NCE | (5) | NEC | Hardware Reset, active Low. Provides a hardware method of resetting the | ||
| NCF | (49) | n Pop & click circuitry eliminates noise during turn-on and t | |||
| NCG | (1) | 1 | UART channel 0 Receive Data or infrared receive data. Normal RXD input i | ||
| NCH | (12) | • Plastic package has Underwriters Laboratory Flammability | |||
| NCJ | (1) | QFP | 02+ | Li-Ion Or Li-Pol Charge Management and Synchronous DC-DC Power Conversion | |
| NCK | (1) | Diode protected input stage for power OFF condition 17 ns typ high speed | |||
| NCL | (30) | NEL | 2007 | Wide supply voltage range3 0V to 15V High noise immunity0 45 VDD (typ ) | |
| NCM | (19) | SANYO | 05+ | Device is in shutdown due to fault condition, normal mode = 1, shutdown = | |
| NCN | (40) | ★Original and new, Special price! | ★Original and new, Special price! | 08+ | • Precision Internal Oscillator: - Factory calibrated to 1% |
| NCO | (3) | A feature of the DS1267 is the ability to control multiple devices from a | |||
| NCP | (2455) | ON | 0237 | Note 3: The maximum power dissipation must be derated at elevated tempera | |
| NCR | (227) | NCR | QFP100 | Notes: 1. Repetitive Rating : Pulse width limited by maximum junction tem | |
| NCS | (97) | ON | 07+ | The optional 16K bytes boot block section includes a repro- gramming wri | |
| NCT | (28) | PHILIPS | 05+ | DIP | The TC55NEM216AFTN is a 4,194,304-bit static random access memory |
| NCV | (604) | ON | 3.9mm | 05+ | Data Bits DB11 to DB0, Port 2 Control inputs for PLL and input port sele |
| NCW | (1) | The 16 uniform sections available form an 8-step dim- mer via 3-bit binar | |||
| NCY | (7) | Note: 1. Enhancement mode technology employs a single positive Vg | |||
| NCZ | (1) | ||||
| ND | (1) | Up to 19 analog measurement channels (including internal measurem | |||
| ND- | (1) | ND | 06+ | 500 | This CMOS device is designed for switching PCM-encoded voice or da |
| ND0 | (8) | NS | SOT23-5 | 1997 | • 200MHz Clock, 400Mbps data rate. • VDD= +2.6V + 0.10V, VDDQ |
| ND1 | (13) | PHILIPS | 2008 | Information at the data (D) inputs meeting the setup time requirements is | |
| ND2 | (28) | ND | 05+ | FEATURES Very Low-Noise, 5 nV/Hz @ 1 kHz Max Excellent Input Offset Vol | |
| ND3 | (26) | NEODIO | 01 | (3) Reset L level input over than 3ms to the RST terminal is init | |
| ND4 | (84) | PRX | SOP | High Efficiency: Up to 95% 4A Output Current Low RDS(ON) Internal Switch | |
| ND5 | (2) | NKK | BGA | OUTPUT CLOCK: This pin is selectable under processor control to be either | |
| ND6 | (10) | The devices also have 64 I/O cells, each of which is directly connected | |||
| ND7 | (5) | NEODIO | QFP | 04+ | |
| ND8 | (6) | PLCC | Optimized for 2.5V LVTTL Guaranteed Low Skew < 25ps (max) Very low d | ||
| ND9 | (6) | ALLEGRO | DIP | 06+ | (1) 300-hour life test at 150C demonstrated randomly distributed variatio |
| NDA | (7) | HS | 06+ | 1000 | Normally, capacitor values on the order of several hundred microfarads ar |
| NDB | (93) | NS | The R4700 is upwardly software compatible with the IDT79R3000͐ | ||
| NDC | (51) | QFP44 | Audio Processing l Decodes MPEG1 (layer-1, 2, 3) stereo channel | ||
| NDD | (7) | NS | 99 | • Categorized for Luminous Intensity Yellow and Gre | |
| NDF | (5) | FAIRCHILD | 01+ | In the interest of memory transfer operation applications, the IS93C56-3 | |
| NDG | (1) | N/A | Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm (one layer, 70&mi | ||
| NDH | (29) | FAI | SOP-8 | 9918/SX | The DS1481 is a dedicated 1Cwire timing generator. The device is normal |
| NDI | (2) | Information furnished by Analog Devices is believed to be accurate and r | |||
| NDK | (7) | FAIRCHILD | 07+/08+ | ICSI reserves the right to make changes to its products at any time withou | |
| NDL | (89) | SDG | TO-220 | The oscillator output is a triangular wave with a minimum value of approx | |
| NDM | (10) | FSC | 06+ | 500 | Low IR, Extends Battery Life 1st in the Market Place with a 10 VR Schott |
| NDO | (1) | Notes: 1. Dominant Wavelength, ëd, is derived from the CIE Chromatic | |||
| NDP | (109) | (AVDD = 2.7V to 5.25V, DVDD = 1.8V to AVDD, AGND = 0, DGND = 0, VREF = 2.5 | |||
| NDQ | (2) | Therefore it should be no problem to achieve the recommended values of r | |||
| NDR | (1) | The current through the resistor RSET determines the timing of the funct | |||
| NDS | (388) | NAS/BD | N/A | N/A | The GS4882 and GS4982 feature an internal color burst filter for minimiza |
| NDT | (65) | FAIRCHILD | 04+ | The 5002C is an audio/video switching device. The device integrates both | |
| NDV | (32) | NS | QFP208 | 04+ | Processor Socket Chipset System memory (GB) DIMM slots Flash EPROM Sy |
| NDX | (1) | NUCORE | QFN-52P | 6+ | Sirenza Microdevices SBB-2089 is a high performance InGaP HBT MMIC amplif |
| NDY | (29) | CDUSD 06+ | As shown in Figure 3, the TIE Corrector Circuit receives one of the two re | ||
| NE- | (3) | DIP-42 | Provides various voltages for DDR-STR applications Provide a swit | ||
| NE/ | (3) | PHI | SOP8S | 06+ | |
| NE0 | (12) | DIP-18 | The SST49LF080A flash memory device is designed to interface with the L | ||
| NE1 | (41) | NEC | SMD | in bursts. An automatic power down feature, controlled by CE0 and CE1, pe | |
| NE2 | (37) | EON | TSOP | 2007 | Standard packing quantities and other packing data are available at www.s |
| NE3 | (97) | NEC | The SY89538L integrated programmable clock synthesizer and fanout is part | ||
| NE4 | (37) | NEC | 0022+ | The device can accommodate astigmatic, single foucault and double fouca | |
| NE5 | (782) | sig | sig | dc84 | Active low input to stop diff outputs. 3.3V input for selecting PLL Ban |
| NE6 | (127) | NEC | Eight GLBs, 32 I/O cells, two dedicated inputs and two ORPs are connecte | ||
| NE7 | (37) | NEC | SOP | 85 | Note 1 Absolute Maximum Ratings are those values beyond which the safety |
| NE8 | (68) | PHILIPS | PLCC-28 | 07+ | n No special start-up sequence required between clock/data and /P |
| NE9 | (10) | NEC | Same package and pin assignment as mask ROM version. 1. LC877400 series | ||
| NEA | (2) | Maximum rated frequency: 133 MHz Low cycle-to-cycle jitter Input to out | |||
| NEB | (5) | NEC | 500 | Operating voltage: 2.9V~5.2V Ten bidirectional I/O lines Six schmitt tri | |
| NEC | (601) | NEC | SMD | CONNECTION MODE In Connection Mode, the addresses of input source | |
| NED | (6) | SOP-14 | 06+ | The upper and lower gates are held low until the driver is initialized. | |
| NEF | (15) | HP | BGA | 9638+ | Added Delay Measurement Methodology table, updated SelectI/O section, Fig |
| NEG | (2) | GND HD15 HD14 HD13 3.3V-VDD HD12 HD11 HD10 1.8V-VDD GND HD9 HD8 | |||
| NEH | (2) | ||||
| NEI | (1) | Digital Ground. All digital signals are referred to this pin. +5V Analo | |||
| NEJ | (1) | N/A | Supply Voltage Input for the internal PMOS Power Switch. Not internally c | ||
| NEK | (1) | Timing specifications are guaranteed by design. Set by 1000pF external ca | |||
| NEL | (9) | NEC | ABA-31563 is fabricated using Agilents HP25 silicon bipolar process, whi | ||
| NEM | (17) | NEC | (LX)high-frequency | 5.2.4 Control of Transceiver Chip The ST20196 runs the firmware controll | |
| NEN | (2) | SONY | ZIP-5 | ZIP-5 | This is not an extensive capacitor list. Capacitors from other ve |
| NEO | (10) | SNK | SOP24 | Notes: 1. The luminous intensity, I v, is measured at the peak of the s | |
| NEP | (3) | SONY | ZIP-5 | ZIP-5 | The low-cost ADS-950 is an 18-bit, 500kHz sampling A/D converter. This |
| NER | (2) | PHI | 00+ | DC Electrical Characteristics (Continued) These limits apply for supply v | |
| NES | (49) | NEC | SOT-89 | The maximum power that can be safely dissipated by the AD8152 is limited | |
| NET | (51) | NSETCHIP | 03+ | The HY64UD16162M is a 16Mbit 1T/1C SRAM featured by high-speed operation | |
| NEW | (6) | AMIS | Ultra low quiescent current (IQ 15 µA for IO 100 µA) Fixed | ||
| NEX | (4) | ST | Note l: I/O state assumes that G VIL. Activation of nonvolatile cycles | ||
| NEZ | (20) | NEC | 96/97+ | SW (Pin 4): Boost Regulator Switch Pin. This pin is the boost regulator s | |
| NF- | (44) | N/A | CMD | 04+ | 10 MHz multiplying bandwidth 50 MHz serial interface 2.5 V to 5.5 V supp |
| NF0 | (3) | 1000 | These Microsemi 30 kW Transient Voltage Suppressors (TVSs) are designed f | ||
| NF1 | (10) | KOITECH | DIP-28 | 9715+ | Integration l MPEG-1 system/audio/video decoding and synchroniza |
| NF2 | (30) | NVIDIA | BGA | 04+ | † Stresses beyond those listed under absolute maximum ratings may c |
| NF3 | (5) | SMD-8 | 04+ | Internal resistors provide accurate full-scale input ranges of 5V, 8V or | |
| NF4 | (29) | NVDIA | BGA | A powerful program sequencer controls the flow of instruction execution. | |
| NF5 | (6) | NVIDIA | BGA | • 1.8V+0.1V/-0.1V Power Supply. • DLL circuitry for wide outp | |
| NF6 | (6) | NVIDIA | BGA | 06+ | Virtex-E devices feature a flexible, regular architecture that comprises |
| NF7 | (1) | The NF74F543D generates a low EMI output clock from a clock input. The | |||
| NF8 | (1) | MURATA | The totem-pole output stage, capable of 600 mA source and 800 mA sink cur | ||
| NF9 | (2) | QFP | 94 | P-doped, Schottky-barrier diodes excel at applications requiring ultra | |
| NFA | (142) | MURATA | 4（1206） | 06+ | • I/O-isolation 6000 VDC • Creeping/ Clearance distances &nb |
| NFB | (31) | agilent | No part of this document may be copied or reproduced in any form or by an | ||
| NFC | (127) | N/A | module | 2005+ | FAST™ is a second generation Schottky logic family that utilizes a |
| NFD | (13) | ON | SOP-16 | 06+ | Connect a resistor from this pin to the drain of the upper PWM MOSFET. |
| NFE | (30) | MURATA | 2008+ | n Reduced Swing Differential Signalling (RSDS™) digital bus | |
| NFK | (2) | 03 | Note 13: Skew is defined as the absolute value of the difference between | ||
| NFL | (18) | MURATA | 0805-107 | 06+PB | Three-State PWM Input for Power Stage Shutdown Internal Bo |
| NFM | (559) | N/A | The LH28F016SU is a very high density, highest per- formance non- | ||
| NFN | (4) | CAUTION: These devices are sensitive to electrostatic discharge; follow p | |||
| NFO | (54) | nvIDIA | 2 | BGA | NOTES 1 iJA e Thermal resistance between junction and the surrounding en |
| NFP | (21) | NVIDIA | BGA | 0609+ | High-speed access time: 8, 10, 12, and 15 ns CMOS low powe |
| NFR | (30) | MUTRA | Each phase can be operated at a switching frequency up to 1-MHz, result | ||
| NFS | (70) | N/A | 1812 | The HYM72V64756T8 H-series are gold plated socket type Dual In-line Memory | |
| NFU | (1) | ||||
| NFW | (15) | MURATA | SMD | 2008 | The ISL6227 can control two independent output voltages adjustable from 0 |
| NFX | (2) | INT | 11 | 93+ | The MAX236X is a complete quadrature transmitter, including a quadrature |
| NG- | (20) | JINAN | 2000 | Up to 97% Efficiency 2MHz PWM Switching 800mA Guaranteed Output Current | |
| NG2 | (3) | AMD | 04+ | 51 | Advanced encryption standard unit (AESU) C Implements the Rinjdae |
| NG3 | (1) | FEATURES 0.5 Typical On Resistance 0.8 Maximum On Resistance at 125C | |||
| NG4 | (1) | With reference to WG 2 Resolution M33.31 in document N 2927, and WG 3 Res | |||
| NG6 | (1) | Genesis Microchip Inc. reserves the right to change or modify the informat | |||
| NG8 | (209) | INTEL | BQFP132 | Prior to placing surface mount components onto a printed circuit | |
| NG9 | (1) | Developed in TIs patented LBC3 BiCMOS process, the new BiMOS amplifiers c | |||
| NGA | (18) | Sirenza | 04+ | the device has a Sector Group Protect function which hardware write pro | |
| NGB | (19) | ON | TO-263 | 08+ | |
| NGD | (12) | ON | TO-252 (D PAK) | 08+ | NOTES: • Use a 0.1 µF capacitor on VDD to decouple the power |
| NGE | (2) | Stresses above the ratings listed below can cause permanent damage to the | |||
| NGH | (5) | Drain-Source Voltage Gate-to-Source Voltage Continuous Drain Cur | |||
| NGM | (1) | The tuning input is typically connected to the output of the PLL loop fil | |||
| NGP | (4) | ON | TO-220 | 08+ | To maximize I/O throughput and improve host and Fibre Channel uti |
| NGS | (4) | INTEL | N/A | 04+ | VDD (16) VDD is the positive supply connection. An internal shunt regul |
| NGT | (1) | ! Available in a single mode (240-bits shift register) or in a dua | |||
| NH- | (2) | Although the information in this catalog has been carefully checked for a | |||
| NH0 | (30) | NS | CAN10 | 03+ | VREFR− Rch Negative Voltage Reference Output Pin, 1.25V Nor |
| NH1 | (5) | 99 | QFP | The Hynix HYM71V16755HGT8 Series are 16Mx72bits ECC Synchronous DRAM Modul | |
| NH2 | (24) | SOP24 | 06+ | The rise and fall time (tr, tf) of the lamp voltage can be limited to red | |
| NH4 | (10) | SOP44W | 2007+ | Analog Signal Range On Resistance, +25C 0 to +70C C55 to | |
| NH5 | (4) | • Cost-effective programming changes and field software upgr | |||
| NH7 | (1) | The Timing and Watchdog Module (TWM) contains a Real- Time timer and a | |||
| NH8 | (98) | INTEL | 2007 | These octal transparent D-type latches feature 3-state outputs designed s | |
| NHA | (3) | The ÉlanSC300 microcontroller from AMD is part of the growing &Ea | |||
| NHB | (1) | NHBT | DIP | DIP | Logic Device C 3.0 to 3.6V Operating Range C 32 Macrocells |
| NHC | (1) | Before programming, the NHC1040 is erased by exposing the chip through th | |||
| NHD | (3) | SOP-16 | 05+ | Driving EN low disables the converter. This disables all internal circuit | |
| NHE | (18) | 63 powerful instructions Up to 1ms instruction cycle with 4MHz system c | |||
| NHG | (1) | JRC | 05+ | The Fairchild Power Switch(FPS) product family is specially designed for | |
| NHH | (1) | NIKON | LQFP48 | The Hynix HYM71V16M655AT8 Series are Dual In-line Memory Modules su | |
| NHI | (11) | NHI | 双列直插64 | Arbitrary trigger levels for receiver and transmitter FIFO interrupts an | |
| NHN | (2) | For proper operation, input and output pins must be constrained to the ra | |||
| NHO | (1) | • Low-power consumption (Standby) Mode •Sleep mode (CP | |||
| NHP | (20) | MINI | 08+ | Any input can be modulated by a pulse train of variable duty cycle (&aum | |
| NHQ | (3) | BOWTHORPE | 00+ | 电阻 | Removed 166MHz part from speed bin Defined IDD specificati |
| NHS | (13) | 24 | 99+ | C 512 Kbytes on-chip flash memory single voltage with erase/ | |
| NHW | (1) | 1850 | The bq4847 also has a built-in watchdog timer to monitor processor opera | ||
| NHX | (2) | int | int | dc0444 | 1.1 Scope. This specification covers the performance requirements |
| NI- | (5) | DATEL | AUCDIP | OUTPUT VOLTAGE LIMITERS Default Limiter Voltage Minimum Limiter Separa | |
| NI1 | (1) | HAR | 10 | The DVR EN*, DATA, and VTT EN pins are digital inputs that control the dr | |
| NI2 | (21) | Trigger Voltage: The measured peak voltage across the ESD suppressor bef | |||
| NI5 | (7) | TIP | Shift clock signal input for the PCMIN and PCMOUT signal. The frequency, | ||
| NI8 | (1) | VOUT Output Voltage The MAX5069A EV kits output (VOUT) is set to | |||
| NIA | (4) | 2007 | DESCRIPTION Using the latest high voltage technology based on a patente | ||
| NIC | (19) | ALCATEL | DIP | 07+ | (1) For more information on the PWP package, refer to TI technical brief, |
| NID | (12) | ON | TO-252 | • Plastic package has Underwriters Laboratories Flammabilit | |
| NIF | (25) | It also has a microprocessor compatible input configuration, which provid | |||
| NIH | (1) | ||||
| NIK | (7) | Jack(Available) | eight CAT34AC02 may be individually addressed by the system. The last b | ||
| NIL | (9) | N/A | TO-92 | 00+ | 4.4.2 Group B inspection. Group B inspection shall be conducted in |
| NIM | (24) | JRC | SOP8L | 0105+ | Notes: 1. See test circuit and waveforms. 2. This parameter is guarant |
| NIN | (17) | INTERSIL | Halt function and wake-up feature reduce power consumption Up to 0.5ms | ||
| NIO | (1) | The pushbutton shown is pressed once on the first day at about 7 | |||
| NIP | (6) | 99/01+ | DMT Signal A DMT signal is basically the sum of N inde- pendently QAM | ||
| NIS | (24) | ICS | SOP-28 | 03+ | Please be aware that an important notice concerning availability, |
| NIT | (6) | AT | 99+ | Limiting values given are in accordance with the Absolute Maximum Rating | |
| NIU | (4) | JRC | 95 | Re a dy / Bus y St a t us . I nd ic a t e s w he t he r a w r it e o r e | |
| NIV | (4) | QFN | 05+ | Bias Supply (Input): This input pin supplies power to operate the switch | |
| NJ1 | (4) | NEMERI | SOP | 05+ | This method corresponds more accurately to the method of test and |
| NJ2 | (8) | 2007 | The TLC372 has internal electrostatic discharge (ESD) protection circuits | ||
| NJ3 | (3) | JRC | SMD | 1998 | Sony reserves the right to change products and specifications without pri |
| NJ5 | (2) | N/A | N/A | 04+ | Figure 2 implements both the current-limit capability and a control sch |
| NJ6 | (2) | The input/output pins (I/O 0 through I/O15) are placed in a high-impeda | |||
| NJ8 | (60) | N/A | SMD | 93+ | deasserted. Data will be read out of the FIFO on both rising and falling |
| NJA | (2) | Note 1: Absolute maximum ratings indicate limits beyond which damage to t | |||
| NJB | (3) | SOP8 | 0 | The Motorola High-End Technical Publications Department provides a fax num | |
| NJC | (4) | JRC | 5500 | We designed this receiver based on the idea that if made smaller, GPS re | |
| NJD | (21) | ON | TO-252 (D PAK) | 08+ | The SPS product family is specially designed for an off-line SMPS with |
| NJE | (11) | MOT | TO-220 | 89+ | Note: 1. H=VIH, L=VIL, X=don't care 2. UB, LB(Upper, Lower Byte enable) |
| NJG | (151) | NJRC | Diagonal 4.5mm (Type 1/4) 752 (H) 582 (V) approx. 440K pixels 795 (H | ||
| NJH | (2) | PARAMETERS Supply Voltage Operating Temperature RF Input Frequ | |||
| NJJ | (1) | VIN TO IOUT TRANSFER FUNCTION Output Specified Range Over | |||
| NJL | (147) | For example, if a block of data is to be transferred from RAM to an I/O | |||
| NJM | (4757) | JRC | 5 | QFP | Please note: The signals and voltages at the Pins REC, INT, FLA, FLB, Q |
| NJN | (13) | 98+ | 120 | After the switch-over mode the watchdog operates in short watchdog mode a | |
| NJP | (1) | Pb−Free Packages are Available* Integrated Power Swit | |||
| NJS | (6) | Glass passivated junction. 500W Peak Pulse Power capability on 10/1000 | |||
| NJT | (5) | JRC | |||
| NJU | (1402) | JRC | SOP | 00+ | High-speed video signal switching/routing HDTV-quality video signal rou |
| NJV | (12) | DIP | After determining which clock edge to use, a start and stop bit, appended | ||
| NJW | (194) | JRC | SOP | 03+/04 | 256K x 36, 512K x 18 memory configurations Supports fast access times: C |
| NJX | (9) | JRC | This application note describes and shows various applica- tion circuits | ||
| NK- | (3) | DIP | Layout Considerations A sufficient number of holes (QTY 12 - 0.2mm diam | ||
| NK0 | (7) | The FB pin monitors the output supply voltage and signals the RESET outpu | |||
| NK1 | (11) | SOT-89 | The DCP0105 family is a series of high efficiency, 5V input isolated DC/ | ||
| NK2 | (28) | HARRIS | SOP | 02+ | Note 1: INSEL=0 > SCLK, SDI, and LOAD pins are active for serial progr |
| NK3 | (11) | SOT23-6 | DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device ad | ||
| NK4 | (5) | MORETEC | DIP16 | Hewlett-Packard Application Note 923, Schottky Barrier Diode Vide | |
| NK5 | (13) | MK | 1988 | DIP | MOSI and MISO are used to send and receive data over SPI. MOSI is a data |
| NK6 | (2) | TO-263 | With 5V power supplies, the PS381/PS383/PS385 guarantee <30Ω on- | ||
| NK7 | (28) | 长电 | SOT-23 | 08+ | Bus timing data is shown in Figure 4 and Figure 5. Data transfer may be i |
| NK8 | (23) | TO-263 | Parameter MAXIMUM CONVERSION RATE MINIMUM CONVERSION RATE DUTY CYCLE E | ||
| NK9 | (4) | N/A | NS | 04+ | Figure 1 shows a typical battery pack application of the bq2050H using th |
| NKA | (21) | mur | mur | dc07 | The DS1270 devices execute a write cycle whenever WE and CE signals are ac |
| NKB | (1) | ta = DS0*/DS1* to the assertion of DTACK* (slave access time). tr = Brx* | |||
| NKD | (3) | SCHIU | 06+ | 500 | Designers are strongly encouraged to provide three kinds of power pairs f |
| NKE | (28) | 07+ | Programmable option for internal pull-up resistor on each input pi | ||
| NKG | (7) | NDK | 19.440MHZ | The AWT6135 meets the increasing demands for higher efficiency and line | |
| NKM | (2) | DIP24 | 01+ | Gain Shaper. The output of the integrator is fed to the gain shaping cir | |
| NKR | (6) | STANLEY | N/A | Output Port 2 Channel A - The output state is defined by the user and thr | |
| NKS | (11) | 04+ | * Specifications will vary with foreign standards certificati | ||
| NKT | (11) | NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 i | |||
| NKX | (1) | Each DS1270 device is shipped from Dallas Semiconductor with its lithium | |||
| NKZ | (14) | IC-Haus | SOP8 | These circuits are completely compatible with most TTL families. Inputs a | |
| NL- | (7) | Agilont | 06+ | The codestrip moves between the emitter and detector, causing the ligh | |
| NL0 | (1) | N/A | N/A | N/A | deasserted. Data will be read out of the FIFO on both rising and falling |
| NL1 | (150) | ON | 523 | The QPro™ series XQ1701L are Xilinx 3.3V high-density configuratio | |
| NL2 | (321) | TDK | ADV/LD is a synchronous input that is used to load the internal registers | ||
| NL3 | (401) | TDK | N/A | For enhanced performance, the VRE304 has an external trim option for user | |
| NL4 | (261) | N/A | This heading on a data sheet indicates that the device is in the f | ||
| NL5 | (67) | N/A | 5650 | and simultaneously sinking maximum current at the ALERT output. For examp | |
| NL6 | (34) | NEC | 9.4 | TFT | SDRAM Controller 64-bit data bus. Up to 90MHz SDRAM clock speed. Inte |
| NL7 | (21) | IDT | 05+ | DESCRIPTION These dual channel diode-darlington optocouple | |
| NL8 | (33) | N/A | N/A | 04+ | pins appear in the upper center of Figure 2:. They are used to write and |
| NL9 | (5) | N/A | N/A | 04+ | CAUTION: These devices are sensitive to electrostatic discharge; f |
| NLA | (163) | ON | |||
| NLB | (10) | RFMD | SOP | 651 | Fully operational to +600V Tolerant to negative transient v |
| NLC | (409) | TDK | Thermal Design The IRU431L is offered in the plastic 8-pin SOIC or the s | ||
| NLD | (39) | HI | QFP | The Hyundai HYM71V75S1601 H-Series are 16Mx72bits ECC Synchronous DRAM Mod | |
| NLE | (6) | MOTOROLA | 模块 | The CM3002 family of regulators is fully protected, offering both overl | |
| NLF | (262) | TDK | • Fast Sector Erase and Word Program: - Sector Erase Time: | ||
| NLG | (7) | (LX)high-frequency | *Absolute Maximum Ratings are those values beyond which damage to the dev | ||
| NLH | (41) | TDK | N/A | involves the following phases : PHASE 0: The duration is a time p | |
| NLK | (4) | NEC | 光纤 | 07+/08+ | • IN-SYSTEM PROGRAMMABLE 3.3V In-System Programmability Us |
| NLL | (15) | TDK | 3225-1R0 | 04+ | JEDEC compatible LVTTL level inputs and outputs 10 output, low skew clock |
| NLM | (12) | SMD/DIP | SN | 500 | Note 1: All voltages are with respect to GND. All currents are positive |
| NLN | (14) | The UCC3961 provides all the circuitry required on the primary side of a | |||
| NLP | (178) | MINI | 08+ | 1. All dimensions are in millimeters. 2. True position spread tolerance o | |
| NLQ | (3) | TDK原盘 | 0805- | ESD damage can range from subtle performance degradation to complete dev | |
| NLS | (50) | 98+ | |||
| NLT | (19) | TDK原盘 | 4532- | Notes: 1. Typical continuous power in a non-ventilated enclosed a | |
| NLU | (87) | N/A | 0603L | When the CAT34AC02 begins a READ mode, it transmits 8 bits of data, rel | |
| NLV | (240) | TDK | 2520 | • Any System Requiring RS-232 Communication Ports - Battery | |
| NLW | (2) | Notes: 1. This parameter is warranted but not production tested. The pro | |||
| NLX | (35) | adaplog | adaplog | dc92 | * 1.1 Scope. This specification covers the performance requirements for N |
| NLZ | (14) | The CLC031A SMPTE 292M / 259M Digital Video Deserializer/Descrambler wi | |||
| NM- | (12) | MINI | 08+ | Stresses above those listed under Absolute Maximum Ratings may cause perm | |
| NM0 | (4) | NNM | 95 | Current Output Models Two settling times are specified to 0.01% of FSR. | |
| NM1 | (13) | NEWAVA | PLCC-44 | 00+ | Note 2. This device assumes a standby mode if either CE1 is disabled (high |
| NM2 | (675) | FAIRCHILD | 05/06+ | +5V reference output. This low-drift zener voltage reference is necessary | |
| NM3 | (20) | PANASONIC | DIP | 94 | All FIFO configurations will meet all stated functional and electrical |
| NM4 | (12) | NS | SOP28W | 2007+ | Electrical characteristics are measured or characterized using a 223 - 1PR |
| NM5 | (17) | The RTC Registers are double-buffered into an internal and external set. | |||
| NM6 | (6) | NEWAVE | SOP | 00+ | Port 2: Is an 8-bit bi-directional I/O port with internal pull-ups. Port |
| NM7 | (18) | ST | SSOP24 | N/A | Figure 1 shows a typical battery pack application of the bq2014 using the |
| NM8 | (5) | NSC | DIP-16 | 1983+ | The bq2000 uses a peak-voltage detection (PVD) scheme to terminate fast c |
| NM9 | (273) | nsc | nsc | dc89 | PWM current drive is integrated with 8 bits of control. Four bits are glo |
| NMA | (70) | C&D | SIP | 99+ | The bq2085 supports the Smart Battery Data (SBData) commandsandcharge-co |
| NMB | (28) | NMBK | O7+ | Split supplies of 3.3V and 2.5V are used. The 3.3V power supply powers a | |
| NMC | (812) | NATIONAL | 1200 | DIP | S3901/S3904 series do not require any DC voltage supply for operation. |
| NMD | (9) | C&D | 98+ | IT887x design for card using INTA# (Sharing IRQx), driver auto detect IRQx | |
| NME | (55) | C&D | 06 | The input clock frequency, Fin, and the internal divider count, Cdiv, de | |
| NMF | (24) | C&D | SIP | 05+ | • Generation 4 IGBTs offer highest efficiencies available • |
| NMH | (41) | C&D | SOP | 99+ | 1. H = HIGH voltage level h = HIGH voltage level one set-up time |
| NMI | (2) | N/A | 0805L | Built-in Power Save Circuit Built-in Current Limit Circuit Built-in Th | |
| NMJ | (15) | C&D | SIP-5 | 06+ | The 16-bit processor is designed for efficient data execution by having di |
| NMK | (2) | N/A | QFP | 96+ | There is no built-in feature to allow software to detect if the device is |
| NML | (20) | C&D Technologies | SOP | 801 | While a single output may be used alone (includ- ing a coupling capacitor |
| NMN | (1) | N/A | 05+ | s 16/32-bit ARM7TDMI-S microcontroller in a LQFP144 package. s 16 kB on- | |
| NMO | (6) | SMD/DIP | SN | 500 | NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATIN |
| NMP | (198) | QFP | |||
| NMR | (47) | C&D | Filter Isolation: Rated voltage Resistance Capacitance Output Voltag | ||
| NMS | (40) | YAMAICHI | The Texas Instruments HPC3130A is a peripheral component interconnect (PC | ||
| NMT | (13) | 02+ | Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS | ||
| NMV | (56) | C&D | The IRU1015 is a low dropout three-terminal adjustable regulator with min | ||
| NMX | (21) | C&D | 0637 | IOAPIC clock output. (14.318 MHz) Poweredby VDDL CPU Output clocks. Powe | |
| NMZ | (1) | 2.3 External Special Function Registers (XFR) The XFR is a group of regis | |||
| NN- | (1) | Notes: 1: VC1 2.4 ,VC2 2.4, VM 2.4, VC1 5.0, VC2 5.0, VC3 5.0, VM13 5.0, | |||
| NN1 | (15) | 100 | O6 | Extremely Low VF Low Power Loss/High Efficiency Low | |
| NN2 | (6) | panasonic | TQFP-M80P | 06+ | ENA (Pin 10) (enable): ENA is a logic input that will en- able the PWM o |
| NN3 | (14) | N/A | N/A | N/A | The QS3V245 is an 8-bit high speed bus switch controlled by LVTTL- |
| NN4 | (4) | MOTOROLA | CAN3 | Stresses above those listed under Absolute Maximum Ratings may cause pe | |
| NN5 | (101) | NPN | 1998+ | SOJ-40 | The STK12C68-20 requires VCC = 5.0V 5% supply to operate at specified sp |
| NN6 | (2) | M | 2008 | (1) If any of the products or technical information described in this boo | |
| NN7 | (4) | NIPPON | 95+ | SOP | Pericom Semiconductor Corporations products are not authorized for use as |
| NN8 | (13) | PQFP | • Plastic package has Underwriters Laboratory Flammability | ||
| NNC | (212) | 霍尔传感器 | The adapter is provided as a low risk solution to a working Bluetooth s | ||
| NND | (6) | LAMBDA | Module | N/A | where CT is in Farads, and RT is in Ohms and tOSC is in seconds. CT can |
| NNJ | (2) | JRC | Chapter 3 - Description of Pin Functions, page 12 Chapter 4 - Description | ||
| NNK | (1) | SAMYOUNG | 05+ | Stresses beyond those listed under "Absolute Maximum Ratings" m | |
| NNL | (13) | C & D | 06+ | Acknowledge Acknowledge is a software convention used to indicate succe | |
| NNM | (1) | The three decades of the intermediate counter can be preset to a binary | |||
| NNP | (2) | SOP16 | The ICL7136 brings together a combination of high accuracy, versatility, | ||
| NNR | (5) | The IDT70V3319/99 is a high-speed 256/128K x 18 bit synchronous D | |||
| NNS | (14) | LAMBDA | Module | N/A | These devices employ the Schottky Barrier principle in a metal |
| NNT | (5) | (2) JC data values stated are derived from MIL-STD-1835B which states the | |||
| NO. | (2) | 2000 | The MAX1555s CHG is an active-low, open-drain charge status indicator. C | ||
| NO2 | (5) | MOT | 2008 | The internal circuit is composed of 2 stages including buffer output, w | |
| NO6 | (1) | Embedded program and block-erase functions are fully automated by an on-c | |||
| NOC | (1) | ||||
| NOD | (2) | A sub-repertoire of 10646 consists entirely of a set of coded characters | |||
| NOF | (1) | NO | The SN65C3223 and SN75C3223 consist of two line drivers, two line receive | ||
| NOH | (1) | QFP-120 | 04+ | Stresses beyond those listed under Absolute Maximum Ratings may cause per | |
| NOI | (1) | On-chip control functions make the ISD1000A Series very easy to use in a | |||
| NOJ | (50) | AVX | 2007+PB | Single supply: 1.8 V to 5.5 V Two-wire serial interface (I2CTM serial bus | |
| NOK | (8) | NOK | DIP | 9818+ | CPU output type select latch input pin 0= K7, 1= CK408 / AGP clock output |
| NOL | (2) | DIP | The FMS6346 provides an internal diode clamp to support AC- coupled inpu | ||
| NON | (11) | ROHM | TO252-3 | Pulse-testing techniques are used to maintain the junction temperature as | |
| NOP | (6) | NS | 05+ | In general, a higher operating frequency decreases the peak ripple curre | |
| NOR | (19) | ST | SOP28 | The NORA transmitter module is ideal for short-range wireless data applica | |
| NOS | (76) | AVX | 06+ | N/A | The IRIS4013(K) is a dual mode voltage and current controller combined wi |
| NOT | (37) | Cycle-by-cycle current limiting prevents the primary current from reachin | |||
| NOV | (16) | NOVACOM | 743 | The TOSHIBA TLP227G series consist of a gallium arsenide infrared emitti | |
| NP- | (2) | EZCHIP | SOP | 05+ | DIR input. The enable input G can be used to disable the device so that |
| NP0 | (25) | N/A | CHIP ENABLE The CE input is the device selection control. When the device | ||
| NP1 | (31) | NEC | TO-252 | 08+ | − Active Mode: 200 µA at 1 MHz, 2.2 V − Standby Mode: 0 |
| NP2 | (28) | ON | 2008+ | To set the new VTRIP voltage, apply the desired VTRIP threshold to the | |
| NP3 | (63) | NEC | TO-252 | 08+ | Atmel's 28C010 has additional features to ensure high quality in manufact |
| NP4 | (13) | NEC | TO-262 | 08+ | Power Diode Module DF75LA/LB is designed for three phase full wave rectif |
| NP5 | (19) | NPL | MQFP | 1998 | External Clock. This signal is used only in synchronous DPSK transmission |
| NP6 | (9) | NEC | TO-263 | 08+ | ICS has been shipping motherboard frequency generators since April 1990, |
| NP7 | (17) | 94 | Note: 6. Distribution data sample size is 398 samples taken from 4 differ | ||
| NP8 | (74) | NEC | TO-220AB | 08+ | When power is applied to VDD, an internal Power On Reset holds the NP84N |
| NP9 | (3) | NEC | TO-263 | 08+ | With a 144 pin package, low power consumption, various 32-bit timers, 8-c |
| NPA | (7) | N/A | When exiting the power-down mode, the application must supply power to | ||
| NPB | (2) | Hynix HYMD212G726(L)S4M-K/H/L series is designed for high speed of up to | |||
| NPC | (93) | N/A | . | The HC4015 consists of two identical, independent, 4-stage serial-input/ | |
| NPD | (17) | NS | 06+ | 500 | Read cycles are initiated with ADSP(regardless of WEx and ADSC)using the |
| NPE | (3) | KOA | 2W-62R | The Universal Serial Bus (USB) interface is a 12-Mb/s or 1.5-Mb/s, multip | |
| NPF | (3) | Agilent | BGA | • Supports up to 4 PHYs for Multi-PHY connections with 2- b | |
| NPG | (8) | stanley | stanley | dc96 | This family of four, eight, and sixteen differential line drivers imple |
| NPH | (44) | 成品 | 成品 | SNT-4A S-817A11APF-CUATFG S-817A12APF-CUBTFG S-817A13APF-CUCTFG | |
| NPI | (6) | N/A | ++ | 模块 | result in significant injury to the user. 2. A critical component is any |
| NPL | (14) | INTEL | PLCC-28 | 99 | The LVT16543 and LVTH16543 16-bit transceivers contain two sets of D-ty |
| NPO | (21) | SMD/DIP | SN | 500 | |
| NPP | (2) | The references for the four DACs are derived from one reference pin. The | |||
| NPQ | (4) | MOTOROLA | SOP | 04+ | clock cycle Interleaved auto refresh mode Programmable burst lengths and |
| NPR | (128) | N/A | Capacitor filter with precharge current limit Isolated gate drive circui | ||
| NPS | (12) | MIT | SMD | 04+ | The C6711/C6711B/C6711C/C6711D uses a two-level cache-based architecture |
| NPV | (1) | NS | QFP240 | 02+ | All functions can be planned by user like an MCU for more product applicat |
| NPX | (23) | MMC | 03/04+ | • Plastic package has Underwriters Laboratories Flammabilit | |
| NPY | (1) | Max. UnitsConditions CCCVVGE = 0V, IC = 500µA CCC V/C VGE = 0V, I | |||
| NQ0 | (12) | The unique differential input sample-and-hold can acquire single-ended or | |||
| NQ1 | (8) | Input Frequency Output Clock Rise Time Output Clock Fall Time Output Cl | |||
| NQ2 | (8) | SEEQ | PLCC32 | 03/+04+ | The Logic Diagram and Truth Table indicate the functional charact |
| NQ4 | (3) | INTEL | NEW | 04+ | CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic ch |
| NQ5 | (6) | NS | 06-07+ | OPERATION OF STEP-UP CONVERTER A step-up converter diagram is illustrated | |
| NQ6 | (12) | INTEL | 06-07+ | The A3280--, A3281--, and A3283-- Hall-effect latches are ex- tre | |
| NQ8 | (137) | SEEQ | PLCC44 | 03/+04+ | the ATU-C/ATU-R receivers and transmitters. Ex- ternal low noise driver |
| NQ9 | (2) | SEEQ | PLCC-28 | 07+ | The programmable single-chip multichannel cordless phone IC includes all |
| NQE | (23) | INTEL | 03+ | BGA | 16-Channel Single-Ended or 8-Channel Differential Inputs Low Supply Curr |
| NQL | (9) | MURATA | This digital clock is designed for use with high-speed CPUs and communicat | ||
| NQP | (2) | 2005 | NOTES: 1. Dimensions are in inches. Lead 1 is emitter, lead 2 is b | ||
| NQR | (6) | TOKO原盘 | SMD | Absolute Maximum Ratings indicate sustained limits beyond which damage to | |
| NQS | (35) | SMD/DIP | SN | 500 | 1. Test conditions: T = 25º C, Supply Voltage = +6 V, Device Voltage |
| NQV | (3) | N/A | 05+ | Figure 2 on page 4 shows one sample configuration of a SPORT using the p | |
| NR- | (23) | MATSUSHI | RELAY | 06+ | CNC7S101 is an AC input compatible optoisolator in which two GaAs |
| NR0 | (1) | MINISCRIBE | 90+ | PLCC | The UC62LV0256 is a high performance, very low power CMOS Static |
| NR1 | (26) | N/A | Synchronous, 95% Efficient, Boost Converter With 500-mA Output Current Fr | ||
| NR2 | (10) | BOSHIDA | 07+ | MODULE | The Motorola NR24D15S5B is a bipolar monolithic differential 2x2 c |
| NR3 | (10) | N/A | The individual iButtons that comprise the keypad can be arranged as desire | ||
| NR4 | (28) | SMD/DIP | SN | 500 | a. Absolute maximum continuous ratings are those maximum values beyond wh |
| NR5 | (23) | 1850 | C Language Compiler. A C language compiler is available that supports Cy | ||
| NR7 | (1) | 3. The analog input terminal (pin 6) has 21pF of input capaci- ta | |||
| NR8 | (6) | 2.3 Order of precedence. In the event of a conflict between the te | |||
| NR9 | (5) | N/A | 1900 | 板 | International Airport Industrial Park • Mailing Address: PO Box 1140 |
| NRA | (103) | NEC | 06+ | C Asynchronous Access Time C 70 ns C Page Mode Read Time C | |
| NRB | (8) | NEC | 06+ | The LH1540 is robust, ideal for telecom and ground fault applications. | |
| NRC | (1112) | NEC | 06+ | (All Min/Max characteristics and specifications are guaranteed over the Sp | |
| NRD | (90) | NEC | 06+ | Low Cost Complete H-Bridge 8 Amp Capability, 75 Volt Maximum Rating Sel | |
| NRE | (14) | 91 | INTERSIL | 3 | Update to speed.txt file 1.96. Corrections for CRs 111036,111137, 112697, |
| NRF | (42) | NORDIC | QFN | 05+ | Note: Stresses greater than those listed under MAXIMUM RATINGS may caus |
| NRG | (4) | Polarity/ Description Bus size RiseClock Feeds internal clock c | |||
| NRJ | (1) | These products are not designed for use in life support appliances, devic | |||
| NRL | (6) | nic | nic | dc0319 | 2.4V to 5.5V Single-Supply Operation Adjustable Gain or Fixed-Gain Option |
| NRM | (2) | The device is entirely command set compatible with the JEDEC 42.4 single | |||
| NRN | (5) | SMD/DIP | SN | 500 | The RST pin is normally driven high and will be clocked low when |
| NRO | (3) | Code Composer Studio and XDS510 are trademarks of Texas Instruments. Oth | |||
| NRP | (12) | The FOD2741 Optically Isolated Amplifier consists of the popular KA | |||
| NRS | (242) | NEC | 06+ | LIFE SUPPORT APPLICATIONS These products are not designed for use in lif | |
| NRT | (15) | SMD/DIP | SN | 500 | The core as delivered is warranted against defects for three years from p |
| NRU | (19) | NEC | 06+ | Serial data input pin. Conforms to the SMBUS specification of a Slave Rec | |
| NRV | (5) | ON | 06+ | The baseband signal can be digitized using Fairchild Semiconductors 8 bi | |
| NRW | (21) | SMD/DIP | SN | 500 | (*) CPD is defined as the value of the ICs internal equivalent capacitanc |
| NRX | (2) | PT | A flexible clock generation system enables the software to control the cl | ||
| NRZ | (1) | SUSUMU | 805 | 05+ | The Am29BDS643 is a 64 Mbit, 1.8 Volt-only, simulta- neous Read/Write, |
| NS- | (10) | DL | 06+/07+ | Input Termination Center-Tap. Each side of the transmitter differential in | |
| NS0 | (24) | NS | TSSOP-14 | SQD200A is a Darlington power transistor module which a high speed, high | |
| NS1 | (38) | NS | 8718 | This block provides a stable regulated output voltage starting from a bat | |
| NS2 | (22) | N/A | ON | 04+ | The MCF5275 family delivers a new level of performance and integration |
| NS3 | (169) | soc | n/a | f = up to 1kHz; COUT = 2.2µF ceramic; CBYP = 10nF f | |
| NS4 | (16) | NS | 05+ | NOTES: 1. Measured at 6.0 Vdc excitation for 100 mmHg pressure di | |
| NS5 | (5) | MOT | 2008 | The recommended dose of ultraviolet light for erasure is a wavelength of | |
| NS6 | (45) | SWAP | Beneficial comments (recommendations, additions, deletions) and any perti | ||
| NS7 | (45) | 95 | • Well Defined Spatial Radiation Patterns • Viewing | ||
| NS8 | (42) | NS | PLCC44 | 04+ | Services at every layer of the OSI networking reference model are impleme |
| NS9 | (26) | NS | 08+ | Hynix HYMD116G725A(L)8-K/H/L series is registered 184-pin double data rate | |
| NSA | (47) | NES | N/A | If the auto-increment flag is set, the three low order bits of the Contr | |
| NSB | (116) | ON | 06+ | 24000 | DESCRIPTION The RA07N3340M is a 7.5-watt RF MOSFET Amplifier Modu |
| NSC | (105) | ST-BUS & GCI Mode for Sin/Rout (Input). When in ST-BUS or GCI operat | |||
| NSD | (46) | NIHON | SMD | 05+ | Notes: 1. For codes not listed in the figure above, please refer to the r |
| NSE | (16) | SMD/DIP | SN | 500 | The PWP and RGE packages are available taped and reeled. Add an R suffix |
| NSF | (31) | Nihon | SMD | 05+ | Furthermore, the MAX104 provides latched, differential PECL outputs, whic |
| NSH | (22) | NIEC | 07/08+ | For example, if a lithium-ion battery (2.5 to 4.5V) is connected to the i | |
| NSI | (3) | Features 1) Power rating of 1 / 4W 2) Limiting element voltage of | |||
| NSJ | (1) | 3 channels of ESD protection for RGB output pins meeting IEC-61000-4-2 | |||
| NSK | (13) | STANLEY | 0403+ | The power MOSFET outputs of these devices are similar to the Internationa | |
| NSL | (25) | TDK | 直插 | Applications This line of Schottky diodes is optimized for use in mixer | |
| NSM | (35) | 0603TEM | The LTC®1628-SYNC is a high performance dual step- down switching reg | ||
| NSN | (2) | Q-LINK原盘 | 1040- | calls, and loops on the 24-bit program counter (PC). In direct addressin | |
| NSP | (49) | N/A | Interrupt Controller C Interrupt control module is responsible for the in | ||
| NSQ | (30) | N/A | outputs, input capture and output compare functions 1 Comm | ||
| NSR | (37) | ON-SEMI | 原装 | 07+08+ | Automatic backup and write protection of an external SRAM is provided thr |
| NSS | (53) | N/A | ON | 04+ | This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed |
| NST | (29) | SMD/DIP | SN | 500 | |
| NSU | (9) | NIHON | SMC | 08+ | Output clock. This pin is selectable under processor control to be either |
| NSV | (24) | JRC | 2not subject to production test, specified by design 3V Loaddump | ||
| NSW | (1) | When calculating synchronous frequencies, use tSU if all inputs are on | |||
| NSX | (10) | Attenuates wander from 2.1 Hz Fast Lock mode Provides Time Interval Err | |||
| NSZ | (3) | Onsemi | 07/260+ | 64K x 16 advanced high-speed CMOS Static RAM Equal access and cycle times | |
| NT- | (13) | • Thermal overload of Windings • Low Voltage Cutout • | |||
| NT0 | (10) | SOP | 00+ | Figure 2 illustrates the address spaces which are accessed by the DS2250( | |
| NT1 | (25) | NOGATECH | QFP-100P | 07+ | Note 4: TPPOS is a measure of transmitter output pulse position in compar |
| NT2 | (27) | NETAC | 1318 | 05+ | Time Out Counter. The Time Out is performed by a 14 Bit Counter that co |
| NT3 | (53) | N/A | N/A | N/A | Features • International standard packages • Low RDS (on) H |
| NT4 | (22) | FUJITSU | TO-220 | 02+ | COOutput capacitance2.533.5pF † All typical values are at respect |
| NT5 | (170) | NANYA | BGA | 2005 | *Standard version is shown in bold. The first letter after the part numb |
| NT6 | (303) | NT | 03+ | The CY7C133/143 has a flow-through architecture that facili- tates repeat | |
| NT7 | (90) | N/A | Power Supply VoltageVCC1.8-15V Error amplifier input voltageVI-.0.2-1.0 | ||
| NT8 | (32) | DIP8 | 05+ | ADSP-triggered write accesses require two clock cycles to complete. If GW | |
| NT9 | (47) | PAN | TO-220 | The MAX4729/MAX4730 single-pole/double-throw (SPDT) switches operate from | |
| NTA | (88) | C&D | SOP-10 | 00+ | attributes through memory-mapped control registers (MMRs) an extension |
| NTB | (156) | ON | TO-263(D2 PAK) | 08+ | Mechanical The primary thermal path for power dissipation is through t |
| NTC | (350) | N/A | The first three digits are significant figures and the last digit sp | ||
| NTD | (414) | ON | TO- | ||
| NTE | (259) | C&D | 06 | • 0.23 µm Process Technology • Simultaneous Read/Write | |
| NTF | (51) | ON | 07+ | ADM has built-in microcontroller and file management firmware that comm | |
| NTG | (43) | ON | SMD | 2008 | The DS1258 devices execute a write cycle whenever WE and either/both of CE |
| NTH | (367) | C&D | 06 | MM1231, and BA7602 VCC Operating Range From 4.5 V to 9 V Wide Frequency | |
| NTJ | (37) | ON | SOT-363 | 04+ | Built-in overvoltage protection prevents the output from going above 115% |
| NTK | (59) | DIP | 97+ | Transmit microphone input and the level adjustment. MAIN is connected to | |
| NTL | (27) | 2007 | 4.3 Screening (JANS, JANTX, and JANTXV levels only). Screening sha | ||
| NTM | (187) | ON | SOP-8 | 05+ | Outputs of the analog signal ground voltage. SGT outputs the analog signa |
| NTN | (14) | The HYM71V16M755HC(L)T8 Series are 16Mx72bits Synchronous DRAM Modules. Th | |||
| NTO | (3) | Ground referenced outputs High PSRR Available in sp | |||
| NTP | (90) | ON | TO-220 | 08+ | This miniature surface mount MOSFET features ultra low RDS(on) an |
| NTQ | (28) | † The PW package is available taped and reeled. Add R suffix to dev | |||
| NTR | (52) | ON | SOT-23 | 07+/08+ | Notes: 1. Test conditions assume signal transition times of 2 ns or less |
| NTS | (33) | P-DUKE | 2007 | Clock output with programmable frequency (up to 48 MHz) Co | |
| NTT | (43) | The Intersil ISL84521CISL84523 devices are CMOS, precision, quad analog | |||
| NTU | (16) | 1000 | Measurement includes the recommended interface connector. | ||
| NTV | (35) | C&D | SOP-10 | 00+ | Designed to interface logic to a wide variety of high current, high vol |
| NTW | (5) | JAT | 05+ | n Reduced Swing Differential Signaling (RSDS) digital bus reduces | |
| NTX | (3) | PTC | SOP14 | 0424+ | PGND (Power Ground): This pin provides a dedicated ground for the output |
| NTY | (3) | ON SEMICON | N/A | 2006 | − Average-Current-Mode Control for Continuous Conduction Mod |
| NTZ | (26) | ic | 06+ | Note: 1. H=VIH, L=VIL, X=don't care(VIH or VIL) 2. UB, LB(Upper, Lower | |
| N-U | (2) | ROHM | Notes: 1. Except for the rating Operating Temperature Range, stresses abo | ||
| NU. | (1) | NEUTRON | 0516+ | PLCC | 64 positions OTP (one-time programmable)1 set-and-forget resistance &nbs |
| NU1 | (14) | 0 | 0 | access is in progress and allows the requested data to propagate to the i | |
| NU2 | (1) | MIC | SOT23-5 | 04+ | Data Polling bit (DQ7). During the internal write cycle, any attempt to |
| NU3 | (1) | QFN | 05+ | The Atmel cell (Figure 4) is simple and small and yet can be programmed | |
| NU7 | (1) | The LF147 is a low cost, high speed quad JFET input operational amplifier | |||
| NU8 | (1) | INTEL | 07+散 | The device offers complete compatibility with the JEDEC 42.4 single-powe | |
| NU9 | (1) | Circuits for safe protective separation against electri- cal shock acco | |||
| NUD | (29) | ON | Control Signal Input. Used to control the flywheel synchronization when | ||
| NUF | (57) | N/A | ON | 04+ | It is based on optical navigation technology which measures changes i |
| NUM | (3) | JRC | (空白) | General Description MC68000/MC68008 Core System Integration Block (SIB) | |
| NUN | (1) | PANASONIC | SOT-23 | 03+ | On the next clock rise the data presented to DQs and DQP[A:D] (or a subse |
| NUP | (42) | ON | 07+ | Notes: 1. Use only a single 1% resistor in either the (R1) or R2 | |
| NUR | (3) | NEC | 06+ | SOT23 | 1. Each side of device measured separately. 2. MTTF calculator availabl |
| NUS | (14) | ON | WDFN6, 2x2, 0.65P | 08+ | • Access times of 70, 85 ns • CMOS low power operation: &nb |
| NUT | (5) | PHILIPS | 04 | Performance Motion Devices, Inc. assumes no liability for applications as | |
| NV- | (1) | The power supply operating range of the EL2244 and EL2444 is from 18V d | |||
| NV0 | (4) | SMD-8 | 04+ | Maximum ratings are those values beyond which device damage can occ | |
| NV1 | (10) | PHI | QFP-44 | 99+ | The 33394 is a multiCoutput power supply integrated circuit with h |
| NV2 | (18) | TAMA | 1206-27V | 05+ | Register-usage rules influence placement of input and results within the |
| NV3 | (12) | PW | QFP-208 | 04+ | Transmit high impedance mode is activated by setting the TXHIM bit in the |
| NV4 | (17) | 805 | Serial Programming I A LOW on this pin selects serial programming of parti | ||
| NV5 | (5) | N/A | N/A | N/A | DESCRIPTION The 74LVX16373 is a low voltage CMOS 16 BIT D-TYPE LATCH w |
| NV6 | (2) | NEC | DIP | 05 | Full-field Image Sensor 3500 x 2300 Pixels Pixel 10 µm x 10 µ |
| NV7 | (6) | KOA | 0805-12V | NOTES: (1) Stresses above these ratings may cause permanent damage. Expo | |
| NV8 | (5) | 2008 | FEATURES 10-Bit ADC with 9 s Conversion Time One (AD7818) and Four (AD7 | ||
| NV9 | (4) | 96 | address inputs @ 133MHz C Data input, address, byte enable and con | ||
| NVB | (1) | It is our intention to provide our valued customers with the best documen | |||
| NVC | (11) | N/A | N/A | N/A | 6. PD = CPD VCC2 fi + Ó (CL VCC2 fo) + Ó (VL2/RL) (Duty Fact |
| NVD | (6) | ST | 00+ | The ADC122S101 operates with a single supply that can range from +2.7V | |
| NVG | (2) | 1 Prior to the onset of overvoltage clamping. For voltages above this valu | |||
| NVI | (8) | NVIDIA | BGA | 03+ | This would allow the system to always power-up to a preset value stored |
| NVM | (4) | micronas | micronas | dc99 | The software Sector Erase mode is initiated by issuing the specific six-w |
| NVO | (1) | The Motorola accelerometer is a surface-microma- chined integrate | |||
| NVP | (6) | ON | TO两脚半 | 04+ | • 256 Resistor Taps • 2-Wire Serial Interface for write, read |
| NVS | (4) | TAIWAN | BGA | 0622+ | (All voltages referenced to GND unless otherwise noted.) VIN to GND VCC |
| NVT | (2) | INNOVENT | 96+ | TQFP1414-80 | An integrated 80-mA, 8-V regulator supplies voltage to the PVCC pin and |
| NW- | (2) | 2001 | Output Capacitors The minimum required output capacitance is 330µF | ||
| NW0 | (1) | Infineon | MQFP80 | 0.5 MICRON CMOS Technology VCCA = 2.3V to 3.6V VCCB = 3V to 5.5V CMOS p | |
| NW1 | (13) | ALI | 03+ | PLCC44 | Logic 0 Input Voltage (OUT = LO) Logic 1 Input Voltage (OUT = HI) ITRI |
| NW2 | (8) | NEWAVE | QFP | 2001 | A single transistor Collpits crystal oscillator provides a refere |
| NW3 | (1) | The integrated receiver is intended to be used as a single-conversion FSK | |||
| NW5 | (3) | N/A | QFP | 2000 | (5) Capacitor Selection A low ESR (Equivalent Series Resistance) |
| NW6 | (13) | N/A | 01+ | SOP-16 | Stresses beyond those listed under absolute maximum ratings may cause pe |
| NW7 | (2) | as Coss while VDS is rising from 0 to 80% VDSS . † Limited | |||
| NW8 | (11) | When a negative voltage is applied to pins 8 and 9, there should be no abn | |||
| NW9 | (2) | † Vres is the minimum input voltage for a valid RESET. The symbol V | |||
| NWA | (1) | The PKA 2000 I Series DC/DC power modules are designed in accordance with | |||
| NWC | (1) | N/A | • High BVCEO - Minimum 100 V for H11G1 - Minimum 80 | ||
| NWI | (1) | N/A | The input stage design of the LM6682/83 enables an input signal range t | ||
| NWK | (16) | N/A | QFP | alternative flash technologies. The total energy con- sumed is a functi | |
| NWP | (3) | NEWAVE | PLCC52 | This INFINEON module is an industry standard 144 pin 8-byte Synchronous D | |
| NWR | (1) | • 0.17 µm Process Technology • Simultaneous Read/Write | |||
| NWT | (3) | N/A | Full synchronous operation on both ports C 3.5ns setup to clock and 0ns | ||
| NWV | (6) | QFN | 05+ | Input Current, IIN, SCLK Pin Input Current, IIN, CS Pin &n | |
| NWW | (1) | Notes 1 Pk/pk voltage at Pins 6 and 7 of a 1MHz sine wave derived throug | |||
| NX- | (1) | TAIKO | N/A | 07+ | The high common-mode input voltage range and the absence of latch-up ma |
| NX1 | (7) | MQFP-128 | 2005 | 50mVp-p 50mVp-p 50mVp-p 50mVp-p 50m | |
| NX2 | (50) | TI | TSSOP-8 | 06+ | The in-Line Micro filter has been specifically designed to implement the |
| NX3 | (4) | NDK | 2005PB | Four (391), Eight (389) or Sixteen (387) Line Drivers Meet or Exceed the | |
| NX4 | (4) | NDK | 07+ | • High-performance RISC CPU • Only 35 single-word instructi | |
| NX5 | (11) | N/A | † Stresses beyond those listed under absolute maximum ratings may c | ||
| NX6 | (6) | WINCHESTER | 08+ | The information contained in this document is subject to change without n | |
| NX7 | (5) | An address access read is initiated by a change in address inputs while | |||
| NX8 | (20) | A/N | 24.000MHZ 24M | HIGH SPEED: fMAX = 180MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: I | |
| NX9 | (4) | PROGATE | MQFP128 | 03+ | These pins along with the HKS form a 4´4 keyboard matrix which can p |
| NXA | (20) | TYCO | 2006 | Designers must not rely on the absence or characteristics of any features | |
| NXC | (1) | ||||
| NXG | (2) | NEXG | TSSOP-16P | 0404 | Fully operational to +600V Tolerant to negative transient voltage dV/d |
| NXI | (5) | Absolute maximum ratings are limiting values, to be applied individually, | |||
| NXL | (1) | MTP805 includes all 8051 functions with the following exceptions: 1.1 PSE | |||
| NXS | (2) | ||||
| NXT | (9) | NXTWAVE | 00+ | QFP | Turn-On Time: In the circuit of Figure 2-1, turning Q1 on applies a low v |
| NXX | (1) | INPAQ | 2004 | TTL/CMOS Output Bank Synchronization Control. Internal 25kΩ pull-dow | |
| NY- | (3) | ||||
| NY1 | (3) | FUJITSU | Relay(new original) | When the configuration data for an FPGA device exceeds the capacity of a | |
| NY2 | (5) | DIP8 | NY | 96+ | The architecture of the current feedback opamp consists of a high impedanc |
| NY4 | (1) | TheHC4538andHCT4538aredual retriggerable/resettable monostable precision | |||
| NY5 | (3) | FUJITSU | Relay(new original) | Notes: Repetitive rating; pulse width limited by max. junc | |
| NY6 | (1) | IF IT DOES NOT WORK Poor soldering (dry joints) is the most common reaso | |||
| NY7 | (2) | The MSM7716 is a single-channel CODEC CMOS IC for voice signals that conta | |||
| NY9 | (1) | OKI | QFP | 0235+ | The HT812L0 provides 32 melody/tone sec- tions at maximum. Each section i |
| NYC | (1) | N/A | NOTES 1Sample tested at 25C to ensure compliance. All input signals are | ||
| NYL | (1) | ||||
| NYN | (6) | As a result of the high precision and low-noise characteristics of the O | |||
| NYP | (8) | saronix | saronix | dc0302 | To read the output of the TMS29xF040, a low-level logic signal is applied |
| NYS | (1) | • TOSHIBA is continually working to improve the quality and reliabil | |||
| NYT | (1) | high-frequency tube | RGAMP | 04+ | The TLV3011 and TLV3012 are available in the tiny SOT23-6 package for s |
| NZ0 | (7) | UNICOR | 03+ | Gate leakage current Collector-emitter saturation voltage(Note 4) Inp | |
| NZ1 | (3) | UNICOR | 03+ | Provide a well decoupled 5V bias supply for the IC to this pin. This pi | |
| NZ2 | (9) | Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output | |||
| NZ3 | (3) | 1206 | Mechanical stress performance is a greater considera- tion for a UCSP. UC | ||
| NZ4 | (4) | INTEL | 2003 | BGA | It is possible to program this family such that the maximum Junction Temp |
| NZ9 | (3) | DIODES | 二极(1812) | The third major contributor to pixel offset is the fact that as the shun | |
| NZD | (2) | ||||
| NZF | (5) | ON | SOT-353 | 04+ | SIGNAL DESCRIPTION Serial Data Output (Q). This output signal is used to |
| NZL | (12) | N/A | ON | 04+ | This Schmitt-Trigger input is used to transmit serial data when SD |
| NZM | (2) | ON | QFN 24 | 02+ | When an acceleration is applied to the sensor the proof mass displaces fr |
| NZP | (1) | N/A | SMD | 2000 | *Measured with full length lead. **Rated DC Current: Based on maximum tem |
| NZQ | (20) | ON | SOT-553 | 05+PB | RESET is asserted and the condition is latched until VHTH > VTH. Reset |
| NZR | (2) | N/A | SMD | 2000 | Cycle-by-cycle current limiting, under-voltage lockout with hyster |
| NZS | (2) | When the Deserializer PLL locks to the embedded clock edge, the Deseria | |||
| NZT | (24) | FAIRCHILD | 04+ | Bild / Fig. 6 B6 - Sechpuls-Brckenschaltung / Six-pulse bridge circuit H |
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