| Mfg | pack | D/C | Descrpion | ||
| O/I | (2) | ||||
| O-0 | (1) | NOTES : 1. In case of 40MHz Frequency, CL1 can be supported. 2. Samsung | |||
| O00 | (2) | gudeco | gudeco | dc00 | Device programming occurs by executing the program command sequence. This |
| O07 | (1) | PHILIPS | 2008 | IAC: (current proportional to input voltage) This input to the analog mul | |
| O08 | (1) | If the X76F102 is in a nonvolatile write cycle a no ACK (SDA=High) resp | |||
| O-1 | (2) | The Discharge Count Register (DCR) is used to update the Last Measured Di | |||
| O11 | (7) | SOP20W | 2007+ | Stresses above those listed under Absolute Maximum Ratings may cause pe | |
| O12 | (9) | O7+ | Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, | ||
| O13 | (4) | TSSOP | 04+ | This access is initiated when both of the following conditions are satisf | |
| O14 | (1) | The clock generator consists essentially of a PLL which generates the int | |||
| O15 | (3) | ADSC write accesses are initiated when the following condi- tions are sat | |||
| O17 | (3) | NS | 06+ | TO220 | The HSDL-3002 can be shutdown completely to achieve very low power co |
| O18 | (2) | NOTES: (1) Test Levels: (A) 100% tested at 25C. Over temperature limits b | |||
| O1D | (1) | N/A | TQFP-100 | The DS1258W provides full functional capability for VCC greater than 3.0V, | |
| O1N | (1) | HAR | TO92 | 2000 | The first step in choosing the right product is to select the diode typ |
| O20 | (4) | DFN-8 | 06+ | Reference inputs The voltage differential between the VREFL and VREFH i | |
| O21 | (4) | MOT | CAN4 | 03+ | Notes: 6. Test conditions assume signal transition time of 3 ns or |
| O23 | (1) | DIP | DIP | ||
| O24 | (3) | After the erase instruction is entered, CS must be brought LOW. The fall | |||
| O25 | (1) | 2007 | The WP pin, in conjuction with a WPEN bit programmed HIGH, provides Har | ||
| O26 | (1) | 04+ | Transmitter Differential Input. Input accepts AC- or DC-coupled differenti | ||
| O27 | (6) | 0 | 0 | NOTE: 1. RX outputs the bus state. If the bus level is below the receive | |
| O28 | (1) | The data strobes, associated with one data byte, sourced with data transfe | |||
| O29 | (2) | MICROCHIP | SSOP-24 | 00+ | NEC's MC-7831-HA is a GaAs Multi-Chip Module designed for use as input |
| O2C | (10) | TOS | SOT-23 | *Stresses above those listed under Absolute Maximum Ratings may cause per | |
| O2D | (9) | TOS | The Transmission Line Pulse tester implements a controlled impedance cabl | ||
| O2R | (1) | ELNA | N/A | 2003 | fast as 6.5 ns. The 256/512/1,024 x 36 dual-port SRAM FIFO buffers data fr |
| O2S | (2) | TheO2S4659-0xxxfamilyofmicroprocessor supervisory circuits monitor syste | |||
| O31 | (1) | The DAC7811 offers excellent 4-quadrant multipli- cation characteristics | |||
| O33 | (1) | FAIRCHILD | SOT-23 | IBREAK ICLK TRST VSS VDDI VDDE NMI P65/INT3 P64/INT2 P63/INT1 P6 | |
| O34 | (1) | The device has several operating modes dependent on the applied | |||
| O35 | (1) | FAI | DIP | 98+ | You can, however, measure the V-I demand of a motor (or any other load) |
| O37 | (2) | ON | DIP | DIP | Also See: • HEDS-9000/HEDS-9100 Encoder Module Data Sheet |
| O38 | (1) | Vsat: Saturation voltage of the output switch. VF: Forward voltage drop | |||
| O39 | (4) | 0 | 0 | For the device-specific interrupt priority configurations, see the Interr | |
| O3C | (1) | All the benefits of current mode control including simpler loop closing | |||
| O3D | (1) | The UC62LV0256 is a high performance, very low power CMOS Static | |||
| O3N | (2) | N/A | SMD | 95+ | An output capacitor of at least 10uF must be used to insure stability o |
| O3P | (2) | NEC/JD18/89 | 04+/05+ | The bq2083−V1P2 SBS-compliant gas gauge IC for battery pack or in | |
| O40 | (3) | POKERC3 | TQFP-216P | 00+ | DESCRIPTION Single rectifier suited for Switch Mode Power Supply and h |
| O42 | (2) | Stresses beyond those listed under "absolute maximum ratings" m | |||
| O45 | (1) | TSSOP-20 | 00+ | The MTC20136 is a dedicated controller chip, spe- cifically designed to | |
| O46 | (5) | TFK | PLCC- | 07+/08+ | FAST data sheets carry several types of AC information. The AC Character |
| O47 | (4) | HAR | SOP | 9913 | When T1 is set to logic 1, the programmable divider out- put signal is s |
| O48 | (4) | HAR | SOP-7.2-20P | 6+ | This pin sets the internal signal gain at the inputs to the ADCs. With |
| O4A | (1) | DATA POLLING: The AT29LV1024 features DATA polling to indicate the end o | |||
| O4F | (1) | Notes: 1. For codes not listed in the figure above, please refer to the r | |||
| O4M | (1) | 3225 | Bidirectional 3-bit input/output port. Software instructions determine the | ||
| O4N | (1) | Thermal Resistance . . . . . . . . . . . . . . . .jajc Ceramic DI | |||
| O4O | (1) | When MULTIPLEX is low, this is DB0. When MULTIPLEX is high this is the | |||
| O50 | (4) | PLCC | The 24XX32A supports a bidirectional, 2-wire bus and data transmission | ||
| O51 | (1) | KONAMI | DIP40 | 8915 | The AFEU processes an algorithm that is compatible with the RC4 stream ci |
| O52 | (3) | KONAMI | DIP28 | 9007 | attributes through memory-mapped control registers (MMRs) an extension |
| O53 | (1) | 100KEP circuits are designed to meet the DC specifications shown in the a | |||
| O54 | (1) | NEC | 00+ | The ADCIN bit selects the input of the on-chip A/D converter. When the | |
| O59 | (1) | USI | SMD | SMD | TOUT C This pin is the buffered output of the temperature sensor. The an |
| O5V | (1) | SHARP | TO220-5 | (8051-compatible) with up to 24 MHz (min. 250 ns) Videotext decoder a | |
| O60 | (3) | 600 | NULL | NULL | Senses motion of ring magnet targets Integrated filter capacitor |
| O61 | (2) | Reference Output Voltage: This output biases to VCC C1.2V. Connect to VT | |||
| O62 | (1) | QFP64 | The Input/Output logic timing diagram is shown in Figure 1. For proper op | ||
| O64 | (2) | BRAUN | 2008 | ||
| O66 | (1) | 1. Set the heater block temperature to 260C +/- 10C. 2. Use pre-stressed | |||
| O68 | (1) | • Microchips Worldwide Web site; http://www.microchip.com • | |||
| O6K | (1) | 0 | 0 | The Mode-Select Inputs permit frequency-synthesizer channel separations | |
| O70 | (1) | SHARP | 01+ | DIP | NOTES: (1) 2.0ms, pulse width, f=1.0 KHZ (2) Pulse test: 300ms pulse wi |
| O71 | (2) | N/A | OKI | 04+ | Military temperature range Output skew 2.0 ns typical Input to outpu |
| O72 | (2) | LHINO | TO220 | The FM25L16 provides substantial benefits to users of serial EEPROM as | |
| O74 | (1) | ||||
| O7N | (1) | Power On Reset: V CC Lock-Out Write Protect In order to prevent data cor | |||
| O80 | (2) | jauch | jauch | dc99 | Notes: 1. For Max. or Min. conditions, use appropriate value specified u |
| O82 | (1) | 0 | 0 | The XP132A1275SR is a P-Channel Power MOS FET with low on-state resistan | |
| O83 | (1) | N/A | QFN-24 | 04+ | NOTES: 1Full Scale Range (FSR) is 10V for unipolar mode. 2Guaranteed b |
| O88 | (1) | NS | SMD | NOTES: 1. The ICC current listed includes both the DC operating current a | |
| O89 | (1) | Table 1 is a memory map of the 1024-bit EPROM section of the bq2022, conf | |||
| O8A | (1) | The PWR5104 and PWR5105 offer respectively 12VDC and 15VDC outputs of r | |||
| O8G | (1) | • Non-Time Delay fuses for high voltage instruments and cir- | |||
| O90 | (2) | 2008 | Optimizing the controller and the synchronous FETs results in the highes | ||
| O93 | (8) | 1 | AMIS | 03+ | 4ž_ÞÐW FUNC [1]‘ôDÈ Aœ Ah FUNC |
| O94 | (1) | 6 | QFN | The CAN driver IC B10011S is a low-speed, high-level interface for 24 V ( | |
| O99 | (3) | AMIS | 06+ | Output Current, IOUT(2) Minimum Load Current, IL (MIN) LBI Input Thresho | |
| O9K | (3) | 0 | 0 | 3.3-V power. I/O 3.3-V circuit power terminals. A combination of high-fre | |
| OA- | (9) | OASIS | 02+ | QFP | Once the deserializer has synchronized to the serializer, the LOCK pin tr |
| OA1 | (12) | tfk | n/a | Single power supply. Crystal/Ring oscillator option. 3-340 seconds voice | |
| OA2 | (7) | BB | 1450 | Output IP3 at 100MHz: 47dBm Maximum Output Power: 21dBm Bandwidth: LF to | |
| OA3 | (7) | Infineon | TQFP144 | 99+ | Drain-to-Source Breakdown Voltage 200 Gate Threshold Voltage …2.04 |
| OA4 | (1) | The clock signal connected to this pin is used to serially shift right th | |||
| OA8 | (2) | csf | n/a | VCXOs are usually used as a narrowband local frequency source that is l | |
| OA9 | (3) | 松下 | The 74HC/HCT299 contain eight edge-triggered D-type flip-flops and the | ||
| OAA | (4) | CPCLARE | DIP-8 | 02+ | THEORY OF OPERATION The MEMSIC device is a complete dual-axis accelerati |
| OAC | (14) | USA | 模块 | 08+ | The output voltage of the PT6520 series of integrated switching regulato |
| OAD | (11) | AD | SOT23 | 6+ | The HD404358 Series is a 4-bit HMCS400-Series microcomputer designed to i |
| OAH | (4) | Notes: 1. Isolation voltage shall be measured using the following method | |||
| OAK | (1) | AMD | Note 11: If the product is in shutdown mode and VDD exceeds 6V (to a max | ||
| OAM | (2) | FEVRE | SSOP-36 | Pin 11 is the clamp gate input pin and is driven by a TTL back po | |
| OAO | (1) | OPTi | O7+ | The chopper stabilized amplifier uses switched ca- pacitor techniq | |
| OAP | (1) | SDRAM read and write accesses are burst oriented starting at a selected | |||
| OAR | (27) | IR | 07+ | All devices provide break-before-make switching and are TTL and CMOS co | |
| OAS | (10) | ST | 00+ | The HYM72V32M636T8 Series are Dual In-line Memory Modules suitable for eas | |
| OAT | (6) | WRI | SOP | 01+ | Hynix HYMD116725B(L)8-M/K/H/L series is designed for high speed of up to |
| OAV | (1) | ||||
| OAW | (1) | Ruotare il selettore su ON . Qunado lalimentazione a ON e si applica i | |||
| OB- | (16) | N/A | SOP14S | 06+ | The AD5620/AD5640/AD5660-1 parts include an internal, 1.25 V, 5 ppm/C re |
| OB0 | (1) | IVENTEX | C.T 3L | 2006 | |
| OB1 | (5) | NAKAMLCHI | DIP | 92 | The LCX74 is a dual D-type flip-flop with Asynchronous Clear and Set in |
| OB2 | (20) | MALAYSIA | TQFP | 97+ | This new series of digital transistors is designed to replace a si |
| OB3 | (4) | ONS BRIGHT | 06+/07+ | The XR16C854/854D1 (854) is an enhanced quad Universal Asynchronous Rec | |
| OB4 | (1) | N/A | SMD | 2000 | The specified performance in the table are results based on the electrical |
| OB5 | (2) | N/A | N/A | The AD581 has the capability to either source or sink current and provid | |
| OB6 | (2) | SAMBU | ¶ Stresses beyond those listed under absolute maximum ratings may ca | ||
| OB9 | (1) | Receive Sync Bit output (Digital). In DN mode, this output is held high u | |||
| OBA | (1) | N/A | SOP | 06+ | Partial Reset also sets the Read and Write pointers to the first locatio |
| OBB | (1) | AD | 04+ | SOT25 | Secured Silicon Sector: Extra 256 Byte sector Factory locked and |
| OBC | (2) | ALCATEL | 06+ | 500 | internal pullCup is provided on LSS allowing the device to |
| OBD | (8) | AD | SOT23 | 6+ | In Europe, Caller ID requirements are defined by ETSI. The CPE documents |
| OBF | (3) | BSE | NA | The MAX1921 sucessfully meets the quality and reliability standard | |
| OBG | (10) | BSE | 04+ | This MOSFET is an enhancement-mode silicon-gate power field-effect | |
| OBH | (9) | Note 2: All input and/or output pins shall not exceed VCC + 0.5V and shal | |||
| OBI | (1) | Note 1: Absolute Maximum Ratings are limits beyond which damage to the dev | |||
| OBL | (2) | The 8 mm (0.31 inch) LED seven segment displays are Agilents most space- | |||
| OBN | (1) | N/A | DIP | 94+ | HIGH SPEED : tPD = 5.4 ns (MAX.) at VCC = 3V 5V TOLERANT INPUTS POWE |
| OBO | (1) | obo | obo | dc04 | The OBO14240ST is a compact high efficiency step-up boost regulat |
| OBP | (27) | DONGAH | 00 | NOTE: Intersil Lead-Free products employ special lead-free material sets; | |
| OBQ | (1) | M | 5P | The MT8931C Subscriber Network Interface Circuit (SNIC) is a multifunctio | |
| OBS | (7) | N/A | NOTES 1Typicals represent average readings at 25C and VDD = 5 V, VS | ||
| OBT | (1) | TSSOP-8 | 99+00+ | Page Write Page write allows up to 64 bytes to be consecu- tively latch | |
| OBU | (2) | ||||
| OBW | (1) | ||||
| OC- | (5) | TARNSFER/MARNUAL | The SNAP! Pulse programming algorithm uses initial pulses of 100 microsec | ||
| OC0 | (3) | OKI | CIRCUIT OPERATION The SP8480 is a complete 8-channel data acqui- sition | ||
| OC1 | (11) | 3580 | NMOS linear image sensors are self-scanning photodiode arrays designed sp | ||
| OC2 | (17) | DSI | n/a | The pre-heat time is determined by an RC combination formed by R3 | |
| OC3 | (11) | 金属帽 | Tiny SOT−353 and SOT−553 Packages Extremely High Speed: tPD 2 | ||
| OC4 | (14) | N/A | 06+ | 500 | Through dynamic, symmetric-mutual authentication, data encryption, and th |
| OC5 | (10) | N/A | NOTES 1Stresses above those listed under Absolute Maximum Ratings may ca | ||
| OC6 | (1) | OKI | DIP16 | 92 | The EM78M612 series has sereval types of packaging. Each type is divided |
| OC7 | (12) | 金属帽 | 202 | Protection features of this controller IC include a set of sophisticated | |
| OC8 | (2) | nkt | n/a | The SG1525A/1527A series of pulse width modulator integrated circuits are | |
| OC9 | (2) | SINSKA | 01 | Available in 1.5V, 1.8V, 2.5V, 3V, 3.3V, 5.0V and adjustable versions | |
| OCA | (3) | PLCC | 03+/04+ | Other features include low quiescent current, typi- cally 70µA, and | |
| OCC | (8) | 150 | SOP | Mitsubishi Electric Corporation puts the maximum effort into making semic | |
| OCE | (14) | PQFP44 | 2007+ | portable equipment applications or wherever the following requirements | |
| OCH | (5) | SAMYOUNG | 03+ | The OCH8107C621 SHARC DSP is the first processor in a new family featuri | |
| OCI | (10) | 00+ | 3.2 KSO8~15 These pins are direct output from the 8051 Port2 and dedicate | ||
| OCK | (2) | The ispLSI 5000VE encompasses the innovative fea- tures of the ispLSI 5 | |||
| OCM | (46) | OKI | SOP-8 | 07+ | The BUF12800 programmable voltage reference allows fast and easy adjust |
| OCN | (2) | DELTA原盘 | SMD | Ideally, the relative size of measurement error should be fairly consta | |
| OCO | (1) | ||||
| OCP | (7) | ORIGIN | 07+ | Voltage follower/buffer/amplifier Charge integrator Photodiode amplifie | |
| OCR | (1) | RoHMIC | 0514+ | VDD: The power input connection for this device. Although quiescent VDD c | |
| OCS | (10) | OKI | DIP | 1993 | BRIDGE input. This input is used to set the Bridge_Aware bits located in |
| OCT | (10) | N/A | SMD | 2000 | In an effort to provide up-to-date information to the customer reg |
| OCV | (1) | PHILI | ++ | PLCC44 | As shown in Figure 4, the falling edge of the 8 kHz input signal (C8Kb for |
| OCX | (2) | ISOTEMP | SOP | 04+ | Stresses above those listed under Absolute Maximum Ratings may cause perm |
| OD- | (16) | IN STOCK | 9007 | NF | a8255 MegaCore function implementing a programmable peripheral interface |
| OD0 | (1) | 68 | PHILIPS | 99/00+ | |
| OD1 | (1) | FAI | 91 | IrDA Data Features • Fully compliant to IrDA physical layer | |
| OD2 | (2) | Note 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS | |||
| OD3 | (4) | N/A | SMD | 2000 | Differential analog Inputs. With a 1.0V reference voltage the differenti |
| OD4 | (1) | The single conversion superheterodyne receiver approach is now generall | |||
| OD5 | (2) | denyo | denyo | dc94 | TKVZat %/K Min.Max. 00.07 0.030.08 0.030.08 0.05 |
| OD6 | (4) | AD | 07+ | CONNECTION MEMORY Data to be output on the serial streams may come | |
| OD8 | (3) | INTEL | CDDIP28 | The HS-800/810 Series of quartz crystal oscillators provide MECL 10K and | |
| OD9 | (4) | Negative chip select, when at a low level allows normal read or write ope | |||
| ODC | (8) | MODEL | 模块 | 08+ | /Power-Good Output 3: Open Collector. Asserted when the following is true |
| ODD | (2) | Complex signal data is input with I data driving one input port and Q dat | |||
| ODE | (7) | Panasonic | SOP14S | 2007+ | For base station radio card unit LNA application where better than 2:1 |
| ODI | (1) | • RAM expandable externally to 64 kbytes • PLCC and LQFP packa | |||
| ODL | (2) | Low-power dissipation Operating: 9 mW/MHz (typical) Single power supply | |||
| ODM | (41) | NA | 03+ | To determine the need for and value of the crystal adjustment capacitor | |
| ODO | (1) | XICOR | CDIP28 | —— | |
| ODP | (5) | N/A | DIP | 07+ | 4.4.3 Group C inspection. Group C inspection shall be conducted in |
| ODS | (6) | HDK | Linux Operating System One of the distributions of Linux One of the dist | ||
| ODT | (1) | Clocks in the ispLSI 1048E device are selected using the Clock Distribut | |||
| ODV | (5) | 05+ | The ODV5D and ODV5D are designed to limit at 0.9-A load. These power dist | ||
| ODZ | (1) | NA | NA | Stresses beyond those listed under Absolute Maximum Ratings may cause perm | |
| OE1 | (3) | (LX)high-frequency | The HS-1135RH is a radiation hardened, high speed, low power current fe | ||
| OE2 | (3) | TI | TSOP56 | 2007+ | ‡ All typical values are at VCC = 5 V, TA = 25C. The output cond |
| OE3 | (4) | FREESCALE | QFP | The OE35D is 33,554,432 bits synchronous high data rate Dynamic R | |
| OE6 | (1) | N/A | 06+ | AD2 lines provide register addresses for data passed through the data pin | |
| OE9 | (4) | TI | SOP-8 | 20+ | Differential LO input with high input impedance. This pin requires extern |
| OEA | (1) | N/A | PQFP-208 | 99 | High Voltage: Operation Up to 72V Synchronizable Operating Frequency and |
| OEC | (265) | N/A | QFP | 04+ | FEATURES 1 pC Charge Injection 2.7 V to 5.5 V Dual Supply +2.7 V |
| OED | (6) | A sub-repertoire of 10646 consists entirely of a set of coded characters | |||
| OEM | (5) | 07+ | The users system monitors the LOCK pin to detect a loss of synchronizati | ||
| OEP | (1) | Escape Characters - An escape sequence may be entered while in data mod | |||
| OES | (9) | DC/DC: | Notes regarding these materials 1. These materials are intended as a ref | ||
| OEU | (1) | ASI | PGA | 9943+ | A simple op-amp circuit is used to program the output voltage of a typic |
| OF- | (3) | TRI-STATE version of LS153 with same pinout Schottky-diode-clamped trans | |||
| OF0 | (2) | DIP-8 | (1) Offset error is the deviation of the average code from mid-code for a | ||
| OF1 | (11) | ORIGIN | SOP | Capacitor mounted close to the power module helps ensure stabilit | |
| OF2 | (10) | NIEC | SOP | Features International standard packages JEDEC TO-264 AA, e | |
| OF3 | (33) | N/A | N/A | 2000 | Host clock frequency selection is achieved by applying the appropriate lo |
| OF4 | (47) | Philips | 2008 | Note 1: Includes temperature rise caused by current flow. Note 2: The ter | |
| OF5 | (8) | The ML6428 is a dual monolithic continuous time video filter desig | |||
| OF6 | (6) | 96 | In order to increase the adjustment range of VCO3 with fixed external tan | ||
| OF7 | (22) | ORIGIN | SOP | Leading edge blanking is also applied to the current limit comparator. | |
| OF8 | (9) | DIP | The SI-3033LSA is designed to meet the requirement for increased | ||
| OF9 | (9) | The Motorola MPC555EVB/ETAS ES200 evaluation board was designed with mult | |||
| OFA | (39) | NULL | N/A | The FM25L16 is a 16-kilobit nonvolatile memory employing an advanced fe | |
| OFF | (1) | The 74HC/HCT147 9-input priority encoders accept data from nine active | |||
| OFG | (1) | OPTO TECH | A | A | All devices present a 1/8 unit load to the RS-485 bus, which allows up to |
| OFJ | (1) | Split power: Core VCC (3.0C3.6 V currently) I/O VCC (3.0C3.6 V current | |||
| OFM | (9) | s Wide supply voltage range from 0.8 V to 3.6 V s High noise immunity s | |||
| OFO | (1) | . | . | 03+ | † Stresses beyond those listed under absolute maximum ratings may c |
| OFR | (1) | Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V | |||
| OFS | (1) | ST | − Read, program, and erase operations from 2.7 to 3.6 V &# | ||
| OFT | (1) | ||||
| OFW | (50) | sie | sie | dc91 | • High current sink/source 25 mA/25 mA • Three external int |
| OFX | (1) | Register oriented 8/16 bit CORE with RUN, WFI, SLOW, HALT and STOP mode | |||
| OG- | (13) | N/A | Room = 25C, Full = as determined by the operating suffix. Typical values | ||
| OG0 | (1) | The standard Xilinx Foundation Series™ and Alliance Series™ | |||
| OG3 | (2) | The TLV2262/4 also makes great upgrades to the TLV2332/4 in standard desi | |||
| OG4 | (1) | Notes: 1. SSSEL has internal pull-up and SSON has pull-down resist | |||
| OG5 | (1) | Maximum ratings are those values beyond which device damage can occur. Ma | |||
| OG8 | (1) | NS | 83+ | DIP | time exhibits drift characteristics of the best low-drift amplifi- ers T |
| OGC | (4) | N/A | The OGC-331610 power amplifier module (PAM) is designed for WCDMA appli | ||
| OGD | (1) | 08+ | Serial configuration control input. This inputs controls the loading of | ||
| OGI | (1) | This output is an open collector stage which requires a pull-up resistor | |||
| OGK | (3) | Ohkura | QFP | 07+ | Flash Media Controller Complete System Solution for interfacing |
| OGM | (6) | ODT | 00+ | These electrically erasable programmable memo- ry (EEPROM) devices are | |
| OGN | (1) | ||||
| OGP | (3) | The following are trademarks of Conexant Systems, Inc.: Conexant, the Con | |||
| OGV | (2) | QFN | 05+ | Notes a. When Mounted on 1 x 1 PCB FR4 Board. b. Not tested, specified | |
| OH- | (3) | DL | 06+/07+ | to be transmitted to the sensor diaphragm. The gel die coat and durable | |
| OH0 | (22) | PANASONIC | SOT23-4 | The CD4009UB and CD4010B types are supplied in 16-lead hermetic dual-in-l | |
| OH1 | (20) | Optek | 3 | n Integrated OLED and white-LED driver n 80% efficiency n Drives up 5 | |
| OH2 | (4) | PH | SOT453B | The graphs and tables provided following this note are a statistical summa | |
| OH3 | (9) | SHARP | TQFP-M100P | 06+ | CAUTION: These devices are sensitive to electrostatic discharge; f |
| OH4 | (1) | ZILOG | DIP | 00+ | Highly specialized electronic sensors have been designed to automate sampl |
| OH7 | (1) | MOT | SOP | 07+ | Note *)NC pin number : No. 33, 34, 47, 48, 49, 50, 63, 64 NC: No Connect |
| OHA | (2) | TI | |||
| OHB | (1) | optekinc | The SST39VF160Q/VF160 devices are 1M x 16 CMOS Multi-Purpose Flash (MPF | ||
| OHC | (2) | 414 | ROHM | 05+ | Reel Options: 3,000 per 7 inch reel/8 mm tape Reel Options |
| OHD | (19) | OPTEK | No external capacitors (919 only) Excellent signal quality Very low jitt | ||
| OHL | (1) | SMT | • Industry Standard Size • Industry Standard Pinout | ||
| OHN | (9) | Optek | 3 | Supply voltage: VCC = 2.7 to 4.0 V, ICC = 28 mA @ VCC = 3.0 V Built-in L | |
| OHO | (1) | The OHO43 center tap Schottky rectifier module series has been optimized | |||
| OHP | (1) | The VCXH16244 contains sixteen non-inverting buffers with 3-STATE outpu | |||
| OHS | (33) | SOP | 02+ | C Seven 16-KB blocks Auto Erase (chip & block) and Auto Program C | |
| OHT | (5) | RAYTRON | 05+ | DESCRIPTION Oscillator. The output current at ROSC pin is mirrored to | |
| OI6 | (2) | • Compliant with ATM, SONET OC-3, SDH STM-1 and SONET OC-12 | |||
| OI7 | (1) | Alternately, you can get accurate time, all the time, by using a radio clo | |||
| OI9 | (1) | Trim sensitivity is a parameter which can be supplied by your crystal v | |||
| OIB | (2) | This link option selects the source of the CONVST input. When this link | |||
| OID | (1) | Note: (1) This parameter is tested initially and after a design or proce | |||
| OIG | (3) | LGS | 02+ | DIP-M30P | The configuration bits work by acting as control inputs for the multiple |
| OIH | (4) | OHSUNG | 03+ | DIP-S28P | RFMs TX-series hybrid transmitters are specifically designed for short-ra |
| OII | (2) | Parameter MAXIMUM CONVERSION RATE MINIMUM CONVERSION RATE DUTY CYCLE & | |||
| OIK | (1) | IC | SOP | Note 1: Absolute Maximum Ratings indicate limits beyond which damage to t | |
| OIL | (2) | N/A | N/A | 04+ | The ADS5423 is available in a 52 pin HTQFP with heatsink package and is p |
| OIM | (14) | LG | 2008 | The default values of the programmable Received Line Signal Detector (R | |
| OIN | (2) | PHIL | QFP | 03 | The OINSL-0003A is a complete 16-bit, - analog-to-digital con- verter wi |
| OIP | (4) | 04+ | a) Adopting new 4th generation planar IGBT chip, which per- forma | ||
| OIS | (10) | 05+ | Unless otherwise specified, the following specifications apply for AGND = | ||
| OIT | (1) | LG.PHILIPS LCD | QFP160 | 06+ | Low End of Resistor High End of Resistor Wiper Terminal of Resistor Sub |
| OIZ | (5) | Discription Data bit 0 of Transmit Symbol, true data Data bit 1 of Tra | |||
| OJ- | (9) | ALEPH | 2001+ | To drive the device from an external clock source XTAL1 should be driven | |
| OJ2 | (1) | ||||
| OJC | (9) | The analog input RGB signals are first sampled by three channels of 8-bit | |||
| OJE | (13) | OEG | Relay(new original) | Agilent Part # and Options Commercial MIL-PRF-38534 Class H Standard | |
| OJG | (1) | The TSOP344..SB1F - series are miniaturized receiv- ers for infrared re | |||
| OJM | (1) | N/A | 08+ | The two address buses (PMA and DMA) share a single external address bus, | |
| OK0 | (2) | Differential clock input. The TFP513 supports both single-ended and fully | |||
| OK1 | (1) | To improve the performance of both Bluetooth and 802.11b/g co-located sys | |||
| OK2 | (1) | ||||
| OK3 | (1) | FRESSCAL | 06 | *6 Half-wave pulse of sine wave: 11ms; detection time: 10µs *7 Hal | |
| OKA | (1) | The triple driver IC includes three non-inverted and current-limited outp | |||
| OKB | (2) | SAMSUNG | . | NOTE: EP circuits are designed to meet the DC specifications shown in the | |
| OKI | (31) | SMD16 | 0 | 4.3 Screening (JANTX level only). Screening shall be in accordance | |
| OKM | (1) | OKSORI | 00+ | DIP-32 | • Lower switching losses allow more cost-effective operatio |
| OKO | (2) | QFP | 9913+ | A write cycle is accomplished by asserting write enable (WE) and both chi | |
| OKS | (6) | kos | kos | dc99 | DESCRIPTION The LD1085 is a LOW DROP Voltage Regulator able to provide |
| OL- | (1) | Frame synchronization input for the data input. When this pin goes low, | |||
| OL1 | (5) | oshinolamps | oshinolamps | dc98 | Designed for broadband commercial and industrial applications with |
| OL2 | (5) | SSOP | 06+ | Notes: 1. V = Valid , x = Dont Care, L = Low Level, H = High Level 2. C | |
| OL3 | (8) | JAT | SOT | 05+ | The simplest circuit is a simple op amp follower as shown in Fig- ure 3A |
| OL4 | (1) | 16 Channels 12-bit (4096 Steps) Grayscale PWM Control Dot Correction C | |||
| OL5 | (1) | NOTE: The inhibit function of the zero or carry outputs does not end wh | |||
| OL6 | (3) | MOT | SMD | When the amplifier is current limiting, there may be small signal | |
| OL7 | (2) | OPTOLAB | 06+ | Notes: 1. All inputs except OE must meet setup and hold times for the L | |
| OL9 | (1) | ODTECH | 05+ | † Stresses beyond those listed under absolute maximum ratings may c | |
| OLA | (15) | N/A | N/A | Serial Programming I A LOW on this pin selects serial programming of parti | |
| OLB | (2) | sie | sie | dc88 | The LEGACY subsystem is the circuitry required to perform SoundBlaster, O |
| OLD | (4) | Panasonic | Output frequency range: 1450 MHz to 1750 MHz Divide-by-2 output 3.0 V t | ||
| OLH | (4) | S | 4 | Leading-edge triggering (A) and trailing edge triggering (B) inputs are | |
| OLI | (4) | NJAPAN | O7+ | Single Schottky rectifier suited to Switched Mode Power Supplies and hi | |
| OLM | (2) | PLCC | 04+ | the part number LM27CIM5-2SJ has TOS = 147˚C, and programmed | |
| OLO | (1) | SANYO | QFP-80 | 04+ | Fully compliant with USB v1.1 specification and USB Device Class Definiti |
| OLS | (4) | osa | osa | dc99 | A: The value of R JA is measured with the device mounted on 1in FR-4 boar |
| OLT | (1) | PHILIPS | 05+ | Note 3 The maximum absolute allowable voltage which may be applied to the | |
| OLX | (1) | kyocera | kyocera | dc07+ | Allows Safe Board Insertion and Removal from a Live Backplane Controls S |
| OLZ | (2) | TOSHIBA | The NJM2591 is a wide - operating voltage, low C current FM IF dem | ||
| OM- | (6) | CYTEL | QFP | 97 | The Fairchild Switch FST162245 provides 16-bits of high- speed CMOS TTL |
| OM0 | (1) | EMC | DIP | 06+ | The 74LVC(H)16244A is a high-performance, low power, low voltage, Si-ga |
| OM1 | (79) | . | Left channel positive output in BTL mode and SE mode. Supply voltage Lef | ||
| OM2 | (10) | This is an analog output which can be used as a reference source and/or | |||
| OM3 | (15) | ph | ph | dc95 | DYNAMIC PERFORMANCE Maximum Output Update Rate (fCLOCK) Outp |
| OM4 | (34) | PHILIPS | 2008 | The OM4031T provides a highly integrated power control and protection s | |
| OM5 | (220) | PHILIPS | 2008 | With CS Low - Figure 3. After initial power-up and the Hold inpu | |
| OM6 | (114) | PHILIPS | BGA | 03+ | VDD3V3 NC VDD2V5 GND TST IRQ0 FIQ RESET GND VDD3V3 NPCSS SPCK |
| OM7 | (70) | PHILIPS | 03/04+ | Chapter 6, "SAM88RCRI Instruction Set," describes the features | |
| OM8 | (73) | DIP | The PI5A317A/381A/319A are fully specified with +5V and +3.3V supplies. | ||
| OM9 | (5) | 0m | 2001 | The input leakage current on VSET is 10 nA maximum. This al- lows large r | |
| OMA | (89) | CPClare | DIP6 | CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic ch | |
| OMB | (3) | CPClare | DIP6 | The only external RF components needed for the transceiver are the antenn | |
| OMC | (1) | QFP | 99 | PowerDrive devices significantly increase performance over PCI-only based | |
| OMD | (5) | CPClare | SOP6 | Input voltage range: 2.25V to 5.5V Ultra-low IQ: Only 16&m | |
| OME | (4) | TRIDENT | QFP | 98 | Note 5: Receiver Skew Margin is defined as the valid data sampling region |
| OMF | (7) | SCHURTER | 434 | The CD4047B-Series types are supplied in 14-lead hermetic dual-in-line ce | |
| OMG | (8) | PHILIPS | QFP0508-32 | 04+ | Resolution better than 1 milli-g Dual axis accelerometer fabricated on |
| OMH | (2) | OPTEK | SOP | 9616 | • Wide frequency rangeC80.0MHz to 135.0MHz • User specified t |
| OMI | (53) | OEG | 原装 | 08+ | Single chip teletext IC Analog CVBS-input with onchip clamp |
| OMM | (2) | Note) 1. At on-state when drain voltage exceeds the "Short circuit l | |||
| OMP | (2) | TI | BGA | 06+ | The B-port drivers are Low-capacitance open collectors with controlled |
| OMR | (18) | 2A Charge Current USB Compliant Charging States Low RdsON in Discharge | |||
| OMS | (3) | PHILIPS | wide variety of external capacitors, and the compact SOT23-5 surface-mou | ||
| OMT | (20) | SMS | PLCC68 | 03/+04+ | Initiating A Conversion Please refer to Figure 4. The SP8480 was de- si |
| OMV | (4) | N/A | N/A | 04+ | The 56F801 supports program execution from either internal or external me |
| OMX | (2) | ALCATEL | BGA | 03+ | GENERAL DESCRIPTION The MXD2020E/F is an ultra low noise and low cost, d |
| ON- | (1) | 02+ | The temperature of the lead should be measured using a ther- mocouple pl | ||
| ON/ | (1) | PulseGuard ESD Suppressors help protect sensitive electronic equipment | |||
| ON0 | (4) | MOT | 铁帽-8P | 6+ | The LCX240 is an inverting octal buffer and line driver designed to be |
| ON1 | (10) | Panasonic | Hynix HYMD216M646A(L)6-J/M/K/H/L series is unbuffered 200-pin double data | ||
| ON2 | (10) | 90 | INTERSIL | 27 | • Cambie las pilas del control remoto cuando el televisor co |
| ON3 | (82) | 2008 | COMP and FB are the available external pins of the error amplifier. The F | ||
| ON4 | (93) | N/A | N/A | 2006+ | Operating Voltage, VDD Input High Voltage, VIH, X1/ICLK pin only Input |
| ON5 | (45) | DIP42 | The 74HC/HCT147 9-input priority encoders accept data from nine active | ||
| ON6 | (2) | ph | ph | dc90 | A completely integrated linear regulator generates the 3.3VDUAL voltage |
| ON7 | (8) | ECHEL | 03+ | SOP8 | † Package drawings, standard packing quantities, thermal data, symb |
| ON8 | (10) | NEC | SMD24 | This device offers a complete solution for charging a photo flash capac | |
| ON9 | (10) | CAN4 | (Unless otherwise indicated, copies of the above specifications, s | ||
| ONA | (1) | PHILIPS | 06+ | The 4K EEPROM devices require an 8-bit device ad- dress word following a | |
| OND | (1) | • Packaged in 28 pin, 300 mil wide SOIC or in 28 pin, 150 m | |||
| ONE | (84) | TI | 07+ | The 8K EEPROM is capable of a 16-byte page write. A page write is initiat | |
| ONK | (3) | SANYO | 652 | The BAST and BASFP series are variable, fixed output low drop-out type vo | |
| ONL | (2) | ON.semi | 00+ | PLCC-28 | The Divided Down Crystal Reference with 50:50 Mark-Space Ratio. May be us |
| ONS | (2) | The ABT162244 contains sixteen non-inverting buffers with 3-STATE output | |||
| ONT | (3) | ON | The SDRAM employs state-of-the-art technology for high performance, relia | ||
| ONW | (27) | MAT | 00+ | Interrupts from the timers, UART, Microwire/SPI interface, and Multi-Inp | |
| ONY | (1) | The devices come in 8- and 10-bit resolution versions (see Figure 2 for | |||
| OO- | (1) | Current Limit Response Timer: A capacitor connected between this pin and | |||
| OO2 | (4) | QFN | 97+ | Operating the two memory banks in an interleaved fashion allows random ac | |
| OO3 | (1) | 00+ | SOP8 | The CH7009 is a Display controller device which accepts a digital graphi | |
| OO4 | (1) | The NT7702 is a 240-bit output segment/common driver LSI suitable for dri | |||
| OO8 | (1) | N/A | N/A | N/A | This bidirectional shift register is designed to incorporate virtually a |
| OOA | (5) | MARVELL | 04+ | Note: Stresses greater than those listed under MAXIMUM RATINGS may caus | |
| OOB | (1) | USING THE SP304 POWER SUPPLIES The SP304 requires 12V and +5V for full | |||
| OOC | (1) | 702 | Full on-chip hardware support of semaphore signaling between ports Fully | ||
| OOD | (2) | SEIKO | SOT-89 | The ALVCH16374 contains sixteen non-inverting D-type flip-flops with 3- | |
| OOM | (1) | The Hynix OOM6357EL/3C3 Series are Dual In-line Memory Modules suit | |||
| OON | (1) | NS | SSOP20 | 2007+ | The TH7899M sensor is a 2048 x 2048 full frame Charge Couple Device (CCD) |
| OOO | (4) | N/A | SMD | 2000 | The ERASE instruction erases data at the specified ad- dresses in the pro |
| OOP | (1) | N/A | N/A | N/A | • 5.0V and 3.3V Versions at 100mA Output • Very Low Quiescent |
| OOT | (1) | − Dynamic Range: − 132 dB (9 V rms, Mono) &nbs | |||
| OP- | (77) | DL | 06+/07+ | Chip Enable input. Used for device selection. A Low level on both CE and | |
| OP0 | (610) | N/A | N/A | N/A | Output Driver Supply Voltage Output Driver Supply Voltage Output Drive |
| OP1 | (664) | 00+ | Output voltage amplitude at f=1 kHz such that total output harmonic distor | ||
| OP2 | (1144) | AD | new | (1) Signal Output The OUT1/1X and OUT2/2X generate respectively L | |
| OP3 | (158) | AD | 00+ | DYNAMIC PERFORMANCE Maximum Output Update Rate (fCLOCK) Outp | |
| OP4 | (689) | 0 | 0 | The power dissipation of the SOTC23 is a function of the pad size | |
| OP5 | (45) | N/A | N/A | N/A | Low-power consumption modes (standby modes) Stop mode (As all oscillatio |
| OP6 | (51) | AD | 99+ | Public key execution unit (PKEU), which supports the following: RSA and | |
| OP7 | (148) | ADI | 07+ | Configuration Register Set Compatible with ISA Plug-and-Play Standard & | |
| OP8 | (45) | AD | 99+ | Operating Voltage, VDD Input High Voltage, VIH, X1/ICLK pin only Input | |
| OP9 | (100) | OPTEK | ACCURACY Linearity Error(1) Linearity Match Differential Linearity E | ||
| OPA | (3566) | BB | 06+ | SOP8 | Life Support Applications These NEC products are not intended for use in |
| OPB | (135) | OPTEEK | 06+ | Ideal for conversion from 1.8V or 1.5V inputs Designed for use with low | |
| OPC | (5) | MOT | 00+ | provide binary representation on the four active LOW inputs (Y0 to Y3). | |
| OPD | (2) | AD | SOP | PWM Capability up to 60 kHz with Duty Cycle from 5% to 100% Very Low Stan | |
| OPE | (3) | ST | 94+ | HiMARK Technology, Inc. reserves the right to change the product describe | |
| OPF | (15) | OPTEK | 05+ | For an overview of ISR programming, refer to the FLASH370i Family data | |
| OPG | (1) | Figure 1 shows the waveforms associated with the commu- tation decoder lo | |||
| OPI | (47) | 0 | 0 | codestrip. These detectors are also spaced such that a light period on | |
| OPK | (1) | DL | 06+/07+ | When setting LB at the high level and other controls are in an active sta | |
| OPL | (11) | OPULAN | BGA | 05+ | The AD7739 is a high precision, high throughput analog front end. True 1 |
| OPM | (1) | Stresses above those listed under Absolute Maximum Ratings may cause per | |||
| OPO | (7) | TI | 20,000 | All parameters, unless otherwise specified, are measured at ambient tempe | |
| OPP | (2) | NS | DIP | 0212+ | 2.7 V to 5.5 V Supply Operation 50 MHz Serial Interface 10 MHz Multiplyi |
| OPR | (34) | SEGA | SOP40W | 2007+ | NOTE : 1.Serial PD interface is standard IIC architecture. 2.Pull-up res |
| OPS | (5) | N/A | SMD | 2000 | The Fairchild Power Switch(FPS) product family is specially designed for |
| OPT | (72) | N/A | QFP | 96+ | HEXFET technology is the key to International Rectifiers advanced line |
| OPU | (1) | ITT | NO | The LM137H is an adjustable 3-terminal negative voltage regulator capable | |
| OPV | (8) | BB | SOP8 | The Read operation outputs the data in order from the initial accessed add | |
| OPX | (3) | accuracy on the transmitted signal frequency Stray capaci- tance can shi | |||
| OPY | (1) | Input Voltage • 10 to 16 VDC HR15X-12XX • 18 | |||
| OPZ | (1) | The oscillator frequency (fosc) can be set between 20 kHz and 500 kHz by | |||
| OQ- | (1) | LED BRIGHT | 04+ | Operating voltage: 2.2V~3.6V Ten bidirectional I/O lines Six schmitt tri | |
| OQ0 | (11) | S/PHI | CDIP24 | 91 | |
| OQ1 | (20) | PHI | DIP | 05+ | • Super bright LED for optical fiber communication • High acc |
| OQ2 | (107) | S/PHI | CDIP40 | —— | When the devices are clocked, data is shifted toward the serial output QH |
| OQ5 | (2) | DIP | The SO-8 has been modified through a customized leadframe for enhanced | ||
| OQ6 | (1) | The MAX1642/MAX1643 are high-efficiency, low-voltage, step-up DC-DC conve | |||
| OQ7 | (1) | The injection-current effect control allows signals at disabled analog in | |||
| OQ8 | (24) | PHI | SSOP24 | 03+/04+ | Caution: Stresses beyond those listed under Absolute Maximum Ratings may |
| OQ9 | (10) | p | p | dc99 | |
| OQO | (1) | PHILIPS | TQFP64 | 03+ | Pin-for-pin compatibility with the MC68EC000 in the plastic QFP and TQFP |
| OR1 | (4) | infineon | QFP-64 | 2004-2005 | Collector-to-Emitter Breakdown Voltage Continuous Collector Current Co |
| OR2 | (543) | ORCA | 06-07+ | UTOPIA Level 2 defines 1 ENB and 1 CLAV signal in each direction. The O | |
| OR3 | (116) | XILINX | BGA | N/A | The device offers stereo line level inputs along with two control input p |
| OR4 | (21) | REN | QFP | 07+/08+ | DELAB, DELCD: Delay Programming Between Complementary Outputs. DELAB pro |
| OR5 | (7) | QFP | 0435+/0405+ | U.S.A.: Hamamatsu Corporation: 360 Foothill Road, P.O.Box 6910, Bridgewat | |
| OR8 | (3) | DIODES | 05+ | DIP | These circuits perform a single function: they assert a reset signal when |
| ORA | (7) | PHI | 03+ | Anti Cross−Conduction Protection Circuitry Floating Top Driver Acc | |
| ORB | (143) | PLCC | The CPU core can use on-chip rather than external memory. This eli | ||
| ORC | (6) | AD | 1 | 1.5 LAN feature set 1 Ethernet 10/100 MII (HPNA compatible) 2 UARTs, | |
| ORD | (15) | OKI | 08+ | Hynix HYMD264726B(L)8-M/K/H/L series is unbuffered 184-pin double data rat | |
| ORE | (6) | SOP16 | 03+/04 | PARAMETER VID Section DAC output voltage (note 1) DAC Output Line Regu | |
| ORI | (12) | ST | DIP | This data sheet contains a variety of typical and guaranteed performance | |
| ORL | (2) | Stresses above those listed in Absolute Maximum Ratings may cause permane | |||
| ORM | (6) | 26 | ST | 01+ | Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS |
| ORN | (9) | VISHAY | 3.9mm | This document contains proprietary and confidential information of Perfor | |
| ORO | (4) | N/A | ATMEL | 04+ | Notes: 1. Repetitive Rating : Pulse width limited by maximum junction tem |
| ORP | (1) | TDK | + | Current Output Models Two settling times are specified to 0.01% of FSR. | |
| ORR | (4) | The ORR3004Rs sector erase architecture allows any number of array sect | |||
| ORS | (11) | SOP-28 | 95+ | This specification is established by characterization and not 100% tested. | |
| ORT | (26) | LATTICE | BGA | 04+ | Glueless interface to an external 10BASE-T transceiver for 10/100/1000BAS |
| ORV | (2) | Note: Absolute maximum ratings are DC values beyond which the device may | |||
| ORZ | (1) | The SG1525A/1527A series of pulse width modulator integrated circuits are | |||
| OS- | (1) | ALEPH | Power Control (SO-14 only) Maximum Logic 0 Minimum Logic 1 Logic Inpu | ||
| OS0 | (3) | These Intersil RS-485/RS-422 devices are BiCMOS 3.3V powered, single tr | |||
| OS1 | (3) | ITT | DIP | 6 | ♦ On-Resistance 0.7Ω (+3V Supply) 1.6Ω ( |
| OS2 | (4) | ST | SMD | 03 04 | • Process Technology: Full CMOS • Organization: 256Kx8 ̶ |
| OS3 | (1) | High Current Transfer Ratio, 800 % Low Input Current Requirement, 0.5 m | |||
| OS7 | (4) | 50 | The OS7032LPB Quad 10Mbps Ethernet Physical Layer (4TPHY) is a 4-Port T | ||
| OS8 | (7) | ST | QFP | 0245+ | Notes: 1. See test circuit and waveforms. 2. This parameter is guarantee |
| OSA | (14) | TYCO | 继电器-6 | 2003+ | Power Back-up pin(+). . At Li Mode, connect a 0.1u capacitor to GND. LCD |
| OSC | (40) | DDC | D/S | 05+06+07+ | The ST16C2552 is a dual asynchronous receiver and transmitter with 16 b |
| OSD | (18) | DATAMAX | PDIP16 | EXAR Corporation does not recommend the use of any of its products in lif | |
| OSE | (7) | 5 | MICROCHIP | 97+ | A sub-repertoire of 10646 consists entirely of a set of coded characters |
| OSF | (1) | CST | The frequency of the VCO is locked to a reference frequency by an on-chip | ||
| OSG | (1) | There are two limitations on the power handling ability of a tran | |||
| OSI | (4) | The Digital Addressable Lighting Interface (DALI), international standard | |||
| OSJ | (1) | SOT-23-5 | This series of Zener diodes is packaged in a SOD−523 surface | ||
| OSK | (2) | Notes: 5. For detailed information about data retention after 100K | |||
| OSM | (19) | osm | osm | dc80+ | Wide Operating VCC Range of 0.8 V to 3.6 V Optimized for 3.3-V Operation |
| OSN | (3) | In order to maintain the lowest output resistance and output ripp | |||
| OSO | (20) | IC | SOP | n Dual full-bridge for a bipolar stepper motor n Constant current contr | |
| OSP | (6) | SSOP16 | Unless otherwise specified, these specifications apply over V12=12V, V5=5V | ||
| OSR | (7) | ST | N/A | After the MASTER sends a START condition and the SLAVE address byte, th | |
| OSS | (5) | NA | 02+ | Note: Stresses greater than those listed under MAXIMUM RATINGS may cause | |
| OST | (2) | ||||
| OSW | (1) | Segment resistors are desirable to minimize power dissipa- tion and chip | |||
| OSX | (1) | ||||
| OSZ | (1) | OEG | 08+ | When calculating synchronous frequencies, use tS1 if all inputs are on t | |
| OT- | (9) | N/A | DIP28 | 06+ | An attenuator from the CONOUT (control output) to the appropriate VCA con |
| OT0 | (2) | 1996+ | QFP-100 | Hynix HYMD232726A(L)8J-J series is designed for high speed of up to 166MHz | |
| OT1 | (25) | 93 | Figure 5 shows the power curves for a power amplifier with 40V supplies | ||
| OT2 | (5) | N/A | N/A | N/A | Increased interconnection bandwidth can be achieved by using TC9208Ms tru |
| OT3 | (12) | ph | ph | dc0606 | Collector-to-Emitter Voltage Continuous Collector Current Continuous |
| OT4 | (1) | SOP | The 74AUP1G79 provides the single positive-edge triggered D-type fl | ||
| OT6 | (1) | RST Reset input A high on this pin for two machine cycles while the oscil | |||
| OTA | (2) | 00+ | • CLK: with each cycle of this signal a one-bit transfer on the comm | ||
| OTB | (1) | ||||
| OTC | (8) | DESCRIPTION The 74LVQ541 is a low voltage CMOS OCTAL BUS BUFFER with 3 | |||
| OTD | (1) | ODTECH | 05+ | International Rectifiers RAD-HardTM HEXFET® MOSFET technology provi | |
| OTG | (4) | ST | 04+ | MAX 3000A devices are supported by Altera development systems, which are | |
| OTI | (170) | OAK | QFP | 6+ | The SDA pin is bidirectional for serial data transfer. This pin is open-d |
| OTM | (1) | CyClocksRT™ is an easy-to-use software application that allows the | |||
| OTO | (1) | 07+ | The Forward Biased Safe Operating Area curves define the maximum | ||
| OTP | (3) | nous Preset/Reset of the macrocells flip-flop. Note that the Power-on Re | |||
| OTS | (4) | ENPLAS | 28 | 08+ | The Peppermint board can be used to serially program a CY22393 and meas |
| OTT | (6) | PLCC | 93+ | The AD7734 analog front end features four single-ended input channels wi | |
| OU5 | (4) | The MX826 is a µProcessor controlled full-duplex audio proc | |||
| OUA | (13) | OEG | Relay(new original) | mode with little power consumption. It can also operate with high speed s | |
| OUC | (2) | Vishay Semiconductors offers a wide range of semi- conductor components | |||
| OUD | (2) | OEG | 05 | Above VCC = 5.0V note the speed power product curve ap- proaches a stra | |
| OUK | (2) | wide band frequency, 200-2000 MHz excellent amplitude unbalance, 0.2 dB | |||
| OUL | (1) | 1) CPD is defined as the value of the ICs internal equivalent capacitance | |||
| OUM | (1) | PHILIPS | 2008 | The insulation displacement and crimping methods are prepared for conne | |
| OUP | (1) | NEC | 05+ | QFP | Ultra low dropout voltage Output adjusts from 1.23V to 15V Guaranteed |
| OUT | (4) | The device offers stereo line level inputs along with two control input p | |||
| OV0 | (1) | OmniVisi | 07+ | The leadless chip carrier (LCC) package represents the logical next ste | |
| OV1 | (1) | IDT | SOP | 05+ | NOTE: EP circuits are designed to meet the DC specifications shown in the |
| OV2 | (4) | OV | CLCC | CLCC | An input capacitor of 1.0 µF (min) should be connected from VIN to |
| OV3 | (4) | OMNIVISION | QFN | 06+ | NOTES: 1. All timing and jitter tolerances apply for FNOM > 25MHz. 2. |
| OV5 | (20) | SANYO | QFP100 | stream. EEPROM emulation (bit or byte alterability) is easily handled wit | |
| OV6 | (14) | OmniVison | CLCC | 1997 | The gain error in the OV6003 ADCs, is defined as the difference between |
| OV7 | (39) | OMNIVISION | BGA | Instruction fetching and execution are pipelined in such a way that a f | |
| OV8 | (1) | OV | LCC | 02+ | Note 4: The LTC1998C is guaranteed to meet specified performance from 0C |
| OV9 | (13) | OMNIVISION | BGA | 04+ | INTERFACE COMMUNICATION: The IC pin determines which interface is operati |
| OVC | (1) | INTEGRATED | SOT-153 | 05+ | Each of the Macrocells of the ispGAL22V10 has two primary func- tional m |
| OVE | (4) | The LVT543 contain two sets of D-type latches for temporary storage of | |||
| OVL | (28) | • Low On-Resistance, (16−ohms typ) Minimizes Distorti | |||
| OVR | (6) | OEG | 04+ | A parallel RC network connected to these pins sets the OFF time of the l | |
| OVS | (20) | Notes: 1. Gate Open 2. Measurement using the gate trigger characteristic | |||
| OVT | (6) | appropriate for some applications. Enable time is approxi- mately k1R5C5 | |||
| OVV | (4) | SOP | 00+ | When a logic 0 of TRB is latched in with the falling edge of CE, the ADP | |
| OW0 | (2) | 0 | The TSOP344..SB1F - series are miniaturized receiv- ers for infrared re | ||
| OW3 | (3) | The DS1642 has a lithium power source that is designed to provide energy | |||
| OW6 | (3) | ? | CDIP28金面 | —— | In the normal mode, these devices are 18-bit universal bus transceivers t |
| OW8 | (1) | QFP | 95 | ||
| OWD | (5) | IPD | 模块 | 08+ | • Single 5V10% Power Supply • High speed - 15/20/25ns(max.) |
| OWI | (10) | OLE | The equalizer improves the cable-induced jitter; the data slicer restor | ||
| OWL | (50) | 2.5V power supply LVCMOS compatible with multiplexed address Dual banks | |||
| OWM | (1) | Digital I/Ps = 0 V or VDD VDD = 4.75 V to 5.25 V, SCLK on or off VDD = | |||
| OWS | (10) | 2000 | Available in the Texas Instruments NanoStar™ and NanoFree™ Pa | ||
| OWT | (3) | N/A | [POWIRTRAIN specifications and ratings are given for system input | ||
| OX1 | (30) | OXFORD | PLCC | 02+ | In addition, the TSC80C31/80C51 has two software-selectable modes of red |
| OX2 | (2) | All rights reserved. No part of this publication may be reproduced, stored | |||
| OX4 | (1) | (3) The products described in this material are intended to be used for s | |||
| OX6 | (1) | The XC4000 families achieve high speed through ad- vanced semiconductor | |||
| OX7 | (2) | • 8-bit I2C GPIO • Operating power supply voltage range of 2.3 | |||
| OX8 | (1) | Purpose non inverting input ÎA inverting input ÎA operation | |||
| OX9 | (3) | Following the filter section is a decoder employing digital counting techn | |||
| OXA | (1) | The joint TLB also contains information to control the cache coher | |||
| OXC | (4) | 2000 | Oxford | 6+ | •Built-in digital delay , mixing amplifiers,input output selector |
| OXF | (6) | OXFORD | QFP128 | QFP128 | This signal is used internally as part of the I and Q ADC calibration cir |
| OXM | (2) | OXMPC | QFP | 0452+ | 2 PHASE OPERATION WITH SYNCRHONOUS RECTIFIER CONTROL ULTRA FAST LOAD |
| OXU | (9) | 50 | OXFORD | • XACT Development System runs on 386/486/ Pentium-type PC, | |
| OXV | (2) | The MAX8550/MAX8551 integrate a synchronous-buck PWM controller to genera | |||
| OYS | (7) | MOT | PLCC52 | 05+ | A/D Converter (sequential conversion type) • 10-bit resolution, 8 |
| OZ- | (12) | OEG | Relay(new original) | The ISR will operate at no load with reduced specifications. For operati | |
| OZ0 | (3) | MICRO | SOP-28 | 2000 | SOT-223, JC -------------------------------------------------------------- |
| OZ1 | (11) | MICRO | QFP | 06+ | The inputs are compatible with 5 V and 12 V logic systemsTTL, Sch |
| OZ2 | (14) | OZ | SOP | SOP | The VP-1000A is totally self-contained. It can access the external memor |
| OZ6 | (34) | OZ | 02+ | TQFP-M128P | Function Standby Read Write: Word (Early Write) Read-Write EDO Page- |
| OZ7 | (23) | MICRO | 02+ | BGA/16*16 | FEATURES D 10-mA Low-Dropout Regulator D Ultralow 1.2-µA Quiescent |
| OZ8 | (14) | OZ | The ÉlanSC300 microcontroller is a highly integrated, low-voltage | ||
| OZ9 | (146) | O2MICRO | SOP | 06+ | * Metal of silicon rectifier, majority carrier conducton * Guard ring for |
| OZD | (2) | NOTE: EP circuits are designed to meet the DC specifications shown in the | |||
| OZH | (1) | MICROCHI | BGA | To 0.1% of full scale, data cycles from zero scale to full scale to zero | |
| OZL | (2) | MICRO | SOP-8 | 05+ | After DC is applied, the bq2902 checks the open-circuit voltage (VOCV) of |
| OZM | (2) | ZiLOG | O7+ | When battery charging is initiated, the charger enters the prequalificati | |
| OZS | (4) | oeg | oeg | dc95 | Speaker output signal can be attenuated either by internal register or ex |
| OZT | (7) | IC | SOP | The OZT01105S completely controls the Facility Data Link (FDL) in T1 en |
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