| Mfg | pack | D/C | Descrpion | ||
| P.7 | (1) | DIALOG | SMD | 05+ | Notes: 2. Multiple Supplies: The voltage on any input or I/O pin ca |
| P.A | (1) | Unlike devices using MOS bilateral switching elements, these bipolar circ | |||
| P/4 | (1) | ||||
| P/S | (1) | ||||
| P-0 | (4) | Support for 12 independent ports. Low power consumption Category II F | |||
| P00 | (103) | Littelfuse | 07+ | T0-92 | |
| P01 | (146) | ST | SOP-8 | 0 | The input waveform may be sinusoidal but below about 20 MHz the operatio |
| P02 | (72) | PLCC44 | Two 16 x 1 memory look-up tables (F-LUT and G-LUT) are used to implement | ||
| P03 | (96) | TECCOR | DO-214AA | 07+ | The HYM72V32636B(L)T8 Series are 32Mx64bits Synchronous DRAM Modules. The |
| P04 | (92) | ALCTEL | QFP | 0 | (VCC = +2.7V to +3.3V, RRBIAS = RRLNA = 24kΩ, BUFFEN = LOW, all RF a |
| P05 | (50) | ST | PQFP-128 | 02+ | 3 channels: Dual 512-position Single 128-position 25 k |
| P06 | (221) | N/A | NOTES : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are | ||
| P07 | (311) | NIKO | SOP-8 | 06+ | The Microchip Technology Inc. 93AA46/56/66 are 1K, 2K and 4K low voltag |
| P08 | (355) | TI | SSOP-20 | Operating temperature: -55C to +150C Storage temperature: -55C to +150C | |
| P09 | (260) | TECCOR | DO-214AA | 07+ | The VCXO may be coarse tuned by a programmable ad- justment of the crys |
| P0F | (1) | For more information refer to Xilinx XC4000E and XC4000X series Field P | |||
| P0G | (2) | MURATA | 5*5-500R | NOTES: 1 Production testing of the device is performed at 25C. Functiona | |
| P0L | (1) | A read cycle is initiated by the falling edge of CAS or OE, whichever o | |||
| P0R | (1) | High-end embedded control applications demand more performance from their | |||
| P0T | (10) | Jitter transfer refers to the portion of jitter allowed to transfer from | |||
| P0Z | (7) | MURATA | 06+ | The ACE1501 (Arithmetic Controller Engine) family of microcon- trollers | |
| P1 | (1) | The HC367, HCT367, HC368, and CD74HCT368 silicon gate CMOS three-state | |||
| P-1 | (13) | TEMIC | 2008 | 2.1 W/Ch Into 4 Ω at 5 V • 1.4 W/Ch Into 8 Ω at 5 V | |
| P1- | (3) | FUJ | 96 | The IC series are composed of circuits required for a switching regulator | |
| P1. | (2) | The MAX3873A successfully meets the quality and reliability standa | |||
| P10 | (165) | ISP | TO-3P | 99+ | • Wide frequency rangeC80.0MHz to 135.0MHz • User specified t |
| P11 | (211) | Littelfu.. | DO214AA | 06 | The HT815D0 has a built-in RC oscillator which requires only one externa |
| P12 | (131) | LF(TEC) | DO-214 | 06+ | All parameters measured at fMAX unless noted otherwise. NOTE 1: Assumin |
| P13 | (144) | TECCOR | DO214AA | 05 | BVDSSDrain-to-Source Breakdown Voltage ∆BV DSS/∆TJ Temperatu |
| P14 | (68) | LF(TEC) | TO-220 | 06+ | The X76F102 is a Password Access Security Supervisor, containing one 89 |
| P15 | (312) | Littelfuse | T0-92 | 07+ | The P1500ECL is a low dropout three terminal regulator with 3A output c |
| P16 | (145) | 02+ | TQFP0707-32 | ||
| P17 | (98) | TECCOR | DO214AA | 05 | 2.1 General. The documents listed in this section are specified in |
| P18 | (143) | LF(TEC) | MS-013 | 06+ | FEATURES D Replaces OR-ing Diodes D Operating Supply Range |
| P19 | (21) | - | - | 0610+ | Unless otherwise noted, limits printed in BOLD characters are guaranteed |
| P1A | (3) | Vertical power TrenchMOS Low on-state resistance CMOS logic compatible | |||
| P1B | (1) | MOTOROLA | 98+ | ||
| P1C | (11) | MKORCHIP | DIP | 02+ | |
| P1E | (2) | ||||
| P1F | (6) | TI | PLCC | 07+ | Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed- |
| P1H | (3) | 2007 | Notes a. The algebraic convention whereby the most negative value is a m | ||
| P1L | (1) | NEC | TO92S | Compliance with PCI Bus Power Management Interface Specification Revisio | |
| P1M | (1) | PHILIPS | SOT163 | 07+/08+ | AMD MirrorBit flash technology combines years of Flash memory manufactu |
| P1N | (3) | NIKO | SOT-23 | 06+ | The P1N02LX supports two hardware interfaces: The FWH/LPC interface for I |
| P1O | (1) | TI | BGA1010 | 0219+ | The AD5620/AD5640/AD5660-1 parts include an internal, 1.25 V, 5 ppm/C re |
| P1S | (1) | THD+N: 20-Hz HPF, 20-kHz apogee LPF Dynamic range: 20-Hz H | |||
| P1T | (7) | OTAX | 07+ | Note A: The above characteristic data has been developed from actual prod | |
| P1V | (1) | C Conceal/reveal C Transparent foreground/background - inside/outside of | |||
| P1X | (1) | ST | BC should be connected to a 3V backup cell for RTC operation and storage | ||
| P1Z | (5) | PRX | SOP | Normally a reset circuit is required to protect the micro- computer syste | |
| P-2 | (4) | MICREL | 03+ | The differential inputs operate from rail-to-rail and the single ended ou | |
| P20 | (134) | LF(TEC) | 06+ | 5-Bit Programmable Output Voltage: 1.05V to 1.825V (VRM8.5) No Sense Res | |
| P21 | (177) | INTEL | 95 | Hitachi AND Flash Write Commands Error Handling and Bad Sector Processi | |
| P22 | (67) | PHI | SOP8S | 2007+ | Loudspeaker amplifier power supply input An external power supply connec |
| P23 | (112) | LF(TEC) | MS-013 | 05+ | Device performance is relatively independent of supply voltage over the |
| P24 | (38) | SMD | 2002 | Please be aware that an important notice concerning availability, | |
| P25 | (63) | TECCOR | DO-214AA | 07+ | Sensitivity is defined as the average signal level measured at the input |
| P26 | (65) | LF(TEC) | DO-214 | 06+ | Hynix HYMD264726A(L)8-M/K/H/L series incorporates SPD(serial presence dete |
| P27 | (131) | LF(TEC) | MS-013 | 05+ | 1. Built-in wideband video amp110MHz@ -3dB (4VP-P output) 2. OSD input ha |
| P28 | (124) | TECCOR | DO-214AA | 07+ | The chip requires a single, even-parity bit to be sent after the 6 comma |
| P29 | (23) | ON | SOT-223 | 01+ | SIGNAL DESCRIPTIONS See Figure 1 and Table 1. Address Inputs (A0-A18). |
| P2A | (1) | A read is accomplished by placing an active LOW signal on CS1, and activ | |||
| P2B | (2) | PHIL | Notes: 1. The algebraic convention, where the most negative value is a m | ||
| P2C | (8) | SMD | 03+/04+ | SOFT START Soft Start is engaged when the device is taken out of Shut- | |
| P2D | (4) | MOT | SOP-28 | 99+ | The DS1543 also contains its own power fail circuitry which automatically |
| P2H | (40) | ST | TO-220 | 07+ | First 14-bit ADC in a SOT-23 package. High throughput with low power co |
| P2K | (2) | 00+ | Input-Address Strobe from Controller, sampled on the rising edge o | ||
| P2M | (5) | PHIL | Note 4: The Absolute Maximum Ratings are those values beyond which the sa | ||
| P2N | (17) | N/A | ON | 04+ | n OSD Window Fade In/Fade Out n OSD Half Tone Transparency n OSD overrid |
| P2P | (2) | The deployment of electronic energy meters has gained a great deal of m | |||
| P2R | (10) | OMRON | Relay(new original) | The CAT34AC02 supports the SMBus data transmission protocol. This seria | |
| P2S | (3) | TSOP | 06/07+ | The MAX1536 constant-off-time, pulse-width-modulated (PWM) step-down DC-t | |
| P2T | (3) | PH | The MODE pin allows to define whether to issue directly the filtered data | ||
| P2V | (54) | MIT | 03+ | *CPU: PGA 478 for Intel Pentium 4 CPU with Hyper-Threading Technol | |
| P2Z | (5) | PRX | SOP | ||
| P-3 | (2) | MSOP | 02+ | clock stream is corrupted during a transmission. In these two modes the | |
| P3- | (2) | 网络电源 | NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATI | ||
| P30 | (120) | Littelfuse | 06/07+ | The data transmitted across the barrier is coded using an internal clock | |
| P31 | (99) | TECCOR | TO-92 | 02年03年定型 | Generates Programmable CPU Clock Output (50 MHz, 60 MHz, or 66 MHz) Gene |
| P32 | (96) | NS | 06+ | 500 | The PIC12CE67X devices have 128 bytes of RAM, 16 bytes of EEPROM data m |
| P33 | (20) | LF(TEC) | TO-220 | 06+ | The operation mode of the M5M51008C series are determined by a combinati |
| P34 | (54) | LF(TEC) | MS-013 | 05+ | After the password sequence, there is always a nonvola- tile write cycl |
| P35 | (90) | LF(TEC) | MS-013 | 06+ | The DS1258AB provides full functional capability for VCC greater than 4.75 |
| P36 | (28) | Littelfuse | TO-220 | 07+ | Clock 155.52MHz (LVDS output). Differential outputs for the 155.52 MHz cl |
| P37 | (22) | The HSP3824 has on-board ADCs for analog I and Q inputs, for which the | |||
| P38 | (13) | LITTELFUSE | SMB | 04+ | Note 1. Test voltage must be applied within dv/dt rating. Note 2. Guaran |
| P39 | (19) | ROCKWELL | 97+ | QFP1420-128 | Note 3. These parameters, although guaranteed over the recommended operat |
| P3B | (1) | H = High Voltage Level (Steady State); L = Low Voltage Level (Steady Stat | |||
| P3C | (12) | Testing of switching parameters is modeled after testing methods speci | |||
| P3D | (2) | TI | *Maximum Ratings are those values beyond which damage to the device may o | ||
| P3G | (3) | vishay | vishay | dc95 | Programmable options include the length of pipeline (Read latency of 1,2 |
| P3J | (1) | 2008 | The CY7C53150L incorporates an external memory interface that can address | ||
| P3L | (1) | ||||
| P3N | (19) | (the last page) transfer the contents of the lower-order byte to the spec | |||
| P3R | (4) | ETT | N/A | 08+ | Two power-saving features are embodied in the HY29DS32x. When addresses |
| P3S | (6) | AT | 07+ | The Effects of Sampling Instant Uncertainty (Aperture Jitter) To conside | |
| P3V | (1) | TI | 00+ | TSSOP24 | Please be aware that an important notice concerning availability, standard |
| P3Z | (21) | 0 | 0 | Similarly, the bq24400 suspends fast charge if the battery temperature i | |
| P-4 | (4) | Koyo | 01+;01+ | Calibration Cycle Initiate. A minimum 80 input clock cycles logic low f | |
| P4- | (1) | The LX1991 features resistor settable output current. Connecting | |||
| P4. | (2) | For this application, the derived voltage reading, Vd, is related to th | |||
| P40 | (83) | 20A/400V/DIODE+SCR/6U | IR | DNL: 1 LSB Max SINAD = 81.5 dB, SFDR = 95 dB THD = 94 dB at 15 kHz fin, | |
| P41 | (11) | The ICSI IC61S6432 is a high-speed, low-power synchronous static RAM des | |||
| P42 | (82) | N/A | TTL/CMOS input enable pin. Used to control the LOUT0-LOUT2 outputs and act | ||
| P43 | (34) | Correlated double sampling PGA Offset compensation Serial interface c | |||
| P44 | (18) | NIKOS | SMD | 05+ | The CD74AC253 and ACT253 dual 4-input multiplexers that utilize Advanced |
| P45 | (29) | NIK0-SEM | 04+ | TO-263 | The HDSP-31xx-51xx Series of displays incorporates a new slim font ch |
| P46 | (14) | TOS | SOP44W | 2007+ | There are 14 devices in this switch series which are differentiated by |
| P47 | (17) | XILINX | 01+ | PLCC28 | Zener Voltage Range: 6.8V to 200V Hermetically sealed DO-13 metal package |
| P48 | (71) | Littelfuse | 06/07+ | The CD54ACT161 and CD74ACT161 devices are 4-bit binary counters. These sy | |
| P49 | (12) | XILINX | 01+ | PLCC28 | Notes: 1. CL includes probe and jig capacitance. 2. Waveform 1 is for an |
| P4A | (2) | TI | QFP | 00+ | A block diagram of the MT8931C is shown in Figure 1. The SNIC has three i |
| P4C | (99) | N/A | N/A | N/A | Array Description The X9269 is comprised of a resistor array (see Figure |
| P4D | (3) | MINI | 08+ | AFEU processing begins after this shared session key is agreed upon. The | |
| P4F | (440) | RECTRON | 07+ | The step-down controllers minimize power loss and noise by operating the | |
| P4K | (168) | gs | gs | dc95 | This is an analog output which can be used as a reference source and/or |
| P4M | (12) | N/A | 07+/08+ | The HSDL-3600 is a low-profile infrared transceiver module that provid | |
| P4N | (19) | ST | TO-220 | 06+ | † All typical values are at VCC = 2.5 V, TA = 25C. ‡ The bus |
| P4S | (749) | CONCORD | 07/08+ | 1) CPD isdefined as the value of the ICsinternal equivalent capacitance w | |
| P4V | (1) | Philips | 2008 | The input buffer threshold has programmable TTL/3.3V/ 2.5V compatible l | |
| P4X | (7) | VIA | BGA | 03+ | The CY7C4261/71/81/91V consists of an array of 16K, 32K, 64K, or 128K w |
| P-5 | (8) | MSOP | 02+ | memory). In the First-Word Fall-Through Mode (FWFT), the first long-word | |
| P50 | (105) | TOSHIBA | 06+ | 500 | 10 years minimum data retention in the absence of external power Data |
| P51 | (110) | Littelfuse | MS-013 | 07+ | Areas where care in design must be observed are thermal ground, RF groun |
| P52 | (52) | CONEXANT | QFP | The VHCT374A is an advanced high speed CMOS octal flip-flop with 3-STAT | |
| P53 | (16) | N/A | PLCC | 03+ | WREN - Set Write Enable Latch The FM25L16 will power up with writes disa |
| P54 | (18) | TI | SOP8 | 02+ | Note) *1: Except for the operating ambient temperature and storage temper |
| P55 | (41) | CSC | 96/P | 1.6 µA Typical Quiescent Current Input Operating Voltage Range: 2.3 | |
| P56 | (16) | MALAY | Absolute Maximum Ratings indicate sustained limits beyond which damage to | ||
| P57 | (15) | TECCOR | TO-220 | 01 | Isolated Hermetic Package, JEDEC TO-257AA Outline Adjustable Output Vol |
| P58 | (5) | NIKOS | SMD | 05+ | The DAC device type identifier default is 0101[b]. In order to ac |
| P59 | (3) | FSC | TSSOP-14 | 06+ | • Portable/battery-powered applications • PCMCIA, USB • |
| P5A | (10) | INTEL | Connective units, called repeaters, spaced every eight cells, divide ea | ||
| P5B | (1) | PHILIPS | N/A | SOD | The P5BYM26B includes a thermal AP5BYM26BC (TAP5BYM26BC) function utiliz |
| P5C | (22) | The LX1991 features resistor settable output current. Connecting | |||
| P5D | (1) | Input Equivalent Circuit To prevent static charges, protective diodes ar | |||
| P5F | (1) | The CD4024B types are supplied in 14-lead hermetic dual-in-line ceramic p | |||
| P5H | (3) | FCS | 05+ | This IC is a sync detection circuit for obtaining the best reception state | |
| P5I | (1) | INTEL | DIP28 | 2007+ | The 256Mb DDR SDRAM operates from a differential clock (CK and CK; the |
| P5K | (3) | MSC | The waveform of the maximum DC applied voltage is flat. When a ripple vol | ||
| P5L | (1) | The TFP513 provides a universal interface to allow a glueless connection | |||
| P5M | (2) | MIRA | QFP-100 | THERMAL CONSIDERATIONS Thermal shutdown protection circuitry prot | |
| P5N | (19) | NIKO | TO252 | 05+ | Stresses in excess of the absolute maximum ratings can cause permanent da |
| P5P | (1) | TO-220 | 05+ | ||
| P5S | (4) | AT | 07+ | QF20AA is six pack Darlington power transistor module which has six trans | |
| P5X | (1) | STM1403 SUPPORTS FIPS-140 SECURITY LEVEL 3+ C 4 High-Impedance Physica | |||
| P5Z | (15) | PHI | PLCC28 | 2007+ | This product is intended for clock generation. It has low output jitter |
| P-6 | (1) | (2) JC data values stated are derived from MIL-STD-1835B which states the | |||
| P6- | (1) | Japan Wide 100k/200k L L H H Dont care Dont care Dont | |||
| P60 | (100) | P600全系列原装现货专营 | 07/08+ | Description Agilent Technologiess ATF- 501P8 is a single-voltage high l | |
| P61 | (25) | TI | 2008 | These chips, when properly assembled, display characteristics similar to | |
| P62 | (26) | TOSHIBA | Makes DRAM Interface and refresh tasks appear virtu- ally transparent to | ||
| P63 | (7) | MOT | 96+ | Once the feature is enabled, the data in the protected sec- tors can no | |
| P64 | (13) | ELANTEC | 03+ | The RC32355 meets the requirements of various embedded commu- nic | |
| P65 | (24) | Limiting values are given in accordance with the Absolute Maximum Rating | |||
| P66 | (19) | N/A | N/A | 00+ | The HY62SF16403A is a high speed, super low power and 4Mbit full CMOS SRA |
| P67 | (6) | PQFP-100 | 99 | The DS1386 executes a read cycle whenever WE (Write Enable) is inactive (H | |
| P68 | (5) | Available in standoff voltage range of 6.5 to 200 V Low ca | |||
| P69 | (1) | Basic building blocks of the HCPL-x710 are a CMOS LED driver IC, a high | |||
| P6A | (5) | GSI | SMB | Spread spectrum may be enabled through I2C programming. Spread spectrum ty | |
| P6B | (10) | OMRON | Relay(new original) | In addition, the CY7B951 has a built-in transitions detector that also c | |
| P6C | (29) | The Hynix P6C-203LNS Series are 16Mx64bits Synchronous DRAM Modules. The | |||
| P6D | (1) | 1) Drive capability: constant-current output 50mA (Max.) 2) | |||
| P6F | (436) | RECTRON | 07+ | ||
| P6I | (1) | To set the new VTRIP voltage, apply the desired VTRIP threshold voltage | |||
| P6K | (748) | VISHAY | DO-15 | 07+ | The COP87L88GD/RD OTP (One Time Programmable) Family microcontrollers a |
| P6L | (14) | Each GLB contains 20 macrocells and a fully populated, programmable AND | |||
| P6M | (5) | ON | 1W | 05+ | Notes: 1. The product is factory calibrated at 3.3V. The device can be po |
| P6N | (16) | ST | TO-220 | 07+ | NOTES: Typical values are at TA = +25C and VCC = 12 V. BOP = oper |
| P6P | (3) | TO-220 | 05+ | The hybrid performs 2 wire to 4 wire conversion by taking the 4 wire signa | |
| P6S | (726) | ON | DO-214AA | 08+ | The MPX5010 series piezoresistive transducer is a stateCofCtheCart |
| P6V | (1) | CHIP ERASE: The entire device can be erased at one time by using the six- | |||
| P70 | (15) | AMD | 98 | LOW QUIESCENT CURRENT: 300µA DESIGNED FOR RS-485 INTERFACE APPLI | |
| P71 | (11) | 2008 | Three operating modes can be programmed using the SNOOZE pin. When SNOOZE | ||
| P72 | (13) | N/A | N/A | Similar To Industry Standard LT1033 Approved To DESC Standardized Milit | |
| P73 | (7) | MOTOROLA | 06+ | BGA | The DDX-2000 converts serial I2S digital audio signals into pulse-width-m |
| P74 | (246) | (LX)high-frequency | As its predecessors SDA 525x the SDA 525x-2 contains a slicer for VPS and | ||
| P75 | (21) | The ISP10160A is designed to interface directly to the PCI bus an | |||
| P76 | (6) | FAIRCHILD | SOP10 | 07+ | The GS4882 and GS4982 are precision sync separators for extracting timing |
| P77 | (4) | TI | SOP8 | 00+ | The EFJ2803 is a high reliability EMI filter for use with the DAC |
| P78 | (2) | NPT IGBT technology low switching losses low tail current no latch up | |||
| P79 | (10) | MOT | QFP | IMPORTANT NOTE: The Virtex-II Platform FPGA data sheet is created and pub | |
| P7B | (1) | SDRAM read and write accesses are burst oriented starting at a selected | |||
| P7C | (2) | The MAX3873A is a compact, low-power 2.488Gbps/ 2.67Gbps clock-recovery a | |||
| P7E | (1) | 97 | (Before using this chip, take a look at the following description note, it | ||
| P7K | (1) | ISD | QFP-26 | 07+/08+ | Thermal Data - Thermal Resistances Some thermal data (e.g., junction tem |
| P7L | (5) | Coilcraft | SOP | 03+ | The RF AGC in the ZL10037 is divided into two stages. The first stage is |
| P7M | (1) | The MAX4106/MAX4107 require only 15mA of supply current while delivering | |||
| P7N | (13) | ST | TO-220 | 07+ | • High-speed access times: 10, 12 and 15 ns • High-p |
| P7S | (3) | AT | 07+ | † Package drawings, standard packing quantities, thermal data, symb | |
| P7T | (1) | The DP8391 Serial Network Interface (SNI) provides the Manchester data e | |||
| P7Z | (5) | PRX | SOP | causes the DQ pins to tri-state. Crystal Connection, drives crystal on st | |
| P-8 | (207) | MHS | 9322 | Frequency response also depends on the phase as well as the magnitude o | |
| P8- | (1) | Note: (1) The minimum DC input voltage is C0.5 V. During transitions, in | |||
| P80 | (899) | DIP40 | INTEL | 85+ | If this clock is applied to the Xin/CLK pin of the SM561, the output clo |
| P81 | (37) | INTEL | DIP | 07+ | This is the inverting input of the transmit gain setting op- erat |
| P82 | (513) | The LM117 adjustable 3-terminal positive voltage regulator is capable of | |||
| P83 | (603) | N/A | N/A | N/A | Input Data Mask: DM(LDM,UDM) is an input mask signal for write data. Input |
| P84 | (19) | NS | 0705+ | - On chip Hall sensor - Rotor-locked shutdown - Automatically restart - | |
| P85 | (49) | N/A | N/A | 04+ | The MAX3320 combines a microprocessor (µP) super- visory circuit wi |
| P86 | (15) | 33 | INTEL | 80+/81+ | The ATA5756/ATA5757 is a PLL transmitter IC which has been developed for |
| P87 | (918) | PHILIPS | PLCC | PLCC | Celeritek reserves the right to make changes without further notice to an |
| P88 | (14) | NS | 92 | Differential Inputs: This input pair is a differential signal input to the | |
| P89 | (687) | PHILIPS | QFP | 02+ | Operation in -40C - 125C Environment TTL/DTL/CMOS Compatible Inputs NAND |
| P8A | (2) | citel | citel | dc02 | All protective features of thermal shutdown, current limiting, and safe-a |
| P8C | (4) | The P8C-215LV contains eight noninverting buffers with 3-state outputs | |||
| P8D | (2) | TI | TTL/CMOS input select control signals for the PECL POUT0-POUT3 outputs. PS | ||
| P8L | (3) | MOT | RELATIVE ACCURACY This term, also known as end point linearity or integr | ||
| P8N | (9) | TO-220 | 05+ | INTERFACE TIMING CHARACTERISTICS Applies to All Parts6, 11 Input | |
| P8O | (2) | PHILIPS | PLCC | 07+ | BT Current Source. Connect this pin to the gate of a suitable N-channel M |
| P8P | (6) | MOT | DIP | 90 | The VCXO provides a tunable, low-jitter frequency refer- ence for the r |
| P8R | (1) | N/A | SMD | 2000 | Data Set Ready (Active-LOW). These inputs are associated with individual |
| P8S | (11) | Features 1) Synchronous rectification enables high efficiency 2) Built- | |||
| P8T | (2) | INTEL | DIP | 91+ | † All typical values are at VCC = 5 V. ‡ The parameters IOZ |
| P8X | (3) | Ideal for space critical applications, the LM4040 precision voltage ref | |||
| P8Y | (1) | high di/dts. The diodes negative di/dt during ta is directly controlled | |||
| P8Z | (1) | CHIPS | PLCC | 07+ | By adopting a newly developed GPS processor (the Sony CXD2931R) and So |
| P90 | (25) | SMD | 00 | Notes: VZ is programmable from -2V to +7V. IOL & IOH programmable | |
| P91 | (3) | CAUTION: These devices are sensitive to electrostatic discharge; follow p | |||
| P92 | (13) | ATGT | QFP | 98+ | Maximum ratings are those values beyond which device damage can occur. Ma |
| P93 | (21) | N/A | TO-92 | 00+ | If an output channel is set to three-state condition, the TDM serial strea |
| P94 | (8) | ST | 00+ | Data contained in the phantom clock register is in binary-coded decimal fo | |
| P95 | (17) | SUPREME | SMD | 2000 | CAUTION: These devices are sensitive to electrostatic discharge; f |
| P96 | (8) | Most Significant Data Bit (MSB). Data Bits 1C6. Least Significant Data B | |||
| P97 | (13) | PLUSTEK | The MPC860 Quad Integrated Communications Controller (PowerQUICC™) | ||
| P98 | (12) | NS | DIP | 1.2.1 RHA designator. Device classes Q and V RHA marked devices me | |
| P99 | (17) | ST | 01+ | SOP44 | FEATURES 11 LDOs Optimized for Specific CDMA Subsystems 4 Backup LDOs f |
| P9B | (1) | This document provides electrical characteristics for the 33, 25 and 16 | |||
| P9C | (2) | 5 | Wide inductance range in small package. Flame retardant coa | ||
| P9E | (1) | MOT | BGA | 99+ | High-end embedded control applications demand more performance from their |
| P9F | (1) | Add to the Interrupt Acknowledge Bus Cycles section on page 3-36: Level s | |||
| P9N | (10) | ST | TO-220 | 06+ | † Package drawings, standard packing quantities, thermal data, symb |
| P9Q | (1) | 4 | SOP-8 | Shipped at room temperature. Recommended storage conditions upon arrival: | |
| P9R | (1) | MOT | DIP | 06+ | IF IT DOES NOT WORK Poor soldering (dry joints) is the most common reaso |
| P9S | (2) | MOT | DIP | 06+ | performance in outdoor signal and sign applications. The high maximum |
| P-A | (1) | FOCI | N/A | The SACD is for interfacing between a microcontroller or micropro | |
| PA- | (11) | 0 | SOP | ∙ 2,097,152-word 8-bit configuration ∙ Single 5V power su | |
| PA. | (1) | While the double-buffered register structure reduces the chance of reading | |||
| PA/ | (8) | PHI | QFP-44 | Drain-to-Source Breakdown Voltage Gate Threshold Voltage Ga | |
| PA0 | (137) | FOXLINK | 6 | DESCRIPTION M62352A is a CMOS structured semiconductor integrated ciruict | |
| PA1 | (118) | 99 | An integrated phase lock loop multiplies the incoming ADC sampling cloc | ||
| PA2 | (275) | INTEL | . | The oscillator is programmed with two resistors and a capacitor to set s | |
| PA3 | (58) | M/A-COM | (3) The products described in this book are intended to be used for stand | ||
| PA4 | (73) | PFU | BGA | 05+ | Functional I/O The HFBR-5710L accepts industry standard differential |
| PA5 | (43) | SSOP | Glass passivated die construction Ideal for printed circuit boards Plast | ||
| PA6 | (13) | 0 | 0 | (5-V Input and Output Voltages With 3.3-V VCC) Typical VOLP (Output Grou | |
| PA7 | (105) | Jack(Available) | The response is thus a logarithmic curve; each doubling of Cs increases | ||
| PA8 | (46) | APEX | PLCC | 99+ | DMA REQUEST: The DMA Request (DREQ) lines are individual asynchronous cha |
| PA9 | (25) | APEX | ZIP | ZIP | The signal value is a direct function of Cs and Cx, where Cs is the fixe |
| PAA | (78) | *) The terminating impedances depend on parasitics and q-values of matchin | |||
| PAB | (4) | n Software selectable I/O options (TRI-STATE ® Output,Push-Pu | |||
| PAC | (402) | CMD | SOP24S | 06+ | This can be a problem if RXDATA is driving a circuit that must sleep when |
| PAD | (35) | 99 | The 82C37A is designed to be used with an external address latch, such | ||
| PAE | (11) | This document is a general product description and is subject to change wi | |||
| PAF | (41) | LAMBDA | SOP | This output pin provides a midCsupply analog ground. This pin sho | |
| PAG | (5) | (LX)high-frequency | The key difference between the PAG-1A and PAG-1 is the faster switching f | ||
| PAH | (152) | N/A | N/A | N/A | Zarlink Semiconductor provides prescaler evaluation boards. These are pri |
| PAI | (3) | TI | QFN32 | 06+ | NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't |
| PAJ | (3) | TI | SOP | 99+ | The device contains a write enable latch. This latch must be SET before |
| PAK | (1) | N/A | |||
| PAL | (2634) | MMI | 97 | The relay is driven by a pulsed signal instead of a continuous signal. Co | |
| PAM | (12) | PANGAEA | SOP | 345 | Note: The user, utilizing the COP8TAx9 Flash based devices during devel- |
| PAN | (35) | PIXART | DIP | 04+ | The HYM72V12C736B(L)S4 Series are Dual In-line Memory Modules suitable for |
| PAO | (1) | HSOP | The ADSP-219x architecture is code compatible with the ADSP- 218x DSP fa | ||
| PAP | (19) | JST | / | 07＋ | The ZL30414 is an analog phase-locked loop (APLL) designed to provide jit |
| PAQ | (57) | DENSEI-LAMBD | 06+ | MODULE- | The 74HC/HCT377 have eight edge-triggered, D-type flip-flops with indiv |
| PAR | (25) | TI | 93+ | NOTES 1Operating temperature range is as follows: C40 C to +85 C. | |
| PAS | (65) | CMD | Absolute Maximum Ratings are stress ratings only. Permanent damage to the | ||
| PAT | (104) | YOKOHAMA | N/A | 1. Characteristics in stand-alone mode • 3-bit ADPCM •Sampli | |
| PAU | (4) | HIT | Most Significant Data Bit (MSB) Data Bits 6-1 Least Significant Data Bit | ||
| PAV | (3) | N/A | When the 5340 pixels are divided into blobks of 100, the maximum o | ||
| PAW | (9) | M/A-COM | The CMPIN pin drives two data slicers, which convert the analog signal fr | ||
| PAX | (2) | The HYM7V63801B F-Series are Dual In-line Memory Modules suitable for easy | |||
| PAY | (2) | PAYER | DIP18 | Limits in standard typeface are for TJ = 25˚C and limits in boldfac | |
| PAZ | (2) | Axial and Surface Mount Power Schottky rectifier suited for Switch Mode | |||
| P-B | (4) | INFINEON | BGA | 06+ | over the full operating temperature range. Unless otherwise specified: VI |
| PB- | (14) | 0012+ | LCC | SDA is a bidirectional pin used to transfer addresses, data or control in | |
| PB0 | (15) | MIT | DIP-5 | 93+ | • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) |
| PB1 | (37) | N/A | The interface should be arranged to allow simple data transmission from t | ||
| PB2 | (16) | SZHG | SOP | 03+ | 1. Test conditions unless otherwise noted: 25º C, Supply Voltage = + |
| PB3 | (7) | N/A | POWER GROUND. Terminals 7 through 17 and 29 through 39 are webbed | ||
| PB4 | (5) | ON | O7+ | The Si9185 is a 500-mA CMOS LDO (low dropout) voltage regulator. The de | |
| PB5 | (9) | SIPEX | CAN | 2001 | † Stresses beyond those listed under absolute maximum ratings may c |
| PB6 | (10) | 98 | Manchester encoding and decoding is made possible through the integrate | ||
| PB7 | (4) | CUSTOMER | 2004+ | The FIN1217 and FIN1215 transform 21-bit wide parallel LVTTL (Low Volta | |
| PB8 | (1) | NEC | 04+ | Quickly pulling and holding any of these pins above 1.25V (using diode-c | |
| PB9 | (2) | The auto identify mode allows the reading out of a binary code from a EPR | |||
| PBA | (106) | TPS76318DBVR | Ti | SOT-23-5 | ♦ Plastic package has Underwriters Laboratory Flammability C |
| PBB | (7) | The EL8300 represents a triple rail-to-rail amplifier with a - 3dB bandwi | |||
| PBC | (29) | N/A | N/A | 04+ | next two cases of single-bit errors give a high on MERR and a low on ERR |
| PBD | (30) | N/A | N/A | N/A | DATA POLLING: The AT49BV16X4(T) features DATA polling to indicate the en |
| PBE | (3) | SIEMENS | SOI39mm/Reel | The transceiver provides an internal loopback capability for self-test pu | |
| PBF | (33) | NIEC | SOP | The MAX5893 programmable interpolating, modulating, 500Msps, dual digital | |
| PBG | (12) | isabellenh黷te | isabellenh黷te | dc00 | Output enable terminal: no matter in what phase MBI5170 operates, the sig |
| PBH | (11) | isabellenh黷te | isabellenh黷te | dc04 | 1.8/3.3 V Dual Supply Operation AD9736 SFDR > 53 dBc to fOUT = 600 |
| PBI | (1) | The devices also have 96 I/O cells, each of which is directly connected | |||
| PBK | (17) | ERICSSON | 03+ | (Reset) - The RST pin functions as a microprocessor reset signa | |
| PBL | (596) | ERICSSON | DIP | Thermal Protection The FAN2500/01 is designed to supply high peak output | |
| PBM | (146) | The HYM72V64C736(L)T4 Series are 64Mx72bits ECC Synchronous DRAM Modules. | |||
| PBN | (2) | Systems calibration Electronics level setting Mechanical Trimmers® r | |||
| PBP | (28) | MINI | 08+ | When VCC is greater than 1V and less than the UVLO threshold, REF is pu | |
| PBQ | (3) | XGI | BGA3131 | 0417CD | The first character of the part number suffix determines the devic |
| PBR | (119) | avx/kyo | avx/kyo | dc0301 | This information is generally descriptive only and is not intended to mak |
| PBS | (207) | PHILIPS | SOT-223 | 05+PB | Vcc = 5.0V10%, TA = 0C to 70C, unless otherwise specified SymbolParameter |
| PBT | (14) | N/A | AMDs Flash technology combines years of Flash memory manufacturing exper | ||
| PBU | (26) | N/A | N/A | 01+ | The fixed 54 MHz clocking of the ADCs and datapath for all modes allows |
| PBV | (10) | TI | na | The K6F2016V4E families are fabricated by SAMSUNGs advanced full | |
| PBW | (13) | NEC | † Package drawings, standard packing quantities, thermal data, symb | ||
| PBX | (1) | Intersil offers a wide range of MOSFET drivers to form highly integrated | |||
| PBY | (280) | N/A | 1206 | Four dedicated test pins are used to observe and control the operation of | |
| PBZ | (1) | The HMS9xC7132/4 is a single-chip microcontroller of the 80C51 family, wh | |||
| P-C | (1) | ||||
| PC- | (51) | DIP-4 | Both full-duplex transmit and receive (with asymmetric 1200/75 bps conn | ||
| PC/ | (8) | SHARP | DIP16 | The HEF4528B is a dual retriggerable-resettable monostable multivibrato | |
| PC0 | (61) | VGG = the gate drive voltage, which varies from zero to VGG RG = the gat | |||
| PC1 | (420) | SHARP | NOTES : 1. In case of 40MHz Frequency, CL1 can be supported. 2. Samsung | ||
| PC2 | (158) | TFK | DIP | The IDT72V205/72V215/72V225/72V235/72V245 are functionally com- p | |
| PC3 | (453) | SHARP | 05+ | Compatible With PC 99 Desktop Line-Out Into 10-kΩ Load Internal Ga | |
| PC4 | (182) | SHARP | SOP/4 | 02+ | The differential inputs provide a full scale differential input swing eq |
| PC5 | (105) | 98+ | I²C uses a two-wire serial interface, comprising a bi-directional | ||
| PC6 | (164) | MOT | N/A | Controlled slew rate reduces EMI Over temperature protection Over curr | |
| PC7 | (891) | PHI | SOP3.9 | 99 | NOTES 1Temperature range is as follows: B Version: C40C to +85C. 2Typic |
| PC8 | (752) | SHARP | SOP | 01+ | Total Power Supply and Zener Current Output Current Source or Sink (Not |
| PC9 | (337) | N/A | N/A | 04+ | The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI/ |
| PCA | (1622) | PHILIPS | 2008 | The 370C/W assumes the use of the recommended foot- print on a gl | |
| PCB | (223) | PHI | SOP28 | 07+/08+ | 5V power supply 5V power supply 5V LNA power supply RF input LNA grou |
| PCC | (49) | PHILIPS | SOP8 | N/A | For those systems using buses wider than a single byte, the four indepen |
| PCD | (735) | PHILIPS | SOP28 | 03+/04 | Deselected, Power-down Deselected, Power-down Deselected, Power-down |
| PCE | (80) | OEG | 原装 | 08+ | NOTES: 1. Minimums are guaranteed but not production tested. 2. This pa |
| PCF | (1529) | PHILIPS | SOP | 07+ | Device performance is relatively independent of supply voltage over the |
| PCG | (8) | TYCO | 继电器-6 | 2003+ | BVDSSDrain-to-Source Breakdown Voltage ∆BV DSS/∆T J Temperat |
| PCH | (72) | NIEC | SOP | Note 1: Devices are tested at TA = +25C and guaranteed by design for TA = | |
| PCI | (526) | TI | TQFP | Typical specifications represent average readings at 25C and VDD = | |
| PCJ | (3) | OEG | Relay(new original) | VIA Twister chip with Integrated S3 Savage4 2D/3D/ Video Accelerator 8/1 | |
| PCK | (139) | PH | 07+ | Only five small 1-µF ceramic capacitors are required to build a com | |
| PCL | (50) | MOT | 05+ | SOP-8 | The ispGDXVA I/Os are designed to withstand live insertion system envir |
| PCM | (1047) | N/A | N/A | 04+ | The DS1642 is in the write mode whenever WE and CE are in their active sta |
| PCN | (49) | N/A | HRS | 05+ | |
| PCO | (2) | Features • Low current consumption : 1.1 mA (typ. at VCC=1. | |||
| PCP | (25) | ON | DIP-8 | 02+ | VDD: Chip power supply pin. VDD should be bypassed to PGND. The C1 and C |
| PCQ | (1) | MOT | sinking and sourcing 20 mA at TTL voltage levels. The Output Disable log | ||
| PCR | (80) | N/A | 6SDQVLRQΠ)ODVK PHPRU\ SURGXFWV FRPELQH \HDUV RI )ODVK PHPRU\ PDQXID | ||
| PCS | (72) | MMC | SOP | 02+ | The decoders receive data that are transmitted by an encoder and interpr |
| PCT | (206) | TI | SOP-16 | 01+ | TerminatorTM technology in StratixTM and Stratix GX devices helps prevent |
| PCU | (5) | The passive bias circuits used in these designs include a dropping resist | |||
| PCV | (28) | DIP | To limit maximum duty cycle, the internal clock pulse blanks both outpu | ||
| PCW | (18) | Description The 18:88 and 88:88 0.56" Four Digit Seven Segment Disp | |||
| PCX | (8) | PHILIPS | QFP0707-32 | 02+ | Complete E1, T1, or J1 line interface unit (LIU) Supports both long- and |
| PCY | (10) | The Bay Linear LM2941 incorporates protection against over-current fault | |||
| PCZ | (5) | COMPLETE TELETEXT DECODER INCLUD- ING ON-CHIP 8 PAGES MEMORY, REDUC- I | |||
| P-D | (2) | Infineon | O7+ | A read cycle is accomplished by asserting output enable (OE), chip enable | |
| PD- | (23) | N/A | This device consists of two independent, high-gain, frequency-compensated | ||
| PD/ | (24) | • Fast access time: 7, 8, 10, 12 ns • CMOS low power operat | |||
| PD0 | (80) | DIP-20 | Internal Organization When ORG is connected to VDD or ORG is floated, th | ||
| PD1 | (158) | Note 8: CIN, COUT, and C1 : Low-ESR Surface-Mount Ceramic Capacitors (MLC | |||
| PD2 | (135) | PIONEER | 08+ | VC (PIN 8): Compensation Node. Connect this pin to GND through a 0.1&micr | |
| PD3 | (64) | 1850 | The HI-5701 is a monolithic, 6-bit, CMOS flash Analog-to- Digital Conver | ||
| PD4 | (165) | SHARP | 05+ | Notes: * Post-radiation performance guaranteed at 25C per MIL-STD-883 Me | |
| PD5 | (143) | STM | SOP-2P | 01+ | This circuit is used to design inductive proximity switches. The resonant |
| PD6 | (98) | CIRRUSLOGIC | 95 | pins 3 & 7 connected See application schematic See application schem | |
| PD7 | (99) | 04+ | 3. Zener voltage is measured with the device junction in thermal equilibr | ||
| PD8 | (31) | N/A | The 3D7205 five-tap delay line architecture is shown in Figure 1. The del | ||
| PD9 | (61) | CINJET | SSOP | JTAG In-System Programming (ISP) reduces de- velopment time, simplifies | |
| PDA | (14) | powerbox | powerbox | dc99 | The criterion above is sharper than the standard (incorrect) time-domain |
| PDB | (20) | PIONEER | Notes: 1. For conditions show as Max. or Min., use appropriate value spe | ||
| PDC | (127) | PIONEER | QFP1420-100 | Silicon chip on Direct-Copper-Bond substrate - High power dissipation - | |
| PDD | (7) | PHI-COMP | DIP | 05+ | VCC IOUT Short Circuit protected to ground. Maximum reliability is ob |
| PDE | (2) | PIONEER | The information provided herein is believed to be reliable at press time. | ||
| (3) | ON | SMD16 | The output clocks from this pad cell are able to have their polarities | ||
| PDG | (23) | SEMTECH | SMD | SMD | Notes: 1. See test circuit and waveforms. 2. This parameter is guarant |
| PDH | (56) | NIEC | SOP | Configuration Programs For Field Programmable Gate Arrays (FPGA) Simple I | |
| PDI | (122) | PHI | SOP14S | 06+ | Output Drivers Each output driver is capable of both sourcing and sinkin |
| PDJ | (4) | ST | SOP | The PDJ949s low power dissipation makes it well suited for portable and | |
| PDK | (9) | Pioneer | QFP | 99 | Multiple pulse inputs (repetitive pulse inputs) can be used to step throug |
| PDL | (21) | P-DUKE | 01+ | Optional Asynchronous JTAG reset. Can be used to reset the TAP controller, | |
| PDM | (204) | N/A | The Motorola High-End Technical Publications Department provides a fax num | ||
| PDN | (17) | CMD | SSOP | 97+ | The MAX1857 low-dropout linear regulator operates from a +2.5V to +5.5V s |
| PDO | (1) | TI | Phone Detection Parallel Phone Exclusion Relay Control Protected Against | ||
| PDP | (6) | MERRIMAC | 16 | Dual Channel 1 Form A Extremely Low Operating Current High-speed Oper | |
| PDQ | (2) | YAMAHA | QFP | 07+/08+ | (5-V Input and Output Voltages With 3.3-V VCC) Bus Hold on Data Inputs E |
| PDR | (6) | AMI | SOP-16 | 98+ | DESCRIPTION Frequency Range Small Signal Gain Small Signal G |
| PDS | (69) | STM | 2150 | Frequency planning is straightforward for single-conversion applications | |
| PDT | (636) | NIEC | SOP | Through its 1-Wire interface, the DS2751 gives the host system read/write | |
| PDU | (11) | N/A | 00 | This device is intended to be used only in a half-bridge which drives in | |
| PDV | (9) | The PDV20-21M-103A is a negative voltage hot swap controller that allows | |||
| PDW | (2) | PARADIGM | 99+ | SOJ | Specifications shown in boldface are tested on all production units at fi |
| PDX | (4) | uei | uei | dc02 | Output Buffer Amplifiers The voltage outputs are from precision unity-ga |
| PDZ | (110) | Philips 06+ | Near-Zero propagation delay RON is 5Ω typical at 3.3V Fast swit | ||
| PE- | (755) | Pulse | A | A | The SN74CB3T3245 is a high-speed TTL-compatible FET bus switch with low O |
| PE0 | (22) | N/A | SOP-24 | The MCP1701 is capable of delivering 250 mA with an input-to-output volta | |
| PE1 | (90) | 2520(1008) | n CCITT G.726 compatible at 40, 32, 24, 16 kbps n ANSI T1.301 compatible | ||
| PE2 | (51) | 250A/1600V/2U | 三社可控硅模块SanRex Thyristors, PK= 两个可控硅串 | The K4M51323LE is 536,870,912 bits synchronous high data rate Dyn | |
| PE3 | (48) | FARADAY | STK | 2003+ | The PE3001-JU is a surface mountable flip chip resistor that utilizes U |
| PE4 | (86) | Peregrine | 01+ | External Clock. This signal is used only in synchronous DPSK transmission | |
| PE5 | (176) | 98+ | The PALCE29MA16 has 29 inputs to drive each product term (up to 58 inpu | ||
| PE6 | (296) | PUISE | 00+ | Transil diode arrays provide high overvoltage protection by clamping ac | |
| PE7 | (20) | SanRex | SOP | This document contains proprietary information of LSI Logic Corporation. | |
| PE8 | (20) | SOP | SOP | ||
| PE9 | (50) | SanRex | SOP | The HYM7V651601B F-Series are Dual In-line Memory Modules suitable for eas | |
| PEA | (4) | NEC | 07+ | Added Delay Measurement Methodology table, updated SelectI/O section, Fig | |
| PEB | (1601) | INF | 06+ | 930 | |
| PEC | (21) | BOURNS | Encoder | 07+ | Hynix HYMD264726(L)8-K/H/L series is unbuffered 184-pin double data rate |
| PED | (9) | Infineon | 1 | Two Line Output Control Because EPROMs are usually used in larger memor | |
| PEE | (242) | 94 | or x is approximately 59.83. This requires an additional lead of 0.17 t | ||
| PEF | (508) | SIEMENS | PLCC44 | 03+ | This familiy is a 64Mbit dynamic RAM organized 4,194,304 x 16bit configura |
| PEG | (59) | PIONEER | QFP | 07+ | The communications interface allows the host to observe and control the c |
| PEH | (34) | evx | evx | dc01 | Four of the seven instructions end with the transmission of the instruc |
| PEI | (23) | JS | 05+ | This dual function pin serves as the SYNC and SHUTDOWN input. To synchron | |
| PEJ | (1) | * The products contained herein may also be controlled under the U.S. Expo | |||
| PEL | (13) | SSOP16 | 02+ | The USB specification defines the following five classes of devices, each | |
| PEM | (88) | PHILIPS | SOT-363 | The instruction set by F2MC-16LX CPU core inherits an AT architecture of | |
| PEN | (55) | Alpha Industries | 2007 | Forward voltage(typ.) IF=20mA Forward voltage(max.) IF=20 | |
| PEO | (1) | ||||
| PEP | (3) | 99+ | The internal circuit is composed of 3 stages including buffer output, wh | ||
| PER | (8) | TeKmos | O7+ | The contents of this specification are subject to change without further | |
| PES | (148) | NXP | 08+PBF | 6. Tlow to Thigh = 0 to +125C for LM317MATlow to Thigh = − 40 to + | |
| PET | (10) | AMIS | BGA | 07+/08+ | The Hynix PET-PH201 Series are Dual In-line Memory Modules suitable |
| PEU | (1) | One or more of the following United States patents apply: 4,454,48 | |||
| PEW | (1) | REFIN Input Capacitance REFIN Input Current PHASE DETECTOR | |||
| PEX | (28) | PLX | 08+ | Receive Output. These ECL 100K outputs (+5V referenced) represent the buf | |
| PF- | (7) | N/A | The second generation CoolSET™-F2 provides several special enhance | ||
| PF0 | (159) | HITACHI | Unless otherwise noted, VCHG-IN = VDD = 5V, VBATT = 4V. Typical values a | ||
| PF1 | (50) | HIT | 01+ | Control Signal Input. Used to enable or disable blanking of the LUMA (DA | |
| PF2 | (38) | 2007 | 2. The maximum rated output power for this series is 20W. An incr | ||
| PF3 | (65) | INTEL | BGA | N/A | A general-purpose data register file is contained in each processing ele |
| PF4 | (31) | Important Information and Disclaimer:The information provided on this pag | |||
| PF5 | (25) | 97+ | Note 3: All currents into device pins are positive; all currents out of d | ||
| PF6 | (4) | LAMBDA | Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shi | ||
| PF7 | (7) | SIEMENS | 07+ | Item Average On-State Current R.M.S. On-State Current Surge On- | |
| PF8 | (3) | Bursts can be initiated with either ADSP (Address Status Processor) or | |||
| PF9 | (7) | QFP | CPU Core power: 0.925V to 2.0V output range 1% reference precision over | ||
| PFA | (46) | Figure 4 shows the ADR512 serving as an external reference to the AD7533 | |||
| PFB | (25) | N/A | Each slave carries an address. The data transfer is initiated by a start | ||
| PFC | (113) | REFU | MODULE | N/A | Function Port 2, Bit 1-7 Analog In 1-7 Reset Oscillator Clock Osci |
| PFD | (16) | NEC | DIP6 | where frequency is in hertz, resistance in ohms, and capacitance in farad | |
| PFE | (36) | samsung | 02+03 | SMD8P | low insertion loss, 0.8 dB typ. excellent isolation 28 dB typ. very go |
| PFF | (21) | TO-220 | 06+ | DESCRIPTION The IS66_ series are optically coupled isolato | |
| PFH | (1) | N/A | 05+ | The MB3836 is a lithium-ion battery protection IC for three cells series | |
| PFI | (3) | ZETEX | 2001/2003 | SOP-8 | s GENERAL DESCRIPTION The NJU7700/01 is a low quiescent current |
| PFK | (26) | ERICSSONS | 94 | 16384 bits of read/write nonvolatile memory 256-bit scratchpad ensures | |
| PFL | (13) | PIoneer | SO-28 | 06+ | Unicorn II is an evolution of the field-proven and mass deployed Unicor |
| PFM | (7) | PULSE | 2005 | The PFM0616NLTF has an on-chip burst counter that allows the user the abi | |
| PFN | (4) | After the password sequence, there is always a nonvola- tile write cycl | |||
| PFP | (7) | SSOP | 99 | Its low-IF architecture highly integrated RF/IF sec- tions include a lo | |
| PFQ | (8) | MMC | BGA | N/A | Inherently Matched LED Current High Efficiency: 84% Typical Drives Up to |
| PFR | (45) | Output voltage is set to a nominal value between 26V and 28V, by an inte | |||
| PFS | (20) | INPAO | 1206-050 | 07+ROHS | Notes: 4. In-Band EI 115.2 kb/s. 5. Logic Low is a pulsed response. Th |
| PFT | (28) | N/A | The devices feature single 3.0 V power supply operation for both read and | ||
| PFU | (1) | NDB | 07+/08+ | Eye Safety Circuit The HFBR-5710L provides Class 1 eye safety by desig | |
| PFV | (17) | 94 | * Specifications same as model 5B45. 1Jumper selectable. Refer to Field C | ||
| PFW | (6) | MURATA | 5*6 | The pin configuration interface comprises 40 configurations, which are sh | |
| PFX | (3) | The device features simultaneous read/write op- eration, which allows t | |||
| PFZ | (1) | Average Rectified Current .375 " lead length @ TA = 75C Pe | |||
| PG- | (6) | NEC | N/A | Note 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS | |
| PG. | (1) | PULSE | SOP-8模块 | Low ON-resistance 2 x 0.2 W , 2 x 0.35 W (typ.) Power - SO 20 - Packag | |
| PG0 | (41) | PULSE | SOP | 312 | 1 Allowable ambient temperature against % coil voltage (max. insi |
| PG1 | (66) | NEC | Relay(new original) | A special mode is introduced to reduce EMI. With pin OSEL connected to GN | |
| PG2 | (13) | PLCC | PLCC | The ispLSI 2128 and 2128A are High Density Program- mable Logic Devices | |
| PG3 | (5) | MARVELL | QFN | 06+ | 1M Home Phoneline Network physical-layer, single- chip transceiver Suppo |
| PG4 | (6) | SOP | The BA178!!T and BA178!!FP series are 3pin fixed positive output voltage | ||
| PG5 | (10) | INTEL | SOP32W | 2007+ | This low-cost accessory board provides an easy way of powering all |
| PG6 | (2) | Notes: 1. CL = Load capacitance: includes jig and probe capacitance. | |||
| PG7 | (1) | Selects the parallel programming interface. The internal PLL divider sett | |||
| PG9 | (2) | FUJI | 03+ | Even Parity. Parity is even parity across AD31-0 and nC/BE3-0. PAR is sta | |
| PGA | (209) | BB | DIP | DIP | Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V |
| PGB | (9) | ＬＩＴＴＥＬＦＵＳＥ | The Hynix HYM4V33100DTYG Series are 1Mx16bits Synchronous DRAM Modules. Th | ||
| PGC | (13) | DIP14 | The Hyundai HYM71V16S755AT8 Series are 16Mx72bits ECC Synchronous DRAM Mod | ||
| PGD | (12) | The 8-bit program status word (PSW) controls ALU operations and in | |||
| PGE | (2) | The Si5311 is a fully integrated high-speed clock multiplier and clock re | |||
| PGF | (3) | etec | etec | dc03 | The PCI I/O region is also a 4 Gbyte space. However, most systems and I/ |
| PGH | (48) | 6. As it might be a cause of degradation of destruction to apply static el | |||
| PGI | (2) | TOKIN | SOP | The MSAU300 converter is encapsulated in a low thermal resistance molding | |
| PGL | (3) | TI | TSSOP-56 | NOTES: 1. VDD, OPTX, and VDDQX must be set to appropriate operating level | |
| PGM | (34) | PGM | DIP | 00+ | The MAX 7000E devicesincluding the EPM7128E, EPM7160E, EPM7192E, and EPM |
| PGP | (1) | 2.1 Subject to the conditions herein and upon initial use of the AMBE-200 | |||
| PGR | (2) | Additional design entry and simulation support provided by EDIF 2 0 0 an | |||
| PGT | (6) | MOT | BGA | N/A | NOTES: 1. Dimensions are in inches. 2. Metric equivalents |
| PGV | (1) | The MC100EP139 is a low skew 2/4, 4/5/6 clock generation chip desi | |||
| PH- | (15) | PHILIPS | 00+ | Error Amp Section Input Voltage Input Bias Current | |
| PH0 | (41) | 117 | 1. Multi-Picture (automatic) Fields are extracted from a sequence | ||
| PH1 | (291) | M/A-COM | The AD5620/AD5640/AD5660-1 parts include an internal, 1.25 V, 5 ppm/C re | ||
| PH2 | (147) | DIP/SMD | CSC | 04+ | How to Write: • Controller (host) sends a start bit. • Cont |
| PH3 | (154) | N/A | slave devices in the I 2C protocol with all memory operations synchroni | ||
| PH4 | (40) | NIEC | SOP | BCD or seven segment outputs are available. Digit strobes are decoded i | |
| PH5 | (87) | N/A | Unlike the other two modes that accept only a single specified input freq | ||
| PH6 | (21) | N/A | If the auto-increment flag (AI) is set, the four low order bits of the C | ||
| PH7 | (98) | LAMBDA | The FM1233A permits a pushbutton (or a signal) to initiate a reset exter | ||
| PH8 | (21) | PHI | 06+ | TOT669/4 | Application of the CY7C403 or CY7C404 Cypress CMOS FIFOs requires knowl |
| PH9 | (29) | PHILIPS | MODULE | 00+ | For high-density packaging applications, the UCN5818EPF is furnish |
| PHA | (56) | NIEC | 04+ | CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic ch | |
| PHB | (200) | PHILIPS | TO | The functional block diagram shows the IEEE Standard 1149.1-1990 4-wire t | |
| PHC | (18) | SOP14 | 06+ | † Stresses beyond those listed under absolute maximum ratings may c | |
| PHD | (131) | PHILIPS | TO | PARAMETER Current Limit Section CS Threshold Set Current CS Comp Offset | |
| PHE | (105) | evx | evx | dc01 | The melting temperature of solder is higher than the rated temper |
| PHG | (3) | This block provides a stable regulated output voltage starting from a bat | |||
| PHI | (24) | sFEATURES qOperating Voltage4.7 to 13V qLow Operating Curr | |||
| PHK | (37) | PHI | 0451+/0452+ | SOP8 | After the software data protections three-byte command code is given, a b |
| PHL | (10) | MOTOROLA | (LX)high-frequency | AVDD Current (Normal Mode) AVDD Current (Reduced Power Mode) AVDD Curren | |
| PHM | (36) | NIEC | SOP | The System ACE file structure setup allows ACE Flash memory not used fo | |
| PHN | (39) | Hynix HYMD264M726A(L)8-J/M/K/H/L series is designed for high speed of up | |||
| PHO | (33) | DIP | 4. Accesses to registers other than CHIPCTL0 are invalid in the reset sta | ||
| PHP | (265) | PH | TO-220 | 06+ | Notes: 1. DQ-to-I/O wiring may be changed within a byte 2. DQ/DQS/DM/CKE |
| PHQ | (3) | N/A | N/A | 04+ | Burst mode operation Auto & self refresh capability (4 |
| PHR | (23) | tyco | tyco | dc06 | For applications requiring guaranteed RF-tested perform- ance up to 26 G |
| PHS | (12) | A read cycle is initiated by the falling edge of CAS or OE, whichever o | |||
| PHT | (54) | N/A | CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RI | ||
| PHU | (11) | PH | 06+ | Two products are offered in the series with different output volt | |
| PHV | (2) | The Am29LV160B is entirely command set compatible w it h t h e J E D E | |||
| PHW | (25) | PHILIPS | TO- | The K6R4004C1D is a 4,194,304-bit high-speed Static Random Access Memory | |
| PHX | (52) | PH | 06+ | 1. Life support devices or systems are devices or systems which, (a) are | |
| PHY | (31) | 0 | 0 | The FSK_ADJ and ASK_ADJ resistors can be adjusted in the system to optim | |
| PHZ | (1) | NIEC | 2007 | Recommended wire bonding uses 3 mils wide and 0.5 mil thick gold ribbon w | |
| PI- | (14) | KDI | 2008 | The UDA1384 is a single-chip consisting of 4 plus 1 Analog-to-Digital Con | |
| PI0 | (8) | N/A | Not only support the programmable gain from 0 to 22.5 dB with 16 steps an | ||
| PI1 | (45) | N/A | SMD | 2000 | Low Cost Complete H-Bridge 28 Volt, 5 Amp Capability, 75 Volt Maximum Ra |
| PI2 | (49) | SSOP24 | The HS-80C85RH is an 8-bit CMOS microprocessor fabricated using the Int | ||
| PI3 | (287) | 66 | PERICOM | Notes: 1. For conditions shown as Max. or Min., use appropriate value sp | |
| PI4 | (229) | PHILIPS | SOP-8 | 06+ | programmable horizontal and vertical expansion ratio - pr |
| PI5 | (527) | PERICOM | SSOP28 | 03+ | Choose among the following memory organizations: IDT72V255LA8,192 |
| PI6 | (273) | PERICOM | SOP8 | 05+ | Hynix HYMD564726(L)8-K/H/L series incorporates SPD(serial presence detect) |
| PI7 | (1350) | 74 | PI | 0146+ | An input capacitor of 2.2µF (nominal value) or greater, connected |
| PI8 | (1) | N/A | SMD | 97+ | This device provides 64 bytes of general-purpose flash memory, 8 bytes |
| PI9 | (71) | Pericom | STK | 2003+ | voltage mode control • Vcc Over-voltage protection (latched) |
| PIA | (3) | N/A | N/A | 06+ | 3.1 The END USER shall have the right to transfer the AMBE-2000™ Vo |
| PIB | (5) | PROGATE | 03+ | QFP | If you have any marketing or sales questions, please contact: Law |
| PIC | (9195) | micro | micro | dc04 | Data inputs for a 18-bit bus. MRS initializes the read and write pointers |
| PID | (5) | LUCENT | 0 | QFP-48 | Programmable options include the length of pipeline (Read latency of 2 or |
| PIF | (28) | MINI | 08+ | Output voltage amplitude at f=1 kHz such that total output harmonic distor | |
| PIH | (5) | PIH | 2007 | Notes: 1. See Figure 1 to establish pulsed conditions. 2. Derate above | |
| PII | (63) | N/A | N/A | 04+ | standard for high-speed system bus running at half the CPU clock High-b |
| PIJ | (2) | DIP18 | 92+ | Note 9: The 1µA limit is based on a testing limitation and does not | |
| PIL | (17) | 01 | A short program illustrating the initialization and basic function of the | ||
| PIM | (20) | MOT | 99 | ||
| PIN | (21) | PANASONIC | 16384 bits of read/write nonvolatile memory 256-bit scratchpad ensures | ||
| PIO | (4) | PIO | 08+ | The output port is controlled in a similar manner by a free- running rea | |
| PIP | (59) | PHILIPS | 04+ | QFN | |
| PIQ | (1) | ACEX 1K device package types include thin quad flat pack (TQFP), plastic | |||
| PIS | (25) | KDS | |||
| PIT | (5) | 38 | AMIS | Low cost integrated monolithic GaAs amplifier with step attenuator. At | |
| PIV | (2) | TI | 00+ | Permanent device damage may occur if Absolute Maximum Ratings are exceede | |
| PIX | (2) | PIXELA | TQFP | 0251+ | The ANADIGICS AWL9224 power amplifier is a high performance InGaP HBT IC |
| PIZ | (1) | The ready/busy status can be determined after the start of a write oper | |||
| PJ- | (25) | CUI | N/A | 2007 | Using the latest high voltage technology based on a patented strip layo |
| PJ0 | (5) | PANJIT | SOP4 | 00+ | 2-bit bidirectional input/output lines with pull-high resis- Wake |
| PJ1 | (70) | PJ | TO-220 | 03+ | Contact resistance measured with 4 terminal method, 1.1" betw |
| PJ2 | (26) | Notes: 1. Due to the Cypress implementation of USB suspend mode support, | |||
| PJ3 | (56) | PROMAX | TO-220 | 03+ | technology available in DIP and SOP packages. The HCF4053B analog multi |
| PJ4 | (17) | RJ | SMD | 04+ | Since the RESET output on the MAX6328/MAX6348 is open drain, these devic |
| PJ5 | (5) | PROMAX | SOT-89 | 05+ | Low profile package Guardring for overvoltage protection Ideal for au |
| PJ6 | (3) | The Hynix HYM71V16M635B(L)T8 Series are Dual In-line Memory Modules | |||
| PJ7 | (42) | PRONAX | TO220 | 02+ | The A64 device has a 10-bit-resolution sample-and-hold MibADC. The MibADC |
| PJ8 | (3) | This device contains protection circuitry to guard against damage | |||
| PJ9 | (1) | . | . | 05+ | . . . employing the Schottky Barrier principle in a large area me |
| PJA | (2) | *The data output functions may be enabled or disabled by various signals | |||
| PJB | (3) | PROMAX | SOT-89 | 05+ | The PJB1386CY features split power supply buses for Banks 1 and 2, Bank 3 |
| PJC | (2) | JAPAN | N/A | N/A | RON is 4Ω typical Low bit-to-bit skew: 200ps Low crosstalk: C6 |
| PJD | (6) | SIS | 2007 | The write cycle is the time from a valid stop condition of a write sequen | |
| PJE | (2) | VBIAS (VCC , VBS1,2,3) = 15V, VS0,1,2,3 = VSS and TA = 25C unless otherw | |||
| PJF | (3) | PROMAX | TO-220 | 03+ | NOTES: A. CL includes probe and test-fixture capacitance. B. Wave |
| PJK | (2) | 2001 | (AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 250.0057MHz, -0.5dBFS; se | ||
| PJL | (1) | Single supply: 1.8 V to 5.5 V Two-wire serial interface (I2CTM serial b | |||
| PJM | (3) | PJM | DIP8 | 04+ | NOTE: EP circuits are designed to meet the DC specifications shown in the |
| PJQ | (1) | The ADS800 employs digital error correction to provide excellent Nyquis | |||
| PJR | (12) | The AD581 represents an alternative to current limiter diodes which requ | |||
| PJS | (2) | YAMAICHI | For more details on the ARCNET protocol engine and traditional dipulse si | ||
| PJT | (1) | SAMSUNG | 03 | Description The HEDS-974x series is a high performance, low cost, opti | |
| PJU | (2) | 90 | With binary logic, four states can be programmed with two control lines | ||
| PJV | (27) | PANSASONSIC | 9720 | SecSi (Secured Silicon) Sector region 128-word sector for | |
| PJW | (21) | N/A | DIP | 06+ | Note A: Characteristic data has been developed from actual products teste |
| PK- | (10) | HOKURIKU | 4X4-1M | 05+ | Port 2 (A8C15), I/O. Port 2 is a bidirectional I/O port. The reset condit |
| PK( | (27) | SUMMARY DESCRIPTION The M29W320D is a 32 Mbit (4Mb x8 or 2Mb x16) non-v | |||
| PK0 | (2) | Te xas Instrume nts and its subsidiarie s (TI) re se rve the right to mak | |||
| PK1 | (86) | SANREX | 可控硅模块 | PLIM: This pin is programmed to set the maximum input power for the conv | |
| PK2 | (84) | 100 | 天龙伟业 | 靳先生 | The buffered CCD output is capacitively coupled to the VSP2232. The purpo |
| PK3 | (2) | N/A | C Seven 16-KB blocks Auto Erase (chip & block) and Auto Program C | ||
| PK4 | (60) | 1850 | UART • 3 channels • Full-duplex double buffer | ||
| PK5 | (37) | N/A | NOTES: 1. For conditions shown as Min. or Max., use the appropriate valu | ||
| PK6 | (2) | ST | SOP24 | 0 | NOTE: Intersil Pb-free plus anneal products employ special Pb-free materi |
| PK7 | (29) | N/A | Vectron International reserves the right to make changes to the product(s | ||
| PK9 | (39) | 1850 | CASE: Hermetically sealed axial-lead glass DO-35 (DO-204AH) package TERM | ||
| PKA | (44) | MOBULE | ERICSSON | 04+ | This pin is connected to a voltage that must be at least 4V higher than th |
| PKB | (23) | Ericsson | Only few external Components required Input Undervoltage Lockout 67kHz | ||
| PKC | (38) | ST | N/A | 03+ | Capacitor connection for short-circuit protection. When voltage across CO |
| PKD | (26) | Ericsson | • N channel FET switches with no parasitic diode to VCC C I | ||
| PKE | (19) | ERICSSON | 0205+ | TEST CONDITION 4.75V<VIN<5.25V, 5mA[IO[1.3A: TJ=258C 08C[ | |
| PKF | (147) | N/A | N/A | N/A | This pin can be connected to either VSS, VCC or left floating. Internal |
| PKG | (69) | Gallium Arsenide Diode Infrared Source Optically Coupled to a Silicon npn | |||
| PKH | (20) | NIEC | SOP | Auto & self refresh capability (8192 Cycles/64ms) LVTT | |
| PKI | (6) | PLCC-28P | 9312+ | The address sequence is completed when the number of address blocks gen | |
| PKJ | (80) | Ericsson | I/OA, I/OB (Pins 7, 14): Card Socket. The I/OA, I/OB pins connect to the | ||
| PKL | (36) | NEC | DIP | 98 | The IR2520D(S) is a complete adaptive ballast controller and 600V half-br |
| PKM | (114) | N/A | The DSP56300 core family members contain the DSP56300 core and additional | ||
| PKN | (10) | Ericsson | Family features include an 8-bit memory mapped architec- ture, 10 MHz C | ||
| PKP | (1) | ON | SOP-8 | 03 | |
| PKR | (22) | ERICSSON | 07+ | The receiver section of the PI90SD1636A accepts a serial PECL- compatibl | |
| PKS | (22) | ERICSSON | 2007 | Notes: 1. Dominant Wavelength, ëd, is derived from the CIE Chromatic | |
| PKT | (17) | N/A | To protect against load faults, the regulators incorporate output over-c | ||
| PKU | (7) | NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATING | |||
| PKV | (19) | ON | 01+ | SOP-8 | Pb−Free Packages are Available Small Compact Surface Mountable Pac |
| PKY | (6) | N/A | N/A | N/A | PLL lock indication signal. 1 indicates positive lock. 0 indicates that th |
| P-L | (3) | Infineon | For example, S/H1 should not be commanded into the sample mode until al | ||
| PL- | (68) | PICOLIGHT | 08+ | Peak Inverse Voltage. . 45 Volts Maximum Average D.C. Output Current... 1 | |
| PL/ | (12) | ||||
| PL0 | (16) | STM | ＳＯＰ-２０ | 04+ | ¡Ultrathin thickness 0.8mm or less. (4.93.10.7mm) ¡It is a c |
| PL1 | (66) | INTERSIL | PLCC | 02+ | If an FSK signal inputs during the brief transition from battery-saving s |
| PL2 | (53) | 5 | PL | 0245+ | Lattice provides many pre-designed IP (Intellectual Property) ispLeverCOR |
| PL3 | (34) | ECHELON | SSOP | The bq2902 is a low-cost charger for rechargeable alkaline batteries such | |
| PL4 | (13) | 12000 | 07+ | The FM pre-amplifier input FMIN (Pin 28) consists of a transistor ground | |
| PL5 | (15) | RICOM | QFP | 07+ | Notes: 1. Typical continuous power in a non-ventilated enclosed a |
| PL6 | (9) | Atmel has successfully translated dozens of existing de- signs from most | |||
| PL7 | (8) | The CY7C235A incorporates a D-type, master-slave register on chip, reduci | |||
| PL8 | (9) | sharp | sharp | dc90 | Note 6: The limits are based on bench characterization of the devices jit |
| PL9 | (2) | 0 | 0 | 5.4 Undervoltege Detection 1) When Vcc supply voltage becomes be | |
| PLA | (117) | SiS | BGA | Infineon Technologies components may only be used in life-support devices | |
| PLB | (32) | Infineon | 03/04+ | BGA | The flexible architecture supports different media and speeds for Blue, D |
| PLC | (309) | BERG | N/A | H = Input Voltage High Level, h = Input voltage high one set-up timer pri | |
| PLD | (109) | CY | CLCC28W | 98 | Address Latch Enable: Output pulse for latching the low byte of the addre |
| PLE | (22) | CONTROL The Connection Memory High bits (Table 4) control the per- | |||
| PLF | (34) | N/A | In ES series models, flag M1083 is not provided. When FROM/TO instruction | ||
| PLG | (2) | Note 3: Typical values are determined with TA = TJ = 25˚C and repres | |||
| PLH | (17) | MURATA | 06+ | Both devices operate from a single +3.0V to +5.5V sup- ply and require no | |
| PLI | (2) | CDIP | Positive And Negative Regulators In One Package Hermetic 6-Pin Metal Pa | ||
| PLL | (276) | TI | 07+ | Controlled slew rate reduces EMI Over temperature protection Over curr | |
| PLM | (65) | murata | murata | dc00+ | MM74HCT640 transfers inverted data from one bus to the other The MM54HCT |
| PLN | (5) | TDK | 4R7-6012 | 04+ | The PLN6012T-4R7M1R1-1 is a synchronous, integrated FET 1A step-down regu |
| PLO | (2) | N/A | SMD | 2000 | Note 5: CPD is defined as the value of the internal equivalent capacitanc |
| PLP | (59) | MURATA | 04+ | SMD | BOOST (Pin 1): Topside (Boosted) Driver Supply. This pin is used to boots |
| PLQ | (1) | RL = 300 Ω, CL = 35 pF; VS1 = 10 V, VS8 = 10 V; Test Circuit 5 RL | |||
| PLR | (4) | DSI | n/a | Stresses greater than those listed under „Absolute Maximum Ratings | |
| PLS | (160) | etc | etc | dc02 | The LIS2L02AL has a full scale of 2g and it is capable of measuring acc |
| PLT | (40) | To have a good approximation of the remaining voltages at both Vin and Vo | |||
| PLU | (80) | SIG | 92+ | The P/R input is latched by the falling edge of the CE pin. A HIGH level | |
| PLV | (66) | TI | 02 | Thermal Resistance, Junction-to-Case - IGBT Thermal Resistance, Junctio | |
| PLW | (27) | MURATA | 5650-351 | 05+ | The STK12C68-20 requires VCC = 5.0V 5% supply to operate at specified sp |
| PLX | (9) | 95 | The HIP6017 provides the power control and protection for three output | ||
| PLY | (4) | . | When the host detects that one or both of the busy sig- nals has returne | ||
| PLZ | (1) | ||||
| PM- | (73) | N/A | This IC contains a zener clamp structure between the chip VCC and COM wh | ||
| PM0 | (71) | 04+ | Data transfer starts with the falling edge of the CS signal. Data must ap | ||
| PM1 | (453) | MITSUBSH | 04+ | Typ. Max. UnitsConditions CCC CCCVVGS = 0V, ID = -250µ | |
| PM2 | (306) | N/A | Sector protection Hardware method of locking a sector, either &n | ||
| PM3 | (274) | MIT | DESCRIPTION The STi7710 is STMicroelectronics first single chip set-top | ||
| PM4 | (192) | PMC | SOP | 126 | The NJM2742 is a high speed single supply operational amplifier .T |
| PM5 | (415) | PMC | BGA | Regulates voltage over a broad operating current and temperature r | |
| PM6 | (142) | N/A | N/A | 04+ | Page 25, Rotated marking text on PBGA package Page 35, Snap rate of 2 i |
| PM7 | (643) | PMI | CAN | 06+ | The products may contain design defects or errors known as errata, which |
| PM8 | (127) | PMC | 2007 | All voltages are referenced to V SS = 0 V (ground). All characteristics | |
| PM9 | (47) | MITSUBISHI | 900A600V | +53 ppm -30 ppm/C from + 25C to - 55C, 60 ppm below 10 pF. X7R & Z5 | |
| PMA | (34) | GFXCELst | BGA | 02+ | Stresses beyond those listed under Absolute Maximum Ratings" may caus |
| PMB | (2248) | SIEMENS | SSOP | N/A | Setting the VTRIP Voltage This procedure sets the VTRIP to a higher volt |
| PMC | (85) | TEMIC | 15A600V | Inputs Are TTL-Voltage Compatible True Outputs Latch-Up Performance Exce | |
| PMD | (40) | ALLEGRO | QFP | 05+ | use in common rectifier circuits, Table 1 indicates suggested factors fo |
| PME | (180) | NXP | 08+PBF | Note: (1) The minimum DC input voltage is C0.5 V. During transitions, in | |
| PMF | (34) | MICROCHIP | 08+PBF | The rectifier schottky barrier diode forward-direction voltage drop | |
| PMG | (28) | N/A | N/A | 04+ | The P8xC31X2/51X2 and P8xC32X2/52X2/54X2/58X2 contain 128 byte RAM and |
| PMH | (23) | PHILIPS | SOT363 | 05+ | Multiple devices can be concatenated by using the CEO output to drive t |
| PMI | (221) | PMI | DIP-8 | The circuits and measurements contained in this document are given only i | |
| PMJ | (11) | PIONEER | SOP | 1993 | DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . - |
| PMK | (7) | PHI | SMD | 3 | Hynix HYMD232G726(L)8-K/H/L series is registered 184-pin double data rate |
| PML | (110) | ＮＸＰ | The PMLL5235B/PMLL5235B charge a single-cell Li+ bat- tery from both USB | ||
| PMM | (63) | MOTOROLA | Typical Data is at TA = +25C and VCC = 5 V and is for design information o | ||
| PMN | (14) | PHILIPS | SOT-163 | 04+PB | When pin 3 (On/Off) is a logical 1, the fan speed will be controlled acco |
| PMO | (7) | Notes: 1. Repetitive Rating : Pulse width limited by maximum junction tem | |||
| PMP | (12) | PMI | SOP8S | 2007+ | Extremely Wide Operating Voltage 1.5 to 3.6 Volts Extended Tempe |
| PMQ | (2) | FAI | SMD | 93 | Tables 2 and 3 summarize the different behaviour and advantages of both |
| PMR | (41) | evx | evx | dc01 | Dimensions in mm. The components are situated on one side of the Rogers |
| PMS | (76) | PHI | 08+PBF | The timing resistors determine the total timing current, IT, available t | |
| PMT | (29) | PMT | SOP | Note 1: Absolute Maximum Ratings are limits beyond which damage to the de | |
| PMU | (4) | PHI | 06+ | The C6203 device program memory consists of two blocks, with a 256K-byte | |
| PMV | (27) | PHILIPS | SOT-23 | 05+ | One master and as many slaves as necessary may be connected in parallel t |
| PMW | (15) | N/A | 05+/06+ | Note 1. Commercial Product : TA=0 to 70C and Industrial Product :TA=-40 t | |
| PMX | (15) | Star | ELECTROMAGNETIC TRANSDUCER | Connect a resistor (ROCSET) from this pin to the drain of the upper MOSFE | |
| PMZ | (2) | evx | evx | dc01 | This low failure rate represents data collected from Maxims reliab |
| PN- | (2) | Panasonic | This method fails if a user applies RESET during the FPGA configuration | ||
| PN. | (3) | CELLNET | SMD28 | 00+ | 8 kinds of time base/WDT clock sources 32´4 LCD driver Built-in 3 |
| PN0 | (10) | Infineon | 05+ | • International standard packages • miniBLOC with Aluminium | |
| PN1 | (76) | FS | 07+ | Note: Stresses greater than those listed under MAXIMUM RATINGS may cause | |
| PN2 | (143) | PANASONIC | Notes: 1. See Figure 1 to establish pulsed conditions. 2. D | ||
| PN3 | (91) | PANASONIC | 1.8 | Absolute linearity is utilized to determine actual wiper voltage versus e | |
| PN4 | (76) | initialize to their default setting upon power-up, and therefore use of t | |||
| PN5 | (32) | PIONEER | SSOP48 | When VCC is between 0 and 1.5 V, the devices are in the high-impedance st | |
| PN6 | (2) | These products are not designed for use in life support appliances, device | |||
| PN7 | (5) | SMD | 99+ | The CS61880 is a full-featured Octal E1 short-haul LIU that supports 2. | |
| PN8 | (6) | VIA | BGA | 04+ | *Note: These are stress ratings only. Stresses exceeding the range specifi |
| PN9 | (6) | 00+ | SOP | Provide a very well decoupled 5V bias supply for the IC to this pin by co | |
| PNA | (46) | PANASONIC | . | SMD | or 2.5V+0.4V/-0.125V for 2.5V I/O. • 5V Tolerant Inputs exc |
| PNB | (4) | The Kawasaki KL5KUSB111 Controller is a unique single chip solution devel | |||
| PNC | (3) | N/A | BGA | 03+ | SENSE (Pin 5): Circuit Breaker Sense Pin. With a sense resistor placed in |
| PND | (6) | SIS | 03+ | C Easy design iteration C In-system logic changes • | |
| PNE | (2) | N/A | 06+ | 500 | FIN and OSC IN input level Max. operating frequency, fFIN and fosc Propa |
| PNF | (5) | Mon. : Oscillation frequency monitor terminal. The output is given from | |||
| PNH | (3) | PHILIPS | SMD8 | 95+ | These devices can be used as two 8-bit transceivers or one 16-bit trans |
| PNJ | (1) | A transmitter must first be learned by the receiver before its use is a | |||
| PNK | (2) | 95 | DIP | NOTES: 1. Stresses beyond those listed may cause permanent damage to the | |
| PNL | (2) | ROHM | 0228+ | QFP-32 | NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATIN |
| PNM | (2) | 00 | Ideal for Coil−on−Plug and Driver−on−Coil Applica | ||
| PNP | (5) | ST | 06+ | QFP | ALE Pulse Width ALE Rising Edge after CK1 Rising Edge (Note 2) ALE Fall |
| PNR | (3) | CMD | SOP | 93+ | Notes: 1. For conditions shown as Max. or Min., use appropriate value sp |
| PNS | (3) | PHIL | ESD damage can range from subtle performance degrada- tion to complete d | ||
| PNX | (220) | PHILIPS | 08+ | This formula guarantees that Q2 and Q4 will always have suf- ficient bas | |
| PNY | (1) | 06+ | sector and then program the latched data using an internal control timer | ||
| PNZ | (25) | hipot | hipot | dc96 | NOTE: All input pulses are supplied by a generator having the following c |
| PO- | (1) | ||||
| PO0 | (5) | SHARP | 97 | A read is accomplished by placing an active LOW signal on CS1, and activ | |
| PO1 | (20) | HAR | TO92 | 2000 | Interrupt Request: Is used as a general purpose interrupt. It is sampled |
| PO2 | (14) | FAIRCHILD | SSOP14 | 92+ | |
| PO3 | (10) | TECC0L | 00+ | SOP | TI assumes no liability for applications assistance or customer product d |
| PO4 | (9) | HARRIS | 08+ | See the Terminology section. These specifications do include full tempera | |
| PO5 | (18) | ST | SON | 05+ | A transmitter must first be learned by the receiver before its use is a |
| PO6 | (4) | The XRT75VL00D incorporates an advanced crystal- less jitter attenuator | |||
| PO7 | (13) | NIKO | 05+ | Temperature Sensor can be connected, on the board, to any of the ADC inpu | |
| PO8 | (11) | cyto | 04+ | 2.5V to 10V input voltage range Output voltage adjustable to 34V 1.2A | |
| PO9 | (1) | When heavy loads require the OUT pin to sink large currents being | |||
| POA | (7) | GPS | QFP52 | The TLE 4476 is a monolithic integrated voltage regulator providing two o | |
| POC | (30) | raltron | raltron | dc02 | The MTV230M micro-controller is an 8051 CPU core embedded device specially |
| POD | (4) | ||||
| POE | (11) | N/A | Introduction The AP1187 regulator is a 7-terminal device designed specif | ||
| POF | (1) | The ispLSI 1032EA is a High Density Programmable Logic Device containin | |||
| POG | (18) | SMD | MURATA | 05+ | A single-ended reference clock on the unselected reference input can caus |
| POI | (1) | 0 | 0 | Conexant products are not intended for use in medical, lifesaving or life | |
| POK | (3) | ERICSSON | MODULE | 01 | Decouple the output of the UC382 with at least 100 µF of high-quali |
| POL | (32) | Jack(Available) | Notes: 1. All minimum and maximum specifications are guaranteed a | ||
| POM | (43) | Logic and internal gate drive supply voltage Oscillator timing resistor | |||
| PON | (1) | C One Assembly/Test Site, One Fabrication Site Enhanced Diminishi | |||
| POO | (1) | such as a gaussian, or a rectangular pulse then the odd nature of (t-t0 | |||
| POP | (16) | Notes: 1. See test circuit and waveforms. 2. This parameter is guarantee | |||
| POR | (5) | TEXAS | QFP | 96+ | The ADSP-TS202S processor has compute blocks that can exe- cute computat |
| POS | (44) | MINI | 08+ | The SONIC (Figure 1-1 ) consists of an encoder decoder (ENDEC) unit media | |
| POT | (33) | MURATA | 4X4-1K | 04+ | Copyright © 1998, Via Technologies Incorporated. Printed in Taiwan. |
| POU | (1) | PHILIPS | PLCC | Stanford Microdevices POUSBP11AD is a high performance Gallium Arsenide H | |
| POW | (29) | TI | BGA | 1) CPD is defined as the value of the ICs internal equivalent capacitance | |
| POZ | (81) | When the Deserializer synchronizes to the Serializer, the LOCK pin is l | |||
| P-P | (1) | SAMSUNG | SMD | SMD | Reader Response: To improve the quality of our publications, we welcome y |
| PP- | (9) | PHI | QFP | 2003 | The use of Differential Rambus Signaling Level (DRSL) tech- nology permi |
| PP0 | (16) | PROD | 07+/08+ | The data receiver block is a decoder for decoding the serial input data fr | |
| PP1 | (84) | INTEL | BGA | 04+ | |
| PP2 | (31) | ABB | MODULE | N/A | The Contek LM79XX series of three-terminal negative regulators ar |
| PP3 | (31) | LAMBDA | SOP | These N-Channel enhancement mode power field effect transistors are produ | |
| PP5 | (29) | SAMSUMG | BGA | 07+ | The information provided herein is believed to be reliable at press time. |
| PP6 | (13) | LAMBDA | N/A | Notes: 1. Clock on/off latency is defined as the number of rising edges o | |
| PP7 | (5) | ABB | MODULE | TapePak and TRI-STATE are registered trademarks of National Semiconductor | |
| PP8 | (7) | PHILIPS | N/A | 98 | Hynix HYMD232646A(L)8-M/K/H/L series incorporates SPD(serial presence dete |
| PP9 | (3) | TO-254 | 9642 | The SDA pin is bidirectional for serial data transfer. This pin is open-d | |
| PPA | (5) | All synchronous inputs pass through input registers controlled by the ris | |||
| PPB | (1) | The 3-wire serial interface operates at clock rates up to 50 MHz and is | |||
| PPC | (404) | N/A | N/A | 04+ | Note 1: At TA = -40C, DC characteristics are guaranteed by design and char |
| PPD | (54) | LAMBDA | Protection diodes are employed at all pins except V+ and V- of th | ||
| PPE | (2) | Infineon | 05+ | The dropout voltage is defined as the input to output voltage differenti | |
| PPF | (1) | Note 5: Dynamic supply current is higher due to the gate charge being de | |||
| PPG | (12) | PPG | 94 | • Internal Avalanche Rugged SenseFET • Low Start-up Current | |
| PPH | (2) | The typical values of the input currents are 25 mA and are equally large | |||
| PPI | (4) | LAMBDA | NOTES 1Temperature range is as follows: B Version: C40C to +85C. 2Typic | ||
| PPJ | (1) | ||||
| PPL | (12) | N/A | The open-collector overtemperature flag output (TFL) is fed back to | ||
| PPM | (10) | AMPERE | DIP | AMDs Flash technology combines years of Flash memory manufacturing expe | |
| PPN | (8) | JS | 05+ | The q denotes the specifications which apply over the full operati | |
| PPO | (1) | Single chip 24-port 10/100M wire speed Ethernet switching controller with | |||
| PPP | (9) | Data-Rate Synchronous DRAM Applications Spread Spectrum Clock Compatible | |||
| PPR | (4) | LUCENT | The Hyundai HYM72V32M636AT6HYM72V32M636AT6 Series are 32Mx64bits Synchrono | ||
| PPS | (27) | JS | 05+ | In the test mode, the normal operation of the SCOPE™ universal bus | |
| PPT | (12) | High-Speed 8051 Architecture One Clock-Per-Machine Cycle DC to 33MHz Ope | |||
| PPX | (1) | 1800 | This device utilizes advanced silicon-gate CMOS technolo- gy to implemen | ||
| PQ- | (4) | N/A | BGA | 03+ | The output stage of most power amplifiers has three distinct limitations |
| PQ0 | (378) | SHARP | 00+ | The AC/ACT161 count in modulo-16 binary sequence. From state 15 (HHHH) | |
| PQ1 | (304) | SHARP | SOT | 01+ | Pin 13 (VSEN) can be used to modify the internal set point for the smoke |
| PQ2 | (91) | SHARP | TO-252 | 04+ | Beneficial comments (recommendations, additions, deletions) and any pertin |
| PQ3 | (59) | SHARP | 04 | The SN74LVT16646 is available in TIs shrink small-outline (DL) and thin s | |
| PQ4 | (72) | Notes: 1. See test circuit and wave forms. 2. This parameter is guarante | |||
| PQ5 | (17) | seeq | seeq | dc92 | • Adjustable Output Down To 1.2V • Fixed Output Voltages 1.5, |
| PQ6 | (38) | SHARP | 2520-6脚 | 05+ | The operation mode of the M5M51008C series are determined by a combinati |
| PQ7 | (14) | SHARP | 05+ | Multi-Input Wake-Up (MIWU) Supports up to 32 wake-up or interrupt input | |
| PQ8 | (21) | 41 | SEEQ | 93+ | The bq2014 measures the voltage differential between the SR and VSS pins. |
| PQ9 | (1) | 01 | The IDT72V2101/72V2111 are exceptionally deep, high speed, CMOS F | ||
| PQA | (1) | Hynix HYMD264G726(L)4-K/H/L series incorporates SPD(serial presence detect | |||
| PQB | (5) | FSC | 07+ | † Stresses beyond those listed under absolute maximum ratings may c | |
| PQC | (5) | VBIAS (VCC, VBS 1,2,3) = 15V unless otherwise specified. The VIN, VTH and | |||
| PQD | (1) | N/A | N/A | N/A | The Atmel cell implements a rich and powerful set of logic functions, s |
| PQF | (5) | N/A | QFP | 94+ | The CH1817 DAA includes circuits that couple the modem signals to the pho |
| PQG | (3) | The MAX4785CMAX4788 family of switches feature inter- nal current limitin | |||
| PQI | (8) | SHAPP | 02/03+ | TO220-5 | The following figure provides a graphical repre- sentation of the MTC20 |
| PQJ | (15) | High output accuracy of 1% Output Adjustable from 1.24V to 26V Output Cu | |||
| PQL | (20) | SHARP | 2001 | 2850 | In addition to the standard output configuration, the outputs of the is |
| PQM | (1) | TI | BGA | 06+ | |
| PQN | (1) | 2000 | ST | 01+ | NOTES: (1) Stresses above these ratings may cause permanent damage. Expo |
| PQO | (2) | 00 | For early-write cycles, the data is latched on the first falling edge of | ||
| PQP | (2) | FAIRCHILD | Member of Texas Instruments Widebus Family OEC Circuitry | ||
| PQR | (7) | FAIR | SOP8 | 04+/05+ | ESD (electrostatic discharge) sensitive device. Electrostatic charges as |
| PQS | (4) | Infiniium has received eight industry awards to date, including EDNs Inn | |||
| PQV | (84) | ALPS | 01 | Note 1: Absolute Maximum Ratings are those values beyond which the life | |
| PQW | (3) | MINI | 08+ | The recommended dose of ultraviolet light for erasure is a wavelength of | |
| PQX | (2) | SHARP | 05+ | The K6T1008C2C families are fabricated by SAMSUNGs advanced CMOS | |
| PQY | (1) | The PCB traces, wiring, and any components associated with or in contact | |||
| PR- | (10) | CIT1ZEN/大1210 | 04+/05+ | Max. UnitsConditions CCCVVGS = 0V, ID = 250µA CCCV/C Refere | |
| PR/ | (1) | ||||
| PR0 | (50) | STM | PLCC20 | 02+ | Address Inputs Byte/Word Enable Data In / Data out Data In/Out (Wor |
| PR1 | (75) | LITEON | N/A | 03+ | The HYM7V63801B F-Series are Dual In-line Memory Modules suitable for easy |
| PR2 | (64) | LPCC | 00 | Designed for space critical applications, the ADR512 is a low voltage (1 | |
| PR3 | (41) | SHARP | O7+ | Operating virtual junction temperature, TJ (see Note 1)C40125C # T | |
| PR4 | (4) | ** | 02+ | This product has been designed to meet the extreme test conditions and env | |
| PR5 | (11) | LAMBDA | MODULE | N/A | Portable and Battery-Powered Equipment PDAs Cell Phones Low Cost Precis |
| PR6 | (5) | DIODES | 06+ | Both circuits have three binary select inputs (A0, A1 and A2) that can b | |
| PR7 | (2) | NEC | QFP-44 | 9422 | The CBT6832D is a 16-bit controlled enable rate 1-of-2 multiplexer/demul |
| PR8 | (11) | INTEL | BGA | 06+ | The output of the oscillator is not directly available outside the 80C18 |
| PR9 | (8) | ST | PLCC84 | 07+ | Connect to the gate of the external N-Channel MOSFET. A capacitor from thi |
| PRA | (7) | ADI | 07+ | The electrical characteristic data has been developed from actual product | |
| PRB | (3) | NEC | 2001+ | DIP-8模块 | • Programmable Switch Mode Controller module: - PWM and PSM |
| PRC | (483) | *This part may also be used in Pollution Degree 3 environments where the | |||
| PRD | (44) | 99+ | DIP-18 | Write Operation Status Detection The SST39VF160Q/VF160 provide two softw | |
| PRE | (7) | NEC | 700 | involves the following phases : PHASE 0: The duration is a time p | |
| PRF | (198) | MOTOROLA | 03+ | The ACQ/ACTQ245 contains eight non-inverting bidirec- tional buffers wi | |
| PRG | (18) | HARRIS | 2008 | The transmission of ADSL/HDSL signals requires very low distortion ampl | |
| PRH | (32) | NIEC | SOP | Mode Select Table A LOW signal on MR overrides all other inputs and asyn | |
| PRI | (36) | SIEMENS | PLCC68 | 06+ | 1. Hitachi neither warrants nor grants licenses of any rights of Hitachis |
| PRJ | (1) | LINEARITY Linearity refers to how well a transducers output follo | |||
| PRK | (1) | ALPS | 01+ | Direct interface with 5 V to 1.8 V logic levels Supports Independent, Syn | |
| PRL | (31) | 2400 | 05+ | The IGBT is ideal for many high voltage switching applications operatin | |
| PRM | (37) | CMD | N/A | 96+ | Supply Voltage Terminal Terminal for OSC, and used for connecting a 45 |
| PRN | (835) | 1312 | CMD | Notes: 1. The algebraic convention, where the most negative value is a m | |
| PRO | (94) | CDIP | All voltages are referenced to ground. This is the absolute accuracy of t | ||
| PRP | (11) | SZX | SOP16S | 06+ | The highest transfection efficiency in many cell types and formats (e.g. |
| PRS | (6) | QFP | 97 | SMBJ5V0(C)A SMBJ6V0(C)A SMBJ6V5(C)A SMBJ7V0(C)A SMBJ7V5(C)A SMBJ8V0(C | |
| PRT | (16) | PHI | PLCC-M44P | 6+ | The RC2207 has a typical drift specification of 20 ppm/C. The osci |
| PRV | (9) | CMD | One or more of the following United States patents apply: 4,616,197; 4,610 | ||
| PRW | (1) | This single-pole, double-throw reflective switch consumes less than 50uA | |||
| PRX | (2) | Note 1: Absolute Maximum Ratings indicate limits beyond which damage to t | |||
| PRY | (1) | The intended application of these devices and signaling technique is bo | |||
| PRZ | (3) | The 74HC/HCT299 contain eight edge-triggered D-type flip-flops and the | |||
| P-S | (1) | SMD | JAT | 05+ | conversion efficiency. Additional features include an integrated input |
| PS- | (120) | N/A | N/A | N/A | CLKA/CLKB (Pins 5, 16): Card Socket. The CLKA/CLKB pins should be connect |
| PS0 | (58) | BT | Initial issue. 1. Note 1 ( Program/Erase Characteristics) is added( page | ||
| PS1 | (260) | MITSUBIS | MODULE | N/A | When an external clock is desired, a clock pulse of ap- proximately 3V |
| PS2 | (1363) | NEC | SOP | During sleep mode the device is still supplied from the battery voltage. | |
| PS3 | (125) | SSOP16 | • 1.8V+0.1V/-0.1V Power Supply. • DLL circuitry for wide outp | ||
| PS4 | (82) | VICOR | N/A | • High electrical noise immunity • High switching capacity in | |
| PS5 | (59) | MICROCHIP | 8+ | The STTH5R06, which is using ST Turbo 2 600V technology, is specially s | |
| PS6 | (24) | BT | PLCC- | 07+ | Mix Lipofectamine™ 2000 gently before use, then dilute the appropria |
| PS7 | (427) | N/A | P&S | 04+ | 44 input lines: • 24 input lines carry the True and Complement of |
| PS8 | (71) | NEC | DIP8 | N/A | A proper value of feed forward capacitor parallel with R1 can impr |
| PS9 | (129) | NEC | 93+ | VBIAS (VCC, VBS) = 15V, VSS = COM and TA = 25C unless otherwise specified. | |
| PSA | (19) | AMIS | SOP-16P | 03+ | Supply voltage: VCC = 2.7 to 4.0 V, ICC = 28 mA @ VCC = 3.0 V Built-in L |
| PSB | (709) | SIEMENS | DIP20 | Note A: Characteristic data has been developed from actual products teste | |
| PSC | (248) | MINI | 08+ | The RC4700 maintains fully precise floating-point exceptions while | |
| PSD | (1359) | WSI | O7+ | The UCC384-ADJ can be programmed for any output voltage between C1.25 V a | |
| PSE | (9) | 2008 | The signal entering the DTMF detection circuitry is filtered by a notch fi | ||
| PSF | (7) | Infineon | 03/04+ | TQFP64 | The 3.3-volt device is fully accessible and data can be written and read |
| PSG | (15) | N/A | #N/A | 04+ | The ADE7756 is a high-accuracy electrical power measurement IC with a se |
| PSH | (12) | SOT-153 | Note that this is independent of the sampling rate, so undersampling does | ||
| PSI | (31) | MMC | QFP160 | Output Ripple and Noise Voltage (See Figures 3 and 10.): R | |
| PSJ | (3) | NOTE: EP circuits are designed to meet the DC specifications shown in the | |||
| PSK | (10) | AMI | PLCC-20 | 07+ | Full on-chip hardware support of semaphore signaling between ports Fully |
| PSL | (52) | N/A | P&S | 04+ | The AMS2907 series develops a 1.25V reference voltage between the outpu |
| PSM | (229) | Philips | 07+ | The IDT72T4088/72T4098/72T40108/72T40118 are exceptionally deep, | |
| PSN | (84) | TI | TQFP-M100P | 6+ | READ CYCLE tRCRead Cycle Time tAAAddress Access Time |
| PSO | (65) | 8702 | 05+ | In addition to high-power/low-power bias modes, the efficiency of the P | |
| PSP | (36) | MOTOROLA | 04+ | The value of Ki may also be slightly different at the extremes of the | |
| PSQ | (1) | This document is a general product description and is subject to change wi | |||
| PSR | (165) | SOP | The default power up state of the mode register is unspecified. The follow | ||
| PSS | (98) | N/A | Chilisin | 04+ | TI assumes no liability for applications assistance or customer product d |
| PST | (788) | MITSUMI | SOT-343 | 04+PB | Universal, 3 way terminals: push-on, wrap around or solder High therma |
| PSU | (7) | N/A | |||
| PSV | (19) | SMD | 96 | The Analog Ground terminal, pin 1, is shown internally connected to the | |
| PSW | (16) | N/A | P&S | 04+ | The HY638256 is a high-speed 32,768 x 8-bits CMOS static RAM fabricated us |
| PSX | (15) | N/A | N/A | N/A | DYNAMIC PERFORMANCE Maximum Output Update Rate (fDAC) Output |
| PSY | (1) | N/A | QFP | 99+ | 5. The DAA Module is a sensitive subsystem that should be treated |
| PSZ | (4) | SIEMENS | 72 | Notes: 1. For Max. or Min. conditions, use appropriate value specified u | |
| P-T | (1) | INFINEON | 2008 | Maximum ratings are those values beyond which device damage can occur. M | |
| PT- | (43) | HT | SOP20 | N/A | Minimum time between read command (i.e. a write to Communication Registe |
| PT0 | (108) | OMRON | Relay(DZ) | 27Y1+ | The FMS6346 provides an internal diode clamp to support AC- coupled inpu |
| PT1 | (222) | NIEC | SOP | Maxim pioneered the use of charge-pump DC/DC converters for RS-232 interf | |
| PT2 | (583) | PTC | O7+ | The IDT72V205/72V215/72V225/72V235/72V245 are functionally com- p | |
| PT3 | (130) | TI | 07+ | Oscillator Pin. If a single-ended reference is used (such as a TCXO), it | |
| PT4 | (411) | TI | 07+ | These are stress ratings. Exposure of devices to any of these conditions | |
| PT5 | (388) | NIEC | SOP | The 74HC/HCT299 contain eight edge-triggered D-type flip-flops and the | |
| PT6 | (716) | TI | 07+ | The power switch is an N-channel MOSFET with a maximum on-state resistanc | |
| PT7 | (455) | NIEC | N/A | A key feature of the P89LV51RB2/RC2/RD2 is its X2 mode option. The design | |
| PT8 | (246) | 94 | wide variety of external capacitors, and the compact SOT23-5 surface-mou | ||
| PT9 | (45) | ASI | • High Resolution Color or Monochrome Raster Graphics Displ | ||
| PTA | (19) | SOP | These transceivers typically draw 910µA of supply current when unlo | ||
| PTB | (170) | high-frequency tube | ERICSSON | 04+ | The SM320C3x internal busing and special digital-signal-processing instru |
| PTC | (110) | TI | TQFP80-1212 | ||
| PTD | (22) | PHILIPS | 08+ | Note 1: Absolute maximum ratings indicate limits beyond which damage to t | |
| PTE | (24) | ERICSSON | 高频管 | N/A | 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATIN |
| PTF | (280) | ERICSSON | 高频管 | 06+ | B. Panasonic is endeavoring to continually improve the quality and reliab |
| PTG | (9) | MURATA | The CS5381 uses a 5th-order, multi-bit delta-sigma modulator followed by | ||
| PTH | (378) | TI | 07+ | Recovery time required when the device goes from power-down mode into byp | |
| PTI | (9) | TI | 04+ | Initial issue. 1. Note 1 ( Program/Erase Characteristics) is added( page | |
| PTJ | (4) | SII | 03+ | TSOP | NOTES 1Stresses above those listed under Absolute Maximum Ratings may ca |
| PTK | (50) | DIP28 | 98 | When reading data via the COUT pin and isolation resistor, the DQ line is | |
| PTL | (111) | 0 | 0 | Note 2: Absolute maximum ratings are those values beyond which damage to | |
| PTM | (78) | TI | 07+ | Two fully-programmable operation modes, Mode0 and Mode1, allow fast switc | |
| PTN | (150) | N/A | The Intersil ICL32XXE devices are 3.0V to 5.5V powered RS-232 transmitte | ||
| PTO | (1) | FOQ | SOP | 611 | † Component qualification in accordance with JEDEC and industry &n |
| PTP | (20) | N/A | N/A | N/A | Notes: 7. The luminous intensity, I V, is measured at the peak of the sp |
| PTQ | (10) | TI | 07+ | The ADSP-21991 provides 40K words of on-chip SRAM memory. This memory is | |
| PTR | (29) | NORDIC | 05+/06+ | 模块 | This PHY was designed from the start with the ULPI interface. No UTMI to |
| PTS | (84) | ITT | SOP | Stresses above those listed under Absolute Maximum Ratings may cause per | |
| PTT | (4) | ZETEX | 06+ | DESCRIPTION The PTT2907A-T1 is a silicon epitaxial-base NPN power trans | |
| PTV | (52) | TI | 07+ | After a program or erase cycle has been com- pleted, or after assertion | |
| PTW | (53) | TI | 1650 | RJC Thermal Resistance (Output Switches)1.5C/W RJC Thermal Resistance (Re | |
| PTX | (8) | FOQ | N/A | Hynix HYMD132G725B(L)8M-M/K/H/L series incorporates SPD(serial presence de | |
| PTZ | (159) | ROHM | 1W-3.9V | 05+NOPB | • Asynchronous loading of control parameters • Rapid (25ns p |
| PU- | (1) | 0 | 0 | OSCILLATOR The UC3823A,B/3825A,B oscillator is a saw tooth. The rising | |
| PU0 | (2) | 99+ | Crystals can be made to resonate either at the fundamental frequency, o | ||
| PU1 | (13) | 6+ | Sirenza Microdevices SBB-1089 is a high performance InGaP HBT MMIC amplif | ||
| PU2 | (9) | TI | SOP-16 | Absolute maximum ratings indicate sustained limits beyond which damage to | |
| PU3 | (18) | SIP | Notes: 1. NC pins are not connected to the die. 2. E3 (DNU) | ||
| PU4 | (56) | SIP | Conexant products are not intended for use in medical, life saving or lif | ||
| PU5 | (16) | N/A | N/A | N/A | This is not an extensive capacitor list. Capacitors from other ve |
| PU6 | (9) | MATSUSHITA | N/A | Ordering Information A complete part number is represented by the digits | |
| PU7 | (7) | SG | 02+ | Note 2: Absolute maximum ratings are those values beyond which damage to | |
| PU9 | (5) | TI | QFP48 | 02+ | (4) Losses that occur during charge transfer (from the co |
| PUA | (33) | 06+ | VCC = 5V ; VPLUSD = 0V (unless otherwise specified). ADC performances are | ||
| PUB | (4) | SIP | The CD74AC174 and ACT174 are hex D flip-flops with reset tha | ||
| PUC | (8) | MICRONAS | |||
| PUD | (7) | NEC | 93 | The UC385 allows for Kelvin sensing the voltage at the load. This improve | |
| PUI | (1) | This axial-lead components packaging requirements use in automatic testing | |||
| PUL | (5) | 1000 | TI | Antiparallel diode for high frequency switching devices Anti saturatio | |
| PUM | (159) | PHI | SOT-363 | Use of the above model permits junction to lead thermal resistanc | |
| PUN | (3) | 0 | 0 | Switching behavior is most easily modeled and predicted by recogn | |
| PUP | (5) | PHILIPS | 2008 | • A single chip solution integrates 100/10 Base-T fast Ethe | |
| PUR | (5) | 2004PB | Margin Down: When this input is asserted to GND, the output voltage is de | ||
| PUS | (6) | TI | TSOP16 | 2007+ | The bq2000 is a programmable, monolithic IC for fast-charge manage- ment |
| PUT | (2) | N/A | puts are controlled by an Output Enable (OEn) input. When OEn is LOW, th | ||
| PV. | (3) | N/A | The Hynix HYM71V8M655HG(L)T6 Series are 8Mx64bits Synchronous DRAM Modules | ||
| PV0 | (10) | N/A | SOP-28 | 2. The inhibit control input is Not compatible with TTL devices | |
| PV1 | (40) | DIP | 94/95 | A heatsink underneath the area of the PCB for the mounted device is str | |
| PV2 | (10) | 00+ | PV | 200 | Up to 10MHz Center Frequency on a Single 3V Supply Easy to UseA Single R |
| PV3 | (62) | MURATA | Pericom Semiconductors PI3V512 is a true bi-directional 5-Port 2: 1 mul | ||
| PV4 | (4) | QFN | 6+ | SDRAM read and write accesses are burst oriented starting at a selected | |
| PV5 | (12) | N/A | N/A | N/A | 8.5 V Supply Voltage Voltage Regulator for Stable Operating Conditions M |
| PV6 | (3) | Panasnoic | N/A | Used as input or output fuses for surge-sensitive compo- nents, such as | |
| PV8 | (8) | 98+ | QFP | Very Low VIN(MIN): 1.5V True Current Mode Control 5V Drive for N-Channel | |
| PV9 | (1) | KEKO | |||
| PVA | (102) | IR | Requiring 15V (or 12V) and +5V supplies, the ADS-929 typically dissipat | ||
| PVB | (5) | TIGER | 197 | The Hitachi HM51(S)4260C is CMOS dynamic RAM organized as 262,144-word 1 | |
| PVC | (36) | NIEC | N/A | Direct Stream Digital (DSD) C Dedicated DSD Input Pins C On-Chip 50 kHz | |
| PVD | (44) | 495 | IR | 95+ | Updated part listing on first page and in Table A. Table AAdded 266 MHz |
| PVG | (66) | PARADISE | PLCC | 05+ | The DAC module can be plugged into the TMC2068P7C decoder demonstration |
| PVH | (3) | MURATA | 3*4 20P | The DAC5687 is a dual-channel 16-bit high-speed digital-to-analog conve | |
| PVI | (50) | PAIRGAIN | QFP | 03+/04+ | |
| PVL | (1) | The PVL34VR177.76MHZ includes a PCI bus interface and a codec. It also in | |||
| PVM | (26) | MURATA | 05+ | PROPAGATION DELAY TIME: tPD = 40ns (TYP.) at VDD = 10V CL = 50pF HIGH | |
| PVN | (17) | IR | DIP-6 | 99+ | The demo boards are designed to verify different features easily and qu |
| PVO | (2) | IOR | SOP8 | 07+ | To blink LEDs at periods greater than 1.6 second the bus master (MCU, MP |
| PVP | (8) | MICRONAS | The Hynix HYM76V16735HGT8 Series are 16Mx72bits ECC Synchronous DRAM Modul | ||
| PVR | (14) | 114 | IR | 01+ | There are two methods of putting this device into a low power con |
| PVS | (14) | MURATA | Whatever crossover current that might occur in the low-power drivers is | ||
| PVT | (53) | IR | SMD | 0035+ | Note 1: Absolute Maximum Ratings are those values beyond which the life o |
| PVU | (6) | IR | 07+ | Sending the WREN op-code causes the internal Write Enable Latch to be s | |
| PVW | (1) | 2.1 General. The documents listed in this section are specified in | |||
| PVX | (3) | IR | 07+ | The CD54AC573/3A and CD54ACT573/3A are octal trans- parent three-state | |
| PVY | (3) | IR | 07+ | MAXIMUM RATINGS ItemSymbolRating Power DissipationPDC150 | |
| PVZ | (114) | MURATA | 04+ | The TMS4x100 and TMS4x100P are offered in a 20- / 26-lead plastic surface | |
| PW- | (12) | IR | 07+ | * 1.1 Scope. This specification covers the performance requirements for a | |
| PW0 | (4) | N/A | N/A | N/A | The DS1330 devices execute a read cycle whenever WE (Write Enable) is inac |
| PW1 | (167) | 96 | PIXELWORKS | O4+ | (with high values of IS, suitable for zero bias applications) are realize |
| PW2 | (50) | MT | BGA | 04+ | ALU AND CPU REGISTERS The ALU can do an 8-bit addition subtraction logic |
| PW3 | (52) | PIXELWORKS | BGA | 05+ | Hynix HYMD232M726A(L)8-J/M/K/H/L series incorporates SPD(serial presence |
| PW4 | (14) | IR | 08+ | SUMMARY DESCRIPTION The M41ST85Y/W Serial TIMEKEEPER®/Con- troller | |
| PW5 | (14) | BGA | 05+ | The EL6839 is a high performance, dual output, laser driv | |
| PW6 | (3) | MT | BGA | 0 | Many electronic appliances use a transient voltage suppressor (TVS) for o |
| PW7 | (3) | TSOP | 07+/08+ | SDRAM read and write accesses are burst oriented starting at a selected | |
| PW8 | (6) | 3-wire serial digital data link requires few I/O pins Analog input trac | |||
| PW9 | (17) | QFP | 0 | Controlled slew rate reduces EMI Over temperature protection Over curr | |
| PWA | (3) | SANREX | N/A | The Generation V of Add-A-pak module combine the excellent thermal perfor | |
| PWB | (28) | H = HIGH Level (steady state), L = LOW Level (steady state) X = Irrelev | |||
| PWC | (14) | ERICSSON | All voltages are referenced to ground. STBY specified for VCC equal to 3. | ||
| PWD | (4) | The RC5051 oscillator section uses a fixed current capacitor charg | |||
| PWF | (1) | Hynix HYMD512G726(L)8-K/H/L series is registered 184-pin double data rate | |||
| PWG | (1) | AMIS | There are two limitations on the power handling ability of a tran | ||
| PWH | (5) | JAPAN | The HS-1135RH is a radiation hardened, high speed, low power current fe | ||
| PWI | (5) | The ABT16543 16-bit registered transceivers contain two sets of D-type | |||
| PWJ | (1) | The 240xA generation offers an array of memory sizes and different periph | |||
| PWK | (1) | Computer-Operating Properly (COP) watchdog timer External interrupts vi | |||
| PWL | (5) | TI | BGA | 03+ | TRADEMARK ACKNOWLEDGMENT The LSI Logic logo design is a registered trad |
| PWM | (17) | FDK | N/A | Automatic backup and write protection of an external SRAM is provided thr | |
| PWN | (1) | The device integrates complete interfaces to stereo or mono microphones a | |||
| PWP | (1) | BB | DIP-8 | 03+ | High Efficiency Operation (No Sense Resistor Required) Wide Input Voltag |
| PWR | (123) | Module | BB | 93+ | The MAX2531 multiband LNA/Mixer IC is optimized for CDMA, GSM, and |
| PWS | (15) | BB | DIP | 04+ | Margin Down: When this input is asserted to GND, the output voltage is de |
| PWV | (3) | Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS | |||
| PWX | (2) | PHI | BGA | 2005 | INTERFACE TIMING CHARACTERISTICS Applies to All Parts6, 11 Input |
| PWY | (1) | • Viewing Angles Match Traffic Management Sign Requi | |||
| PX- | (9) | LOGISYS | 95 | The ADM2486 driver has an active-high enable feature. The driver differe | |
| PX0 | (119) | CIRRUS LOGIC | MQFP100 | 1995 | The incoming analog signal appearing between TIP and RING is presented at |
| PX1 | (23) | 03 | The circuit will remain in synchronization as long as the input frequency | ||
| PX2 | (8) | SOP | 05+ | 4.4.2 Group B inspection. Group B inspection shall be conducted in | |
| PX3 | (16) | 0 | 0 | The microphone input transfers its signal to the on-chip preamplifier. An | |
| PX4 | (2) | prolink | QFP | 97 | The clock input is fully differential to be compatible with DRAM devices |
| PX5 | (2) | N/A | SOP- 8 | ISOLATION Voltage Rated Continuous ISO120: AC 60HzTMIN to TMAX | |
| PX6 | (1) | The transmitter section of the PI90SD1636A accepts 10-bit wide parallel | |||
| PX7 | (3) | KANEKO | QFP/120 | 00+ | Deadtime High-Current Totem-Pole Dual Output Stage Drives Push-Pull Conf |
| PX8 | (3) | QFP120 | Internal filters in all HR300 converters provide low noise on both the i | ||
| PX9 | (1) | The Preliminary Information presented herein represents a product in prot | |||
| PXA | (174) | NCC | SMD | 4 | Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are e |
| PXB | (57) | Infineon | Data on the A or B data bus, or both, can be stored in the inter- nal D | ||
| PXC | (2) | The three GRID outputs are gated by the GREN input. When GREN is | |||
| PXD | (1) | DESCRIPTION The PXD301/050/01/1 is manufactured in a hybrid structure, u | |||
| PXF | (19) | INFINEON | SOP | 524 | The FPD-Link receiver supports graphics controllers with Spread Spectrum |
| PXG | (3) | NEC | QFP- | 07+/08+ | SINGLE 5V10% SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS AC |
| PXH | (1) | TI | 07+ | Steering Input/Guard time (Output) Bidirectional. A voltage greater than | |
| PXI | (1) | TI | BGA | 04+ | Note: 1. Except for the rating "Operating Temperature Range", s |
| PXL | (3) | PIXEL WORKS | 04+ | BGA3535 | Serial data input A/B. The serial information (data) received from seria |
| PXO | (11) | TI | QFP | 95+ | 1. H = HIGH voltage level L = LOW voltage level X = dont |
| PXP | (4) | CMD | SOP-8 | 97+ | Description The HSMx-C177 and HSMx-C197 ChipLEDs are designed specific |
| PXR | (29) | CMD | 06+ | • CMOS Process Technology • 1M x 16 bit Organization • | |
| PXS | (1) | For applications requiring zero input-output delay, all outputs including | |||
| PXT | (43) | PHI | 08+PBF | the related gate drive output pin high. A logic low input on one of the s | |
| PXU | (1) | These miniature surface mount MOSFETs low RDS(on) assure minimal | |||
| PXV | (2) | N/A | N/A | Low voltage noise density of 2.1nV/Hz and -88dBc spurious-free dynamic ra | |
| PXX | (1) | The V62C51864 is a 65,536-bit static random access memory organi | |||
| PY. | (1) | N/A | SMD | 98+ | FEATURES 5 V Stereo Audio System with 3.3 V Tolerant Digital Int |
| PY0 | (4) | OMRON | Relay(DZ) | 2597+ | The SDA pin is bidirectional for serial data transfer. This pin is open-d |
| PY1 | (34) | STANLEY | The LVC11A triple 3-input AND gate is built using advanced dual me | ||
| PY2 | (51) | DSI | n/a | Note 1: The power rating is based on a printed circuit board heat spreadi | |
| PY3 | (8) | MOTO | 97 | Fast transient response Available in Adjustable, 1.5V, and 3.3V version | |
| PY4 | (1) | The voltage range of the CPU has shown a downwards trend for the past 5 | |||
| PY5 | (1) | MOT | stream and 24 Mbps downstream. This device is ide- al for power and are | ||
| PY6 | (5) | The NCS2002 is an industry first sub−one volt operational am | |||
| PY7 | (6) | PANASONIC | 8917N | The HYM72V32656AT8 Series are Dual In-line Memory Modules suitable | |
| PY8 | (3) | Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital | |||
| PY9 | (8) | MOT | QFN | 95+ | 1-5ms Power Good (PG) control signal Regulated 1.2V output 150mA outpu |
| PYC | (11) | RIVER | Adjustable/1.5 V Dual Voltage Detector (TPS3805): Adjustable/3.3 V High | ||
| PYF | (21) | OMRON | Relay(DZ) | 20X3Y7+ | The ADXL278 is the fourth-generation surface micromachined iMEMS® ac |
| PYN | (1) | PHI | PLCC28 | 2007+ | 2. Chip operation is not guaranteed after access to any of the reserved d |
| PYO | (1) | QFP | 97+ | Meet or Exceed the Requirements of TIA/EIA-232-F and ITU Recommendation | |
| PYS | (1) | are selected in the First Word Fall Through mode. IR indicates whether or | |||
| PYT | (4) | 爱立信 | SOP | 05+ | The EP7311 uses its powerful 32-bit RISC processing engine to implement |
| PZ- | (1) | The 329C/W for the SC-74 package assumes the use of the recommend | |||
| PZ1 | (2) | BGA | 02+ | Description Receiver Negative Bipolar Input. Line analog input. Receive | |
| PZ2 | (3) | PC Power Supply Outputs Supervisory Circuitry Few External Components | |||
| PZ3 | (72) | PHI | PQFP44 | 06+ | Organization . . . 512K 16 2 Banks 3.3-V Power Supply ( 10% Tolerance) |
| PZ4 | (9) | FOX | 07+ | Applying a LOW to the INIT input causes an immediate load of the program | |
| PZ5 | (61) | PHILIPS | QFP-44 | • FCRAM core with Single Data Rate SDRAM interface • | |
| PZ6 | (2) | A/N | DIP | The ISSI 4400 Series is a 4,194,304 x 4-bit high-performance CMOS Dynami | |
| PZ7 | (1) | The ABT162244 contains sixteen non-inverting buffers with 3-STATE output | |||
| PZA | (5) | PHILIPS | PLL3 generates a frequency that is equal to the reference divided by an 8 | ||
| PZB | (10) | INFINEON | MP-144 | 06+ | Using the Schottky Barrier principle with a Molybdenum barrier metal. Thes |
| PZC | (6) | IL5 through IL0 are available on the TP3070. IL4 through IL0 are availa | |||
| PZD | (1) | The PZD33B is an optically integrated circuit detector with schmi | |||
| PZE | (2) | nRF902 is a single-chip transmitter for the 868 MHz ISM band, designed to | |||
| PZF | (4) | INFINEON | MP-144 | 06+ | Surface mount equivalents to the JEDEC registered 1N5221 thru 1N5281B ser |
| PZH | (3) | Data is read from the HY29F040A by using stan- dard microprocessor read | |||
| PZI | (1) | An ideal (lossless) capacitive voltage doubler, unregulated, produces 6.6 | |||
| PZM | (159) | PHILIPS | 23 | time exhibits drift characteristics of the best low-drift amplifi- ers T | |
| PZP | (1) | 05+ | Figure 1 shows a typical battery pack application of the bq2050 using the | ||
| PZT | (139) | FAIRCHILD | 04+ | The CM3004 is a very-low-dropout regulator that offers both fixed outpu | |
| PZU | (10) | PHILIPS | 0805-8.2V | 07NOPB | The RESET (SVS, POR, or power on reset) output of the TPS752xx initiates |
| PZV | (1) | 1394b-2002 at S100B Signaling Rates Provides One Transceiver to Drive IEE | |||
| PZX | (2) | PHILIPS | SOT223 | The accuracy of a successive approximation A/D converter is described by |
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