| Mfg | pack | D/C | Descrpion | ||
| Q.O | (1) | The COP8TAB9/TAC9 Flash microcontrollers are highly in- tegrated COP8&# | |||
| Q00 | (13) | PHI | DIP | Tiny SOT−353 and SOT−553 Packages 2.7 ns TPD at 5 V (typ) So | |
| Q01 | (5) | FAI | DIP8 | 08+ | Note 9: I1 and I2 are the external sink currents at the inputs (refer to |
| Q02 | (8) | MIC | Input Channels 0-3 PECL/ECL differential signal inputs. Multiplexing of t | ||
| Q03 | (1) | • Only 35 instructions to learn - All single cycle instructi | |||
| Q07 | (1) | N/A | QFP-32 | The SC5388 is a 2-channel digital preset equalizer utilizing CMOS | |
| Q08 | (7) | FLT | 芯片 | The amplifier works on any total power supply voltage between 2.7V and 36 | |
| Q0A | (1) | To maximize I/O throughput and improve host and SCSI bus utilizat | |||
| Q0M | (1) | jauch | jauch | dc02 | One master and as many slaves as necessary may be connected in parallel t |
| Q-1 | (5) | Pulse | SOP | 01+ | The CMX866 shares internal register addresses and structure with the CMX86 |
| Q1- | (1) | LT | 管 | Changes throughout document including the following chapters and/or secti | |
| Q10 | (29) | SDRAM read and write accesses are burst oriented starting at a selected | |||
| Q11 | (7) | N/A | SOP | 00+ | Reset and Idle Upon power-up and between Read and Erase/Write instruc- |
| Q12 | (4) | FUJITSU | In typical cellular phone architectures, the transmit filter fits betwee | ||
| Q13 | (26) | AMCC | PGA | ||
| Q14 | (5) | AMCC | PLCC | 07+ | The Detection Integrator can also be viewed as a 'consensus' filter, tha |
| Q15 | (10) | PRX | 2008+ | Figure 1 shows the proper connection of the VRE114 series voltage | |
| Q16 | (6) | is described in the AT&T publication TR 54016 (Re- quirements for I | |||
| Q17 | (1) | nVIDIA | O7+ | The TPS752xx or the TPS754xx are offered in 1.5-V, 1.8-V, 2.5-V, and 3.3- | |
| Q18 | (6) | jauch | jauch | dc04 | |
| Q19 | (10) | The oscilloscope traces, Figures 2 and 3, show the waveforms at Tx, Rx, | |||
| Q1A | (1) | The Intersil Q1A501025K00 contains 3.0V to 5.5V powered RS-232 transmitt | |||
| Q1L | (1) | Each arbitrary length of data packet consists of 3 portions viz, Row addre | |||
| Q1M | (2) | SHARP | Program Strobe Enable: The read strobe to external program memory. When | ||
| Q-2 | (1) | MHS | CLCC68 | 95+ | It is possible to choose from the four different modulation schemes: Bin |
| Q2- | (1) | LT | 管 | 1. Electronic Industrial Association of Japan. 2. Pulsed measurement, p | |
| Q20 | (154) | AMCC | 03+ | Note 4: The Absolute Maximum Ratings are those values beyond which the sa | |
| Q21 | (10) | amcc | PGA | © Atmel Corporation 2003. All rights reserved. Atmel ® and combin | |
| Q22 | (13) | QUALCOMM | PLCC | 00+ | ➀ Models are specified at "full load" (5V & 3. |
| Q23 | (20) | QUALCOMM | PLCC | Very high speed: 55 ns and 70 ns Voltage range: 1.65V to 1.95V Pin compa | |
| Q24 | (22) | QUALCOMM | PLCC | The HIP6601B drives the lower gate in a synchronous rectifier to 12V, w | |
| Q25 | (6) | AMCC | PGA | − Provide software confirmation of completion of program or | |
| Q26 | (1) | OCL or capacitively coupled outputs (patent pending) Exter | |||
| Q27 | (2) | Parameter Carrier Frequency Operating Voltage (VDD_MEM) Operati | |||
| Q28 | (1) | jauch | jauch | dc01 | Dual pins: OUTPUTA, OUTPUTB, PVDDA1 and PVDDB1 must have both pins connec |
| Q29 | (3) | jauch | jauch | dc05 | Pin Description Serial Data Address: This is a bi-directional data pin f |
| Q2D | (3) | Connecting the inhibit input (Pin 2) to input common (Pin 10) will cause | |||
| Q2E | (1) | RL/VL. The low (VL/RL) terminals of the X9C102/103/104/503 are equivalent | |||
| Q2H | (2) | Devices range in size from 5,000 to 50,000 usable gates in the family, an | |||
| Q2N | (5) | LF(TEC) | DO-214 | 06+ | Notes: 5. Distribution data sample size is 500 samples taken from 5 diffe |
| Q2O | (1) | 0 | 0 | Clocking of the register is very flexible. Four global synchronous cloc | |
| Q2S | (2) | Operating Temperature: - 55C to + 85C. (To + 125C with voltage derating. | |||
| Q2T | (5) | Texas | 79 | Dual Gate Inverter Oscillator Circuit The LED oscillator circuit, | |
| Q2X | (8) | LF(TEC) | DO-214 | 06+ | In addition to the standard output configuration, the outputs of the is |
| Q3- | (2) | LT | 管 | The IP4001S has a thermal protection against the abnormal operation. When | |
| Q30 | (10) | Write Operation All writes begin with a device address, then a memory a | |||
| Q31 | (2) | 08+ | The MAX1973/MAX1974 are constant-frequency 1.4MHz pulse-width-modulated ( | ||
| Q32 | (24) | QUALCOMM | PLCC44 | 07+ | The Q32161-16NP uses VDD and GND to set the output range of the DAC. Th |
| Q33 | (12) | NA | SOP | 02+ | The load can see a voltage spike of up to 1 µs, the amount of time |
| Q34 | (8) | ST | SOP-16 | 06+ | Notes: 5. CX1 must be placed within 0.7 cm of the HSDL-3600 to obtain op |
| Q35 | (12) | AMCC | 07+ | NOTES: 1. All VDD pins must be connected to 3.3V power supply. 2. All VD | |
| Q36 | (3) | high-frequency tube | HP | 04+ | TOSHIBA is continually working to improve the quality and reliability of |
| Q37 | (4) | MOT | SOP8现货 | ||
| Q38 | (2) | EPSON | 07+ | The serializer enters the high-impedance mode when the DEN pin is driven | |
| Q3A | (1) | LT | 管 | The ISD MicroTAD-16M interrupt pin goes LOW and stays LOW when an Overfl | |
| Q3G | (2) | 1. If lead-bearing terminal plating is required, please contact your Diode | |||
| Q3M | (2) | jauch | jauch | dc02 | The SPI interface can communicate at a maximum of 5Mbps data rate with a |
| Q3V | (1) | IDT | 0 | tLOW Low Period of SCL Clock tHIGH High Period of SCL Clock tSU;STA Setu | |
| Q4- | (1) | LT | 管 | Transmitter Input Reference Voltage. This output biases to VCC-1.3V. It is | |
| Q40 | (109) | LF(TEC) | TO-220 | 06+ | The CY7C63xxx is a family of 8-bit RISC One Time Programmable (OTP) micro |
| Q41 | (4) | COILCRAFT | 04+ | The AC/ACT258 is a quad 2-input multiplexer with TRI-STATE outputs. Fou | |
| Q43 | (2) | *1 If the switching voltage exceeds the rated contact voltage, reduce the | |||
| Q44 | (3) | UALCOMM | PQFP | Areas where care in design must be observed are thermal ground, RF groun | |
| Q45 | (4) | FSC | 05+ | DIP-6 | • Meets or Exceeds the Requirements of ANSI TIA/EIA-644-199 |
| Q46 | (1) | A problem arises in a CPE where the CAS detector is connected only to the | |||
| Q47 | (11) | QTC | 05+ | SOP-8 | The SL531 transfer characteristic has two regions For small input |
| Q48 | (23) | Figure 33 provides the Motorola part numbering nomenclature for the MPC82 | |||
| Q49 | (4) | Both potentiometers can be connected in series (or stacked) for an increas | |||
| Q4N | (6) | LF(TEC) | DO-214 | 06+ | SWITCHING PERFORMANCE Maximum Conversion Rate Minimum Conver |
| Q4X | (8) | LITTELFUSE | SOP | 05+ | *1 : Under development *2 : If the one clock system is used, equip X0A |
| Q5- | (1) | LT | 管 | The MAX6672/MAX6673 are low-current temperature sensors with a single-wir | |
| Q50 | (52) | AMCC | . | High quality picture representation with RGB delta arranged color filters | |
| Q51 | (59) | N/A | QFP | N/A | Bus timing data is shown in Figure 4 and Figure 5. Data transfer may be i |
| Q52 | (16) | QUALOMM | QFP | 03/+04+ | The ZL30414 accepts a CMOS compatible reference at 19.44 MHz and generate |
| Q53 | (35) | TTL/CMOS input select control signal for the LVDS LOUT0-LOUT2 outputs. LSE | |||
| Q54 | (6) | For applications requiring powerful I/O capabilities, the Z86C83/C84 de | |||
| Q55 | (28) | QS | 07+ | An analog to digital (A/D) conversion can be accomplished with ei | |
| Q56 | (15) | N/A | SMD | 2000 | • Solid-state Relay (Equivalent to AQW210S) - Typical RON 2 |
| Q57 | (2) | Parameter REFERENCE INPUTS REFIN(+) to REFIN(C) Voltage1, 9 &nbs | |||
| Q58 | (5) | N/A | QFP-100 | The digital visual interface (DVI) specification is an industry standard | |
| Q59 | (6) | PHIL | QFP | The 160 product terms are grouped in 32 sets of five and sent into a Pr | |
| Q5A | (1) | LT | 管 | These modes are entered by placing a high voltage VPP on pin 19, with pin | |
| Q5E | (2) | 2007 | |||
| Q5L | (1) | The Q5L107010M00 is GaAlAs infrared emitting diode that is design | |||
| Q5R | (1) | In contrast to the direction switches, the hazard input is a low-side typ | |||
| Q-6 | (1) | The frequency characteristic for the phase locked loop is established by | |||
| Q6- | (1) | LT | 管 | • Internal self-timed write cycle • Individual Byte Write C | |
| Q60 | (123) | TECCOR | . | N/A | Internal registers include available capacity, temperature, scaled avail- |
| Q61 | (3) | NORTEL | QFP2828-160 | 02+ | Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7 |
| Q62 | (183) | OSRAM | 01+ | The 25-40 watts PKA 2000 series hybrid DC/DC power modules are especially | |
| Q63 | (12) | s+m | s+m | dc97 | Note 8: CIN, COUT, C1, and C2 : Low-ESR Surface-Mount Ceramic Capacitors |
| Q65 | (3) | osram | osram | dc05+ | 16-bit multi-function timer supporting PWM mode External e |
| Q67 | (23) | INFINEON | 01+ | Muting all channel drivers can be obtained using the REF (signal referenc | |
| Q68 | (19) | Ifinieon | SOT23 | 04+ | 1) CPD is defined as the value of the ICs internal equivalent capacitance |
| Q69 | (76) | s+m | s+m | dc95 | Capacitor Table Table 1-1 identifies the characteristics of capacitors f |
| Q6A | (1) | LT | 管 | In the chip there is a block "Power On Reset" (POR), which trac | |
| Q6M | (1) | jauch | jauch | dc00 | The digital blocks can be connected to any GPIO through a series of glo |
| Q6N | (8) | LF(TEC) | DO-214 | 06+ | USB Hub -1 Upstream and up to 4 Downstream Ports -Compliant with USB Spe |
| Q6X | (8) | LF(TEC) | DO-214 | 06+ | One independent programmable bi-level 1D-resolution conversion block is |
| Q70 | (23) | 2000 | PHILIPS | 03+ | The ERASE instruction erases data at the specified addresses in the progr |
| Q71 | (3) | AMCC | DIP | 97+ | DESCRIPTION The HCF4098B is a monolithic integrated circuit fabricated |
| Q72 | (1) | MXIC | The Q7286-18012 provides high security, low cost, and ease of implementat | ||
| Q73 | (1) | INTEL | Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V | ||
| Q74 | (4) | TQFP-96 | Thermal Resistance, Junction-to-Case - IGBT Thermal Resistance, Junctio | ||
| Q75 | (2) | 2000 | PHILIPS | 04+ | The APA2020A also served well in low-voltage applications , which provide |
| Q77 | (3) | 2000 | PHILIPS | 01+ | Collector-Emitter Cutoff Current VCE = 50 Vdc VCE = 75 Vdc |
| Q79 | (1) | Drain-Source Voltage Gate-to-Source Voltage Continuous Drain Cur | |||
| Q7M | (1) | jauch | jauch | dc05 | • 2 0.7 amp. full bridge outputs • Integrated driver, cont |
| Q80 | (75) | LF(TEC) | TO-252 | 06+ | Normally the signal source for the LM1881 is assumed to be clean and re |
| Q81 | (10) | EPSON | 07+ | READ clock input with pull-high resistor. Data in the RAM of the HT1625 ar | |
| Q82 | (1) | Note 1: Absolute maximum ratings indicate limits beyond which damage to t | |||
| Q83 | (3) | 2000 | PHILIPS | 01+ | * On products compliant to MIL-PRF-38535, this parameter does not apply. |
| Q86 | (5) | N/A | N/A | N/A | The HX1000 is a miniature transmitter module that generates on-off keyed |
| Q88 | (1) | • Four-element contained in one package, allowing high-density &nbs | |||
| Q8E | (1) | PLCC | 99+ | INPUT CAPACITOR To improve load transient response and noise reje | |
| Q-9 | (1) | QTRONIX | DIP-18 | 07+/08+ | Operation above maximum ratings may cause permanent damage to the device. |
| Q90 | (5) | high-frequency tube | HP | 04+ | The operation mode of the M5M51008C series are determined by a combinati |
| Q91 | (11) | AMCC | PGA | remains on until either the high-side switch turns on again or the induct | |
| Q92 | (1) | CURRENT LIMIT PROTECTION The LX8819 includes over current protect | |||
| Q93 | (9) | The HAL 805 is a recent member of the Micronas fam- ily of programmable | |||
| Q94 | (2) | The specified voltage (VS) applies for a dual () supply having eq | |||
| Q95 | (10) | N/A | CAI | ‡ Stresses beyond those listed under absolute maximum ratings may c | |
| Q96 | (4) | A single pulse is defined as being greater than 1 ms but lasting no lon | |||
| Q97 | (4) | STM | QFP-32 | 01+ | No Auxiliary Winding Operation Internal Output Short−Circuit Prote |
| Q98 | (71) | AGILENT | 2007 | The GS1117 is a low dropout three terminal regulator with 800mA output | |
| Q99 | (2) | NORTEL | QFP | 00+ | Low profile 0.047" [1.19mm] maximum thickness. Self s |
| QA- | (1) | NO | Hynix HYMD512726(L)8-K/H/L series incorporates SPD(serial presence detect) | ||
| QA0 | (3) | Furthermore, this circuit block compares the input signal to a threshold, | |||
| QA1 | (8) | N/A | PLCC | 2000 | DESCRIPTION These diode-transistor optocouplers use a ligh |
| QA4 | (2) | Note 1: Absolute Maximum Ratings are those values beyond which the life | |||
| QA6 | (1) | Notes: 1. TA = +25C, where TA is defined to be the temperature at the pac | |||
| QA8 | (2) | INTEL | CPGA68 | The HYS64D128020GBDL are industry standard 200-pin 8-byte Small Outline D | |
| QAA | (2) | N/A | N/A | 2003 | This active low-control input transfers the contents of the input registe |
| QAB | (3) | FAROUDJA | The HYM72V12C736B(L)S4 Series are Dual In-line Memory Modules suitable for | ||
| QAC | (1) | This applies to SAA7120 only. The device is protected by USA patent num | |||
| QAD | (1) | Hynix HYMD232M726A(L)8-J/M/K/H/L series is designed for high speed of up | |||
| QAE | (2) | SANREX | MODULE | The DAC101S101 is a direct replacement for the AD5310 and is one of a f | |
| QAH | (5) | 96 | SOP | DESCRIPTION The Device is a monolithic integrated high volt- age, high | |
| QAL | (1) | Maximum Ratings are those values beyond which damage to the device may oc | |||
| QAM | (8) | TIM | The initialization and resynchronization methods described in their res | ||
| QAN | (6) | QUALITY | SSOP | 2002 | The QAN030A is a monolithic driver for controlling air-core (or differen |
| QAP | (1) | Available in the Texas Instruments NanoStar™ and NanoFree™ Pa | |||
| QAR | (3) | 99 | The ISA-HUB-Kit is designed to serve as a repeater application example | ||
| QAS | (6) | Description Clock output from VCO. Output frequency equals the input fre | |||
| QAT | (3) | POWER-ONE | N/A | In-band Interference Rejection 20dB max. 2103dBm Sensitivit | |
| QAX | (2) | External compensation is only necessary at gains of 30v/v or less | |||
| Q-B | (1) | ||||
| QB- | (7) | ||||
| QB0 | (1) | Sleep Mode The MX841 goes into sleep mode when the VCTRL input is less t | |||
| QB1 | (2) | 1850 | 1. Product of input modulation f1 at 4.43MHz p-p deviation and f2 at 6MHz | ||
| QB3 | (1) | N/A | 3. All devices are guaranteed to trigger at an IF value less than or equa | ||
| QB4 | (4) | Electrical Characteristics: Unless otherwise specified, all limits are est | |||
| QB5 | (3) | IPD | N/A | The L-Series of DC/DC converters are radiation toler- ant, high reliabi | |
| QB6 | (1) | INTER | SOP-16 | 03+ | The HYS64/72D32000GU and HYS64/72D64020GU are industry standard 184-pin 8 |
| QB7 | (8) | fsc | fsc | dc73+ | Depending on the four address inputs, the 4-to-14 line decoder se |
| QB8 | (2) | INTEL | SOP | 00+ | The PCA9544A is a quad bidirectional translating switch controlled via th |
| QBA | (10) | MINI | 08+ | Chapter 4, "Control Registers," contains overview tables for all | |
| QBB | (5) | SanRex | SOP | Each QBB100A40 contains a unique ROM code that is 64 bits long. The first | |
| QBC | (1) | The software driver for PS700 was developed for a PIC® microcontroll | |||
| QBD | (1) | Optional accessories for module-type MCC 56 version 1 B Keyed gate/catho | |||
| QBH | (26) | CAN | 2. Chip operation is not guaranteed after access to any of the reserved d | ||
| QBK | (2) | SUMMARY DESCRIPTION The M68AW128ML is a 2 Mbit (2,097,152 bit) CMOS SRA | |||
| QBL | (1) | 98 | Fig55 | 07+ | The C6203 device program memory consists of two blocks, with a 256K-byte |
| QBM | (1) | • Array Format: 1,280H x 1,024 V (1,310,720 pixels) • Pixel | |||
| QBP | (1) | These edge-triggered multivibrators feature output pulse-duration contr | |||
| QBR | (5) | ASTEC | 50W | This material and the information herein is the property ofFuji Electric | |
| QBS | (23) | POWER-ONE | SOP | Wide frequency range 1.5 to 100MHz Wide fractional bandwidt | |
| QBT | (1) | N/A | When used with an optocoupler, the AT431 is ideal voltage reference in | ||
| QBU | (2) | ROHM | QFP | 2000 | The attached table of replies indicates that this DIS has been approved. |
| QBV | (7) | MOT | 08-6 | This calculation is based on typical operating conditions using a patter | |
| QBW | (3) | The 512K EPROM and OTP PROM are programmed using the TI SNAP! Pulse progr | |||
| QBY | (1) | Figure 4 shows the waveforms of the circuit of Figure 3. Note that the | |||
| QC0 | (15) | † Stresses beyond those listed under absolute maximum ratings may c | |||
| QC1 | (3) | AMCC | The out-of-band receiver in the QC100 contains a frequency agile oscilla | ||
| QC2 | (37) | AMCC | QFP | Unless otherwise stated, VDD = 3.3V 10%, no load on any output, and ambi | |
| QC4 | (1) | Signal isolation by transformer coupling uses a proprietary modulation t | |||
| QC6 | (2) | NOTE: Intersil Pb-free plus anneal products employ special Pb-free materia | |||
| QC7 | (2) | For NTSC applications without the peaking capacitor the rejection at 27M | |||
| QC8 | (3) | INTEL | N/A | This device can be used as four 8-bit transceivers, two 16-bit transceive | |
| QC9 | (2) | QC9099CD technology makes use of an important new variant of charge-trans | |||
| QCA | (85) | 1850 | In an application together with the Dolby Digital decoder MAS 3528E, ei | ||
| QCB | (16) | SanRex | SOP | A single sampling sequence is taken during every inter- rupt routine. T | |
| QCC | (2) | MINI | 08+ | Attenuation range: 0 to C79dB in 1dB steps Operating voltage: 4 to 9V Lo | |
| QCH | (1) | SANREX | 04+ | Unique test circuitry and reprogrammable cells allow complete AC, DC, an | |
| QCI | (5) | INTEL | PBGA | 06+ | Maximum ratings are those values beyond which device damage can occur. Ma |
| QCJ | (1) | /Power-Good Output 3: Open Collector. Asserted when the following is true | |||
| QCK | (4) | 仙童 | The HSDL-3610 is a low-profile infrared transceiver module that provid | ||
| QCM | (10) | 01+ | Agilent | 99 | Extended Data Out Mode capability Read-modify-write capability Multi-bit |
| QCN | (14) | MINI | 08+ | FEATURES l Multi quantum wells (MQW) DFB Laser Diode module l E | |
| QCP | (93) | AGILENT | QFN | 0446+ | Junction CapacitancepF Test Conditions: f = 1 GHz Video Resistancek͐ |
| QCR | (2) | DVANCE | stock | Conforms to JEDEC byte-wide standard Reliable CMOS with MNO | |
| QCT | (1) | AGILENT | 03+ | Both, the TLE 6250 G as well as the TLE 6250 C offer three different oper | |
| QCX | (4) | The Philips microcontrollers described in this data sheet are high-perfo | |||
| QCZ | (1) | Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V | |||
| QD- | (6) | MSC | The 40L..CW center tap Schottky rectifier has been optimized for very low | ||
| QD. | (1) | INTEL | CDIP40 | 2007+ | The LM236-2.5, LM336-2.5, and LM336B-2.5 integrated circuits are precis |
| QD/ | (1) | INTEL | CDIP40 | —— | Notes: 1. All dimensions are in millimeters (inches). 2. Tolerance is |
| QD0 | (1) | Transmit Input. Balanced differential line receiver inputs to the Transmi | |||
| QD1 | (5) | ST | The TSH330 is a current feedback operational amplifier using a very hig | ||
| QD2 | (92) | INTEL | CWDIP28 | —— | The LVTH18512 and LVTH182512 scan test devices with 18-bit universal bus |
| QD3 | (1) | SMD-8 | IDT | 00+ | STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions |
| QD4 | (3) | Note: Stresses greater than those listed under MAXIMUM RATINGS may cause | |||
| QD5 | (2) | INTEL | 00+ | BGA4242 | The GS82032A is an SCD (Single Cycle Deselect) pipelined synchronous SR |
| QD7 | (1) | BB | DIP渡金 | The TLE 6363 G is a multifunctional power supply circuit especially design | |
| QD8 | (80) | INTEL | CDIP40 | N/A | 3.1 POWER SUPPLY & VOLTAGE REFERENCE The internal regulator circuit |
| QDC | (1) | Agilent | PLCC | 00+ | CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic ch |
| QDE | (1) | high-frequency tube | MIT | 04+ | Industrial Standard SPI Pin-out 8 Mbits of Page-Erasable Flash Memory |
| QDF | (1) | Drain-to-Source Breakdown Voltage Gate Threshold Voltage ➃ | |||
| QDK | (1) | Logic supply Logic input for high side gate driver output (HO), in phase | |||
| QDP | (1) | N/A | SOP-14 | 96+ | for an overvoltage condition on unselected channels without dis- rupting |
| QDR | (2) | ASTEC | DC电源模块 | 2007+ | I2C uses a two-wire serial interface, comprising a bi-directional data |
| QDS | (58) | AGILENT | 0102+ | The Hynix QDSJ-F000 Series are Dual In-line Memory Modules suitable | |
| QDX | (1) | QDI | 06+ | QFP | These circuits perform a single function: they assert a reset signal when |
| QE- | (1) | NOTES: 1. Dimensions are in inches. 2. Metric equivalents ar | |||
| QE1 | (4) | FAIRCHILD | 05/06+ | • Frequency Output (SW Selectable: Off, 1Hz, 100Hz, or 32.76 | |
| QE2 | (1) | SEEQ | 陶DIP28 | † All typical values are at VCC = 12 V, TA = 25C. ‡ The alg | |
| QE4 | (2) | NA | P | BGA | KEY FEATURES ADSP-219x, 16-Bit, Fixed Point DSP Core with up to |
| QE7 | (1) | MOT | 99 | The device is entirely command set compatible with the JEDEC single-powe | |
| QE8 | (1) | IC | QFP | 0324+ | Address Latch Enable output for latching the low byte of the address dur |
| QEA | (1) | The AD1833A is fully compatible with all known DVD formats, accommodatin | |||
| QEB | (11) | FSC | T-3/4 | 08+ | |
| QEC | (10) | FAIRCHILD | 05/06+ | Caution: The BiCMOS inherent to the design of this component increases th | |
| QED | (118) | AGILENT | 2007 | The LTC®1981/LTC1982 are low-power, self-contained N-channel MOSFET d | |
| QEE | (6) | FS | 07+ | The isolation voltage is a galvanic isolation and is verified in an elect | |
| QEH | (2) | BVDSSDrain-to-Source Breakdown Voltage ∆BVDSS/∆TJ Temperatur | |||
| QEK | (1) | 03+ | The IRK.L240 Series of MAGN-A-paks uses fast re- covery power diodes in f | ||
| QEL | (1) | Loop Back Select. This input is used to select the input data stream sour | |||
| QEM | (1) | The HYM72V32756B(L)T8 Series are Dual In-line Memory Modules suitab | |||
| QEP | (2) | N/A | 00+ | PLCC44 | (e) For a dual device surface mounted on 85 sq cm single sided 2oz copper |
| QES | (14) | POWER-ONE | SOP | Two channels of EMI filtering Pi-style EMI filters in a capacitor-resis | |
| QET | (1) | Reading from the device is accomplished by taking Chip En- able (CE) an | |||
| QEX | (2) | The GS82032 is a 2,097,152-bit high performance synchronous SRAM with a | |||
| Q-F | (1) | • Fast I2C-bus controlled (max. 400 kHz) • PLL controlled soun | |||
| QF- | (1) | N/A | N/A | N/A | Figure 1 is a block diagram of the bq4847. The bq4847 is functionally equ |
| QF0 | (3) | The CPU provides fast instruction (up to 10 MHz clock speed) execution | |||
| QF1 | (5) | SANSHA | SOP | Supports a 33-MHz, 64-bit PCI host bus interface with a 264 MB/sec maxim | |
| QF2 | (3) | SANSHA | SOP | Resale of TI products or services with statements different from or beyon | |
| QF3 | (5) | SanRex | SOP | ADC data outputs are internally connected directly to the receivers digi | |
| QF4 | (3) | An QF4333JZHF bypass capacitor should be used on the Vdd input. A 100 pF | |||
| QF5 | (4) | SanRex | SOP | 2005+ | The IP4001S has a thermal protection against the abnormal operation. When |
| QF7 | (1) | SANREX | 04+ | only, and functional operation of the device at these or any other conditi | |
| QFB | (61) | AGILENT | OPTICAL FIBER HEAD | 03 | TI is not confident of the operation of the DLL in this product at this t |
| QFC | (7) | HP | 98 | Operating Range In the operating range the functions given in the circui | |
| QFE | (11) | 1 | In addition to high integration, the CS8920A offers a broad range of pe | ||
| QFF | (12) | The user assumes all responsibility and liability for proper and safe han | |||
| QFL | (2) | The TC58DxM72x1xxxx is a 128-Mbit (138,412,032) bit NAND Electrica | |||
| QFN | (5) | TI | 06+ | QFN | These solid state surface mount LEDs are designed with a reflector cup |
| QFP | (40) | Silicon chip on Direct-Copper-Bond substrate - High power dissipation | |||
| QFR | (2) | HP | . | • Compact Solid-State Bidirectional Switch • Normal | |
| QFS | (2) | FUJI | Erase Command Erase Command is the command for chip-erase, and chip-eras | ||
| QFW | (1) | PHI | BGA | 2005 | AMDs Flash technology combines years of Flash memory manufacturing expe |
| QFZ | (1) | Output current rating may be limited by duty cycle, ambient temp | |||
| QG- | (2) | CHINA | 0403+ | WRITE PROTECT (WP): The AT24C01A/02/04/08A/16A has a Write Protect pin th | |
| QG3 | (1) | Contact Resistance Operation Time (including bounce time) Relea | |||
| QG4 | (2) | ||||
| QG5 | (6) | INTEL | 06+PB | ADJUSTABLE OUTPUT VOLTAGE The LX8819 develops a 1.25V reference v | |
| QG6 | (2) | INTEL | 06+ | BGA | The VRE114 series voltage references have the ground terminal bro |
| QG8 | (102) | INTEL | BGA | The Fairchild Switch FSTD16211 provides 24-bits of high- speed CMOS TTL | |
| QGA | (13) | PQFP | 450 | YAMAHM | An export permit needs to be obtained from the competent authorities of t |
| QGB | (1) | DONBERG | 07+ | Transmit PCM serial data input. TSI is an 8-bit PCM data stream and is | |
| QGD | (2) | for reads or writes to any location in memory. An automatic power down f | |||
| QGE | (4) | INTEL | 06+ | optimized for use in many industrial and com- mercial applications where | |
| QGF | (2) | The CDS mode of operation supports both line and pixel-clamp modes and | |||
| QGP | (1) | ERICSSON | QFP-32 | 98 | Track: This is an analog control input that enables the output voltage t |
| QGS | (1) | HP | PLCC | 07+ | output selectable). On-chip RAM performs buffering for EFM demodulation |
| QGV | (3) | RSENSE B - Is the connection for the bottom of the B half bridge. This c | |||
| QH- | (1) | N/A | SMD | 98+ | This document may not, in whole or in part be copied, photocopied, reprod |
| QH1 | (1) | Buffered Clock Output This pin provides a buffered output of the 14.31818 | |||
| QH3 | (1) | Purchase of I2C components from Maxim Integrated Products, Inc., or one | |||
| QH4 | (2) | The HC259 and HCT299 are 8-bit shift/storage registers with three-state | |||
| QH7 | (14) | Sharp | DIP-42 | 07+/08+ | This specification contains ADVANCE INFORMATION data. ISSI reserves the r |
| QH8 | (22) | QFP160 | The 3 Volt Intel® Advanced+ Boot Block Flash Memory (C3) Stacked-Ch | ||
| QHD | (3) | 4. Design your application so that the product is used within the ranges | |||
| QHL | (1) | MAGIC | Each device requires only a single 3.0 volt power supply for read, progra | ||
| QHO | (1) | Notes: 4. Test conditions assume signal transition time of 3 ns or | |||
| QHP | (13) | PULSE | 00+ | Maximum ratings are those values beyond which device damage can occur. M | |
| QHS | (8) | SOP | The control signals for the configuration memory device (CE, RESET/OE and | ||
| QHW | (38) | tyco | As shown in the functional block diagram on page 1, the ADSP-21365/6 use | ||
| QHZ | (2) | 98 | In the Bellcore SR-TSV-002476 Issue 1 off-hook protocol, the CPE should n | ||
| QI1 | (1) | N/A | 01+ | PLCC-44 | Notes: 1. TC is defined as case temperature, the temperature of the under |
| QI3 | (1) | AMIS | PLCC-44P | 03+ | INPUT OFFSET VOLTAGE OFFSET VOLTAGE vs. temperature OFFSET VOLTAGE vs. |
| QI8 | (1) | No products described or contained herein are intended for use in surgica | |||
| QIA | (2) | PRX | SOP | These chips, when properly assembled, display characteristics similar to | |
| QIB | (1) | PRX | SOP | NOTES 1Temperature range C40C to +85C. 2Guaranteed by design and/or char | |
| QIC | (15) | PRX | SOP | The CDCLVP110 clock driver distributes one differential clock pair of e | |
| QID | (4) | PRX | SOP | The PCI subsystem is a bus master interface that performs the memory acce | |
| QIL | (5) | BUR | n/a | 99 | The oscillator frequency is inversely proportional to the timing capacito |
| QIQ | (3) | PRX | SOP | SDA is a bidirectional pin used to transfer addresses, data or control in | |
| QIR | (1) | PRX | SOP | Because the P87LPC768 combines an embedded ADC and PWM, it is especially | |
| QIS | (2) | PRX | SOP | • Plastic package has Underwriters Laboratory Flammability | |
| QIV | (1) | MITSUBSHI | 达林顿 | • Two Channel Quadrature Output with Optional Index | |
| QJ- | (1) | JEPICO | QFP | 03+ | FEATURES Faults detected on 7 independent supplies • 1 High Volta |
| QJA | (2) | ADC | SOP | 01+ | This is a special part of the memory used to save the contents of the pro |
| QJL | (1) | ||||
| QJM | (12) | AD | N/A | 02(advantage) | When WP is low, nonvolatile writes to the QJM38510/45 are disabled, but |
| QJS | (1) | PRX | SOP | The DAC101S101 is a direct replacement for the AD5310 and is one of a f | |
| QK0 | (56) | LF(TEC) | 06+ | VGC =1.25V (measured to single-ended out- put) VGC =1.95V (measured to | |
| QK1 | (1) | 04+ | The ADM2486 differential bus transceiver is an integrated, galvanically | ||
| QK5 | (2) | INTEL | 06+ | BGA/38*38 | The HSMx-S670 is the industry standard 2.0 x 1.25 mm package, and is |
| QL- | (9) | The ADSP-21262 includes an on-chip instruction cache that enables three- | |||
| QL0 | (1) | Spartan-IIE devices deliver more gates, I/Os, and features per dollar t | |||
| QL1 | (112) | QUICKLOG | PLCC | 03+ | The AT84CS001 DMUX is started by the ASYNCRST control input that acts as |
| QL2 | (127) | 1 | QUICKLOGIC | 01+ | Leads are Readily Solderable • Lead and Mounting Surface Temp |
| QL3 | (106) | 3 | QUICKLOGIC | 01+ | |
| QL4 | (67) | ＱＵＩＣＫＬＯＧＩＣ | SMD | 02+ | sFEATURES q PWM switching control q Operating Voltage(3.6 |
| QL5 | (19) | - | - | - | RF Micro Devices believes the furnished information is correct and accura |
| QL6 | (5) | QUICKLOGIC | 04+ | Notes: 6. Test conditions assume signal transition time of 5 ns or | |
| QL7 | (1) | 2 | QUICKLOGIC | 02+ | Phase Reference Planes The positions of the reference planes used to mea |
| QL8 | (66) | 1 | QUICKLOGIC | 05+ | An input capacitor of 1.0 µF (min) should be connected from VIN to |
| QL9 | (3) | Output Voltage Consider Figure 2. The resistance R1 generates a constant | |||
| QLA | (16) | FAIRCHILD | 06/07+ | Note 4 A 1 0 MX resistor is connected to the compensation pin (which is t | |
| QLC | (17) | 95 | Active low signal from ATM signifying that data will be sampled on RDAT[7 | ||
| QLD | (3) | . | The purpose of this paper is to define the terms relating to aperture e | ||
| QLE | (1) | FLock detection The automatic restart circuit detects a motor lock condi | |||
| QLG | (1) | Referenced to VCCA Voltage VCC Isolation Feature − If Either VCC In | |||
| QLL | (1) | ST | DIP8 | Description negative analog output, left channel positive analog outpu | |
| QLM | (117) | N/A | These amplifiers may be used in applications such as high speed integrat | ||
| QLN | (3) | Stresses above those listed under "Absolute Maximum Ratings" ma | |||
| QLO | (1) | The QLOGIC10811-00P 10.7 Gbits/s fiber-optic receiver consists of a high | |||
| QLP | (3) | AU | N/A | 07+ | Test Condition Vss < VIN < Vcc Vss < VOUT < Vcc, /CS |
| QLS | (9) | (For a differential input unit) An example of I/O voltage characteristic | |||
| QLT | (1) | 2008 | The devices in this family differ from each other in their switch- point | ||
| QLV | (2) | Any offset and/or gain calibration procedures should not be implemented | |||
| QM- | (6) | The two voltage-controlled amplifiers are full Class A current in/curren | |||
| QM1 | (242) | MITSUBISHI | SOP | The QM150E2Y-2H/7 are high performance frequency synthesiz- ers with an | |
| QM2 | (99) | INTEL | DIP | N/A | Short circuit current is internally limited. The device re- sponds to a |
| QM3 | (126) | MITSUBISHI | SOP | ||
| QM4 | (32) | MIT | 2. These limits define the range of operation for which the part wi | ||
| QM5 | (103) | MITSUBISHI | N/A | The active polarity of CLPDM and SHP (active high or active low) can be c | |
| QM6 | (29) | 03+ | • 1 to 10 differential clock distribution • Optimized for cl | ||
| QM7 | (97) | 1850 | for this lower supply voltage operation, in which case the sensiti | ||
| QM8 | (56) | AMD | N/A | Secondary-side control assumes that output voltage and current measuremen | |
| QM9 | (6) | NULL | 04+ | Three circuit topologies were presented that provide the capability to di | |
| QMA | (6) | XADRE | BGA | 0235+ | System C Two equal amplitude RF signals, separated in frequency |
| QMB | (2) | Isolated Hermetic Package, JEDEC TO-257AA Outline Adjustable Output Vol | |||
| QMC | (7) | QMC | SSOP | 07+ | with A10 defining auto precharge) to select one location out of the memor |
| QMD | (8) | BGA | 99+ | A colour co-processor is required to convert the VV6404 sensors video da | |
| QME | (2) | 1850 | The digital control section is built around the PIC16F628 Microchip micro | ||
| QMF | (2) | HYQ | 2001 | The MPC852T is a PowerPC architecture-based derivative of the Motorola | |
| QMG | (4) | ASIX | QFP | 06+ | Choose among the following memory organizations: IDT72V2101 262, |
| QMI | (8) | ILF | 05+ | 3: Regulation is measured at a constant junction temperature using low du | |
| QMK | (45) | ＴＡＩＹＯ ＹＵＤＥＮ | 06+ | DESCRIPTION The VN920PEP is a monolithic device designed in STMicroelec | |
| QML | (6) | Qnix | SOP44W | 2007+ | Discontinuous mode operation provides high efficiency operation at light |
| QMM | (2) | SHARP | QFP | 03+ | The small form factor and simple interface make the DataFlash Card ideal |
| QMN | (2) | PHILIPS | 06+ | 500 | The "double sampling" aspect of CDS refers to the operation of |
| QMP | (2) | Ground Bit 1, Most Significant Bit (MSB) Bit 2 Bit 3 Bit 4 Bit 5 Bi | |||
| QMR | (2) | PMI | DIP | † Stresses beyond those listed under absolute maximum ratings may c | |
| QMS | (21) | 0 | 0 | Each GLB contains 32 macrocells and a fully populated, programmable AND | |
| QMT | (16) | Genesis Microchip Inc. reserves the right to change or modify the informat | |||
| QMU | (4) | NORTEL | PLCC | 00+ | • State-of-the-art architecture Non-volatile data storage |
| QMV | (924) | ALTERA | 05+ | BGA | The UC1524 is a fixed-frequency pulse-width-modulation voltage regulato |
| QMW | (2) | 1000 | NORTEL | When High, this input holds the address counter reset and puts the DATA | |
| QMX | (7) | AD | 4 | INTERFACE RESET: The RST pin is used for both FWH/LPC and A/A Mux interf | |
| QMY | (3) | NORTEL | 97+ | International standard packages JEDEC TO-264 AA, epoxy meet UL 94 V-0, | |
| Q-N | (1) | Spansions Flash technology combines years of Flash memory manufacturing e | |||
| QN- | (1) | The capacitance (Ciss) is read from the capacitance curve at a voltage co | |||
| QN1 | (3) | n 5 Volt Read, Program, and Erase C Minimizes system-level power | |||
| QN2 | (2) | MITSUBSHI | 达林顿 | As shown in the functional block diagram on Page 1, the ADSP- 21262 uses | |
| QN5 | (2) | GENERAL DESCRIPTION The QN50E2Y/E3Y-2H provides dual 512-position and a | |||
| QN6 | (1) | CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic ch | |||
| QN7 | (1) | The HYM72V32M736B(L)T8 Series are 32Mx72bits Synchronous DRAM Modules. The | |||
| QNB | (1) | ROHM | 95 | The MAX3320 transceivers have a proprietary low- dropout transmitter outp | |
| QNM | (45) | CTS | 06+ | 500 | The LW025 Single-Output-Series Power Modules are low-profile dc-dc conver |
| QNN | (1) | ||||
| QNS | (2) | When the PCB trace between the clock output and the load is over 1 inch | |||
| QNU | (1) | Note 2: These specifications apply for −55˚C TA +125˚C f | |||
| QNV | (1) | Collision Output. Balanced differential line driver outputs from the coll | |||
| QO1 | (3) | aegtfk | aegtfk | dc79+ | Note 11: Maximum power dissipation in the device (PDMAX) occurs at an out |
| QO2 | (1) | QUALCOMM | PLCC | Blanking in the RF or mixer sections of the receiver removes most | |
| QOI | (1) | N/A | 3225 | Case: JEDEC DO-214AA molded plastic body Terminals: Solder plated, solder | |
| QOM | (1) | This pin is the system ground for the NCP5008/NCP5009 and carries both th | |||
| QOS | (1) | 0 | 0 | A key application-specific feature of the 56F801 is the inclusion of a Pu | |
| QP- | (5) | H - High-Terminal Potentiometer. This is the high terminal of the potenti | |||
| QP0 | (25) | OPTI | QFP-160 | Using this configuration, the device will support SVHS mode for four enco | |
| QP1 | (4) | MIT | 模块 | nal pull-up resistor should be connected between SDA and V CC . The value | |
| QP2 | (1) | MIT | 模块 | mode 4: fast mode, CS active (low) continuously, 16-clock transfer | |
| QP4 | (2) | IBM | BGA | 02+ | SUBCARRIER: The output of the encoder stage (Manchester or Miller) gates |
| QP7 | (5) | SEMI | DIP | 0423+ | The DDX-2000 converts serial I2S digital audio signals into pulse-width-m |
| QP8 | (38) | INTEL | DIP | 00+ | NOTES: 1. For conditions shown as Min. or Max., use the appropriate valu |
| QPA | (6) | SMD-8 | 96 | is a registered trademark of VIA Technologies, Incorporated. Wind | |
| QPC | (29) | N/A | The 32-bit multiplexed bus interface unit of MX98715A provides a direct | ||
| QPD | (2) | 2.2.1 Specifications and standards. The following specifications a | |||
| QPH | (1) | Typ, min, and max values at TA = 25C, full temperature range is TMIN = &# | |||
| QPI | (3) | MAGIC | 1206-220M | 05+ | Chapter 6, "Instruction Set," describes the features and convent |
| QPL | (3) | where N is the number of cells, RB1 is connected to the positive battery | |||
| QPM | (4) | AGILENT | 01+ | The bq26220 is an advanced battery monitoring device designed to accura | |
| QPN | (1) | The MAX3058/MAX3059 interface between the con- troller area network (CAN) | |||
| QPO | (3) | N/A | VICOR | 04+ | The on-time of the laser current (IM-pin) can be increased up to 20% by c |
| QPP | (7) | XEMOD | 00+ | N/A | This document contains information on a product under development at Adva |
| QPQ | (1) | Upon power-up, the FIFO must be reset with a Reset (RS) cycle. This cau | |||
| QPS | (2) | ST | SOP-3.9-8P | 6+ | By combining a conventional thin-film R-2R ladder DAC, a digital offset |
| QPW | (12) | PIXELWORHS | BGA | 0240+ | Although the QPW166-10T-M can withstand differential voltages up t |
| QQ0 | (1) | PHI | SOP28W | 2007+ | Cathode-to-Anode Voltage Continuous Forward Current Continuous Forward C |
| QQ1 | (2) | 国产 | DIP | 04 | International standard package miniBLOC (ISOTOP compatible) Isolation |
| QQ8 | (44) | SEEQ | QFP | 07+ | Ring Detection. Referring to the block diagram in Figure 1, incoming ring |
| QQA | (1) | MOT | PLCC68 | 99+ | AEC-Q100† Qualified for Automotive Applications Customer-Specific |
| QQB | (2) | Precise control of the differential input voltage thresholds now allows f | |||
| QQI | (1) | 02+ | PHILIPS | 14 | To set the new VTRIP voltage, apply the desired VTRIP threshold to the |
| QQL | (2) | • AN765, Using Microchips Micropower LDOs, DS00765, Microchi | |||
| QQR | (1) | The QQR0582001Z and QQR0582001Z are L-Band Frequency Up- Converters man | |||
| QQS | (1) | The OXCF950 is a low cost asynchronous 16-bit PC card (henceforth referr | |||
| QQV | (1) | TAOperating free-air temperature−4085C NOTES: 4. VCCI is th | |||
| QR/ | (7) | AD5381-5 is calibrated using an external 2.5 V reference. Temperat | |||
| QR0 | (4) | NS | PQFP-160 | 98 | The HSDL-3610 can be completely shut down to achieve very low power c |
| QR1 | (3) | NSC | 2002 | Setting up a password is done essentially in the same way as writing data | |
| QR2 | (1) | 6. The analog input signal is sampled on the positive-going edge | |||
| QR8 | (4) | INTERSIL | 金 | The ILED is the constant current programmed by the RLED. When the | |
| QRA | (2) | JANS level Thermal impedance (see 4.3.4) hFE1 and ICEX hFE1 an | |||
| QRB | (4) | FSC | 08+ | 2-channel, 250 kSPS, 10-/12-bit ADCs in TSOT package. Low power consumpt | |
| QRC | (19) | PRX | SOP | Note) 1. Measuring methods are based on JAPANESE INDUSTRIAL STANDARD JIS | |
| QRD | (15) | PRX | SOP | Up to 18-A Output Current 5-V Input Bus Wide-Output Voltage Adjust (0.8 | |
| QRE | (11) | FAIRCHILD | 05/06+ | A Read Command will interrupt a burst write operation on the same clock cy | |
| QRF | (13) | PRX | SOP | This device features an Erase Suspend mode. While in this mode, the hos | |
| QRJ | (1) | TAIYO | 07+ | 圆柱0603 | Rapid Synchronization: The serializer has the capability to send specific |
| QRP | (11) | Each arbitrary length of data packet consists of 3 portions viz, Row addre | |||
| QRR | (22) | N/A | Two on-chip Programmable Current Generators may be independently progra | ||
| QRS | (12) | PRX | SOP | The following describes a procedure for evaluating the RMBA19500, a monol | |
| QRT | (1) | The HIDRV driver has a power supply, VCCQP, supplied from a 12V source a | |||
| QRW | (10) | TYCO | SOP | The beginning of a block of 16 serial data at port A or B is determined b | |
| QRX | (1) | N/A | N/A | 03+ | (OSCIN) Serial Interface With Microprocessor (SPI) Programmable Gain Pr |
| QRY | (1) | 322 | AMS | O4 | The crystal used should be a fundamental mode (do not use third overton |
| QRZ | (1) | ||||
| QS- | (1) | Notes; (1) Repetitive Rating: Pulse Width Limited by Maximum Junction Te | |||
| QS. | (1) | IDT/Q | DIP20 | 2007+ | The following Functional Description describes the base architecture of |
| QS0 | (23) | 2007 | The system clock for the microcontroller is derived from either 6MHz or 1 | ||
| QS1 | (16) | QDSP | 96 | • IDT54/74FCT240/241/244/540/541 equivalent to FAST speed a | |
| QS2 | (73) | IRC | SSOP | 07+ | Power Good output. This is an open drain output and functions as a supply |
| QS3 | (413) | TRI-STATE is a registered trademark of National Semiconductor Corporation | |||
| QS4 | (18) | SK | QFP | 0 | Guaranteed by design. Not production tested. All digital inputs (DB_, A_, |
| QS5 | (329) | IDT | 04+ | 110 | Turn-On Propagation Delay Turn-Off Propagation Delay Turn-On Rise Tim |
| QS6 | (38) | ROHM | SOT-163 | 05+PB | s 16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package. s 8/16/ |
| QS7 | (1271) | N/A | 01+ | SSOP48 | The LM236-2.5, LM336-2.5, and LM336B-2.5 integrated circuits are precis |
| QS8 | (47) | QTRONIX | QFP | 9631+ | Precision voltage sensor Two threshold options: 2.93V or 4.63V Stable |
| QS9 | (3) | QS | SSOP24L | 9610 | The QS95003-1AQX is a PFM inductive boost converter designed to provide |
| QSA | (6) | FAIRCHILD | TO-18 | 03+ | Note 1: Specifications at TA +25C are guaranteed by production testing. S |
| QSB | (23) | QT | 06+ | The devices low VCC detection circuitry protects the users system from | |
| QSC | (31) | IRC | TSSOP | 02+ | This IC conforms to the HBS (Home Bus) specification (Electronic Industrie |
| QSD | (38) | Designed for WLL/MMDS/BWA or UMTS driver applications with frequen | |||
| QSE | (36) | FEATURES High breakdown voltage (BVCEO 50V) High-current d | |||
| QSF | (3) | QSF; | . | AS6UA25616 Intelliwatt™ active power circuitry Industrial and comm | |
| QSG | (1) | IDT | 0339+ | SSOP24 | Picture Structure Improvement including Color Transition Improvement, L |
| QSH | (11) | SAMTEC | 08+ | After POR, the controller determines the user-defined configuration opti | |
| QSI | (32) | SANYO | SOT-252-5 | The K6F8016U6C families are fabricated by SAMSUNGs advanced full | |
| QSK | (1) | 4-channel Pulse Width Modulator (PWM) generator Configurable resolution | |||
| QSL | (6) | ROHM | SOT23-5 | 0412+ | The Master begins a transmission by sending a START condition. The Mast |
| QSM | (91) | Agilent | SMD | 2006 | The Divided Down Crystal Reference with 50:50 Mark-Space Ratio. May be us |
| QSN | (3) | A voltage follower may be balanced by the technique shown in Figure 4. R | |||
| QSO | (7) | IRC | SSOP20 | 2004 | Diffusion & Thin Films Well (field) Sheet Resistance N+ Sheet Resis |
| QSP | (42) | SSOP16 | The 5B45 and 5B46 are single-channel isolated frequency input modules th | ||
| QSS | (5) | IDT | SOP | 2002 | BVDSSDrain-to-Source Breakdown Voltage-200 ∆BV DSS /∆T J Tem |
| QST | (15) | DIP8 | All information contained in this document is subject to change without n | ||
| QSW | (5) | Todo el material que no es necesario fu retirado del embalaje del product | |||
| QSX | (8) | ROHM? | SOT-236? | 04+ | • Providing capacitance values in the range of electrolytic types |
| QSZ | (11) | ROHM | SOT-153 | The TFP401/401A supports display resolutions up to UXGA in 24-bit true co | |
| QT- | (1) | QTS | 0 | 6 | PRECAUTIONS • The exterior of this product can melt since due to t |
| QT0 | (10) | N/A | N/A | N/A | Notes: 1. All inputs except OE must meet setup and hold times for the L |
| QT1 | (61) | 07/08+ | Input load capacitors are placed on the CY22050 die to reduce external co | ||
| QT2 | (25) | FIGURE 5 Transfer Function Display Gain is displayed as the slope | |||
| QT3 | (11) | N/A | 1206L | The MDU28C tolerances are guaranteed for input pulse widths and periods g | |
| QT4 | (3) | Notes : 1. * Checked No Connect(NC) pins are reserved for higher density a | |||
| QT5 | (3) | N/A | N/A | 04+ | These power transistors are produced by PPC's DOUBLE DIFFUSED PLANAR pro |
| QT6 | (17) | MICROCHI | SOP-14P | O507 | Short circuit current is internally limited. The device re- sponds to a |
| QT8 | (6) | QT | 06+ | The D-channel is primarily intended to carry signalling information for c | |
| QTB | (3) | N/A | The EB-2100x is an evaluation amplifier that showcases Apogees all-digita | ||
| QTC | (49) | SOP | 95 | 3 Micron Radiation Hardened SOS CMOS Total Dose 200K RAD (Si) SEP Effect | |
| QTD | (2) | QFP | Overcharging and Over-Discharging Dedicated for One-Cell Applications In | ||
| QTE | (9) | Referenced to VCCA Voltage VCC Isolation Feature − If Either VCC In | |||
| QTF | (5) | The REFCLK input can be configured three ways. When both REFCLK+ and RE | |||
| QTH | (7) | THINE | QFP | 0317+ | (Segment mode) ! Shift Clock frequency: 20 MHz (Max.) (VDD = 5 V |
| QTI | (1) | AUDIA | 9748 | 3. Power consumption figures assume device is driving line load over oper | |
| QTK | (27) | 97 | I/O performance is increased to 622 Mb/s using Source Synchronous data | ||
| QTL | (310) | FAIRCHILD | 06+ | 发光管 | HN58X24xxSFPIAG series are two-wire serial interface EEPROM (Electrically |
| QTM | (4) | SANSYO | 03+ | The UC3825A,B has dual alternating outputs and the same pin configuratio | |
| QTS | (4) | Widebus Family Operates From 1.65 V to 3.6 V Inputs Accept Volt | |||
| QTT | (2) | Simultaneous 50Hz/60Hz Rejection (87dB Minimum) Differential Input and D | |||
| QTW | (3) | PHI | BGA | FEATURES 600 kHz PWM Frequency Fully Integrated 1.5 A Power Switch 3% | |
| QTX | (3) | C-MAC | SOP | 9946 | Fully asynchronous operation from either port Separate byte controls fo |
| QU1 | (1) | aegtfk | aegtfk | dc79+ | Input Capacitors The recommended input capacitance is determined by the |
| QU8 | (13) | C Glueless Interface to Synchronous Memories: SDRAM or SBSRAM C G | |||
| QUA | (52) | NVIDIA | 00+ | BGA3535 | Note 6: This IC includes overtemperature protection that is intended to |
| QUE | (1) | The information contained herein is presented only as a guide for the app | |||
| QUG | (1) | N/A | allow adjacent I/O cell outputs to be directly connected without passing | ||
| QUI | (2) | QSI | Technology • Positive VCE(ON)Temperature Coefficient ̶ | ||
| QUO | (1) | Shutdown. When SHUTD input is low, the internal clock is stopped and the | |||
| QUQ | (1) | Output clock data format C Controls the output clock (ODCK) format for ei | |||
| QUS | (1) | SOP | The floating-point unit operations set includes floating-point add | ||
| QV0 | (1) | N/A | SMD | 2000 | The 132C/W for the TSOP−6 package assumes the use of the re |
| QV1 | (2) | ALARIS | QFP | 00+ | speed 3.3V applications; it can be interfaced to 5V signal environment |
| QV2 | (1) | This information is generally descriptive only and is not intended to mak | |||
| QV4 | (3) | Note 5: This parameter is guaranteed by design but is not tested. The bus | |||
| QV5 | (2) | This device contains protection circuitry to guard against damage | |||
| QVA | (3) | FAIRCHILD | The output stage of the MD1811 has separate power connections enabling th | ||
| QVB | (2) | FAIRCHILD | Single Chip With Easy Interface Between UART and Serial-Port Connector of | ||
| QVC | (34) | TDK | new | Thermal Protection The FAN2500/01 is designed to supply high peak output | |
| QVE | (10) | FAIRCHILD | 03+ | The device has numerous display capabilities. It has an integrated video | |
| QVK | (1) | YAMAHA | N/A | 06+ | POWER-ON INITIALIZATION When power is first applied, power-on reset circ |
| QVL | (1) | Note 7: Maximum ambient temperature (TA-MAX) is dependent on the maximum | |||
| QVS | (8) | A temperature-compensated comparator circuit monitors the level of VCC W | |||
| QW0 | (11) | LUCENT | MODULE | N/A | DESCRIPTION The 74V1T77 is an advanced high-speed CMOS SINGLE D-TYPE L |
| QW1 | (1) | N/A | NSC | 04+ | At each input-line/product-term intersection there is an EEPROM memory |
| QW2 | (1) | The DDX-2100 Power Device is a dual channel H-Bridge that can deliver ove | |||
| QW3 | (1) | N/A | cycle waveforms. The Main Memory Erase operation is internally controll | ||
| QW6 | (1) | The QW62256 uses bus cycles of 8 bits each for commands, data, and address | |||
| QW9 | (2) | BGA80 | 2007+ | The ADS800 is a low-power, monolithic 12-bit, 40MHz Ana- log-to-Digital | |
| QWA | (1) | DIP-8 | There is no provision to abort an Erase or Program operation, once initia | ||
| QWD | (2) | PLCC | Case: SOT-26, Molded Plastic Case material - UL Flammability Rating 94V-0 | ||
| QWE | (1) | Pin 1 VCC1 ( a 5V) The logic and clock power supply pin Pin 2 DIRECTION | |||
| QWQ | (3) | Two clock sources are used to drive the microcontroller, a main clock dri | |||
| QWS | (1) | IPD | N/A | Offset Drift is a measure of the actual change in output with all 1s on | |
| QWT | (1) | 8-bit Resolution 500 Msps (min) Sampling Rate Power Consumption: 3.8W Ty | |||
| QWV | (6) | N/A | 98+ | 60000 | CML outputs have a common-mode voltage near VCC. To avoid changing this o |
| QWX | (1) | NVIDIA | 04+ | PBGA | • New specifications • Dual frequency standard for indu |
| QX- | (2) | The QX-1030 has sufficient phase margin when compensated for unit | |||
| QX1 | (2) | This line of Schottky diodes is optimized for use in mixer appli- cation | |||
| QX2 | (21) | MITSUMI | SOP | 1997 | † Stress beyond those listed under absolute maximum ratings may cau |
| QX3 | (3) | QUICKLOGIC | QFP | 03+ | dresses are stable, the address access time (tAVQV) is equal to the del |
| QX4 | (1) | QX | SOT-23-5 | 08+ | The size and placement of the capacitors for the main voltage bus for th |
| QX6 | (1) | QX | SOT | 08+ | The QX62726 is intended to be used with a small companion IC, the PNX8510 |
| QX7 | (2) | QX | 08+ | Organized as 2M x 8 bits Single 3.3V Power Supply Stacks of 16 SRAM 128K | |
| QX8 | (5) | INTEL | 2007 | 2. Stand-by SW function By means of controlling pin(4) (stand-by | |
| QX9 | (2) | QX | SOP8 | 08+ | 1) Skew is defined as the absolute value of the difference between the ac |
| QXC | (1) | capacitance | NICHICON | 08+ | Master) generate TCLK (Transmit Clock), the internal clock used to trans |
| QXE | (1) | Note: 1. A write cycle occurs during the overlap of a low CS and a low WE | |||
| QXF | (2) | Industry Standard MICROWIRE Bus Single Supply Voltage: C 4.5 to 5.5V | |||
| QXJ | (3) | • Meets or Exceeds the Requirements of ANSI TIA/EIA-644-199 | |||
| QXN | (5) | Stability The IRU1015-33 requires the use of an output capacitor as part | |||
| QXO | (1) | The special built-in green functions allow the efficiency to be optimum | |||
| QXR | (1) | N/A | XT | 04+ | Category voltage UC: The maximum direct voltage, or the maximum r.m.s. v |
| QXT | (1) | The contents of the memory address range 0DH to 1FH is FFH. These cells ca | |||
| QXW | (1) | capacitance | NICHICON | 08+ | Self-synchronization to main channel output Free-run mode for buck regu |
| QXX | (21) | TOSHIBA | SOT-183 | 05+ | The QXXAD2G34HDCP is a high-speed low-noise clock generator designed to w |
| QY1 | (1) | Network Systems Programmable Current Slew Rate Power Supply Sequencing | |||
| QY2 | (1) | 747+ | The AT40KAL is a family of fully PCI-compliant, SRAM-based FPGAs with dis | ||
| QY3 | (1) | In Discontinuous mode, when the inductor current drops to zero, the vol | |||
| QY4 | (1) | 7 | UNLESS OTHERWISE NOTED this document contains PRO- DUCTION DATA informa | ||
| QYA | (1) | Fault Flag FLG is an N-channel, open-drain MOSFET output. The fault-flag | |||
| QYP | (1) | The HS-6254RH is a Radiation Hardened array of five NPN transistor | |||
| QYS | (1) | capacitance | NICHICON | 08+ | The MAX3060E features slew-rate-limited drivers that minimize EMI and red |
| QYX | (9) | capacitance | NICHICON | 08+ | Hynix HYMD132725A(L)8-K/H/L series is designed for high speed of up to 133 |
| QZ0 | (1) | TI | TSSOP8 | 06+ | The H-Bridge contains integrated free-wheel di- odes. In case of free-w |
| QZ8 | (1) | N/A | SSOP | 02+ | Two Independent Regulated Outputs Accurate Output Voltages Typical Drop |
| QZ9 | (2) | OZ | SMD | 2005 | 1. H = HIGH voltage level h = HIGH voltage level one set-up time |
| QZF | (1) | Ultra compact package. Wide frequency range in 8 to 16 MHz. C4 (G type | |||
| QZX | (3) | DIODES | 2008 | Vth can be expressed as voltage between gate and source when low o |
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