| Mfg | pack | D/C | Descrpion | ||
| S.E | (1) | As the LEDs are driven directly by the MCU, care had to be taken to avoid | |||
| S.F | (1) | Amplifier dissipation reaches a maximum when the peaks of the ac output | |||
| S.M | (2) | JAT | 2W | 05+ | The Am29SL800D is an 8 Mbit, 1.8 V volt-only Flash memory organized as |
| S.T | (1) | All MAX® II devices provide Joint Test Action Group (JTAG) boundary- | |||
| S.X | (1) | MOT | SOP16S | 2007+ | (1) The minimum supply voltage for the REF3212 is 1.8V. (2) Thermal hys |
| S/B | (9) | ||||
| S/C | (2) | ||||
| S/H | (1) | ||||
| S/P | (1) | ||||
| S/S | (1) | ||||
| S/T | (2) | ||||
| S/W | (3) | ||||
| S-0 | (11) | SUMIDA | 04+ | 5. The ALD1704 operational amplifier has been designed to provide full & | |
| S0- | (1) | 00+ | SOP-16 | The S0-16 OptoRec interface has been designed for ease of use and flexi | |
| S00 | (66) | stock | 2 MHz (typ.) PWM Switching Frequency Operates from a single | ||
| S01 | (62) | SGNEC | SOP-20 | N/A | Maxim evaluates pressure pot stress from every assembly process du |
| S02 | (81) | NSC | 07+ | TMS320C62x, VelociTI, and C62x are trademarks of Texas Instruments. Moto | |
| S03 | (59) | SMK | The digital controlled potentiometer is implemented using 255 resistive | ||
| S04 | (38) | STMicroelectronics | n/a | The XC6203E series are highly precise, low power consumption, positive v | |
| S05 | (71) | TECCOR | 05+ | !Features 1) 4 -input 1-output switch. 2) Built-in 6dB amplifier and 75& | |
| S06 | (31) | ST | TO-220 | 04+ | Four 8-bit registers are provided for control, option select and status m |
| S07 | (47) | SGNEC | QFP | 03+ | ASYNCHRONOUS OPERATION For asynchronous operation, separate transmit and |
| S08 | (72) | DSI | n/a | ACEx™FACT™ ActiveArray™FACT Quiet Series™ Bottomless | |
| S09 | (4) | INFINEON | 2008 | n OSD Window Fade In/Fade Out n OSD Half Tone Transparency n OSD overrid | |
| S0B | (1) | † All characteristics are measured with a 0.33-µF capacitor a | |||
| S0C | (9) | INTEL | 2007+ | DESCRIPTION This new generation of TRENCH MOSFETs from Zetex utilises a | |
| S0G | (1) | The US member body, Canada and some other member bodies have expressed th | |||
| S0I | (3) | HANA | SOP-3.9-8P | 6+ | *Absolute maximum ratings apply at 25C, unless otherwise noted. Stresses |
| S0J | (1) | FLEX 8000 devices provide a large number of storage elements for applica | |||
| S0L | (4) | SOP | 505 | Differential termination for Stratix devices is supported for the left an | |
| S0M | (28) | N/A | N/A | 04+ | FEATURES • Normally Open, Single Pole Single Throw Operation ̶ |
| S0N | (1) | TECCOR | 05+ | • The information contained herein is presented only as a guide for | |
| S0P | (1) | ||||
| S0R | (1) | IOAPIC clock output. (14.318 MHz) Poweredby VDDL CPU Output clocks. Powe | |||
| S0T | (1) | MAIN PRODUCT CHARACTERISTICS: Where EMI filtering in ESD sensitive equip | |||
| S0U | (2) | After the CMX866 has been successfully powered up, both the CMX866 Transmi | |||
| S0V | (1) | Operating Temperature, -40C to 85C Storage Temperature, -55C to 100C * | |||
| S0X | (1) | VCU1 3.80 to 4.40 Adjustment VCD1 3.45 to 4.40 Adjustment VDD1 2.00 t | |||
| S-1 | (310) | SII-IC | 20/SOP | 07+/08+ | The selection of the reference crystal frequency is based on some assumpti |
| S1- | (6) | SANKEN | N/A | SmartVoltagetechnology provides a choice of Voc and V,, combinations,as s | |
| S1/ | (1) | DIP | 94 | • Low On-Resistance (17W typ.) Minimizes Distortion and Erro | |
| S10 | (501) | TECCOR | 05+ | (Note 1) (Unless otherwise specified, these specifications apply | |
| S11 | (123) | SHARP | 06+ | Rectifiers advanced line of power MOSFET transistors. The efficient geo | |
| S12 | (182) | INOVA | DIP | DIP | Note that the ASH radio RX Data output signal is inverted before being ap |
| S13 | (134) | Deep Power Down Mode is a additional operating mode for Low Power SDRAM. | |||
| S14 | (163) | SEIKO | SOP | GENERAL FEATURES Simultaneous SD and HD Inputs and Outputs Oversampling | |
| S15 | (131) | MOSPEC | TO-220 | 04+ | The two address buses (PMA and DMA) share a single external address bus, |
| S16 | (157) | DSI | n/a | This datasheet contains new product information. Anachip Corp. reserves th | |
| S17 | (67) | skyworks | 04+ | The VFC measures bipolar signals up to 250mV. The bq2060 detects charge a | |
| S18 | (89) | The LM4040 utilizes fuse and zener-zap reverse breakdown voltage trim d | |||
| S19 | (127) | SPANSION | 07+ | The innovative design of the internal T/H assures an exceptionally wide 1 | |
| S1A | (92) | There are three different types of ground pins on the S1A13A. They are | |||
| S1B | (30) | FSC | SMA | 05+ | The TMS320LF240xA and TMS320LC240xA devices, new members of the TMS320C24 |
| S1C | (48) | The SecSi™ (Secured Silicon) Sector is an extra 256 byte sector ca | |||
| S1D | (259) | EPSON | 2007 | Note - If any of the identified ranges include code positions to which no | |
| S1E | (5) | DIODES | DO214AC | 05 | Soldering/Cleaning Cleaning agents from the ketone family (acetone, me |
| S1F | (30) | murata | murata | dc79+ | GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic |
| S1G | (45) | VISHAY | SMA | 05+ | The S1G/11T and S1G/11T are 4,718,592-bit Syn- chronous Static Random Acc |
| S1H | (18) | EPSON/ | SOP | 03+ | This supplemental information applies to the GS816118/36T datasheet, which |
| S1I | (2) | o dcOutput Duty Cycle48 NOTE 1: Defined as skew between outputs at the | |||
| S1J | (31) | VISHAY | SMA | 04+ | The most common application for the S1J/11T/1226/ 1227 devices i |
| S1K | (18) | LITEON | 06/07+ | BUS OPERATIONS There are five standard bus operations that control the | |
| S1L | (77) | SAM | 2008 | 1) Skew is defined as the absolute value of the difference between the ac | |
| S1M | (59) | DIODES | SMA | 04+ | • International standard packages • miniBLOC with Aluminium |
| S1N | (13) | SHINDEGE | SMD | 06+ | 6.7MHz Y and C filters, with CV out for NTSC or PAL 75Ω cabl |
| S1P | (7) | DIP | The AFEU accepts data in 32-bit words per write cycle and produces 4 byte | ||
| S1R | (16) | EPSON | BGA | 01+ | Features • Hole-less TO-247 package for clip mounting • |
| S1S | (16) | 96 | |||
| S1T | (52) | SAMSUNG | 2002 | The frequency of the VCO is locked to a reference frequency by an on-chip | |
| S1V | (14) | EPSON | 02+ | 7.1 The parties agree that the AMBE® Voice Compression Software shal | |
| S1W | (34) | 6 | BGA | The absolute maximum ratings are values which must not individuall | |
| S1X | (7) | SEIKO | QFP PB | 05+ | DESCRIPTION The HCF4013B is a monolithic integrated circuit fabricated |
| S1Y | (4) | shi | n/a | Maximum Charge Current Charge Current Load Dependency Trickle Charge Cur | |
| S1Z | (41) | SANYO | 03+ | This series of hermetic packaged MOSFETs are ideally suited for low volta | |
| Ｓ－２ | (261) | SEIKO | SOP/8 | 04+ | It includes Selectable A-law/u-law function, Internal Gain Adjustment fro |
| S2- | (9) | FUJITSU | 2008 | AC CHARACTERISTICS PARAMETER DQM to input data delay WRITE command to | |
| S20 | (515) | N/A | N/A | N/A | CBR refresh is utilized by bringing CAS low earlier than RAS (see paramet |
| S21 | (122) | SHARP | DIP-6 | (1) The algebraic convention, in which the least positive (most negative) | |
| S22 | (127) | N/A | SMD | 2000 | The self-refresh mode is entered by dropping CAS low prior to RAS going l |
| S23 | (49) | S | DIP-8 | Specifically designed for Automotive applications, this HEXFET® Powe | |
| S24 | (191) | SILICONI | SOP8 | Data pin for I2C circuitry 5V tolerant Clock input of I2C input Analog | |
| S25 | (136) | ST | . | N/A | Timer counter 5 : 8-bit 1 (square-wave output, event count, serial baud |
| S26 | (37) | VISHAY | 2003+ | The external bus interface (EBI) provides a glueless interface to 8 and 1 | |
| S27 | (38) | N/A | N/A | N/A | Operating temperature range is: C40C to +85C. Guaranteed b |
| S28 | (47) | DSI | n/a | Hynix HYMD564M646(L)6-K/H/L series is designed for high speed of up to 133 | |
| S29 | (949) | MIT | 2350 | All parameters measured at fMAX unless noted otherwise. NOTE 1: Assumin | |
| S2A | (27) | N/A | the device has a Sector Protect function which hardware write protects | ||
| S2B | (32) | 2W | High speed 8-bit ADC up to 110MHz conversion rate Support display res | ||
| S2C | (19) | DIODES | DO214AA | 05 | Reset In: Sets the Program Counter to zero and resets the Interrupt Enabl |
| S2D | (20) | VISHAY | Notes: 5. Distribution data sample size is 500 samples taken from 5 diffe | ||
| S2E | (16) | TOSHIBA | MOUDLE | N/A | Write cycle time Write pulse width Address setup time Address setup tim |
| S2F | (9) | DIODES | DO214AA | 05 | * This is a stress rating only and functional operation of the device at |
| S2G | (20) | ST | 07+ | CD players read out the digital signal from the disc using a built-in p | |
| S2H | (1) | 铁帽4脚 | 08+ | The switched-capacitor lowpass filter (IC1), with a transition ratio of 1 | |
| S2J | (18) | GS | 08+ | Crystal input, has internal load cap (36pF) and feedback resistor from | |
| S2K | (12) | GSI | SMB | The maximum graphics resolution supported is 1280 x 1024 in 16 Million | |
| S2L | (14) | Shindengen | N/A | DIP | Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pull-ups |
| S2M | (21) | ＶＩＳＨＡＹ | 8V to 15V IC supply. A 220µF bypass capacitor to GND with a 470nF | ||
| S2N | (7) | LF(TEC) | DO-214 | 06+ | Note 5: Rise and fall times are measured using 10% and 90% levels. Duty |
| S2P | (4) | MOT | 06+ | The modem includes a programmable single/dual tone transmitter, a progra | |
| S2S | (32) | LF(TEC) | DO-214 | 06+ | The device is suited to high-density applications in which data is sequen |
| S2T | (6) | NSC | SOP8 | 03+ | The SK-2910 Series of quartz crystal oscillators provide DPECL Fast Edge |
| S2V | (6) | SHINDENGEN | The APX9142 is an integrated Hall Effect Sensor IC designed for electric | ||
| S2W | (1) | The 16-bit synchronization counter is the basis behind the transmitted | |||
| S2X | (1) | SOP | The OPA363 and OPA364 families offer excellent CMRR without the crossov | ||
| S2Y | (3) | TOS | TO-126F | 04+ | Enhanced N channel FET with no inherent diode to Vcc 5Ω bidirectio |
| S2Z | (2) | The BALBSG (the indicates the output voltage value) is a low-saturation | |||
| S-3 | (68) | SEIKO | SOP | 1999 | Min. Typ Max. Min. Typ. Max. UnitsTest Conditions 80 80VApplied drain-t |
| S3- | (5) | HARRIS | PDIP40L | 8437 | Drain-to-Source Breakdown Voltage 500 Gate Threshold Voltage …2.0 |
| S3/ | (2) | NOTES 1. Data inputs have internal pull-up resistors to enable them to b | |||
| S30 | (350) | AMCC | QFP | 05+ | NOTE: Device will meet the specifications after thermal equilibrium has b |
| S31 | (33) | PANJIT | SMD | 04+ | As an example lets find the total power consumption for an MM74C00 opera |
| S32 | (66) | SOP24 | I2C INTERFACE TIMING CHARACTERISTICS6, 11 (Specifications Apply to All Pa | ||
| S33 | (43) | N/A | SOP8 | The TC57 series of precision low dropout regulator controllers use an e | |
| S34 | (26) | ST | TO-252 | SUPPLY VOLTAGE, +VS to CVS BOOST VOLTAGE, +Vb to -Vb OUTPUT CURRENT, wit | |
| S35 | (107) | AMI | CDIP | CDIP | TRI-STATE is a registered trademark of National Semiconductor Corporation |
| S36 | (10) | ST | 99+ | SOT252 | There are three ways to terminate the Idle mode. Activation of any enabl |
| S37 | (11) | DSI | n/a | As a alternative to a full chip erase, the device is organized into four | |
| S38 | (74) | DC Characteristics for FCT Family Devices (Continued) Typical values are | |||
| S39 | (52) | SEIKO | Unless otherwise specified, the following specifications apply over the o | ||
| S3A | (21) | VISHAY | 07+ | SHORT-CIRCUITS Some amplifier applications must be designed to survive a | |
| S3B | (34) | VISHAY | 07+ | The receive section of the CY7C9689 HOTLink accepts a se- rial bit-strea | |
| S3C | (498) | SAM | SOP20 | 01+ | The 56F802 supports program execution from either internal or external me |
| S3D | (33) | vishay | vishay | dc00 | The accelerated program (ACC) feature allows the system to program the d |
| S3E | (6) | DIODES | DO214AB | 05 | Erase Command Erase Command is the command for chip-erase, and chip-eras |
| S3F | (85) | SAMSUNG | 08+ | Mechanical The primary thermal path for power dissipation is through t | |
| S3G | (22) | VISHAY | 07+ | Second-generation HOTLink® technology AMD™ AM7968/7969 TAXIchip | |
| S3H | (3) | NEC | 06+ | 1. Measured using a 750 mV source, 50% duty cycle clock source. All loadin | |
| S3J | (18) | VISHAY | 07+ | Note 1: Calculated by measuring the combined oscillator and prescaler supp | |
| S3K | (13) | VISHAY | 07+ | Dimensions are in inches. Metric equivalents are given for general info | |
| S3L | (30) | COILCRAFT | N/A | The Secured Silicon Sector is an extra 256 byte sec- tor capable of bein | |
| S3M | (19) | VISHAY | 07+ | n Floating channel designed for bootstrap operation Fully | |
| S3N | (3) | MOT | SOP-8 | The ZL50018 is a maximum 2,048 x 2,048 channel non-blocking digital Time | |
| S3O | (1) | 01+ | BGA | The CM8560 is a low cost linear regulator designed to provide a desired o | |
| S3P | (185) | SAMSUNG | 2007 | Note: 1) Inverter low-side is composed of three sense-IGBTs including fre | |
| S3Q | (1) | ||||
| S3R | (7) | N/A | SOP | 06+ | The single conversion superheterodyne receiver approach is now generall |
| S3S | (8) | NSC | SO-8 | 06+ | (1) VDRM and VRRM for all types can be applied on a continuous basis. Rat |
| S3T | (3) | ALCATEL | QFP-100P | 03+ | This pin provides a 6 µA current source to linearly charge an exte |
| S3V | (12) | SHINDENGEN | •RAD-PAK® Technology Hardened Against Natural Space Radia | ||
| S3W | (2) | SHINDENG | 07+ | Hynix HYMD116645A(L)8-K/H/L series incorporates SPD(serial presence detect | |
| S-4 | (8) | 模块 | 08+ | Maxim evaluates pressure pot stress from every assembly process du | |
| S4- | (6) | MITSUMI | 4×5 | The PA50 is a MOSFET power operational amplifier that exten | |
| S4. | (1) | The Am29PDS322D is a 32 Mbit, 1.8 V-only Flash memory organized as 2,09 | |||
| S40 | (180) | TECCOR | TO-218 | 05+ | Notes: 1. R= Read only RW= Read and Write 2. PWD = Power on Default 3 |
| S41 | (38) | MSOP/8 | Page Write Page write allows up to 64 bytes to be consecu- tively latch | ||
| S42 | (65) | MOT | SMD-8 | 99+ | Stresses beyond those listed in the Absolute Maximum Ratings may cause pe |
| S43 | (25) | SENSITRON | 2002 | The 2-wire control interface implements a read/write slave only interface | |
| S44 | (47) | SIEMENS | SMD-8 | CMOS imager sensor CMOS imager sensor 2:1 Interlace2:1 Interlace | |
| S45 | (29) | AUK | DIP8 | 04+ | Hynix HYMD18M725A(L)6-K/H/L series is unbuffered 200-pin double data rate |
| S46 | (5) | 93 | Notes: 1. For Max. or Min. conditions, use appropriate value specified un | ||
| S47 | (13) | BEL | 2000 | Portable Instrumentation Automatic Test Equipment (ATE) Digital Offset a | |
| S48 | (39) | AMCC | BGA | 08+ | • Microchip's web site: www.microchip.com • Microchip's Techni |
| S49 | (14) | MOT | more than 99% when deselected (CE HIGH or both BLE and BHE are HIGH). The | ||
| S4A | (7) | (1) Power saving driver (2) Built in DA converter accepting 6 | |||
| S4B | (20) | TI | 07+ | This series of TTL DTL compatible MOS analog switches feature high speed | |
| S4C | (3) | Differential and Single-Ended Analog Input/Output Built-In Analog Functi | |||
| S4D | (22) | TI | 07+ | 1. Typical characteristics are at TA = 25oC.2. Fmax = 1/tRC . 3. These ar | |
| S4E | (6) | EPSON | 1. A17 is a NC for IDT70V3399. 2. All VDD pins must be connected to 3.3V | ||
| S4F | (6) | N/A | NOTES: 1. Both VCC pins must be connected to the power supply to ensure r | ||
| S4G | (1) | The XC62FP series is a group of positive voltage output, three-pin regul | |||
| S4H | (2) | N/A | DIP8 | 06+ | Fb (Bump B1): Output voltage feedback connection. The white LED string n |
| S4L | (13) | For alternating current, such as that from the mains, average power als | |||
| S4M | (1) | SGNEC | DIP-32 | 03+ | 1) Limited by junction temperature. Pulsed current is also limited by wir |
| S4N | (5) | MOT | SMD | The EB-2100x accommodates either a coaxial or an optical S/PDIF digital a | |
| S4P | (2) | MOT | SMD | Flexible serial port communication combinations 2 integrated USARTs 2 in | |
| S4S | (9) | LF(TEC) | DO-214 | 06+ | Information in this document is provided in connection with Conexant Syst |
| S4V | (6) | TW | A 75 Ω termination resistor with short traces should be attached be | ||
| S-5 | (26) | EVERLIGHT | 0403+ | s Up to 47 5 V tolerant general purpose I/O pins in tiny LQFP64 package. | |
| S5- | (1) | SIEMENS | 01+ | PLCC28 | MXIC's Automatic Programming algorithm requires the user to only write |
| S50 | (122) | MOSPEC | TO-3P | 04+ | |
| S51 | (34) | SOP16M | 2007+ | The MAX2640 and MAX2641 are ultra-low-noise ampli- fiers that operate wit | |
| S52 | (125) | 31 | TEMIC | 99+ | (2) Storage The LEDs should be stored at 30C or less and 70%RH o |
| S53 | (32) | N/A | SOP-8 | 02+ | The primary function of the HPC3130A is to allow noninterfering hot-plug |
| S54 | (272) | CDIP | The next value to choose is the Q factor. As dispersion is employ | ||
| S55 | (195) | BEL | 01+ | 1450 | Semelab Plc reserves the right to change test conditions, parameter limits |
| S56 | (43) | BEL | SOP | 9927+ | DISCUSSION OF TILT APPLICATIONS AND RESOLUTION Tilt Applications: One of |
| S57 | (31) | SIEMENS | . | TACHYON Architecture Tachyon TS continues with the TACHYON architectu | |
| S58 | (14) | BEL | SMD | 06+04+ | |
| S59 | (78) | TEMIC | SOT-143 | 1 Under all conditions, VDDQ must be less than or equal to VDD 2 Peak t | |
| S5A | (8) | For the most current package and ordering information, see the Package Op | |||
| S5B | (23) | Fifth Generation HEXFETs from International Rectifier utilize advanced p | |||
| S5C | (31) | Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, | |||
| S5D | (104) | SAMSUNG | DIP | Start Condition All commands are preceeded by the start condition, whic | |
| S5E | (2) | DIODES | DO214AB | 05 | Hynix HYMD564646(L)8-K/H/L series is unbuffered 184-pin double data rate |
| S5F | (9) | SAMSUNG | 05+ | Power Thyristor/Diode Module PK25FG series are designed for various recti | |
| S5G | (8) | SAMSUNG | DIP40 | 2001 | AL,BL,CL - Are the lowside logic level digital inputs. These three input |
| S5H | (16) | Note 2: The maximum power dissipation is dictated by TJMAX, JA, and the a | |||
| S5J | (9) | When the Transmit FIFO is bypassed (FIFOBYP is LOW), the TXFULL output c | |||
| S5K | (10) | DIODES | 08+ | Note 1) The specified condition Tj=25˚C means that the test should | |
| S5L | (153) | SAMSUNG | 0318+ | TQFP | Most modern speakerphones use half-duplex operation, which switches tra |
| S5M | (8) | MODULE | QtyDescription Resistors 610KΩ, 5% 1/4W, leaded 11KΩ, 5% 1/ | ||
| S5N | (29) | N/A | N/A | N/A | Propagation delay time high-to-low level output from A, B, C or D |
| S5P | (7) | dt71v632 | 99+ | TQFP1420-100 | SDRAM device attributes: Minimum clock delay back-to-back column access |
| S5R | (1) | The voltage regulator uses a p-channel MOS transistor as a regulating ele | |||
| S5S | (2) | TO-252 | for reads or writes to any location in memory. An automatic power down f | ||
| S5T | (21) | SAMSUNG | 2008 | Output Bit Driver Voltage Supply Ground Output Enable: HI = High Imped | |
| S5U | (3) | Testing of the switching parameters is modeled after testing methods spec | |||
| S5V | (5) | SSOP28 | 07+ | Current Limit Protection Isolation Test Voltage 5300 V RMS Typical RON | |
| S5X | (1) | The PICmicro family meets the specifications contained in the Microchip Da | |||
| S-6 | (12) | SMD-8 | 99 | When pin 23 (FIFO/DIR) has a logic "1" applied, the FIFO is in | |
| S6- | (1) | The 24XX32A supports a bidirectional, 2-wire bus and data transmission | |||
| S6. | (1) | • FullCduplex capability • External loopback mode allows testin | |||
| S60 | (159) | vangnard | vangnard | dc87+ | Working Standoff Voltages: 5.5 volts to 171 volts Metallurgi |
| S61 | (20) | AGILENT | 04+ | SOP8 | The LTC®4252 negative voltage Hot SwapTM controller allows a board to |
| S62 | (11) | ACST4-7S triggering current has to be sunk from the gate pin G. The switc | |||
| S63 | (45) | 94 | The DLYBLK input can be used to halt address generation at the end of a | ||
| S64 | (12) | JAPAN | ZIP-10P | Please be aware that an important notice concerning availability, | |
| S65 | (16) | AUK | 2008 | The Hitachi HM5112805F, HM5113805F are 128M-bit dynamic RAMs organized as | |
| S66 | (13) | N/A | N/A | N/A | Regulates voltage over a broad operating current and temperature range S |
| S67 | (17) | SOP | flying capacitor transfers charge to the COUT, elevating both the voltag | ||
| S68 | (50) | AMI | DIP40 | 2007+ | Guaranteed monotonic INL error: 4 LSB max On-chip 1.25 V/2.5 V, 10 ppm/C |
| S69 | (8) | 01+ | All unused inputs of the device must be held at VCC or GND to ensure pro | ||
| S6A | (69) | SAMSUNG | 06 | • 6A Output Current • Input Voltage Range: 3.1 V to 5 | |
| S6B | (92) | SAMSUNG | Each device includes a voltage regulator, two Hall transducers, temperatu | ||
| S6C | (10) | 2001 | SAMSUNG | 790 | a) Adopting new 4th generation planar IGBT chip, which per- forma |
| S6D | (11) | SAMSUNG | D/S | 05+06+07+ | 1. Hysteresis denotes the difference in forward LED current value |
| S6E | (2) | DIODES | DO214AB | 05 | Supply Voltage.-0.3V to 6.5V Voltage at any Pin.-0.3V to +Vs +0.3V Input |
| S6F | (2) | DIODES | DO214AB | 05 | It is not necessary to write to all the offset registers at one time. A |
| S6G | (2) | DIODES | DO214AB | 05 | Note 2: Absolute maximum ratings are those values beyond which damage to |
| S6J | (2) | TSC | DO214AB | 05 | The HCT646 devices consist of bus-transceiver circuits with 3-state outpu |
| S6K | (3) | TO-220 | For the most current package and ordering information, see the Package Op | ||
| S6M | (2) | DIODES | DO214AB | 05 | Two-Wire I2C Serial Interface Supports 400kHz Protocol Single Supply V |
| S6N | (4) | LF(TEC) | DO-214 | 06+ | Maxwell Technologies 28LV010 high density, 3.3V, 1 Megabit EEPROM microci |
| S6P | (1) | The transmitter accepts CMOS logic level clock (TCLK), positive data (TPO | |||
| S6R | (1) | HAR | SOT-23 | 00+ | Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 sec |
| S6S | (12) | LF(TEC) | DO-214 | 06+ | ‡ All typical values are at VCC = 5 V, TA = 25C. The output cond |
| S-7 | (87) | SEIKO | SOT-353 | 05+ | 1. Two coil latching relay 4C series are for intermittent operation only. |
| S70 | (46) | N/A | N/A | 98 | Meets or exceeds PC133 registered DIMM specification 1.1 Spread Spectru |
| S71 | (168) | IC | BGA | 04+ | Notes: 1. Repetitive Rating : Pulse width limited by maximum junction tem |
| S72 | (80) | seiko | seiko | dc97 | After power-on-reset, the ATA5275 is in standby mode. For minimum power c |
| S73 | (8) | S | DIP24 | 8243+ | For applications where efficiency is a prime consideration, the buck cont |
| S74 | (280) | Signetics | DIP-14 | 07+/08+ | The AD7818 and AD7817 are 10-bit, single- and 4-channel A/D converters w |
| S75 | (24) | HAMAMATSU | 2005 | ON Semiconductor andare registered trademarks of Semiconductor Components | |
| S76 | (12) | SOP | 01 | Atmel Colorado Springs, USA Atmel Nantes, France Atmel Colorado Springs, | |
| S77 | (8) | ROHM | QFP | 03+ | DESCRIPTION The STP25NM60N is realized with the second generation of MD |
| S78 | (26) | [H] | PLCC | en = Noise Voltage of the Transistor referred to the input. (Figure 3) & | |
| S79 | (22) | AUK | TO-220 | 04+ | PWM Current Limit for Short Circuit Protection Over-Temperature Protect |
| S7A | (5) | Each VR has its own VR latch, which holds its programmed resistance valu | |||
| S7B | (8) | TYPE | N/A | 2004 | The 32 registered macrocells in the GLB are driven by the 32 outputs fr |
| S7C | (8) | N/A | N/A | 04+ | The MAX4641/MAX4642/MAX4643 are monolithic, dual, single-pole/single-thro |
| S7D | (4) | EPSON | QFP1420-100 | Notes: 1. Unless otherwise specified, these specifications apply for (VI | |
| S7H | (1) | The RC4700 ALU consists of the integer adder and logic unit. The | |||
| S7L | (1) | Main CLK(Hz)Under 3.58M14.3M Operating Voltage(min)2.2V3.6V | |||
| S7N | (3) | ST | SOP-3.9-8P | 6+ | The CS61880 is a full-featured Octal E1 short-haul LIU that supports 2. |
| S7P | (2) | MOT | SMD-8 | 95+ | Product Description/Features: • Low skew, low jitter PLL clock dri |
| S7S | (1) | SOP8 | A random read requires a dummy byte write sequence to load in the data wo | ||
| S7W | (1) | floeth | floeth | dc99 | Serial data for this mode is entered at the shift-right data input When |
| S-8 | (2950) | SEIKO | SOT-153 | Hynix HYMD264G726(L)4M-K/H/L series incorporates SPD(serial presence detec | |
| S8- | (1) | N/A | For proper operation, a 0.1µF or greater bypass capacitor must be | ||
| S80 | (576) | N/A | N/A | 04+ | Once in synchronization, the falling edge of the reference signal (C8Kb or |
| S81 | (136) | SEIKO EPSON | SOT23 | 0515+ | The device is manufactured using Atmels high-density nonvolatile memory t |
| S82 | (324) | HIT | 0433+ | TSSOP14 | The BS616LV4018 is a high performance, very low power CMOS Static Random |
| S83 | (111) | N/A | TSSOP8 | ||
| S84 | (61) | MITSUMI | DIP | The PCI subsystem is a bus master interface that performs the memory acce | |
| S85 | (44) | seiko | seiko | dc99 | The 556C/W for the SOTC23 package assumes the use of the recommen |
| S86 | (21) | 1 | As shown in Figure 1, the Sequence Generator is subdivided into the addr | ||
| S87 | (250) | S/PHI | CWDIP40 | 96 | The FS6322 is a ROM-based CMOS clock generator IC designed to minimize co |
| S88 | (42) | LITTELFUSE | SOT-89 | 05+ | The algebraic convention is used in this data sheet; the most negative val |
| S89 | (28) | AMCC | BGA | VIN and VOUT Limited Only by External Components Adjustable Slope Compens | |
| S8A | (4) | LEI | SOP/18 | 00+ | There are dishonest and possibly illegal methods used to breach the code |
| S8B | (6) | JST | 07+ | The addition of software reset enables recovery from unforeseen error co | |
| S8C | (1) | QFP | TJ=PD X (RJC +RCS +RSA) +TA Where TJ=Junction Temperature & | ||
| S8D | (3) | stock | The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, | ||
| S8E | (5) | The TSH8x serie offers Single and Dual opera- tional amplifiers featuri | |||
| S8G | (1) | This manual includes hardware details and programming information for the | |||
| S8H | (1) | S | 218 | Drop-in replacement for IBM AT computer clock/calendar Pin compatible wi | |
| S8I | (2) | VISHAY | C.T 3L | 2007 | The PTH03000 series of non-isolated power modules are small in si |
| S8J | (3) | ||||
| S8M | (3) | SGNEC | DIP-28 | 04+ | Suffix denotes Vz tolerance: non suffix for 20%, A suffix for 10%. Measu |
| S8N | (2) | ST | SMD | 04+ | THEORY OF OPERATION The MEMSIC device is a complete dual-axis accelerati |
| S8O | (1) | 08+ | The AHC138 decoders/demultiplexers are designed for high-performance memo | ||
| S8P | (4) | 73 | SONIX | O6 | The DS1330 256k NV SRAMs are 262,144-bit, fully static, NV SRAMs organized |
| S8S | (1) | NSC | nation for the bus as follows. If the DIFSENS signal is below 0.5V, the | ||
| S8T | (14) | floeth | floeth | dc93 | Life Support Applications These NEC products are not intended for use i |
| S8U | (1) | SEMTECH | SOP-8P | 409 | Description The S8ULCC05-2 is an interline CCD solid-state image |
| S8V | (61) | SAMSUNG | 00+ | DESCRIPTION The S8V67ZVFI, S8V67ZVSP is a monolithic high voltage integ | |
| S-9 | (107) | SEIKO | 04 | The LTC®1709-7 is a 2-phase, VID programmable, synchro- nous step-dow | |
| S9- | (1) | HARR | 2008 | If the 1-Wire port is used, the memory functions will not be available unt | |
| S90 | (88) | SANYO | 05+/06+ | High Efficiency: Up to 95% Very Low Quiescent Current: Only 40µA 2 | |
| S91 | (37) | N/A | In general, a higher operating frequency decreases the peak ripple curre | ||
| S92 | (35) | 2008 | Output clock data format C Controls the output clock (ODCK) format for ei | ||
| S93 | (104) | NSC | PLCC20 | 03/+04+ | The IALUs have hardware support for circular buffers, bit reverse, and z |
| S94 | (55) | SUMMIT | 98 | Clocks in the ispLSI 2032 and 2032A devices are se- lected using the de | |
| S95 | (37) | SANYO | DIP-40 | 07+/08+ | 1. These values of VI are used to test DC electrical characteristics only |
| S96 | (17) | SC | PLCC | 07+ | Use with 10 to 14-bit A/D converters 5 Megapixels/second minimum throughp |
| S97 | (31) | NSC | DIP48 | Chroma Output/Green Output A 75 Ω termination resistor with short t | |
| S98 | (22) | 97+ | INF | 2 | IOB has more versatile clocking polarity options. IOB has programmable in |
| S99 | (41) | SPANSION | BGA | 06+ | Features NPT IGBT technology low saturation voltage l |
| S9A | (1) | External Load Capacitance Output Current (At IO < IO, min, the | |||
| S9B | (7) | 13 | 2005 | ||
| S9C | (2) | • 3V, single power supply operation - Full voltage range: 2.7-3.6 | |||
| S9E | (1) | MOT | BGA | 1 | Similarly, the bq24400 suspends fast charge if the battery temperature i |
| S9F | (1) | TOSHIBA | SMT | 96+ | The Fairchild Power Switch(FPS) product family is specially designed for |
| S9G | (4) | TOSHIBA | (LX)high-frequency | 256K x 4 advanced high-speed CMOS static RAM JEDEC revolutionary pinout ( | |
| S9N | (2) | ST | SMD | The AMI signal first enters a fixed equalizer, which is designed to overc | |
| S9P | (1) | For DC coupled single supply operation, it is recom- mended that input | |||
| S9S | (1) | By this setting, the function of F0/DATA, F1/REQ, and F2/SCK are changed. | |||
| S9X | (1) | SUMMIT | SOP-8 | 03+ | This INFINEON module is an industry standard 144 pin 8-byte Synchronous D |
| S9Z | (1) | MOT | TSSOP | 1) CPD is defined as the value of the ICs internal equivalent capacitance | |
| S-A | (46) | The internal circuit is composed of 3 stages including buffer output, w | |||
| SA- | (41) | JDS | module | • N channel FET switches with no parasitic diode to VCC C I | |
| SA/ | (4) | PHI | SOP16S | 06+ | Low skew: < 200ps Fast switching frequency >133 MHz Fast output |
| SA0 | (54) | NS | DIP | 86 | The charge pump is a doubler configuration that uses one external flying |
| SA1 | (536) | AVX | 2.2.1 Specifications and standards. The following specifications a | ||
| SA2 | (175) | SAIFUN | SOP8 | 05+ | Ground. Oscillator input. Oscillator output. Active high reset. (with i |
| SA3 | (166) | SA全系列专营 | 07/08+ | 4. Values for two Turn-On loss conditions are shown for the convenience o | |
| SA4 | (76) | AVXCOPR | Stresses beyond those listed under Absolute Maximum Ratings may cause perm | ||
| SA5 | (711) | PHILIPS | SOT23-5 | 0335+ | MISCELLANEOUS PERFORMANCE input capacitance input resistance |
| SA6 | (280) | PHI | STK | 2005+ | Caveat: This calculation has assumed that the voltage drops due to the v |
| SA7 | (109) | SA全系列专营 | 07/08+ | RJC Thermal Resistance (Output Switches)1.5C/W RJC Thermal Resistance (Re | |
| SA8 | (154) | SA全系列专营 | 07/08+ | Circuit Board Material: Top RF layer is .014 Getek, 4 total layers (0.062 | |
| SA9 | (115) | SILAN | 06+ | SOP/16 | A start may be issued to terminate the input of a con- trol byte or the |
| SAA | (2265) | PHILPS | DIP | DIP | Typicals represent average readings at 25C and VDD = 5 V. |
| SAB | (1686) | N/A | DIP | † Stresses beyond those listed under absolute maximum ratings may c | |
| SAC | (80) | MOTOROLA | 2007 | When no data transfer occurs, you can use the Powerdown state. The Seri | |
| SAD | (39) | 91 | The HC670 and CD74HCT670 are 16-bit register files organized as 4 words | ||
| SAE | (45) | SIEMENS | 06+ | 500 | Note 1: Absolute maximum ratings are DC values beyond which the device m |
| SAF | (988) | muRata | In the Write mode (See fig6A, p.9), the clock gen. acknowledges Address B | ||
| SAG | (36) | QFP- | These devices employ the Schottky Barrier principle in a large are | ||
| SAH | (53) | SIEMENS | 0834++ | NOTES: A. CL includes probe and test-fixture capacitance. B. Wave | |
| SAI | (14) | SOP4 | 2003 | • Control and safety devices for airplanes, trains, automobiles, and | |
| SAJ | (19) | sie | sie | dc89 | All parameters measured at fMAX unless noted otherwise. NOTE 1: Assumin |
| SAK | (423) | inf | 0 | 458/tray/qfp | Note 1 These AC characteristics are guaranteed with external clock drive |
| SAL | (39) | MINI | 08+ | This new option of integrated digital transistors is designed to | |
| SAM | (148) | SAM | 1994 | QFP | †The MAX6326/MAX6327/MAX6328/MAX6346/MAX6347/ MAX6348 are available |
| SAN | (10) | N/A | SOP- 8 | The Programmable Interconnect Matrix (PIM) consists of a completely glo | |
| SAP | (41) | 04+ | SOP/18 | for reads or writes to any location in memory. An automatic power down f | |
| SAQ | (1) | MURATA | 07+ | Sets the oscillator frequency and maximum duty cycle Frequency modulati | |
| SAR | (24) | QFP208 | Single LEDs are often driven using either a high side or low side | ||
| SAS | (27) | TI | SOP14 | -Port 92 Support -Fast Gate A20 and KRESET Outputs Serial Ports -Two Fu | |
| SAT | (39) | Other | 07+ | V2 Voltage Fail Output. This open drain output goes LOW when V2MON is les | |
| SAU | (2) | EXAR Corporation does not recommend the use of any of its products in lif | |||
| SAV | (5) | TOSHIBA | MOUDLE | N/A | In Case 1 of Figure 3, the signal from the DSX-3 cross-connect feeds di |
| SAW | (24) | SAWTEK | 00+ | Finally, the CY7C372i features a very simple timing model. Unlike other h | |
| SAY | (25) | MINI | 08+ | With every advance of this magnitude, there arise new considerations th | |
| S-B | (2) | TBGA | All information contained in this document is subject to change without n | ||
| SB- | (18) | LUCENT | PLCC-28 | 9749 | Two-frame transmit and receive PCM slip buffers Clock rate adapter synth |
| SB( | (1) | Junction CapacitancepF Test Conditions: f = 1 GHz Video Resistancek͐ | |||
| SB0 | (280) | SANYO | SOT-23 | ECOS1VA332AA ECOS1VA392AA ECOS1VA472AA ECOS1VA152BL ECOS1VA152BA ECOS | |
| SB1 | (247) | GS | TO-220 | 07+ | Figure 1 shows a block diagram of the 80C186EB 80C188EB The Execution Un |
| SB2 | (199) | SANYO | 08+ | The total power consumption is then simplified to: Total Power = (CPD + | |
| SB3 | (172) | SMD | 1993 | 2.1 General. The documents listed in this section are specified in | |
| SB4 | (32) | 12 | ATI | O6 | NOTES: (1) Junction Temperature = Ambient Temperature for low temperature |
| SB5 | (85) | FSC | DO214A | 06+ | These signal conditioners are designed to provide an easy and convenient |
| SB6 | (71) | . | The power dissipation of the SOTC23 is a function of the drain pa | ||
| SB7 | (13) | SANYO | NOTES: 1. Input voltages may exceed the supply voltages provided the inpu | ||
| SB8 | (216) | INTEL | 9714 | The CS8920A is a low-cost Ethernet LAN Control- ler optimized for Indus | |
| SB9 | (3) | Notes: (1) Measured with baluns on the input and output of the device. ( | |||
| SBA | (52) | SANYO | 01+ | SMD | OUTPUT VOLTAGE LIMITERS Default Limiter Voltage Minimum Limiter Separa |
| SBB | (23) | SIRENZA | N/A | 06+ | The current source provides a closely regulated zener current, wh |
| SBC | (44) | AUK | 96 | 2N73734581008.55.05.010-65 to +200 Derate linearly 22.8 mW/qC for TA &g | |
| SBD | (3) | S | TO- | Data flow from A to Y is controlled by Output Enable (OE). The device op | |
| SBE | (32) | SANYO | SOT-163 | 05+NOPB 5k | NOTES: 1. Dimensions are in inches. 2. Metric equivalents ar |
| SBF | (40) | 04+ | Functional Description Hardware USB Interface Transceiver Interface E | ||
| SBG | (34) | TO-220 | All of the bytes in the chip must be verified to check whether they have | ||
| SBH | (6) | SANYO | SOD-123 | 04+ | CASE: Molded, surface mountable TERMINALS: Gull-wing or C-bend (modified |
| SBI | (5) | ZILOG | 00+ | The input/output pins (I/O1 through I/O16) are placed in a high-impedan | |
| SBJ | (2) | GS | ISENSE: This is the input to the X10 wide bandwidth current-sense amplifi | ||
| SBK | (68) | N/A | Supply Voltage Input. From it a stable internal reference voltage VREF an | ||
| SBL | (226) | GSI | TO-220 | 05+ | The Thermal DF Series Thermal Cutoffs are single action devices th |
| SBM | (41) | DIODES | SMB-3 | 05+ | |
| SBN | (27) | GIE | TO-220 | 05+ | Receive master clock. Must be 1.536 MHz, 1.544 MHz or 2.048 MHz. May be |
| SBP | (58) | GIE | TO-220 | 05+ | |
| SBQ | (7) | (For a single-phase input unit) An example of the I/O voltage characteri | |||
| SBR | (133) | DIODES | ITO-220AB | 07+ | The MTC20136 is a dedicated controller chip, spe- cifically designed to |
| SBS | (63) | GIE | TO-220 | 05+ | The product term allocator is a dynamic, configurable resource that shift |
| SBT | (74) | MINI | 08+ | The A128 devices contain the following: • ARM7TDMI 16/32-Bit RISC | |
| SBU | (9) | TOS | 01+ | QFN/4*13 | CAUTION: The BiCMOS inherent to the design of this component increases the |
| SBV | (3) | DC Supply Voltage Reverse DC Supply Voltage DC Reverse Ground Pin Cur | |||
| SBW | (5) | NINEX | 02+ | Output Capacitors (Optional) For applications with load transients (sudd | |
| SBX | (53) | SONY | 1997 | The TLE 4299 is a monolithic voltage regulator with fixed 5-V output, sup | |
| SBY | (73) | 2008 | There are five Voltage Identification Pins, VID4-VID0, on the | ||
| S-C | (2) | TEMIC | 01+ | PLCC44 | NOTE: EP circuits are designed to meet the DC specifications shown in the |
| SC- | (82) | 99 | • Solid-state Relay (Equivalent to AQW210S) - Typical RON 2 | ||
| SC( | (1) | PHILIPS | 05+ | The ADP3419 includes an anticross-conduction protection circuit, undervo | |
| SC. | (1) | The LM75 is a temperature sensor, Delta-Sigma analog-to- digital conver | |||
| SC/ | (1) | ♦ Features • Generates high frequency clock from a high stabi | |||
| SC0 | (179) | FUJI | SMA | 05+ | Timer Clearing A negative edge or pulse at the TCL input longer than 15 |
| SC1 | (1872) | SC | SOP | 97P3 | • SuperBIG HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC |
| SC2 | (614) | MITSUBISHI | 805 | This document is a general product description and is subject to change wi | |
| SC3 | (525) | MOTOROLA | 83+ | CDIP40 | This pin is active only when the chip transmits tone dialing signals. Othe |
| SC4 | (1819) | OKI | SOP | 02+ | NOTE: Device will meet the specifications after thermal equilibrium has b |
| SC5 | (868) | MOT | 02/03+ | PLCC52 | • Plastic package has Underwriters Laboratory Flammability |
| SC6 | (390) | MOTOROLA | CAN8 | The QS4A205 is a high-performance CMOS analog Four-Channel SPDT m | |
| SC7 | (505) | The input sample period is defined between rising edges of wordclock (WD | |||
| SC8 | (447) | N/A | PLCC44 | 06+ | HyperPHY transceiver technology includes a full clock recovery mec |
| SC9 | (302) | SC | SOP | 03/+04+ | The ISL43140/ISL43141/ISL43142 are quad single-pole/ single-throw (SPST |
| SCA | (243) | NS | 07+ | AND Flash Memory: (2048 + 64) bytes (More than 16,057 se | |
| SCB | (52) | PHIL | 05+ | Analog Overvoltage input. When OV is pulled above the 1.223V threshold, an | |
| SCC | (322) | PHI | 96+ | SOP | These devices consist of four independent high-gain frequency-compensat |
| SCD | (197) | N/A | The IDT5T907 2.5V single data rate (SDR) clock buffer is a user-se | ||
| SCE | (22) | CONEXANT | QFP | 99+ | |
| SCF | (29) | MOTOROLA | QFP | Since the 1996 model year, North American automobiles have been | |
| SCG | (19) | SHARP | TQFP-M120P | 6+ | en = Noise Voltage of the Transistor referred to the input. (Figure 3) & |
| SCH | (74) | SMSC | 05+ | QFP | |
| SCI | (227) | SEIKO | SOT-89 | 05+ | When only the S1 pin is at a logic one the temperature measuring |
| SCJ | (5) | ON | 02+ | TOP BOOT SECTOR LOCK: When the TBL pin is held low, program and erase ope | |
| SCK | (17) | 2001 | Hynix HYMD216646(L)6-K/H/L series is designed for high speed of up to 133M | ||
| SCL | (361) | SCL | 96 | Efficient 16-bit 56800 family controller engine with dual Harvard archite | |
| SCM | (187) | CHENMKO | Electrical Characteristics AVIN = PVIN = 5V unless otherwise indicated un | ||
| SCN | (280) | Notes: 1: VC1,VC2, VM12 = 3.3V, TC = 25C, 50Ω system. 2: Bias cur | |||
| SCO | (195) | SUNNY | Information provided by Graychip is believed to be accurate and re | ||
| SCP | (53) | SSS | DIP | 03+ | 2. Indirect addressing resources (registers and initial load memory) &nb |
| SCQ | (25) | MOT | • Speziell geeignet fr Anwendungen im Bereich von 400 nm bi | ||
| SCR | (94) | N/A | Wave shaping is incorporated into the transmitter to minimize EMI radiate | ||
| SCS | (70) | 04+ | MSOP8 | † The D packages are available taped and reeled. Add R suffix to de | |
| SCT | (29) | If a specific pattern is repetitive, the Deserializer could enter false | |||
| SCU | (2) | 50 | ATMEL | These Ultrafast, soft recovery diodes are optimized to reduce losses and | |
| SCV | (23) | MOTOROLA | 07+/08+;0729+ | For convenience, a sample of the LM2650 and eight other components have | |
| SCW | (17) | N/A | The CY22393, CY22394, and CY22395 are a family of parts designed as upgra | ||
| SCX | (558) | NSC | 98 | NOTES: 1. See Test Conditions under TEST CIRCUITS AND WAVEFORMS. 2. Thi | |
| SCY | (52) | ON | SOP24 | Maximum Recurrent Peak Reverse Voltage Maximum RMS Voltage Maximum DC | |
| SCZ | (4) | freesc | freesc | dc0647 | Description Reserved PCI6 Output Control 1 = enabled, 0 = forced LOW P |
| SD | (1) | The HIP6017 includes an Intel-compatible, TTL 5-input digital-to-analog | |||
| S-D | (1) | OKI | QFP-44 | 3.9 Verification and review for device class M. For device class M | |
| SD- | (74) | The shaft locking device consists of a tapered nut tightening a slotted | |||
| SD0 | (63) | (空白) | 1206 | Operating Temperature Range (Note 2) LM136−55˚C to +15 | |
| SD1 | (515) | AE | 06+/07+ | Always use semiconductor devices within their recommended operating condi | |
| SD2 | (165) | IR | DO-200AB (B-Puk) | 00+ | Data flow from A to Y is controlled by Output Enable (OE). The device op |
| SD3 | (82) | NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected w | |||
| SD4 | (87) | IR | B-8 | 00+ | Soft−Start Timing control pin. An external soft−start capacit |
| SD5 | (160) | VISHAY | SOP-14 | 95+ | the device has a Sector Protect function which hardware write protects |
| SD6 | (96) | MOT | 01+ | TO-3 | PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFER |
| SD7 | (91) | neosid | neosid | dc94 | • Internal self-timed write cycle • Individual Byte Write C |
| SD8 | (58) | IR | B-43 (E-Puk) | 00+ | Packaged in the new innovative 3mm x 2mm MLP this combination dual compr |
| SD9 | (14) | TAIWAN | DIP-14P | 6+ | Signal input pin. A internal matching circuit, configured with resisto |
| SDA | (1030) | micronas | micronas | dc00 | All data transfers are initiated after CS goes LOW and a logic 1 is clo |
| SDB | (65) | MCC | 07+ | The LTC6101 monitors current via the voltage across an external sense res | |
| SDC | (169) | ADI | 07+ | The MAX1589A low-dropout linear regulator operates from a +1.62V to +3.6V | |
| SDD | (25) | MSC | SOP-8 | 00+ | The IDT72V3623/72V3633/72V3643 are pin and functionally compatible |
| SDE | (28) | SIEMENS | Note: Hitachis serial EEPROM are authorized for using consumer applicatio | ||
| SDF | (31) | MSC | SOP-8 | 00+ | CEL certifies, to its knowledge, that semiconductor and laser products de |
| SDG | (32) | SIL | . | Tangent of loss angle: 5000 pF < C 20000 pF 20000 pF & | |
| SDH | (16) | MSC | SOP-8 | 00+ | Out Short Circuit to GND Duration (VIN< 12V)...Continuous Out Short Ci |
| SDI | (34) | crydom | crydom | dc00 | The device incorporates auto-calibration and built-in self-test (BIST) ro |
| SDJ | (1) | TOSHIBA | Figure 17-4. Figure 18-1. Figure 18-2. Figure 18-3. Figure 19-1. Figu | ||
| SDK | (25) | schurter | schurter | dc00 | The 80C186XL provides a local bus controller to generate the local bus c |
| SDL | (30) | MSC | SOP-8 | 00+ | This series of hermetically packaged products feature the latest advanced |
| SDM | (154) | N/A | N/A | N/A | The product can also be used for general analog signal isolation applica |
| SDN | (13) | FAIRCHILD | 2004 | SOT-3 | The OPA682 provides an easy to use, broadband fixed gain buffer amplifie |
| SDO | (4) | SEMITECH | 02+ | ||
| SDP | (92) | INFINEON | TO-220 | 05+ | The CY7C9689 HOTLink Transceiver is a point-to-point com- munications b |
| SDQ | (8) | OEL | 05+ | Applying loads outside of the specified output range may result in uninte | |
| SDR | (104) | Note 4: Receiver Skew Margin is defined as the valid data sampling region | |||
| SDS | (113) | AUK | SOT-23 | 05+ | ISOLATION PARAMETERS Rated Voltage, Continuous Partial Discharge, 100% |
| SDT | (255) | 08+ | International Rectifiers RADHard HEXFET® technol- ogy provides high p | ||
| SDU | (11) | CEM | 05+ | 2.2.1 Specifications, standards, and handbooks. The following spec | |
| SDV | (14) | AUK | 0805-V8 | When pin CPH exceeds 5.1V, the IR21592 enables the over-current protectio | |
| SDW | (21) | MITSUBISHI | MODULE | N/A | ispVHDL™ Systems VHDL/Verilog-HDL/Schematic Design Options Funct |
| SDX | (36) | HOWELLEY | SENSOR | N/A | CAUTION: These devices are sensitive to electrostatic discharge; f |
| SDZ | (7) | AUK | 23-33V | 04+ | The chopper stabilization technique uses a 170 kHz high frequency clock. |
| S-E | (3) | CENTILLIUM | O7+ | • High self-resonant frequency values. • High Q values at hig | |
| SE- | (12) | SERVEENGINES | 06+ | BGA | * Specifications will vary with foreign standards certificati |
| SE0 | (95) | DN | Room = 25C, Full = as determined by the operating suffix. Typical values | ||
| SE1 | (125) | DENSO | DIP16 | 91 | The NetPHY™ 4LP devices on-chip input filtering and output waveshap |
| SE2 | (100) | D | O7+ | Power supply voltage VCCs = 2.7 V~3.6 V VCCf = 2.7 V~3.6 V | |
| SE3 | (70) | DENSO | SOP | The ISD5008 series is also ideal for playback-only applications, where s | |
| SE4 | (62) | SiGe | 56 | Couples AC and DC signals 0.01 % Servo Linearity Wide Bandwidth, > | |
| SE5 | (256) | N/A | SOP16 | N/A | *Part Numbers listed are for units with outer plastic-film insulation and |
| SE6 | (69) | MOT / ST | CAN3 | 01+ | eight-pin, hermetic, dual-in-line, ceramic packages. The devices opera |
| SE7 | (53) | D | SMD-8 | . . . employing the Schottky Barrier principle in a large area me | |
| SE8 | (50) | MOT | CAN3 | The TLC3704C is characterized for operation over the commercial tempera | |
| SE9 | (38) | MOT | 01+ | TO-3 | To streamline development time, JTAG-compliant scan-based emulation has b |
| SEA | (31) | The pressure is monitored by a voltage comparator, which compares | |||
| SEB | (2) | ST | DIP-28 | Altera® ACEX 1K devices provide a die-efficient, low-cost architectur | |
| SEC | (150) | SIEMENS | 96/97+ | PLCC84 | The SEC51C805-8.0E2C devices combine 10-bit CMOS shift registers, |
| SED | (276) | EPSON | QFP | 99+ | If an output channel is set to three-state condition, the TDM serial strea |
| SEE | (8) | KYOCERA | SOP | 94+ | The MSK 3017 is an all N-Channel three phase power MOSFET Bridge C |
| SEF | (12) | JRC | SOP8 | N/A | Fully Differential Architecture Centered Input Common-mode Range Minimum |
| SEG | (14) | SOP | 94 | The SEGA315-5289CSEGA315-5289 have internal termination resistors for use | |
| SEH | (6) | SHOFI | 1994 | Operating from a wide-input voltage range of 7 V to 36 V, the PTN78000 pr | |
| SEI | (12) | IC | SOP | Package[1] A: 7.6 mm (0.3 inch) Single Digit Seven Segment Display F: | |
| SEJ | (4) | . | SOT-23 | 05+/06+ | Modulus control output for controlling an external dual-modulus prescaler |
| SEK | (7) | EPSON | 2008 | Notes: 1. For Max. or Min. conditions, use appropriate value specified u | |
| SEL | (49) | The clear function for the LV163A devices is synchronous. A low level at | |||
| SEM | (161) | SEMIKRON | 311A/1200V/IGBT/2U | The 78ST100 is a series of wide input voltage, 3-terminal Integra | |
| SEN | (13) | SEN | DIP | NOTES: 1. 'X' in part numbers indicates power rating (S or L). 2. VCC = | |
| SEO | (2) | ALCATEL | 06+ | 500 | The TPS736xx family of low-dropout (LDO) linear voltage regulators uses |
| SEP | (40) | Notes: 1. Measurements taken on 50Ω test board shown on Figure 1. E | |||
| SEQ | (1) | Updated values in Current Consumption per Power Supply Pin, Table | |||
| SER | (34) | N/A | The WCFS0808V1E is a high-performance 3.3V CMOS Static RAM organized as 3 | ||
| SES | (17) | PHI | QFP | 2005 | The third step is the internal Program operation which is initiated after |
| SET | (15) | DOWA | Logic and internal gate drive supply voltage Oscillator timing resistor | ||
| SEV | (2) | Notes: Repetitive rating; pulse width limited by max. jun | |||
| SEW | (3) | ON | SOP | 107 | Two times of receiving check Built-in oscillator needs only a 5% resisto |
| SEX | (1) | SIPEX | 04+ | TR6 | In ES series models, flag M1083 is not provided. When FROM/TO instruction |
| S-F | (3) | N/A | N/A | Each sense amp consists of 1K bytes of fast storage (512 bytes for DQA | |
| SF- | (58) | N/A | *Stresses greater than those listed above may cause permanent damage to th | ||
| SF/ | (1) | NOTES: 1. For conditions shown as Max. or Min., use appropriate value sp | |||
| SF0 | (62) | NEC | 03+ | 225 | * All specs and applications shown above subject to change without prior |
| SF1 | (310) | SOP16W | 2007+ | The TSOP48..ON1 - series are miniaturized receivers for infrared remote | |
| SF2 | (116) | SHINDENGEN | TO-220F | 05+ | Quad channel Low-Side-Switch (2x5A/2x3A) in Smart Power Technology (SPT) |
| SF3 | (126) | TW SEMI | N/A | 03+ | The MSA-series is fabricated using Agilents 10 GHz fT, 25 GHz fMAX, sil |
| SF4 | (46) | N/A | 00+ | DIP-18 | Boot Blocks : The two boot blocks are intended to replace a dedicated bo |
| SF5 | (106) | TOS | TO-220 | 04+ | These ICs are analog stereo enhancement processors. They use patented Q Xp |
| SF6 | (32) | 96 | Advanced submicron CMOS technology makes the Am79Q02/021/031 QSLAC devi | ||
| SF7 | (14) | CAN4 | The MBRS320TRPbF surface-mount Schottky rectifier has been designed for a | ||
| SF8 | (40) | To overcome this limitation, TI design engineers developed the patented E | |||
| SF9 | (16) | SAM | PQFP48 | 2007+ | Surface mount equivalent to 1N4728 to 1N4764A Ideal for high-density and |
| SFA | (39) | CET | TO | The chip supports an optional start and stop bit (either 0 or 1) that p | |
| SFB | (20) | N/A | Notes: 1. For Max. or Min. conditions, use appropriate value specified u | ||
| SFC | (246) | SESCOSEM | 2008 | Hynix HYMD264646B(L)8J-J series is designed for high speed of up to 166MHz | |
| SFD | (38) | N/A | Notes: 1. CL = Load capacitance: includes jig and probe capacitance. | ||
| SFE | (132) | MOT | 2008 | CPU output type select latch input pin 0= K7, 1= CK408 / AGP clock output | |
| SFF | (21) | TSC | TO | To achieve the same timer Reset period on the PIC18F8490 family as the | |
| SFG | (34) | NS | PLCC | 89+ | Guaranteed by design and characterization. ESD voltage applied between |
| SFH | (1257) | sie | sie | dc94 | since an approaching finger could be compensated for partially or entire |
| SFI | (117) | N/A | FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN | ||
| SFJ | (5) | ||||
| SFK | (1) | The information provided herein is believed to be reliable at press time. | |||
| SFL | (2) | N/A | QFP | 96+ | The Bay Linear B3800 series is monolithic control circuit containing th |
| SFM | (98) | FORMOSA | 06/07+ | Analog output. The output signal amplitude is a maximum of 2.4 VPP above | |
| SFN | (1) | Reference Acknowledgement (REF_ACK) Output The REF_ACK (reference acknowl | |||
| SFO | (21) | JST | na | Serial data input; receives serial data from the control device; serial d | |
| SFP | (166) | SANKENC | 08+ | • Single 3.3V 0.3V power supply • All device pins are LVTTL c | |
| SFR | (228) | FAIFCHILD | TO-251/252 | 04+ | As load current is reduced, the energy required in the inductor diminis |
| SFS | (126) | VISHAY | TO- | Parameter REFERENCE INPUTS REFIN(+) to REFIN(C) Voltage1, 9 &nbs | |
| SFT | (107) | murata | murata | dc00 | Once the supplies are above the UVLO threshold, the soft-start ca |
| SFU | (37) | FAIRCHLD | TO-251 | 05+ | |
| SFV | (40) | FCI | SMD | 4 | Positive digital power supply. Ring oscillator/crystal input pin. Rese |
| SFW | (99) | HARRIS | TO-263 | The 512Mb DDR SDRAM uses a double-data-rate archi- tecture to achieve h | |
| SFX | (17) | SAMSUNG | 03+ | QFN | The STR73xF requires an external 4.5 to 5.5V power supply. There are two |
| SFY | (3) | N/A | N/A | The bq2085 uses an integrating converter with continuous sampling for t | |
| SFZ | (4) | MURATA | The HSDL-3600 is a low-profile infrared transceiver module that provid | ||
| S-G | (1) | INTERFACE TIMING CHARACTERISTICS Applies to All Parts6, 11 Input | |||
| SG- | (429) | KODENSHI | Power Thyristor/Diode Module PK90F series are designed for various rectif | ||
| SG0 | (22) | SGA | 04+ | The SG0102/M1 is a low-cost, digitally controlled, variable gain ampli- | |
| SG1 | (522) | SG | DIP-16 | 6+ | The information provided herein is believed to be reliable at press time. |
| SG2 | (320) | 1850 | Drain-to-Source Breakdown Voltage Gate Threshold Voltage Gate-to-Sourc | ||
| SG3 | (380) | LINFINITY | DIP | DIP | • An accelerated 80C51 CPU provides instruction cycle times |
| SG4 | (37) | SanKen | SOP | Because it is a synchronous device, address, data inputs, and read/ writ | |
| SG5 | (378) | SILICON | SOP | 9748 | For the device-specific interrupt priority configurations, see the Interr |
| SG6 | (503) | SG /SYSTEMGE | 05.04+ | DIP-8 | Pin NamePin TX Data 031 TX Data 147 TX Data 25 TX Data 38 TX Data 410 |
| SG7 | (213) | SG | TO-2P | 6+ | C Program entire chip in 10-25 seconds with no in- volvement of t |
| SG8 | (133) | EPSON | SOIC/3.9mm | 20+ | Common Flash Memory Interface (CFI) The SST39VF160Q/VF160 also contain t |
| SG9 | (23) | SG | 04+ | On a single 5V supply, the LT1990 has an adjustable 85V input range, 70dB | |
| SGA | (215) | RFMD(Sirenza) | 07+ | The DDU4C tolerances are guaranteed for input pulse widths and periods gr | |
| SGB | (35) | INFINEON | 07+ | The devices come in 8- and 10-bit resolution versions (see Figure 2 for | |
| SGC | (19) | N/A | Case: JEDEC TO-220AC, ITO-220AC & TO-263AB molded plastic body Term | ||
| SGD | (18) | FAIRCHILD | TO-252 | 08+ | The transceiver contains a supervisory circuit to control the power supp |
| SGE | (16) | SG | SOP-7 | 6+ | The sensors include a temperature-compensated Hall plate with active of |
| SGF | (36) | FAIRCHILD | TO-3PF | 08+ | HIGH SPEED: tPD = 9ns (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC = |
| SGH | (96) | YAMAHA | QFP | 04+ | PROBES The circuit effectively measures the thermal resistance of the p |
| SGI | (5) | INFINEON | 0703+ | TO-262 | INVALID OP-CODE: If an invalid op-code is received, no data will be shif |
| SGJ | (5) | LINFINITY | CERDIP-14 | 98+ | Stresses beyond those listed under absolute maximum ratings may cause per |
| SGK | (1) | NS | PDIP | 06+ | Internal Organization When ORG is connected to VDD or ORG is floated, the |
| SGL | (133) | SIRENZA | Intersils Satellite Applications(SAF) devices are fully tested and guar | ||
| SGM | (96) | SONY | SOT-343 | Output channel data strobe input terminal: in the Normal Mode phase, seri | |
| SGN | (9) | ST | QFP | NOTES: JA is specified for worst case mounting conditions, i.e., JA is s | |
| SGP | (56) | LINFINITY | 97+ | 3000 | Receiver gain control pin, Receiver signal output pin. Capable of contro |
| SGQ | (2) | PULSE | The SGQ1553-51A/SGQ1553-51A are 8-bit successive approxima- tion Analog | ||
| SGR | (26) | IMP | PDIP28宽 | 9241 | ♦ Adjustable Accurate DPWM Frequency with Sync Function |
| SGS | (200) | ST | TO-3 | small signal bandwidth from VREF to output up to 15 MHz (typ), fast outp | |
| SGT | (40) | SEAGATE | TQFP1414-100 | The H11NX-M series has a high speed integrated circuit detector optically | |
| SGU | (34) | N/A | 晶振 | 06+ | The VHC125 contains four independent non-inverting buff- ers with 3-STAT |
| SGW | (48) | 01+ | TQFP | NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATING | |
| SH- | (17) | Semtech | STO-24 | 99+ | The TLC156 series is a family of low-cost, high speed, high noise immunity |
| SH0 | (19) | yageo | yageo | dc04 | Microprocessors with bidirectional reset pins (such as the Motorola 68HC1 |
| SH1 | (120) | 四脚铁帽 | 08+ | The SC5388 is a 2-channel digital preset equalizer utilizing CMOS | |
| SH2 | (44) | DIP-32 | 98+ | Operating free air temperature range Storage temperature range Lead Tem | |
| SH3 | (64) | ABCO | 06+ | Notes * Indicates JEDEC registered data. 1. The current transfer ratio | |
| SH4 | (15) | ABC | 4M-100 | 05+ | Places the 1-bit bypass register between the TDI and TDO pins, which al |
| SH5 | (28) | N/A | N/A | N/A | 2Mbit of Page-Erasable Flash Memory Page Write (up to 256 Bytes) in 11m |
| SH6 | (121) | ZHONGYIN | SMD-8 | 04+ | Input HIGH Voltage Input LOW Voltage Input HIGH Current Input HIGH Curr |
| SH7 | (36) | HITA | TQFP | 2001 | The K6T8016C3M families are fabricated by SAMSUNGs advanced CMOS |
| SH8 | (17) | The RC4700 ALU consists of the integer adder and logic unit. The | |||
| SH9 | (27) | N/A | N/A | N/A | DC Electrical CharacteristicsOct.22.2002 - ICC changed 4mA -> |
| SHA | (28) | TI | DIP-16 | 98+ | State-of-the-Art EPIC-B™ BiCMOS Design Significantly Reduces Power |
| SHB | (9) | N/A | 0603B | C Glueless Interface to Synchronous Memories: SDRAM or SBSRAM C G | |
| SHC | (75) | BB | DIP | 04+ | s Meets or exceeds the requirements of ANSI TIA/EIA-644 Standard s Low-V |
| SHD | (13) | FREESCALE | 05+ | PLCC52 | Accesses to the MBAR register at long word $3FF00 are internal only, and |
| SHE | (5) | The K7B803625B and K7B801825B are 9,437,184-bit Synchro- nous Static Rand | |||
| SHF | (29) | Sirenza | 04+ | ||
| SHI | (12) | HOLTEK | SOP28 | 07+/08+ | Pin-Out Compatible with Standard 125 Logic Products 5Ω A/B bi-direc |
| SHJ | (33) | NEC | QFP | 97 | Interrupt Request (active high). Interrupts are enabled in the interrupt |
| SHK | (2) | Internal fixed off-time, PWM current-control circuitry can be used | |||
| SHL | (19) | MOTOROLA | (LX)high-frequency | A unique feature of the ISL6310 is the combined use of both DCR and rDS(O | |
| SHM | (67) | DESTINY | 708 | ＣＤＩＰ | Of the 87 product terms, 80 are for general-purpose use for the 16 macroc |
| SHO | (9) | N/A | SMD | 2000 | † Stresses beyond those listed under absolute maximum ratings may c |
| SHP | (39) | TOKYO COIL | 07+ | Expansion header J7 is provided to monitor or apply input signals to the | |
| SHQ | (9) | N/A | 45321812 | • TOSHIBA is continually working to improve the quality and reliabil | |
| SHR | (29) | NAIS | RELAY | 06+ | The MK2049-34 produces low-jitter output clocks. In addition, this part h |
| SHS | (43) | TOSHIBA | Power Diode Module DF200BA is designed for three phase full wave rectific | ||
| SHT | (12) | SENSIRION | Notes: 1. The Standby input must be controlled using an open- co | ||
| SHU | (6) | SAMSUNG | 99+ | Code protection is constantly evolving. We at Microchip are committed to | |
| SHV | (22) | SANKEN | conditions, the contents of the memory lo cation specified on the address | ||
| SHW | (79) | N/A | N/A | N/A | Specifications Outline Dimensions Pin Connections and Short Description |
| SHY | (1) | Simple Setup and Versatile Choices C Setting the threshold and hysteres | |||
| SI- | (433) | SANKEN | TO220-5L | 06+ | If the signal is bipolar, such as a sine wave centered around zero, each |
| SI0 | (27) | SMSC | QFN | The Edge646 driver supports three distinct programmable driver levels; hi | |
| SI1 | (358) | VISHAY | SOT-523 | 04+ | Conclusion As digitizing systems increase in speed, aperture effects pl |
| SI2 | (299) | SILICON | 04+ | The DS8830, SN55183, and SN75183 dual differential line drivers are des | |
| SI3 | (600) | Siliconix | 06+ | SOT163 | No output filter required for inductive loads Externally configurable g |
| SI4 | (1677) | VISHAY | SOP-8 | 05+ | s Two 64 Megabit (Am29LV640D) in a single 64-ball 13 x 11 mm Fort |
| SI5 | (197) | SILCONIX | MLP1206-8 | 06+ | 150V Power Schottky rectifier are suited for switch Mode Power Supplies |
| SI6 | (407) | 9049 | Note 2: Absolute Maximum continuous ratings are those values beyond which | ||
| SI7 | (565) | ST | 94 | Lead temperature, Tsol, 1,6 mm (1/16 inch) from case for 10 seconds | |
| SI8 | (139) | SI | MSOP-8 | 03+ | This octal buffer/driver is built using advanced dual metal CMOS t |
| SI9 | (1033) | SI | DIP | 07+ | Compliance with draft ANSI X3.302-199x Ultra2 SCSI (SPI-2) standard 64- |
| SIA | (50) | DIP | Notes: 2. Multiple Supplies: The voltage on any input or I/O pin ca | ||
| SIB | (8) | SANKEN | DIP | The UC3854A/B products are pin compatible enhanced versions of the UC38 | |
| SIC | (50) | PMX | MQFP | 04+ | 2-channel, 250 kSPS, 10-/12-bit ADCs in TSOT package. Low power consumpt |
| SID | (67) | 三肯 | ALO,BLO,CLO - are the logic inputs for controlling the switching of the | ||
| SIE | (39) | Maximum Input Voltage Power Dissipation Thermal Resistance Junction t | |||
| SIF | (19) | NOTE: Intersil Pb-free plus anneal products employ special Pb-free materia | |||
| SIG | (81) | JGD | 00+ | The SecSiTM (Secured Silicon) Sector is an 256 byte extra sector capabl | |
| SIH | (14) | SAM | SIL-9 | 03+ | NOTES 1Stresses above those listed under Absolute Maximum Ratings may ca |
| SII | (208) | SILICON LMGE | TQFP1414-100 | Vo Adjust: Using a single resistor, this pin allows the modules complemen | |
| SIK | (4) | SIK | The 70C version utilizes an industry standard line driver IC (26LS31) wh | ||
| SIL | (409) | SILICON | QFP144 | 07+PB | Integrated 4-band Graphic Equaliser Adjustable output stage filter compen |
| SIM | (114) | SIMcom | 07+ | The APW 7093 uses a unique current-mode, constant-off-time, PWM control s | |
| SIN | (26) | PHILIPS | PLCC44 | 05+ | When the receiver is placed in the power-down (sleep) mode, the output im |
| SIO | (21) | SMSC | LQFP | The numeric devices decode positive BCD logic into characters 0-9, a | |
| SIP | (121) | NEC | DIP | 1993 | Problems relating to playback of sound on audio sys- tems. With natural |
| SIQ | (30) | The CY7C133 (master) and CY7C143 (slave) consist of an array of 2K words | |||
| SIR | (56) | N/A | N/A | N/A | sFEATURES qOperating Voltage4.7 to 13V qWOW Function |
| SIS | (410) | SiS | PQFP | 1995 | Widebus Family Supports SSTL_2 Data Inputs Outputs Meet SSTL_2 C |
| SIT | (36) | SANSUNG | DIP | 2000 | All devices provide break-before-make switching and are TTL and CMOS co |
| SIU | (3) | rohm | rohm | dc95 | Dallastats maintain the position of the wiper in the absence of power. |
| SIV | (10) | SI | 00+ | This device contains protection circuitry to guard against damage | |
| SIW | (56) | siliconwave | 811 | The MHF converters are switching regulators which use a quasi- square wa | |
| SIX | (4) | INTEL | QFP | QFP | At the moment the supply voltage on pin VDD or HV exceeds the level of |
| SIY | (2) | SI | DIP | High-Density Function Blocks The XC7354, XC7372, XC73108 and XC73144 dev | |
| SIZ | (10) | SOT-89 | 4 DMA controllers, each with 4 data streams manage memory to memory, peri | ||
| SJ- | (27) | SJ | The SPS product family is specially designed for an off-line SMPS with m | ||
| SJ0 | (7) | TQFP | 01+ | The XC3000A family has additional interconnect resources to drive the I | |
| SJ1 | (11) | In addition, Dallas Semiconductor's continuous reliability monitor program | |||
| SJ2 | (16) | DIP-5 | 07+/08+ | ✔ Molded JEDEC SO-16 (Wide Body) Package ✔ Weight 0.15 gram | |
| SJ3 | (2) | The EL6119 is a dual four-channel laser diode current amp | |||
| SJ4 | (6) | TO-3 | Note 3: Although power dissipation is internally limited, these specifica | ||
| SJ5 | (9) | HOLTEK | 00+ | Hynix HYMD116G725A(L)8M-K/H/L series incorporates SPD(serial presence dete | |
| SJ6 | (3) | SANYO | SOT-252 | MAX 3000A devices are supported by Altera development systems, which are | |
| SJ7 | (9) | ON | 66/133-MHz, 64-bit, true multifunction PCI-X host bus interface Backwar | ||
| SJ8 | (5) | 03+ | When writing data to the memory it responds to the 8 bits received by a | ||
| SJ9 | (4) | N/A | N/A | N/A | Amplitude compensation (harmonic compensation) To maintain appropriate |
| SJA | (32) | ?? | 4 | 1. A 0.1 µF low frequency tantalum bypass capacitor in parallel with | |
| SJB | (4) | ON | T0-92 | 05+/06+ | Note 11: Skew is defined as the absolute value of the difference between |
| SJC | (3) | SMD20 | 03+ | Three parallel I/O registers with open-drain capability Four baud-rate g | |
| SJD | (15) | ON | SOT252 | -Complex functions (up to 16 inputs) in a single logic cell -High synthe | |
| SJE | (36) | MOTOROLA | TO220 | When the receiver is placed in the power-down (sleep) mode, the output im | |
| SJF | (1) | Caution: The BiCMOS inherent to the design of this component increases th | |||
| SJG | (1) | Collector C Base Cutoff Current, IE= 0mA, VCB=-10V Emitter C Base Cuto | |||
| SJH | (3) | 100 | SOP | 00+ | The SJH011-RA is a miniature slotted optical switch designed for surface |
| SJI | (4) | dc05 | TJ = 25C VIN = -14.5V to -30V, TJ = 25C VIN = -16V to -22V, TJ = 25C | ||
| SJM | (3) | INTERSIL | H00 | DIP28 | Temperature measurements are made by determining the time to charge and |
| SJR | (1) | N/A | The Hyundai HYM71V65801 X-Series are 8Mx64bits Synchronous DRAM Modules. | ||
| SJS | (9) | PLCC | The device comes with extensive serial communication capabilities. On-ch | ||
| SJT | (4) | NEC JAPAN | DIP64 | 94+ | The C-suffix devices are characterized for operation from 0C to 70C. The |
| SJW | (1) | VBIAS (VCC, VBS 1,2,3) = 15V unless otherwise specified. The VIN, VTH and | |||
| SJX | (1) | 30 fully-programmable I/Os (5V tolerant) 4 external interrupts 8-bit p | |||
| SJZ | (2) | FAST data sheets carry several types of AC information. The AC Character | |||
| SK- | (52) | 滤波器 | The Customer Demonstration Board provides the ROC093XC radio with a PIC mi | ||
| SK0 | (168) | YAG | The HCT161A/163A are programmable 4Cbit synchronous counters that | ||
| SK1 | (173) | 32K x 16 Bank-Switchable Dual-Ported SRAM Architecture C Four independent | |||
| SK2 | (104) | DIP | 07+ | tPZLOutput enable time to low level1025 See Figure 6ns &nb | |
| SK3 | (269) | N/A | HAR | 04+ | SWITCHING CHARACTERISTICS 3 Propagation Delay A to B or B to A, tPD |
| SK4 | (67) | Notes: 1. SSSEL has internal pull-up and SSON has pull-down resist | |||
| SK5 | (82) | EUPLE | 04+ | Stresses beyond those listed under Absolute Maximum Ratings may cause per | |
| SK6 | (34) | N/A | Note 6: CPD is defined as the value of the internal equivalent capacitanc | ||
| SK7 | (86) | POLYFET | TO | 00+ | For example, if a block of data is to be transferred from RAM to an I/O |
| SK8 | (60) | SK | 04+ | The CMPIN pin drives data slicer DS1, which convert the analog signal fro | |
| SK9 | (27) | For AGC with a maximum gain of 24 dB, AGCFIL should be set to 3 V and AGC | |||
| SKA | (30) | infneon | The TTL parallel I/O interface may be configured as either a FIFO (confi | ||
| SKB | (248) | MIC | 2008+ | The ChipCorder I5216 is an 8 to 16 minute Voice and Data Record and Playba | |
| SKC | (77) | skc | skc | dc00 | Pulse loading: The capacitors charged which unsinusoidal voltage pulses |
| SKD | (357) | SEMIKRON | SOP | Initial version Add 17.91MHz main CLK ADD eFHP5830D, eFHP5830AD, and e | |
| SKE | (107) | ALPS | SALE--STOCK!! | 08/09+ | Notes: 1. See test circuit and waveforms. 2. This parameter is guarantee |
| SKF | (52) | ELNA | 02+ | The CZ80CPU is designed to run at frequencies up to 80 MHz on a typical 0. | |
| SKG | (3) | MOT | 01+ | TO-3 | These three terminal negative regulators are supplied in a high density h |
| SKH | (83) | SEMIKRON | 55 | MODULE | • 0.13µ CMOS design allows industrys lowest power &nbs |
| SKI | (721) | SEMIKRON | MODULE | N/A | The Microwire/SPI (MWSPI) interface module supports syn- chronous serial |
| SKJ | (9) | TELECOM SEMI | 98+ | C System Speeds > 100 MHz C Flip-flop Toggle Rates > | |
| SKK | (2060) | 1850 | The LT®1990 is a micropower precision difference ampli- fier with a | ||
| SKL | (17) | ZILOG | DIP | 93 | The four address select inputs (ADD0 to ADD3) allow up to 16 MAX1169 devi |
| SKM | (573) | 西门康 | MOSFET | between X2 and ground. Stuffing of these capacitors on the PCB is optio | |
| SKN | (279) | DSI | n/a | 1.9GHz gain-bandwidth product 1.05nV/Hz input voltage noise 0.8pA/Hz | |
| SKP | (49) | INFINEON | TO-220 | 05+ | Optical transmitter The optical transmitter in a fiber optic system conve |
| SKQ | (62) | ALPS | SALE--STOCK!! | 08/09+ | VCC and GND are the supply voltage pins for the digital control inputs |
| SKR | (162) | semikron | semikron | dc04 | The TPS773xx or TPS774xx is offered in 1.5-V, 1.6 V (TPS77316 only), 1.8- |
| SKS | (93) | MITSUBISHI | SOD-123 | 04+ | Precision fixed operating frequency (100 / 67 / 50KHz ) Pulse by pulse |
| SKT | (385) | SEMIKRON | SOP | Power supply for the A/D converter. Connect this pin as close as possib | |
| SKU | (9) | MMC | 06+ | 1. Use this component within operating temperature range. It might not be | |
| SKV | (6) | lup fung | lup fung | dc01 | Bursts can be initiated with either ADSP (Address Status Processor) or |
| SKW | (28) | N/A | N/A | N/A | clock stream is corrupted during a transmission. In these two modes the D |
| SKX | (6) | While on probation, the sync separator outputs remain enabled and separat | |||
| SKY | (165) | SKYWORKS | 0524+ | Note 1: Absolute Maximum Ratings are limits beyond which damage to the de | |
| S-L | (30) | SEIKO | 06+ROHS | Serial Control Interface Clock (For MPI)/Timeslot Selection (For GCI). I | |
| SL- | (120) | SANYO | N/A | The improvements in the DG411/883 series are made possi- ble by using a | |
| SL0 | (67) | VISHAY | SOD-123 | 04+ | The flowchar t in the Programming section of the EPROM Products Data Bo |
| SL1 | (382) | LINEAR | SMD | 03+ | Positive digital power supply. Ring oscillator/crystal input pin. Rese |
| SL2 | (167) | GPS | SOP16P | 96+ | Most everything applies to driving the P-Channel gates as the N-Ch |
| SL3 | (136) | N/A | N/A | N/A | The SN74CB3T16212 operates as a 24-bit bus switch or as a 12-bit bus exch |
| SL4 | (135) | HYNIX | 01+ | DIP-S14P | These solid state display devices are designed and tested for use in a |
| SL5 | (164) | 5) Next, a heat sink with lower SA than the one calcu- lated in s | |||
| SL6 | (176) | PS | CAN | 86+ | The HT815D0 is a single chip LOG-PCM voice synthesizer LSI with 11.2-sec |
| SL7 | (76) | HYNIX | 02+ | SOP-3.9-16P | • Live Insertion and Removal Power Manager • Adjustable Powe |
| SL8 | (55) | NS | 96+ | The Hitachi HM5264165F is a 64-Mbit SDRAM organized as 1048576-word 16-b | |
| SL9 | (33) | LT | SOP | 03/+04+ | Reset (Input). A logic low at this input resets the SL90067. To ensure pro |
| SLA | (604) | ZIP9 | 01+ | Incorporating a successive approximation architecture with on-board sampl | |
| SLB | (42) | SIEMENS | DIP8 | 08+ | • Two isolated elements are contained in one package, allowing &nbs |
| SLC | (73) | ero | ero | dc77+ | The ispLSI 5000VE Family features 3.3V, non-volatile in- system programm |
| SLD | (40) | 95+ | Notes: 1. S-parameters include bond wires. Gate: Total 2 wire (s | ||
| SLE | (56) | N/A | 05+ | Note 5: CPD is defined as the value of the internal equivalent capacitanc | |
| SLF | (435) | TDK | SMD | 05+ | Upon power-up, the FIFO must be reset with a Reset (RS) cycle. This cau |
| SLG | (45) | N/A | Independent operation of the serial input and the two serial outputs is g | ||
| SLH | (21) | HITACHI | The MAX 3000A architecture supports 100% transistor-to-transistor logic | ||
| SLI | (36) | N/A | The MAX4667 has two normally closed (NC) switches, the MAX4668 has two no | ||
| SLK | (23) | 97 | The DS2745 provides current-flow, voltage, and temperature measurement da | ||
| SLL | (23) | hit | hit | dc99 | The software Sector Erase mode is initiated by issuing the specific six-w |
| SLM | (67) | SAMTEC | 08+ | ISENSE: This is the input to the X10 wide bandwidth current-sense amplifi | |
| SLN | (19) | N/A | Port 3: Port 3 is an 8-bit I/O port with a user configurable output type. | ||
| SLO | (6) | SIEMENS | DIP14 | 03+ | ADJ: In the adjustable version, the user programs the output voltage with |
| SLP | (58) | MINI | 08+ | ||
| SLQ | (1) | N/A | JEDEC standard 3.3V power supply LVTTL compatible with multiplexed addres | ||
| SLR | (160) | ROHM | 2003 | 1 phase, full-wave, linear DC motor driver Built-in TSD (Thermal shutdo | |
| SLS | (57) | HYNIX | 01+ | Escape Characters - An escape sequence may be entered while in data mod | |
| SLT | (36) | HITACHI | CASE: DO-214AA (SMBJ) outline Terminals solderable per MIL-STD-750, Metho | ||
| SLU | (2) | LEGERITY | QFN | 99 | operational when the bus is attached to an off-board service node. This n |
| SLV | (46) | PROTEK | SOP-8 | 06+ | The internal PFD, a high-speed rising edge triggered type, has an interna |
| SLW | (47) | samtec | SOP | 05+ | Data Outputs: A 4-bit parallel data word, forming a HEX character represen |
| SLX | (29) | SIRENZA | The Z86C83/C84 Consumer Controller Processors (CCP™) are full-feat | ||
| SLY | (3) | The 3-state control gate is a 2-input AND gate with active-low inputs s | |||
| SLZ | (5) | MOT | DL-34 | (Notes) 1. Power types and 1 Form A types are available on request. (Not | |
| S-M | (3) | 97 | • ML22Q54 The ML22Q54 is a speech synthesis device with a 4- | ||
| SM- | (75) | COPAL | 05+ | SMD | Pb−Free Package is Available Small Compact Surface Mountable Packa |
| SM/ | (2) | ||||
| SM0 | (166) | STC | SOP | connected from Drain to Source internally. This diode helps to control | |
| SM1 | (425) | SOP | 97+ | High FSK Sensitivity: -106 dBm at 20 kBaud/-109.5 dBm at 2.4 kBaud (433.92 | |
| SM2 | (192) | STMicroectronics | 07+ | Operating the four memory banks in an interleave fashion allows random ac | |
| SM3 | (177) | JAT | SMB | 05+ | 80C51 based architecture 4K x 8 ROM (IC80C51 only) 128 x 8 RAM Two 16 |
| SM4 | (164) | ST | 07+ | DO-214AC | |
| SM5 | (736) | DIP | 96 | Notes: 1. Synchronous preset (SPE) input can set max 256 down counts. &n | |
| SM6 | (296) | SG | TO-3 | 99+ | The LCA Series are low capacitance, bidirectional TVS arrays that are des |
| SM7 | (182) | pin signalised an interrupt (logic 0). However, if the Mode 0 & 1 pin | |||
| SM8 | (446) | SMC | DIP | enables to plan a circuit to detect welding or go back to the beginning | |
| SM9 | (63) | ANPEC | 06+ | Data input for AUI interface. This differential signal is coupled through | |
| SMA | (1776) | SANKEN | SIP | 00+ | 135-mΩ -Maximum (5-V Input) High-Side MOSFET Switch 250 mA Continu |
| SMB | (2203) | GS/VISHAY | 05+ | To measure the performance of the sensor in the module, a sensor test mod | |
| SMC | (1145) | DIP | 04/05+ | Note 4: The Temperature Coefficient of the adjusted input offset voltage | |
| SMD | (948) | For a typical application, where 2kbaud date has to be sent to a transpon | |||
| SME | (283) | SUN | BGA | N/A | Non-repetitive current pulse per Figure 5 and derate above TA = 25C per |
| SMF | (172) | SEMTECH | SC70-5 | 04+ | • Triple Logic Voltage Outputs (Independently Regulated !) |
| SMG | (108) | BOSCH | PLCC | 05+ | ESD (electrostatic discharge) sensitive device. Although the MX841 feature |
| SMH | (81) | SOP16S | 2007+ | The AT40KAL is a family of fully PCI-compliant, SRAM-based FPGAs with dis | |
| SMI | (88) | N/A | 45321812 | The LTC3722-1/LTC3722-2 feature adjustable synchro- nous rectifier timing | |
| SMJ | (230) | TI | 00+ | The SMJ27C128-12JM is a fully integrated multiprotocol serial interface. | |
| SMK | (74) | TAIYO | . | 09+ | - Removed all references to XCLKS, since function is removed. - typo - r |
| SML | (691) | Microsemi | DO-214AB | 07+ | Note 12: For VIN(−) VIN(+) the digital code will be 0000 0000. Two |
| SMM | (785) | vishay | vishay | dc03 | Note 1: Specifications to -40C are guaranteed by design and not production |
| SMN | (7) | T | Peak current lasting <30 seconds with a maximum 10% duty cycle. At 25 | ||
| SMO | (20) | ZILOG | DIP | 98+ | DESCRIPTION Using the latest high voltage technology based on a patente |
| SMP | (560) | ST | 08+ | With the sense pin connected, the difference between the voltage measure | |
| SMQ | (16) | N/A | ON | 04+ | For use with 1/4-inch optical systems Sensitivity increased by 4 dB ove |
| SMR | (97) | LEGIC | TSSOP-24 | Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V | |
| SMS | (350) | SEMTECH | 00+ | Power Dissipation and Thermal Characteristics Maximum Power Dissi | |
| SMT | (262) | ST | 2008+ | Maximum ratings are those values beyond which device damage can occur. M | |
| SMU | (45) | T | PLCC | The SDA 525x contains a slicer for TTX, VPS and WSS, an accelerating acqu | |
| SMV | (246) | AI | SOD523 | 04+ | At power-up or reset, all sectors are unlocked. To activate the lockdown |
| SMW | (29) | N/A | • Flexible architecture with abundant routing resources Ve | ||
| SMX | (7) | STAR | 06+ | DIP | Cntrl (Bump A1): Shutdown control pin. When VCntrl is 1.4V, the LM3502 |
| SMY | (1) | SM | PLCC | N/A | The CY22393, CY22394, and CY22395 are a family of parts designed as upgra |
| SMZ | (89) | VISHAY | 07+ | The AT8xC5111 has 3 software-selectable modes of reduced activity for fur | |
| S-N | (1) | N/A | 日本航空 | 05+ | HIGH SPEED: tPD = 5.5ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC |
| SN- | (12) | 05-07+ | 4. Design your application so that the product is used within the ranges | ||
| SN0 | (120) | TI | O7+ | AVS, BVS, CVS - are the return pins on the bottom of each half bridge. T | |
| SN1 | (756) | QFP | TI | 97+ | Maximum ratings are those values beyond which device damage can occur. Ma |
| SN2 | (366) | TI | QFP-44 | 00+ | Storage Temperature Ambient Temperature under Bias Junction Temperature |
| SN3 | (215) | TI | SOP8 | 99+ | Vo Adjust: This pin is used to trim the output voltage to a value within |
| SN4 | (55) | TI | 07+ | Max. UnitsConditions VVGE = 0V, IC = 250µA V/C VGE = 0 | |
| SN5 | (2437) | TI | SOP | 9733 | Notes: (1) Clip mounting (on case), where lead does not overlap heatsink |
| SN6 | (1577) | TI | N/A | 2006+ | Note 4: The maximum allowable power dissipation is a function of the maxi |
| SN7 | (26285) | Power Supply Input. These parts can be operated from 1.65 V to 2.75 V; V | |||
| SN8 | (169) | SONIX | PDIP48 | 06+ | DESCRIPTION This MOSFET series realized with STMicroelec- tronics uniqu |
| SN9 | (81) | S | 06+ | 1500 | The ground return for the digital supply for the ADC11DL066s output dri |
| SNA | (62) | TI | 99/P | • Plastic package has Underwriters Laboratory Flammability | |
| SNB | (57) | TI | SMD | 93 | Boost converter with a 2A, 0.18Ω switch Boost output voltage adju |
| SNC | (402) | DIP | 03+ | The received serial data is internally converted to parallel by th | |
| SND | (15) | The Intersil ISL83699 device is a low ON-resistance, low voltage, bidire | |||
| SNE | (6) | The parameter tAOH indicates the system compatibility of this device when | |||
| SNF | (3) | TOKYO COIL | The bq2083−V1P2 SBS-compliant gas gauge IC for battery pack or in | ||
| SNG | (1) | Notes: 1. All inputs except OE must meet setup and hold times for the L | |||
| SNH | (6) | TI | 07+ | SNHVD3082EDGKG4 800MHz FSB P4 SBC w/Serial ATA, CRT/LVDS, Audio, Dual G L | |
| SNI | (1) | TI | DIP-16 | 98 | |
| SNJ | (2799) | TI | Data Output Control The usual state of the data output is the High-Z s | ||
| SNK | (2) | ∗1 Period Jitter 1: This value is the standard deviation of an outp | |||
| SNL | (14) | TI | 07+ | The built-in LDO can be used for a second output voltage derived either | |
| SNM | (11) | NPC | SOP | 07+ | Boot PROM data line 0(EECS=0): boot PROM or flash data line 0. EEPROM da |
| SNN | (3) | 13 | HITACHI | 00+ | (VDD = 2.7V to 3.6V (SNN5165805FJ6/SNN5165805FJ6), VDD = 4.5V to 5.5V (SNN |
| SNO | (3) | N/A | SMD | 2000 | The MHF Series is designed to provide full power operation over the inpu |
| SNP | (21) | This series of optically coupled isolators consist of a Gallium Arsenid | |||
| SNR | (2) | bosch | bosch | dc97 | The SNR0270200164 is designed to convert three lines of input data |
| SNS | (11) | 06/ | TI | 550 | sample capacitor before powering down the measuring cir- cuitry. |
| SNT | (14) | SAMTEC | 717 | † Package drawings, standard packing quantities, thermal data, symb | |
| SNU | (1) | The LS323 contains eight edge-triggered D-type flip-flops and the inters | |||
| SNV | (1) | SMD | 1998 | © 2002 PLX Technology, Inc. All rights reserved. PLX and the PLX log | |
| SNY | (9) | ST | 04+ | The HS I2C™-compatible module is a reference solution for implement | |
| SO- | (8) | PHILIPS | SOP16 | 06+ | This device contains two independent positive pulse trig- gered J-K flip |
| SO0 | (1) | ||||
| SO1 | (37) | SMK | SMD | 95+ | The high-current output drivers consist of MOSFET output devices, which s |
| SO2 | (50) | SMK | 97 | Tachyon TS focuses on mass storage applications for any topology that | |
| SO3 | (19) | HITACHI | SMD | NOTES: 1. Dimensions are in inches. 2. Metric equivalents | |
| SO4 | (17) | SANYO | SOT-23 | 07+（ROHS） | Literature Distribution Centers: USA: Motorola Literature Distribution; |
| SO5 | (15) | SGS | 06+ | - | The transmitter consists of an integrated VCO and tank circuit, a complet |
| SO6 | (5) | 06+ | Low temperature coefficient Wide operating current of 400 µA to 1 | ||
| SO7 | (4) | SGNEC | QFP52 | 0419+ | The following circuit shows a charged monitor for pro- tection against ba |
| SO8 | (11) | 07+ | Note 2: When the analog signal exceeds +13.5V or -12V, the blocking action | ||
| SO9 | (5) | SGS | 06+ | - | This is a dual function pin. In the IDT Standard mode, the FFC function is |
| SOA | (12) | SGS | 06+ | SOT23 | In addition, the ISD1000A Series has an internal VCC detect circuit to ma |
| SOB | (3) | BSE | 05+ | The ICS91309 provides synchronization between the input and output. The | |
| SOC | (326) | Repetitive rating; VGE = 20V, pulse width limited by max. junction temper | |||
| SOD | (10) | FAIRCHLD | 04+ | This datasheet contains new product information. Analog Technology reserve | |
| SOF | (5) | AMIS | 06+ | 500 | Notes: 1. Minimum voltage is equal to C 2.0V for pulse durations o |
| SOG | (21) | VISHAY | SOP | 01+ | standard for high-speed system bus running at half the CPU clock High-b |
| SOH | (8) | BB | UNUSUAL LOADS Usually an op amp sources current to the load (Q1 conduct- | ||
| SOI | (53) | SOP | 04+ | Both drivers incorporate adaptive shoot-through protection to prevent u | |
| SOJ | (3) | SOPJ20 | 2007+ | Drain-to-Source Breakdown Voltage Gate Threshold Voltage Ga | |
| SOL | (34) | TOPLINE | SOP | 03+ | Comprehensive Power Management Capability for Mobile and Desktop Applicat |
| SOM | (411) | N/A | ACTIVE: Product device recommended for new designs. LIFEBUY: TI has annou | ||
| SON | (31) | No part of this document may be copied or reproduced in any form or by an | |||
| SOO | (3) | ROHM | 2008 | When the cell voltage falls below the undervoltage threshold for two cons | |
| SOP | (45) | PTC | SOP8 | 05+ | s FEATURES • Low Operating Current • Output Curren |
| SOQ | (4) | MITSUI & CO.,LTD. | Maxims MAX312/MAX313/MAX314 analog switches feature low on-resistance (10 | ||
| SOR | (1) | The TL05x series of JFET-input operational amplifiers offers improved dc | |||
| SOS | (6) | The SOS-440-16 user selects the mode of operation (deci- mate, interpola | |||
| SOT | (89) | NO | 04+ | 77 instructions C-Language friendly architecture PI | |
| SOU | (3) | MHS | DIP40 | 2007+ | The Hynix HYM71V32C735AT4 Series are Dual In-line Memory Modules su |
| SOW | (6) | 01 | Notes: 1. See test circuit and wave forms. 2. This parameter is guarante | ||
| SOY | (1) | The ACE1501 (Arithmetic Controller Engine) family of microcon- trollers | |||
| SOZ | (1) | The PCM1780/81/82 is a CMOS, monolithic, inte- grated circuit, which in | |||
| S-P | (2) | SMD4 | Note that the S-PV/TE1781 contains a limited low voltage write protectio | ||
| SP- | (98) | TI | DIP-16P | The Idle mode stops the CPU while allowing the other chip function to con | |
| SP/ | (4) | ||||
| SP0 | (103) | MICROC | DIP | 8943 | The A8430 incorporates a power switch and feedback sense amplifier to p |
| SP1 | (231) | N/A | ZIP-3P | DATEL makes no representation that the use of its products in the circuit | |
| SP2 | (782) | SB: The voltage on SB sets the output current level at which standby mod | |||
| SP3 | (1087) | XR | The ISL422XE features an automatic powerdown function that powers down t | ||
| SP4 | (567) | SIPEX | SSOP-8 | 03+ | Divide bit - this bit sets the frequency of the internal PWM clock. Writi |
| SP5 | (274) | GPS | CDIP | CDIP | Allows Safe Board Insertion and Removal from a Live Backplane Controls S |
| SP6 | (1010) | The products described herein are TTL compatible dual high speed circuit | |||
| SP7 | (498) | The BS616LV4017 is a high performance, very low power CMOS Static Random | |||
| SP8 | (620) | SIPEX | 08+ | - 10, 8, 6 or 4bit up/down counting - Parallel load - 8 different inp | |
| SP9 | (69) | PLESSEY | DIP-8 | 02+ | We recommend that the worst case current be no greater than 80% of the ma |
| SPA | (144) | LNFINEON | 04+ | (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V) Control Inputs Can be Dri | |
| SPB | (147) | infineon | P-TO263-3-2 | 07+ | The EM39LV040 provides two software methods to detect the completion of a |
| SPC | (362) | N/A | These devices can be used in a wide range of digital panel meter applicat | ||
| SPD | (149) | INFINEON | TO-252/251 | 05+ | In applications using one DAC per channel, where the track- and-hold fea |
| SPE | (36) | IR | TO-3P | Protection diodes are employed at all pins except V+ and V- of th | |
| SPF | (77) | SUNRISE | QFP | 06+ | 505µA supply current 75MHz bandwidth Power down to Is = 33µA |
| SPG | (44) | EPSONS | The skew between CLKOUT and the CLKA/B outputs is not dynamically adjuste | ||
| SPH | (61) | TDK | 2003 | (Unless otherwise indicated, copies of the above specifications, s | |
| SPI | (161) | † Stresses beyond those listed under absolute maximum ratings may c | |||
| SPJ | (3) | JAT | SOT-23 | 05+ | Rev. A Information furnished by Analog Devices is believed to be accurat |
| SPK | (5) | N/A | MOTOROLA | 04+ | an automatic power-down feature that significantly reduces power consump |
| SPL | (108) | OSRAM | DIP-2 | 07+ | Time timer and a Watchdog unit. The Real-Time Clock Tim- ing function c |
| SPM | (145) | SUNPLUS | 02+ | This document describes how to design a platform with a common footprint | |
| SPN | (42) | MICREL | 06+ | 100mV/A 10% max. DC offset 200mV active high, 15V CMOS active high, 15V | |
| SPO | (13) | SIEMENS | 07+/08+ | Input and output signals to and from the internal clock generation circui | |
| SPP | (155) | ALPS | SALE--STOCK!! | 08/09+ | Figure 5 shows the output levels overlayed using a storage scope. The at |
| SPQ | (4) | SPQ | DIP8 | Length is measured from the mounting surface to the free end of the sha | |
| SPR | (79) | GI | 87+ | DIP48 | Notes: The gain for the unmatched device in 50 ohm system is shown as th |
| SPS | (151) | SANYO | 06+ | The ÉlanSC300 microcontroller from AMD is part of the growing &Ea | |
| SPT | (206) | FS | 07+ | Once the feature is enabled, the data in the boot block can no longer b | |
| SPU | (112) | INFINEON | TO-251 | 08+ | The CS8920As analog front end incorporates a Manchester encoder/decoder |
| SPV | (36) | SUNPLUS | MQFP | 02+ | FEATURES High Definition Input Formats 8-Bit or 16-Bit (4:2:2) Parallel |
| SPW | (39) | INFINEON | TO-3P | 06+Pb-Free | 2) Limiting the external clock frequency to 12 MHz AND making sure the on- |
| SPX | (2007) | SIPEX | 07+ | Timer Clearing A negative edge or pulse at the TCL input longer than 15 | |
| SPY | (10) | SUNPLUS | 1999 | 芯片 | The second switching regulator operates in the same manner, but with a 17 |
| SPZ | (4) | SANKEN | 00+ | Stability The IRU1015 requires the use of an output capacitor as part of | |
| SQ- | (19) | 2001+/ | The CLK output is switched on if the amplitude of the current flowing thr | ||
| SQ0 | (3) | N/A | SMD | 02+ | Unless otherwise specified, these specifications apply over Vcc=5V, VcH1=V |
| SQ1 | (9) | Notes: 1. The regulator will operate down to no load with reduced specifi | |||
| SQ2 | (15) | Agilent | DIP | 04+ | TI does not warrant or represent that any license, either express or impl |
| SQ3 | (31) | ATMEL | QFP-100 | 9823 | VDD (16) VDD is the positive supply connection. An internal shunt regul |
| SQ4 | (10) | N/A | 45321812 | Designed for pulse-width modulated (PWM) current control of bipol | |
| SQ5 | (4) | 1 | The status of this pin determines the sampling edge on RClk to RPOS/ RNE | ||
| SQ6 | (9) | SQ | SMD | 9522+ | If you have any marketing or sales questions, please contact: Law |
| SQ7 | (5) | N/A | QFP/52 | 06+ | A doubled buffered serial data interface offers high-speed, 3-wire, SPI |
| SQ8 | (5) | 03+ | QFP/128 | The MK2049-34 produces low-jitter output clocks. In addition, this part h | |
| SQ9 | (14) | (3) The products described in this material are intended to be used for s | |||
| SQA | (1) | SanRex | SOP | Jumper JU1 connects the MAX1737 thermistor input (THERM) to GND through a | |
| SQB | (1) | Each of the 32 macrocells generates a buried feedback that goes to the gl | |||
| SQC | (12) | SIEMENS | O7+ | The CE input of the lead (or only) PROM is driven by the DONE output of | |
| SQD | (50) | SANREX | n I2C/SPI Control Interface n I2C/SPI programmable National 3D Audio n | ||
| SQE | (1) | These versatile devices are useful for driving a wide range of loads in | |||
| SQF | (3) | infineon | 08+;07+ | The SQF6186F is a high frequency, 100V Half Bridge N-Channel power MOSF | |
| SQG | (2) | The SM561 is a PLL-type clock generator using a proprietary Cypress desi | |||
| SQH | (3) | N/A | Support Mode 3 (11 MB s) timing proposal on en- hanced IDE (IDE-2 or ATA | ||
| SQL | (7) | Unknown | The PI74LPT573 is an 8-bit transparent latch designed with 3-state outpu | ||
| SQM | (18) | Edition 10.97 Published by Siemens AG, Bereich Halbleiter, Marketing- K | |||
| SQN | (1) | SEQUANS | 0617+ | BGA | Sample tested during initial release and after any redesign or pro |
| SQO | (2) | Optional accessories for module-type MCC 95 version 1 B Keyed gate/catho | |||
| SQP | (25) | infineon | 03+/04+ | Maximum ratings are those values beyond which device damage can occur. Ma | |
| SQR | (1) | Notes: 1. Unless otherwise specified, these specifications apply for (VI | |||
| SQS | (13) | BI | SSOP-16 | 00/04+ | Fast throughput rate: 100 kSPS Specified for VDD of 2.5 V to 5.5 V Low p |
| SQT | (24) | samtec | samtec | dc99 | The LTC®4210 is a 6-pin SOT-23 Hot SwapTM controller that allows a bo |
| SQU | (2) | SAMSUNG | 03+ | An active bias circuit can be implemented if the user does not wish to sa | |
| SQV | (2) | YAGEO | 4532 | The MAX1536 constant-off-time, pulse-width-modulated (PWM) step-down DC-t | |
| SQW | (16) | samtec | samtec | dc01 | The LVTH162245 data inputs include bushold, eliminating the need for ex |
| SQZ | (1) | 4. Multiple-Message Playback, Controller Interface The 8M EPROM is divid | |||
| S-R | (1) | ADC Output (LSB) ADC Output ADC Output ADC Output ADC Output ADC Out | |||
| SR- | (34) | NANA | International Airport Industrial Park • Mailing Address: PO Box 1140 | ||
| SR/ | (1) | ||||
| SR0 | (67) | SOP14 | 03+ | 1.1 EMI REDUCTION The COP8SAx family of devices incorporates circuitry t | |
| SR1 | (458) | N/A | N/A | N/A | • Five protective functions (over-current, over-voltage, short-circu |
| SR2 | (545) | PROTEK | 05+ | Regulatory Compliance See Table 1 for transceiver Regulatory Complianc | |
| SR3 | (201) | AVX | ０８+ | Fully static RISC processor core, capable of operating from 0 to 24 MHz | |
| SR4 | (46) | POLYFET | HIGHFREQUENCY | 06+ | Features • Wide frequency rangeC15.0MHz to 250.0MHz • User s |
| SR5 | (93) | teledyne | teledyne | dc72+ | • Microchip's web site: www.microchip.com • Microchip's Techni |
| SR6 | (81) | N/A | |||
| SR7 | (165) | N/A | The EFJ2803 is a high reliability EMI filter for use with the DAC | ||
| SR8 | (37) | SANYO | 98+ | This is a family of products based on the most advance CMOS mixed signal | |
| SR9 | (9) | MOT | 93 | 3000 | C Supports both Firmware Hub (FWH) and LPC Memory Read and Write C |
| SRA | (155) | MINI | 08+ | To enhance device driver efficiency and reduce interrupt latency, intern | |
| SRB | (8) | HIT | SOD-323 | 05+ | Note 3 tHAE is specd for case with HLD falling edge occurring at the lates |
| SRC | (133) | TI | 07+ | In addition to low distortion, the large amount of loop gain and fl | |
| SRD | (91) | SIEMENS | 04+ | ||
| SRE | (20) | MITSUMI | 04+ | 1.2.1 RHA designator. Device classes Q and V RHA marked devices me | |
| SRF | (293) | MOTOROLA | high-frequency tube | and output enable ( OE ) controls. The device requires only a single 3.0 | |
| SRG | (48) | ALPS | SALE--STOCK!! | 08/09+ | The over range devices display 1 and decimal point. The character he |
| SRH | (7) | UNRISE | 05+ | PLCC | C Internal Address and Data Latches C Internal Control Tim |
| SRI | (5) | ST | 07+ | The compensation capacitor is connected between pins 1 and 3 and | |
| SRJ | (3) | Any and all SANYO products described or contained herein do not have speci | |||
| SRK | (7) | NEC | 91+ | If the heating up feature is present, it inhibits the Auto Shut-Off funct | |
| SRL | (25) | 08+ | |||
| SRM | (260) | TSSOP | 38503 | EPSON | The external compensation capacitor CC is connected between pins |
| SRN | (28) | EIC | 07+ | • Integrated Pulse Shaping Circuit. • Built-in B3ZS/HDB3 Encod | |
| SRO | (10) | HN58X24xxI series are two-wire serial interface EEPROM (Electrically Eras | |||
| SRP | (53) | RAYCHEM | RAYCHEM | 08+ | DATA POLLING: The AT49BV16X4(T) features DATA polling to indicate the en |
| SRQ | (1) | Within each processing element is a set of computational units. The comp | |||
| SRR | (19) | 94 | Extensive applications information for Hall-effect sensors is avai | ||
| SRS | (60) | 97 | The HY51V(S)16163HG/HGL is the new generation dynamic RAM organized 1,048, | ||
| SRT | (19) | OMRON | Calibrated directly in Celsius (Centigrade) Linear a 10 0 mV C scale fact | ||
| SRU | (23) | BOURNS | 2007+PB | Each device requires only a single 3.0 volt power supply for both read a | |
| SRV | (19) | SEMTECH INTERNATIONAL | 08+ | SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIM | |
| SRW | (13) | TDK | The 7640 group, an enhanced family of CMOS 8-bit microcontrollers, offers | ||
| SRX | (25) | Positive driver supply pin for the ADC12DL065s output drivers. This pin | |||
| SRY | (2) | ||||
| SRZ | (4) | ||||
| S-S | (2) | The product term select multiplexer (PTMUX) allocates the five product te | |||
| SS- | (185) | ST | 07+ | Designed for 802.16 WiBro and dual mode applications with frequenc | |
| SS0 | (42) | N/A | The 3K bytes of static RAM are used for temporary storage of data and for | ||
| SS1 | (231) | ON | DO214AC | 05 | The BALBSG (the indicates the output voltage value) is a low-saturation |
| SS2 | (161) | gs | gs | dc04 | |
| SS3 | (102) | N/A | N/A | N/A | Regulators (ISRs). These ISRs are de- signed with premium low threshold |
| SS4 | (76) | HONEYWELL | Eight GLBs, 16 I/O cells, dedicated inputs (if available) and one ORP a | ||
| SS5 | (45) | Honeywell | SOT89S | 06+ | Texas Instruments LinCMOS process offers superior analog perfor |
| SS6 | (78) | sam | sam | dc87 | A burst write access to an active row is initiated with the WRITE comman |
| SS7 | (23) | MOT | 01+ | The Simtek STK12C68 is a fast static RAM with a nonvolatile, electrical | |
| SS8 | (99) | N/A | N/A | N/A | Precision Fixed Operating Frequency KA1M0265R (70kHz) , KA1H0265R (100k |
| SS9 | (84) | FAIRCHILD | 06/07+ | Internally current controlled to cover extended range of 70 cm. Cur | |
| SSA | (52) | AUK | SOT23 | 07+ | The HYB 39L128160AC Mobile-RAM is a new generation of low power, four ban |
| SSB | (53) | ALLEGRO | SOT-23 | 05+ | The Intersil ICL32XXE devices are 3.0V to 5.5V powered RS-232 transmitte |
| SSC | (94) | ????? | Phase Jitter has long been recognized as one of the most critical and def | ||
| SSD | (196) | FAIRCHILD | 0231+ | SO-8 | Suffix denotes Vz tolerance: non suffix for 20%, A suffix for 10%. Measu |
| SSE | (4) | Address, active High. These 18 inputs, combined with the DQ[15]/A[ | |||
| SSF | (186) | FAIRCHILD | TO-3P | 05+ | TSOP40 C 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline . |
| SSG | (36) | The PSoC architecture, as illustrated on the left, is comprised of four | |||
| SSH | (132) | FAIRCHLD | TO-247 | 05+ | 3) Down convert to an I.F. of 1MHz then digitize at a rate of 1MHz. In |
| SSI | (214) | SSI | QFP- | 07+/08+ | The Hitachi HN58S256A is a electrically erasable and programmable EEPROMs |
| SSK | (8) | N/A | OKI | 04+ | Micropower Operation Single 5V or 15V Supply Operation Low Charge Inject |
| SSL | (192) | . | Synchronous Address Advance. ADV is an active LOW input that is used to ad | ||
| SSM | (680) | ADI | 07+ | Maximum ratings are those values beyond which device damage can occur. M | |
| SSN | (16) | BI | O7+ | SIGNAL DESCRIPTIONS See Figure 1, Logic Diagram, and Table 1, Signal Na | |
| SSO | (38) | siliconsensor | siliconsensor | dc99 | Channel 0 Red (V) Video Input. Input for Red component video channel or |
| SSP | (231) | FAIRCHILD | The GS82032A is an SCD (Single Cycle Deselect) pipelined synchronous SR | ||
| SSQ | (77) | N/A | In this mode, CS is active (low) between serial I/O CLOCK transfers and e | ||
| SSR | (123) | FAIRCHILD | TO-251/252 | 05+ | Har d war e Res et , ac t iv e L o w. Provides a hardware method of reset |
| SSS | (175) | FAIRCHILD | TO-220 | 06+ | OUTPUT VOLTAGE PROGRAMMING Resistors R1 and R2 program the output |
| SST | (2675) | SST | 08+ | Configuration of a single-ended input has been facilitated by biasing n | |
| SSU | (45) | FAIRCHILD | TO-251/252 | 05+ | The AV34063 is a monolithic control circuit containing the primar |
| SSV | (21) | N/A | OTAX | 05+ | WRITE ENABLE (W) A write cycle is initiated on the falling edge of |
| SSW | (202) | FAIRCHILD | TO | The beginning of a block of 16 serial data at port A or B is determined b | |
| SSX | (1) | SINOSUN | TSSOP28 | 07+ | |
| SSY | (6) | ST | CAN | 03+ | 1. Configure the A/D to use the VREF+ and VREF- pins for the volt |
| SSZ | (1) | N/A | TI | 04+ | Forward-Current Transfer Ratio IC = 1.0 Adc, VCE = 2.0 Vdc |
| S-T | (11) | SEIKO | 03+ | This center tap Schottky rectifier series has been optimized for low reve | |
| ST- | (550) | COPAL | 3X3-2K | The address space is divided into eight areas. The data bus width and acc | |
| ST. | (2) | N/A | SMD | 98+ | The FCT374T and FCT574T are high-speed low-power octal D-type flip |
| ST/ | (28) | These phase detector outputs can be combined externally for a loo | |||
| ST0 | (89) | IDT | CDIP20 | † Stresses beyond those listed under absolute maximum ratings may c | |
| ST1 | (1075) | 94 | The digitally controlled potentiometers are imple- mented using 255 res | ||
| ST2 | (945) | N/A | N/A | N/A | Once the device detects a button press, it reads the button inputs and |
| ST3 | (453) | ST | SSOP-20 | Notes regarding these materials 1. These materials are intended as a re | |
| ST4 | (265) | ♦ Four Regulators in One Package ♦ Bias Power Using Charge | |||
| ST5 | (228) | ST | SOP-8 | The information contained herein is the exclusive property of Prime View | |
| ST6 | (1064) | 01+ | QFP | Host HCI Transport (3-Wire UART) To reduce the number of signals and to | |
| ST7 | (1479) | STM | is high. The CARRY and BORROW signals are high when the counter is coun | ||
| ST8 | (86) | SGS | 96+ | SOP-8 | Two on-chip low-dropout voltage regulators (LDO) are provided to minimize |
| ST9 | (787) | ST | Since Xilinx FPGAs can be reprogrammed an unlimited number of times, th | ||
| STA | (564) | SANKEN | 05+ | TRI-STATE is a registered trademark of National Semiconductor Corporation | |
| STB | (686) | ST | TO-263 | 04+ | For serial programming, SEN together with LD on each rising edge |
| STC | (518) | STM | TSSOP8 | 08 | The STC5NF20VA/STC5NF20V75A/STC5NF20V76A ensure that the output voltage d |
| STD | (910) | ST | TO-252 | 08+ | This product has been designed to meet the extreme test conditions and env |
| STE | (285) | AMI | NEW | 95+ | Charge in Li-Ion and Li-Polymer Batteries Supports the Smart Battery Spec |
| STF | (119) | ST | 07+ | These very small, low cost filters are intended for use with A-D and D-A | |
| STG | (284) | ST | QFN16 | 04+ | The internal circuit is composed of 3 stages (2- INPUT) or 5 stages (3- |
| STH | (148) | ST | TO-247 | 05+ | The AD581 can also be used in a two-terminal mode to develop a positive |
| STI | (520) | ST | QFP | N/A | SDA is a bidirectional pin used to transfer data into and out of the de |
| STJ | (10) | ST8 | 07+ | As with all power integrated circuits, the UDN2987A and UDN2987LW | |
| STK | (2454) | SANYO | A recommended PCB pad layout for the miniature SOT-323 (SC-70) package i | ||
| STL | (334) | ST | QFP | 05+ | The DS1386 executes a read cycle whenever WE (Write Enable) is inactive (H |
| STM | (686) | ST | 306 | The INFINEON Direct RDRAM is a general purpose high-performance m | |
| STN | (136) | ST | 06+ | EN (enable) is a CMOS input. A logic low turns the oscillator off. The t | |
| STO | (15) | N/A | International Rectifiers RAD-HardTM HEXFET® MOSFET technology provi | ||
| STP | (1937) | ST | TO-220 | 06+ | Dual MOSFET Drives for Synchronous Rectified Bridge Adaptive Shoot-Throug |
| STQ | (38) | N/A | Under many operating conditions, both the high-side (GH) and low-side ( | ||
| STR | (1190) | SK | DQ7, the Toggle Bits DQ6 and DQ2, the Error bit DQ5 or the Erase Timer | ||
| STS | (224) | TI | 07+ | 1. In certain applications, the external load-resistor current may includ | |
| STT | (536) | ST | 2008+ | *All outputs loaded; thresholds on input associated with output under tes | |
| STU | (102) | ST | TO | This device is intended to be used only in a half-bridge which drives in | |
| STV | (899) | PHI | Test data input. One of four terminals required by IEEE Std 1149.1-1990. | ||
| STW | (222) | ST | TO-247 | 06+ | † NOTICE: Stresses above those listed under Absolute Maximum Rating |
| STX | (31) | ON | TSSOP | 04+ | 4.3 Screening (JANTX, JANTXV, and JANS levels only). Screening sha |
| STY | (25) | ST | TO-247 | 05+ | Oxide passivated structure for very low leakage currents Epitaxial struc |
| STZ | (50) | ROHM | 23-5.6V | 05+ | . . . using the Schottky Barrier principle with a large area metalCtoCsil |
| SU- | (8) | N/A | 00+ | DIP-10 | The SU-103 is a ultra high-speed (UHS) CMOS compatible single-pole/singl |
| SU1 | (27) | SOP | 00+ | 10-Year Minimum Data Retention in the Absence of External Power Data is | |
| SU2 | (57) | st | 07+ | 10000 | 1. Sound spreading is easily modified using an external VR. 2. Few extern |
| SU3 | (5) | MOT | 01+ | TO-3 | Input Current, IIN, SCLK Pin Input Current, IIN, CS Pin &n |
| SU4 | (53) | Other | 07+ | RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/AN11/KBI0 RB3/AN9/CCP2* RB | |
| SU5 | (5) | N/A | N/A | N/A | Spansions Flash technology combines years of Flash memory manufacturing e |
| SU6 | (3) | Over voltage recovery (1) Ideal input span, does not include gain | |||
| SU7 | (1) | R2 sets the balanced output impedance to 500 Ω. L1 and C2 serve dua | |||
| SU8 | (5) | KEHYTAS | 29 (leap year - valid until year 2100), 30 and 31 day months are made a | ||
| SU9 | (2) | SANKEN | QFP100 | 00+ | The TMS551xx multiport video RAMs are high-speed dual-ported memory devic |
| SUA | (6) | QFP | 05+ | The timing diagrams in Figure 1 illustrate XDR DRAM device write and rea | |
| SUB | (112) | VISHIBY | 12000 | 07+ | Stresses beyond those listed under absolute maximum ratings may cause per |
| SUC | (97) | Cosel | Product term sharing is the process of using the same product term among | ||
| SUD | (194) | VISHAY | TO | To allow for simple in-system reprogrammability, the AT29LV1024 does not | |
| SUE | (1) | Several features have been designed in for added value. A thermal overlo | |||
| SUF | (21) | Vishay | GP20 | 08+ | RS is perhaps the easiest to measure accurately. The V-I curve is measur |
| SUG | (1) | SOP-28P | 05+ | Left Feedback Amplifier Inverting Input Left Feedback Amplifier Non-Inver | |
| SUK | (1) | ROHM | TO252-3 | Microcontrollers are often used in harsh environments where power supply | |
| SUM | (129) | VIHSYA | TO | requires that the differential linearity error not exceed 1 LSB in the n | |
| SUN | (27) | DIP | DIP | The reference level is sampled during SHP active period, and the voltage | |
| SUP | (151) | VISHAY | TO-220 | 04+ | The internal circuit is composed of 3 stages in- cluding buffer output, |
| SUR | (76) | TR | SOT363 | Parameter Remote On/Off Signal Interface (VI = 0 V to 75 | |
| SUS | (75) | Cosel | The device is an 8-bit high performance RISC-like microcontroller desig | ||
| SUT | (15) | AUK | SOT-363 | FEATURES D Replaces OR-ing Diodes D Operating Supply Range | |
| SUU | (20) | VISHAY | 06+ | Note: All information contained in this data sheet has been carefully che | |
| SUV | (4) | • General-purpose optical design independent of objective len | |||
| SUW | (32) | Cosel | switch and a second IMP8980D for communication with the line interface c | ||
| SUY | (8) | VISHAY | SOT-252-3 | 04+ | The MSK 0002 is a general purpose current amplifier. It is the ind |
| SUZ | (1) | SMD28 | All synchronous inputs pass through input registers controlled by the ris | ||
| SV- | (5) | SIEMENS | SOP | 07+ | s Anyone purchasing any products described or contained herein for an abo |
| SV/ | (2) | All voltages are referenced to VSS. Offset specified after auto-calibrati | |||
| SV0 | (38) | SANKEN | The Watchdog Timer provides an independent protection mechanism for mic | ||
| SV1 | (28) | SGC | 1999 | Maximum Ratings are those values beyond which damage to the device may oc | |
| SV2 | (13) | JAT | SOT | 05+ | Power Thyristor/Diode Module PK110F series are designed for various rect |
| SV3 | (6) | NEC | 06+PB | TTL/CMOS input select control signal for the LVDS LOUT0-LOUT2 outputs. LSE | |
| SV4 | (10) | ACBLE | stock | An IIC interface allows full programmability of internal algorithms and c | |
| SV5 | (16) | SILICON7 | BGA0811 | 03+/04+ | The Hynix HYM71V32755AT8 Series are Dual In-line Memory Modules sui |
| SV6 | (13) | SILICON7 | 02+ | Test conditions unless otherwise noted. 1. T = 25º C, Supply Volta | |
| SV7 | (4) | Package drawings, standard packing quantities, thermal data, symbolizatio | |||
| SV8 | (7) | SBGA | 01+ | is the case then the N-Channel MOSFET is fully enhanced and the CTIM capa | |
| SV9 | (11) | SGC | 1999 | dresses are stable, the address access time (tAVQV) is equal to the del | |
| SVA | (7) | SAMSUNG | The C6701 includes a large bank of on-chip memory and has a powerful and | ||
| SVC | (225) | SANYO | 04+ | The Current Transfer Ratio (CTR) ranges from 100% to 200%. It also has an | |
| SVD | (9) | 8300 | functional operation of the device at these or any other conditions beyon | ||
| SVE | (8) | N/A | 06+ | NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaran | |
| SVF | (1) | ‡ The D packages are available taped and reeled. To oerder a taped | |||
| SVH | (14) | JST | 2008 | 4,500 | Information in this document is provided in connection with Intel product |
| SVI | (35) | TECHNICS | MODULE | N/A | 6. Cleaning solvents compatibility Dip cleaning with an organic solvent |
| SVL | (1) | A 6:1 stereo input multiplexer is included for selecting between line l | |||
| SVM | (145) | The SVM5550A is a physical layer device for a single wire data link capab | |||
| SVN | (2) | DIP8 | Description 48MDOT Output Control 1 = enabled, 0 = forced LOW 48MUSB Ou | ||
| SVP | (36) | CVA | DIP8 | The high-performance, 10-bit analog-to-digital converter (ADC) has a mini | |
| SVR | (17) | HCH | 3X3-20K | 05+ | Peripheral Features D 34 I/O Pins D Additional 32-Bit Accumulator D Thr |
| SVS | (7) | The power supply operating range of the EL2244 and EL2444 is from 18V d | |||
| SVT | (7) | DRIVE | • Learn C Learning involves the receiver calculating the tra | ||
| SVV | (7) | Assembler. The macro assembler allows the assembly code to be merged sea | |||
| SVX | (1) | HOSIDEN | 02+ | software developers, enabling the design of highly efficient and compac | |
| SVZ | (1) | SILICON | 04+ | Notes: 1. Non-repetitive Current Pulse Per Fig. 3 and Derated above TA=25 | |
| S-W | (3) | Nintendo | SOP64W | 2007+ | Figure 9(a) presents the 3-wire serial port protocol. As shown, the 3-wire |
| SW- | (183) | MACOM 03+ | (See Notes 1 and 4 and Figure 1 thru Figure 5 ) VCC e 5 0V g10% unless oth | ||
| SW/ | (1) | ||||
| SW0 | (63) | IC | SOP | The TPS72xx is offered in 2.5-V, 3-V, 3.3-V, 4.85-V, and 5-V fixed-voltag | |
| SW1 | (54) | M/A-COM | The TC650/TC651 acquire and convert their junction temperature (TJ) inf | ||
| SW2 | (104) | N/A | Overall ground is improved if a dense population of plated through holes | ||
| SW3 | (50) | MICROCHIP | 08+PBF | The H8S/2000 CPU can execute basic instructions in one state, and is prov | |
| SW4 | (11) | macom | macom | dc98 | provided by an active LOW chip enable (CE1), an active HIGH chip enable |
| SW5 | (3) | TO-220 | 06环保 | ||
| SW6 | (21) | LSI | 2007 | 524,288-word by 8-bit CMOS static RAM. The IS61LV5128 is fabricated usi | |
| SW7 | (32) | WS | DIP | The MM74HC14 utilizes advanced silicon-gate CMOS technology to achieve | |
| SW8 | (10) | TO | 01+ | switch either ac or dc loads. Connection B, with the polarity and pin | |
| SW9 | (11) | M/A-COM | the device can work also with dynamic ones). Many of its electrical cha | ||
| SWA | (6) | ON | 05+ | The SWAJ0311LT1 is a timing controller that combines an LVDS single pixe | |
| SWB | (12) | ZILOG | DIP | 99+ | The driver controls the gate voltage of the power switch. To limit large |
| SWC | (103) | SERVER | BGA | N/A | DESCRIPTION This new generation of TRENCH MOSFETs from Zetex utilises a |
| SWD | (19) | The internal circuit is composed of 2 stages including buffer output, w | |||
| SWE | (10) | Power down for voltage regulator. When driven low, the device uses an int | |||
| SWF | (32) | AD | A resistively-coupled lower-power complementary pair offers extremely l | ||
| SWG | (8) | SOP | • Plastic package has Underwriters Laboratories Flammabilit | ||
| SWI | (91) | N/A | 0805L | If the DPs are not required, then the connections shown in Table 2 can be | |
| SWL | (9) | Description These displays have a 32.9 mm (1.3 inch) character height. | |||
| SWM | (4) | MINI | 08+ | PRELIMINARY INFORMATION describes products that are not in full production | |
| SWN | (1) | SHAREWAVE | 0052 | 4.4.3.2 Group C sample selection. Samples for subgroups in group C | |
| SWO | (5) | DIP4 | 07+ | degradation of reliable operation. In addition, the high effi- ciency of | |
| SWP | (3) | BB | DIP | 00+ | The PSoC device incorporates flexible internal clock genera- tors, inclu |
| SWR | (10) | N/A | 01+ | The feedback network provides a closed loop gain of 1 000 and the integr | |
| SWS | (10) | IC | SOP | The SWSS0157/9 low voltage CMOS LDOs feature fixed or adjustable o | |
| SWT | (24) | The HPR2XX Series is designed for multiple channel applications that req | |||
| SWV | (1) | NOTE: 1. The level to be set on FS is determined by the nominal operatin | |||
| SWW | (2) | The architecture of the Direct RDRAM allows the highest sustained bandw | |||
| SWZ | (1) | Ideal for conversion from 1.8V or 1.5V inputs Designed for use with low | |||
| SX- | (33) | NANA | NO | In theory, the proportionality and digitization constants should adequat | |
| SX0 | (32) | AMIS/WavePlex | SOP-24P | 02+ | |
| SX1 | (75) | SENSYM | TO-39 | 9829 | Left Channel Input. Left Bass Control Pin 1. A Capacitor may be Connect |
| SX2 | (30) | MOT | SOP7.2mm | 1999 | A synchronized data clock, programmable for most common data rates, is pr |
| SX3 | (41) | (空白) | 1808 | Vishay Siliconix maintains worldwide manufacturing capability. Products ma | |
| SX4 | (6) | UBICOM | QFP-48 | Advantages n Replace expensive hybrid and module FET op amps n Rugged J | |
| SX5 | (19) | SMI | 4532 | 04+ | POWER-ON INITIALIZATION When power is first applied, power-on reset circ |
| SX6 | (17) | TOUODA | SOT-23 | 05+ | The CCITT V.22 standard defines synchronous operation at 600 and 1200 bit |
| SX7 | (14) | Honeywell | (LX)high-frequency | The Set Default command resets all conditions to the power on default sta | |
| SX8 | (4) | SANYO | 05+ | BGA | The 32K x 8 Radiation Hardened Static RAM is a high performance 32,768 |
| SXA | (96) | ARTESYN | SOP | The UVS-312A/313A/315A is 0.3 inch (7.62mm) height single digit display. | |
| SXB | (7) | SONY | 1997 | Notes ; 1O Repetitive Rating : Pulse Width Limited by Maximum Junc | |
| SXC | (4) | ABB | PLCC | 96+ | This pin supplies +5V supply voltage to the PLL circuit. We recommend tha |
| SXD | (3) | MOT | The ATF1502ASV macrocell, shown in Figure 1, is flexible enough to suppor | ||
| SXE | (82) | nec | nec | dc04 | Input switch. For V0 to V8 output, VL is output for low; VH for high. |
| SXF | (4) | MOTO | 0 | 1.1 Scope. This specification covers the performance requirements | |
| SXH | (6) | SIRENZA | SOT-89 | 06+ | Parameter Total Gate Charge (turn-on) Gate - Emitter Charge (turn-on) |
| SXI | (3) | SENSONIX | SOP-16 | 06+ | Recordings are stored into on-chip nonvolatile memory cells, providing zer |
| SXK | (8) | SONY | CDIP32 | 06+ | The ISP1563 is a Peripheral Component Interconnect (PCI)-based, single-ch |
| SXL | (4) | SIRENZA | SOT89 | 2003 | This center tap Schottky rectifier series has been optimized for low reve |
| SXM | (4) | Uses inexpensive 4 MHz reference crystal FIN capability greater than 120 | |||
| SXN | (14) | Fault protection is provided by an output overvoltage comparator and opti | |||
| SXO | (8) | N/A | SEOAN | 04+ | The TLV2262/4 also makes great upgrades to the TLV2332/4 in standard desi |
| SXP | (1) | MOTO | MODULE | 00+ | TEST LEVELS 1. Production test at room temperature and nominal supply vol |
| SXQ | (6) | JAT | 2520 | 05+ | |
| SXR | (1) | The main loop is responsible for updating the kWh counter and maintaini | |||
| SXS | (7) | JAT | 2520 | 05+ | • Up to 6-A Output Current • 5-V Input Voltage • Wide- |
| SXT | (33) | VISHAY/SI | SOT-89 | Guaranteed by design but not tested. Typical parameters are repres | |
| SXZ | (1) | SILICON | SOP | The block SelectRAM memory resources are 18 Kb of True Dual-Port RAM, p | |
| SY- | (18) | ||||
| SY/ | (1) | ZETEX | 100000 | functional operation of the device at these or any other conditions beyon | |
| SY0 | (10) | DIP-18P | 94+ | Revision 1.0 Supports up to Four Independently Controlled Hot-Plug Slots | |
| SY1 | (985) | MICREL | 2004 | Dual tones for the ringing signal are illustrated in the time domain (Fig | |
| SY2 | (44) | N/A | DIP | N/A | DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . - |
| SY3 | (17) | 07+/08+ | The MP3275 is a complete 16-channel, 12-bit Data Acquisi- tion Su | ||
| SY4 | (12) | MICREL | Note: 5. This input level is calculated from the input power delivered t | ||
| SY5 | (125) | MICREL | MSOP10 | 2004 | Serial Clock Input. By default, data is clocked into the input shift regi |
| SY6 | (54) | ELNA | 2008+ | OUTPUT DRIVE ENABLE (ODE) The ODE pin is the master output three-s | |
| SY7 | (1) | ELNA | The R/B output indicates the status of the device operation. When low, it | ||
| SY8 | (351) | synergy | synergy | dc02 | Device types identified as current may not be a first choice for n |
| SY9 | (3) | 07+/08+ | RESET: A RESET input pin is provided to ease some sys- tem applications. | ||
| SYA | (3) | MINI | 08+ | The SYAS-1 high current Schottky rectifier module series has been optimiz | |
| SYB | (2) | TDK | QFP | 07+/08+ | Makes DRAM Interface and refresh tasks appear virtu- ally transparent to |
| SYC | (18) | SYVANTEK | O7+ | The state of the OUT pin is driven by a voltage comparator whose | |
| SYD | (2) | MINI | 08+ | The ISP10160A SXP supports the following: s Ultra (Fast-20), Ultra2 (Fas | |
| SYF | (8) | ELNA | SMD | 06+ | When no data transfer is required, the power-down mode can be used. The s |
| SYG | (2) | ST | PLCC | 04+ | 1. One output at a time for a maximum duration of one second. VOUT = 0.5V |
| SYH | (5) | SYMBIOS | 03+ | • Internal VCO adjustment free circuit eliminating need for | |
| SYI | (1) | MTCREL | SOP | 602 | Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds D, DB, |
| SYK | (1) | MINI | 08+ | 专业射频微波 | The shift register bits are initialized to zero. Then starting with the le |
| SYL | (3) | ELNA | 2008+ | The F157A is a high-speed quad 2-Input multiplexer. Four bits of data fro | |
| SYM | (162) | SYMBIOS | QFP176 | Description Agilents MGA-71543 is an economical, easy-to-use GaAs MMIC | |
| SYN | (3) | DELAY: Delay programming pin for restart after overcurrent condition. A c | |||
| SYP | (24) | SYK | 38503 | SYK | Synchronous Address Advance. ADV is an active LOW input that is used to a |
| SYQ | (1) | Differential current outputs are provided to support single- ended or di | |||
| SYR | (3) | ST | SOP | 03/+04+ | Silicon implementations are much more cost effective than multi-wire cabl |
| SYS | (29) | N/A | 65 | The LXT974/975 provides three separate LED drivers for each of the four P | |
| SYT | (5) | synertek | synertek | dc77 | product term timing. For optimization of logic, the XPLA3 CPLD architect |
| SYU | (5) | DIP | N/A | The Hynix HYM71V8M635HC(L)T6 Series are 8Mx64bits Synchronous DRAM Modules | |
| SYV | (1) | N/A | QFP | This pin accepts a data enable signal which is high when active video da | |
| SYX | (13) | SYNERGY | SOP8 | 05+ | Internally trimmed offset voltage Low input bias current Low input noise |
| SYY | (1) | SYMBIOS | 03+ | RESET (RS) Reset is accomplished whenever the Reset (RS) input is | |
| SYZ | (1) | Infineon Technologies Components may only be used in life- support device | |||
| S-Z | (1) | The DS1554 is available in two packages (32-pin DIP and 34-pin PowerCap m | |||
| SZ- | (4) | BUFFER READ: Data can be read from either one of the two buffers, using d | |||
| SZ1 | (84) | N/A | ON | 04+ | Eight GLBs, 32 I/O cells, two dedicated inputs and two ORPs are connecte |
| SZ2 | (48) | DIP | 06+ | This N-Channel power MOSFET is manufactured using the inn | |
| SZ3 | (15) | LSI | PQFP-144 | 98 | One master and as many slaves as necessary may be connected in parallel t |
| SZ4 | (57) | delta | delta | dc0323 | During a Read or Write command cycle, Address input defines the colum addr |
| SZ5 | (51) | EIC | SMA | 07+ | Anyone purchasing any products described or contained herein for an above |
| SZ6 | (76) | EIC | SMB | 07+ | Hardware data protection measures include a low V CC detector that autom |
| SZ7 | (18) | MOT | • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) | ||
| SZ8 | (3) | delta | delta | dc0402 | IS61C6416AL and IS64C6416AL • High-speed access time: 12 ns |
| SZA | (19) | PHI | SOP | 97/P1 | Exposure of the device under conditions beyond the limits specified by Ma |
| SZB | (11) | The ADC12081 is a monolithic CMOS analog-to-digital con- verter capable | |||
| SZC | (7) | TDK | 99/00+ | Intels Series 2 Flash Memory Card facilitates high-performance disk emula | |
| SZF | (2) | ||||
| SZG | (10) | reliable operation, the stored energy from circuit inductance dissipated | |||
| SZH | (4) | jst | jst | dc01 | In addition to increased performance and FIFO size, the OXCF950 also pro |
| SZI | (7) | AMIS | SOP | 07+ | TI assumes no liability for applications assistance, customer product des |
| SZL | (4) | 7. Series resistance of the resonator (ceramic resonator or crystal) shoul | |||
| SZM | (244) | DIP42 | 4.4.2 Group B inspection. Group B inspection shall be conducted in | ||
| SZN | (1) | PH | 0744+ | NOTES 1Sample tested during initial release and after any redesign or pr | |
| SZP | (31) | on | on | dc00 | Figure 5. Block diagram of 2 GHz production test board used for Noise Fig |
| SZR | (1) | 84 dB dynamic range TX/RX Integrated analog front end (AFE) and 2- to 4- | |||
| SZT | (29) | ZILOG | SOP | 02+ | The transmitter data path consists of a transmit input buffer, pulse-sha |
| SZW | (1) | N/A | The spacings between the request packets are constrained by the followin | ||
| SZX | (8) | Maximum ratings are those values beyond which device damage can occur. Ma | |||
| SZZ | (2) | SZI | 91 | NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATIN |
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