| Mfg | pack | D/C | Descrpion | ||
| B.H | (1) | 1. MC100ES6139 circuits are designed to meet the DC specifications shown | |||
| B/S | (1) | ||||
| B/T | (1) | ||||
| B-0 | (3) | AMI | SSOP-28 | + | Maximum ratings are those values beyond which device damage can occur. Ma |
| B0- | (1) | B | 管 | The first bit of all commands is a Manchester 0, which is defined as mo | |
| B00 | (25) | ST | TSOP | To ensure good thermal conductivity, the backside of the FM20 die is dir | |
| B01 | (18) | BOSCH | 模块 | 模块 | need very low flicker noise. The HSMS-285x is a family of zero bias de |
| B02 | (19) | Members of the Texas Instruments Widebus™ Family Flow-Through Arch | |||
| B03 | (12) | 95 | Uses inexpensive 4 MHz reference crystal FIN capability greater than 120 | ||
| B04 | (13) | © 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, regi | |||
| B05 | (78) | PHI | TQFP/80 | 03+ | The outstanding Vitesse web managed switch software system that runs on |
| B06 | (19) | 汇桥 | 4K/R | The Virtex-E FPGA family delivers high-performance, high-capacity progr | |
| B07 | (9) | PHI | PQFP44 | 07+ | Collision Output. Balanced differential line driver outputs from the coll |
| B08 | (25) | 94 | SANYO assumes no responsibility for equipment failures that result from us | ||
| B09 | (11) | PHILIPS | TQFP80 | 07+ | The FCT138T is a 1-of-8 decoder. The FCT138T accepts three binary weigh |
| B0A | (2) | 06+ | QFN-12 | In order to increase the adjustment range of VCO3 with fixed external tan | |
| B0J | (2) | ROHM | 0805 | The LTC®1628-SYNC is a high performance dual step- down switching reg | |
| B0S | (3) | 0243+ | Refer to the Timing Chart below. In normal steady-state C | ||
| B0U | (1) | In Power-Save mode, HCLK Clock is driven by Slow Clock, which is typical | |||
| B0W | (1) | ST | QFP | 07+ | Note 8: CIN, COUT, C1, and C2: Low-ESR Surface-Mount Ceramic Capacitors ( |
| B0Y | (1) | The UC385 is a low dropout linear regulator providing a quick response to | |||
| B-1 | (14) | 06+ | SMD | Evolving network speeds require critical functions such as forward | |
| B1- | (4) | Analog supply pin. Crystal oscillator interface. XTAL1 is an oscillator | |||
| B1. | (1) | Filtering The Freescale Semiconductor accelerometers contain an | |||
| B1/ | (1) | The isolation voltage is a galvanic isolation and is verified in an elect | |||
| B10 | (139) | TEMIC | SOP8S | 2007+ | The FAN7382 is a monolithic half-bridge gate driver IC for driving MOSFE |
| B11 | (155) | LF(TEC) | MS-013 | 06+ | For maximum output regulation, the HR301-2805 is provided with external |
| B12 | (172) | The EM39LV040 is a 4M bits Flash memory organized as 512K x 8 bits. The EM | |||
| B13 | (61) | LITEON | 06/07+ | TVS devices are not typically used for dc power dissipation and ar | |
| B14 | (79) | LITEON | SMA | Isolation Barrier The isolation barrier consists of two transformers and | |
| B15 | (60) | BAYSEMIT | 2008 | Note: All information contained in this data sheet has been carefully che | |
| B16 | (56) | VISHAY | SMA | 05+ | 1. All characteristics are measured with C = 0.1µF from Pin 1 to GN |
| B17 | (17) | LITEON | 06/07+ | • Wide frequency rangeC122.0MHz to 300.0MHz • User specified | |
| B18 | (22) | LITEON | 06/07+ | The 80C186EB Timer Counter Unit (TCU) provides three 16-bit programmable | |
| B19 | (23) | TFK | O7+ | The Discharge Count Register is used to update the Last Measured Discharg | |
| B1A | (8) | s+m | s+m | dc95 | DATEL makes no representation that the use of its products in the circuit |
| B1C | (6) | MAT | PLCC | 2006 | DRIVE ADDRESS LINE 0 OR TEST The DA0 address line is asserted by the host |
| B1D | (1) | ROHM | SOT-163 | HEXFET technology is the key to International Rectifiers advanced line | |
| B1H | (2) | ROHM | SOT-363 | Delay from CKI Rising Edge to ALE Rising Edge Delay from CKI Rising Edge | |
| B1P | (1) | Program memory can store both instructions and data, permit- ting the AD | |||
| B1S | (2) | PAN JIT | 光偶SMD4L | 0609+无铅 | ICS91309 comes in a 16-pin 150 mil SOIC, SSOP or 4.40mm TSSOP package. I |
| B1T | (1) | The macrocell register can be configured as a D-type or T-type flip-flop | |||
| B2 | (1) | • THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DEN | |||
| B-2 | (7) | NO | 04+ | C Replaces TTL, MSI, and other PLD logic C Integrates compl | |
| B2- | (1) | The MSK 3554 is a pin compatible, low gain stable, drop-in replace | |||
| B2. | (1) | Parameter STATIC PERFORMANCE2 Resolution (Each DAC) Accur | |||
| B20 | (96) | PULSE | 36831 | "Absolute Maximum Ratings" are those values beyond which the sa | |
| B21 | (33) | LITEON | 06/07+ | Open-Drain Output to Power Transistor Driving Fan. Connect to the gate of | |
| B22 | (36) | LITEON | SMB | 04+ | Most of our DC tach generators are housed in aluminum casings protected |
| B23 | (23) | LITEON | 06/07+ | Note 1: The data-input transition time is controlled by a 4th-order Bessel | |
| B24 | (60) | MORNSUN | 08+ | This document is a general product description and is subject to change wi | |
| B25 | (63) | LITEON | 06/07+ | The B250CC/B250B and B250CC/B250 are 5- stage and 4-stage Johnson counte | |
| B26 | (25) | DIODES | DO-214 | 07+ | The HYM72V12C736B(L)S4 Series are 128Mx72bits ECC Synchronous DRAM Modules |
| B27 | (21) | LITEON | 06/07+ | The MPC92429 is a 3.3V compatible, PLL based clock synthesizer ta | |
| B28 | (11) | VIN = 3.4V VIN = 3.4V or VIN = GND, OE = GND, fI = 10Mhz, outputs open | |||
| B29 | (15) | LITEON | 06/07+ | The MX841 is specifically designed to be operated from a single cell batt | |
| B2A | (2) | The Agilent 54830D Series Mixed-Signal Oscilloscopes unique- ly combine | |||
| B2B | (26) | JST | connector | 06+ | (Multiple winds are connected in parallel) Inductance Range: 10µH |
| B2D | (1) | SSOP-3.9-20P | 6+ | 260C for more than 10 seconds. • When shifting from preheatin | |
| B2F | (1) | PHILIPS | QFP-80 | QFP-80 | DESCRIPTION The M74HC4514 is an high speed CMOS 4 LINE TO 16 LINE SEGM |
| B2G | (1) | The LM2696 is capable of switching frequencies in the range of 100 kHz | |||
| B2H | (1) | This publication is issued to provide information only, which (unl | |||
| B2N | (2) | To program the offset values, PEN can be brought low after reset. On the | |||
| B2P | (11) | JST | connector | 06+ | Input Leakage Current, IIL Input Capacitance VDD = |
| B2R | (1) | For Surface Mount Applications Protection from switching transients, indu | |||
| B2S | (4) | NEC | FDIP | 97+ | The MAX1165/MAX1166 16-bit, low-power, successive- approximation analog-t |
| B2T | (2) | (Note 1) Derate 0.5mA above 70C. (Note 2) 50% duty cycle,1ms pulse width. | |||
| B2V | (1) | eupec | eupec | dc96 | Hynix HYMD132725B(L)8-M/K/H/L series is designed for high speed of up to |
| B2X | (7) | The functional block diagram shows the IEEE Standard 1149.1-1990 4-wire t | |||
| B-3 | (5) | Software Data Protection (SDP) The SST39VF160Q/VF160 provide the JEDEC a | |||
| B3- | (4) | ACRIAN | (LX)high-frequency | The MARC4 microcontroller consists of an advanced stack-based, 4-bit CPU | |
| B3/ | (1) | Infineon | 2004 | TQFP | The output modulation current can be controlled in the range from 0 mA to |
| B30 | (44) | KDS | DIP-3 | 08+ | The reference level is sampled during SHP active period, and the voltage |
| B31 | (26) | DIODES | 06/07+ | The PHY uses the S5_LKON_DS2 terminal to notify the LLC to power up and b | |
| B32 | (469) | epcos | epcos | dc00 | 3 lines symetrical (I/O) low-pass-filter High efficiency in EMI filteri |
| B33 | (23) | LITEON | 06/07+ | The negative terminal of the battery pack (negative terminal available to | |
| B34 | (46) | VISHAY | O7+ | AF Bypass terminal. It is connected to one of the input of a differential | |
| B35 | (87) | LITEON | 06/07+ | Analog ground Downstream port 2 USB data- Downstream port 2 USB data+ | |
| B36 | (28) | 93 | (1) VDRM and VRRM for all types can be applied on a continuous basis. Rat | ||
| B37 | (1011) | epcos | epcos | dc03 | The 6B Series digital subsystem communication is compatible with the ove |
| B38 | (29) | LITEON | 06/07+ | HIGH VOLTAGE TESTING Burr-Brown Corporation has adopted a partial discha | |
| B39 | (493) | s+m | s+m | dc99 | The MAX3060E/MAX3061E/MAX3062E high-speed transceivers for RS-485/RS-422 |
| B3B | (68) | N/A | 05+ | Dimensions InchesMillimeters MinMaxMinMax .178.195 | |
| B3C | (1) | The XC5200 Field-Programmable Gate Array Family is engineered to delive | |||
| B3D | (2) | OMRON | 原装 | 08+ | NOTES: (1) See High Voltage Testing Section. (2) IMR is defined with resp |
| B3F | (80) | OMRON | 原装 | 08+ | available. The data applied to the data inputs are transferred to the Q |
| B3G | (7) | NO | 04+ | ||
| B3J | (22) | OMRON | 05+ | ||
| B3M | (1) | OMRON | 原装 | 08+ | • Bidirectional data strobe(DQS) • Differential clock inputs( |
| B3N | (1) | ST | 2007 | If two or more UC1524 regulators are to operated synchro- nously, all o | |
| B3P | (7) | 05+ | SOP-5 | Six pairs of current referenced differential clocks Two 3V 180 displaced | |
| B3R | (9) | 06+ | SOP-5 | 6.2 ST20196 FEATURES DMT modulation Max. number of bit per tone: 15 b | |
| B3S | (16) | OMRON | 原装 | 08+ | Each DS1249 device is shipped from Dallas Semiconductor with its lithium |
| B3V | (2) | MAXIM | 00+ | (For a differential input unit) An example of I/O voltage characteristic | |
| B3W | (24) | OMRON | 05+ | The nominal value of the RF choke L1 is 100 nH. At frequencies below 10 | |
| B-4 | (13) | NO | 03+ | WRITE PROTECT: The write protect pin (WP) will allow normal read/write op | |
| B4- | (2) | Designed for use in solid state relays, MPU interface, TTL logic a | |||
| B4. | (1) | In Case 2 of Figure 3, external line build-out (LBO) and equalizer netw | |||
| B40 | (107) | N/A | The MAX104 is a fast silicon monolithic analog-to-digital converter (ADC) | ||
| B41 | (77) | BAY | 02+ | ||
| B42 | (31) | NEC | DIP | 06+ | where R CS = parallel combination of R14 and R15, VSENSE = 0.314V, NS = 2 |
| B43 | (59) | 06+ | SOP-13 | Inherently Matched LED Current High Efficiency: 84% Typical Drives Up to | |
| B44 | (1) | Serial-test information is conveyed by means of a 4-wire test bus or TAP | |||
| B45 | (524) | s+m | s+m | dc99 | |
| B46 | (16) | IB | 04+ | Notice: Stresses greater than those listed under Absolute Maximum Ratin | |
| B47 | (9) | The ripple rejection values are measured with the adjustment pin bypasse | |||
| B48 | (11) | SMHKO | Using the latest high voltage technology based on a patented strip layo | ||
| B49 | (6) | EPCOS | 00+ | The segment and backplane drivers each consist of a CMOS inverter, with t | |
| B4A | (1) | JAT | 32-position digital potentiometer 10 kΩ, 50 kΩ, 100 kΩ | ||
| B4B | (41) | PCS | 2008 | • Low Jitter • High Q Crystal actively tuned oscillator circu | |
| B4C | (1) | 12 | INTERSIL | 04+ | This document is a general product description and is subject to change wi |
| B4D | (19) | 250 | INTERSIL | 04+ | High speed Fast access time: 55/70/85 ns (max) Low power Active: 50 |
| B4F | (2) | The next value to choose is the Q factor. As dispersion is employ | |||
| B4G | (2) | F.T | SMD 8P | 08+ | † Stresses beyond those listed under absolute maximum ratings may c |
| B4P | (10) | JST | The B4P-VH 4096k NV SRAM with Phantom Clock is a fully static nonvolatile | ||
| B4Q | (3) | N/A | The instruction set consists of 51 instructions with three formats and | ||
| B4S | (3) | Full or Partial Card compliance checking LUN configuration and assignment | |||
| B4T | (1) | JAT | 2512 | 05+ | † All characteristics are measured with zero common-mode input volt |
| B4U | (1) | Each device requires only a single 3.0 volt power supply for both read a | |||
| B4V | (1) | NOTE: Intersil Pb-free plus anneal products employ special Pb-free materia | |||
| B4X | (1) | 0 | QFP | Also See: • HEDS-9000/HEDS-9100 Encoder Module Data Sheet | |
| B4Y | (1) | Maximum Ratings are those values beyond which damage to the device may oc | |||
| B-5 | (1) | l Rectangular-shaped, automatic mounting type l High tactile feedback (va | |||
| B5- | (1) | B | 管 | AS6UA25616 Intelliwatt™ active power circuitry Industrial and comm | |
| B5. | (1) | TOS | DIP-4 | 08+ | On Board 24Mhz Crystal Driver Circuit Can be clocked by 48MHz external so |
| B50 | (57) | BROADCOM | PBGA3535 | 03+ | deasserted. Data will be read out of the FIFO on both rising and falling |
| B51 | (48) | TOS | T0-220 | 01+ | The L1 memory system is the primary highest performance memory available |
| B52 | (19) | 2008 | The APW7004 provides a complete control and mul- tiple protection for a D | ||
| B53 | (15) | LITEON | 06/07+ | The receiver senses signals through the RXI input, which minimizes refl | |
| B54 | (145) | Serial data output; 5-V CMOS logic level tri-state output for output (sta | |||
| B55 | (31) | DIODES | DO214AC | 05 | USB Hub -1 Upstream and up to 4 Downstream Ports -Compliant with USB Spe |
| B56 | (25) | DIP8 | 03+ | • The products described in this document are subject to the foreign | |
| B57 | (342) | PHILIPS | SOP-14 | 98+ | Maximum / minimum signal levels The following table gives the transmitte |
| B58 | (297) | 长电 | SOD-123 | Recordings are stored in on-chip nonvolatile memory cells, providing zer | |
| B59 | (212) | 1. Data patterns are to have maximum run lengths and DC balance shifts no | |||
| B5A | (9) | Digital signal processing with the 16-bit RISC performance enables effect | |||
| B5B | (14) | JST | THERMAL CHARACTERISTICS Proper thermal management is critical for | ||
| B5D | (1) | Note(READ CYCLE): 1. tCHZ and tOHZ are defined as the time at which the o | |||
| B5E | (1) | 0 | QFP | Figure 7 shows the timing of the decoder output in short frame mo | |
| B5F | (6) | LT | SOP8L | 01+ | Hynix HYMD264G726B(L)4-M/K/H/L series is registered 184-pin double data ra |
| B5H | (1) | Hynix HYMD264726B(L)8-M/K/H/L series incorporates SPD(serial presence dete | |||
| B5J | (1) | initio | TQFP | 00+ | The Power-saving (PS) module implements the Idle mode (ARM7TDMI core cloc |
| B5K | (2) | TEMIC | O7+ | • High speed response (cut-off frequency: 40 MHz) • Built-in | |
| B5M | (3) | GENESIS | QFP160 | International Rectifiers R5 TM technology provides high performance pow | |
| B5N | (3) | ST | TO-263 | Notes: 1. The dominant wavelength, ëd, is derived from the 1931 CI | |
| B5P | (4) | Notes: 1. Test conditions assume signal transition times of 3 ns or less | |||
| B5S | (1) | The SY88713V operates from a single +3.3V or +5V power supply, o | |||
| B5V | (1) | MAXIM | 00+ | • High Brightness AlInGaP Material • Industry Stand | |
| B-6 | (3) | NAKAMICH.. | 05+ | †For information on tape and reel specifications, including part or | |
| B6- | (1) | ||||
| B6. | (1) | TC | DIP4 | ||
| B60 | (31) | The VC pin provides a connection point to the output of the error amplifi | |||
| B61 | (47) | NEC | DIP | Integrated Feature Set Static Modular CPU Clock Generato | |
| B62 | (17) | RICOH | BGA | 07+ | |
| B63 | (17) | QFP | NEC | 98+ | Optimized for 3.3-V Operation 3.6-V I/O Tolerant to Support Mixed-Mode S |
| B64 | (16) | s+m | s+m | dc91 | The Am186ED/EDLV microcontrollers have been designed to meet the most c |
| B65 | (151) | epcos | epcos | dc01 | The Advanced Interrupt Controller (AIC) controls the internal sources fro |
| B66 | (55) | MOTOROLA | 00+ | Spread spectrum may be enabled through I2C programming. Spread spectrum | |
| B67 | (55) | 9832 | Special handling is required for Flash Memory products in TFBGA packages. | ||
| B68 | (13) | The Hyundai HYM71V733201 H-Series are 32Mx72bits ECC Synchronous DRAM Modu | |||
| B69 | (139) | epcos | epcos | dc00 | The information provided herein is believed to be reliable; however, BURR |
| B6A | (1) | The SMBus block utilizes the read-byte/write-byte pro- tocol. It only sup | |||
| B6B | (24) | MICROLOGIC | QFP | 97+ | Input Voltage Range Quiescent Current Soft Start Time SD, PWM/PSM,SY |
| B6D | (1) | SIE | PLCC | • CASE: Hermetically sealed glass case with DO-7 (DO-204AA) | |
| B6E | (1) | RENESAS | 04+ | BGA | The ZiLOG ZHX1010 SIR transceiver is the ideal choice for applications in |
| B6P | (3) | itt | itt | dc95 | Preliminary Information- These data sheets contain minimum and maximum s |
| B6S | (5) | HY | SOP4 | 1999 | RC: RC is the oscillator timing pin. For fixed frequency operation, set |
| B6T | (4) | Allows Safe Board Insertion and Removal from a Live C 48V Backplane Circ | |||
| B6U | (4) | sie | sie | dc94 | 2.Controlling dimension: millimeters. 3.Maximum lead thickness includes l |
| B7- | (2) | B | 管 | Operation in -40C - 125C Environment TTL/DTL/CMOS Compatible Inputs NAND | |
| B7. | (2) | TOS | DIP-4 | 02+ | Ultra low dropout voltage Guaranteed 500 mA continuous output current |
| B70 | (20) | EPCOS | Red Negative Analog Input No Connect, (Note 5) Green Positive Analog | ||
| B71 | (16) | 88 | 96+/99+ | The LP358 and LP2904 are dual low-power operational amplifiers especially | |
| B72 | (261) | epcos | epcos | dc06 | The modulation format is chosen by the state of the CNTRL0 and the CNTRL1 |
| B73 | (20) | EPCOS | SMD | 2002 | A hardware method of locking a sector to prevent any program or e |
| B74 | (63) | SANYO | TO-92 | Low capacitance 7-fold bidirectional ESD protection diode arrays in small | |
| B75 | (6) | 92 | The values for the equation are found in the maximum ratings tabl | ||
| B76 | (18) | EPCOS | 2005+ | The upper ESD diodes for the R, G and B channels are connected to a sep | |
| B77 | (46) | EPCOS | 05+ | Drain-to-Source Breakdown Voltage Gate Threshold Voltage Ga | |
| B78 | (120) | = 111, then all 4 bits are high. If TECH[2:0] = 001, then only bit 5 is h | |||
| B79 | (10) | PLCC | 02+ | Internal Sample-and-Hold Single +1.9V 0.1V Operation Choice of SDR o | |
| B7A | (2) | OMRON | DC/DC: | structed as a multi-chip hybrid device. Actuation control is via an Inf | |
| B7B | (14) | JST | 2.0mm 7 Circuits in hand | 06+ | A functional block diagram of the MT8985 device is shown in Figure 1. The |
| B7C | (1) | ATMEL | QFP | 98+ | The LTC®3703 is a synchronous step-down switching regulator controlle |
| B7D | (1) | AT | 9838+ | 977 | Sony Ericsson has earlier announced (June 24, 2003) the decision to increa |
| B7H | (1) | Higher speed signalling timing. XHST = 1 normal synchronous to asynchrono | |||
| B7J | (1) | The Serializer transmits serialized data and clock bits (10+2 bits) from | |||
| B7N | (4) | ST | TO-252 | The MAX4060/MAX4061/MAX4062 are differential-input microphone preamplifie | |
| B7P | (9) | itt | itt | dc95 | Selections for 5.0 to 170 volts standoff voltages (VWM) Protection from s |
| B7X | (1) | TELEFILTERGmbH Potsdamer Straße 18 D 14 513 TELTOW / Germany Tel: | |||
| B-8 | (2) | The feedback voltage pin is the non-inverting input to the PWM comparator. | |||
| B80 | (42) | PT | SMD | 03/+04+ | Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Forward |
| B81 | (95) | epcos | epcos | dc01 | The B81130C1105M26 meets the increasing demands for higher output power |
| B82 | (487) | EPCOS | 2007+PB | The ceramic resonator of the stereo decoder PLL circuit is used as a sto | |
| B83 | (15) | SOP-16 | 1.1 Scope. This drawing documents two product assurance class leve | ||
| B84 | (30) | sie | sie | dc93 | for each channel of each device listed in this data sheet, absolute ma |
| B85 | (16) | SOP-8 | 601+ | • An accelerated 80C51 CPU provides instruction cycle times | |
| B86 | (9) | N/A | DIP | 2006 | Programmable for 13-Bit Linear Data or 8-Bit Companded (µ-Law) Data |
| B87 | (5) | DIP-24 | Supply voltage for the LNA, bias circuits, and control logic. External RF | ||
| B88 | (39) | EPCOS | SOT | 05+PB | Bus interface • Maximum of 25 MHz internal operation rate |
| B89 | (4) | TOSHIBA | 05+ | The serial output data word is comprised of 12 bits of data. In operatio | |
| B8A | (1) | NS | DIP-8 | 97+ | Reading from the device is accomplished by taking Chip Enable (CE) and |
| B8B | (13) | 96 | The device is organized as a 12-bit or 24-bit bus switch. When OE1 is LO | ||
| B8D | (2) | ZILOG | DIP | 03+ | AMDs Flash technology combines years of Flash memory manufacturing expe |
| B8J | (1) | TAOperating free-air temperature−55125−4085C ‡ Wi | |||
| B8N | (2) | ST | TO-263 | As address generators, the IALUs perform immediate or indi- rect (pre- a | |
| B8P | (4) | The ZL5011x are cost effective devices aimed at the low density applicatio | |||
| B8S | (2) | WTE | 07+ | NOTES ** Note that the Test Output pins on the flat pack are pads locate | |
| B-9 | (1) | The output pulse duration is programmed by selecting external resistance | |||
| B9- | (1) | B | 管 | *1 If the internal sync separation circuit is not used, either CSYNC &nb | |
| B9( | (1) | The MX98715A controller is an IEEE802.3u compliant single chip 32-bit f | |||
| B90 | (30) | SOP-16 | The functional block diagram shows the IEEE Standard 1149.1-1990 4-wire t | ||
| B91 | (8) | SANYO | N/A | 98+ | The Hynix HYM76V4M655HG(L)T6 Series are 4Mx64bits Synchronous DRAM Modules |
| B92 | (15) | BENCHMARQ | DIP | 96 | The HT75XX-1 series is a set of three-terminal high cur- rent low voltage |
| B93 | (7) | 08+ | When VCC is applied to the serializer and/or deserializer, the respective | ||
| B94 | (17) | With a fixed level on the BCLKR/CLKSEL pin, BCLKX will be selected as t | |||
| B95 | (32) | N/A | DIP | 07+ | Compact, highly efficient silicon rectifiers for mediumCcurrent a |
| B96 | (11) | ST | SMD | 2008 | The EM39LV040 provides two software methods to detect the completion of a |
| B97 | (4) | Note 2: Absolute maximum ratings are those values beyond which damage to | |||
| B98 | (7) | IMI | SMD | 98 | Real-time clock keeps track of hundredths of seconds, minutes, hours, day |
| B99 | (8) | N/A | As shown in Figure 4, the VSENSE input is connected to the collector of | ||
| B9B | (9) | JST | 07+ | The THS9001 is a medium power, cascadeable, gain block optimized for high | |
| B9C | (2) | GENESIS | QFP | 01+ | The onboard bandgap reference is stable with temperature and scaled for a |
| B9D | (1) | Perpendicular recording drive support for 2.88 MBytes Burst (16- | |||
| B9N | (4) | ST | TO-263 | The window comparator stage generates two serial data streams, one havin | |
| B9V | (1) | Parameter MASTER CLOCK (CLI) (See Figure 16) CLI Clock Period & | |||
| BA- | (34) | DIP | LEDBRIGHT | 3.04 | The input thresholds can be globally configured for either TTL ( 1.2 V |
| BA/ | (1) | 99 | QFP | Available in various package configurations, these detector diodes provi | |
| BA0 | (182) | ROHM | 00+ | Isolated Hermetic Package, JEDEC TO-257AA Outline Adjustable Output Vol | |
| BA1 | (493) | ROHM | SOP-14 | 04+ | The on-chip charge pump high side driver stage is floating and reference |
| BA2 | (180) | ROHM | SSOP20 | 03+ | The external bootstrap capacitor is necessary to achieve the fastest gat |
| BA3 | (575) | ROHM | JIP | JIP | * Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" |
| BA4 | (235) | N/A | SOP8 | 07+ | The ML6102 is a group of high-precision and low-power voltage detectors. |
| BA5 | (515) | 96 | The Texas Instruments MSP430 family of ultralow power microcontrollers co | ||
| BA6 | (1216) | ROHM | SMD | Note 3: The maximum allowable power dissipation is a function of the maxi | |
| BA7 | (526) | ROHM | 03/04+ | The undervoltage-lockout circuit turns the output transistor off whenever | |
| BA8 | (195) | ROHM | SMD | 2000 | NOTES: 1. All VDD pins must be connected to 3.3V power supply. 2. All V |
| BA9 | (208) | ROHM | SOP8 | The input waveform may be sinusoidal but below about 20 MHz the operatio | |
| BAA | (13) | M | 04+ | The TV-Out processor will perform non-interlace to interlace conversion | |
| BAB | (7) | AMIS | All devices provide break-before-make switching and are TTL and CMOS co | ||
| BAC | (5) | FAIRCHILD | SOP | 07+ | VDD (16) VDD is the positive supply connection. An internal shunt regul |
| BAD | (7) | NOTES 1Measured at I OUTA, driving a virtual ground. 2Nominal full-scale | |||
| BAE | (2) | PHILIPS | SOT-23 | Each device has 2 rows for identification. The first row designates the de | |
| BAF | (5) | TESA | SOP-8 | 06+ | Composite type with a P-Channel Sillicon MOSFET (MCH3339) and a Sc |
| BAG | (11) | • 200MHz Clock, 400Mbps data rate. • VDD= +2.6V + 0.10V, VDDQ | |||
| BAH | (3) | Intersil | sot23-5 | 06+ | The LTC®3416 is a high efficiency monolithic synchro- nous, step-down |
| BAI | (5) | SMD-16 | This is Preliminary document release. All specifications are subject to ch | ||
| BAJ | (12) | ROHM | SOT252 | 04+ | After setting SDP, any attempt to write to the device without the 3-byte |
| BAK | (5) | ROHM | 06+ | Outputs the result of whether the signal is PAL, SECAM or NTSC. Connect | |
| BAL | (34) | BAL | 高频管 | The VSP5000 device is a complete application specific standard product | |
| BAM | (12) | 广达 | SOT-252 | 07+ | |
| BAN | (10) | The ISL6434 includes an Intel® -compatible, TTL 5-input digital-to-a | |||
| BAO | (3) | ROHM | SMD | 07+ | CAUTION: These devices are sensitive to electrostatic discharge; f |
| BAP | (125) | NXP | 08+PBF | ||
| BAQ | (23) | Vishay | MiniMELF Glass (SOD80) | 08+ | Recovered Clock. These ECL 100K outputs (+5V referenced) represent the re |
| BAR | (343) | INFINEON/BD | N/A | N/A | |
| BAS | (1003) | All Data I/O Ports − 5-V Input Down To 3.3-V Output Level S | |||
| BAT | (882) | Infineon | SOT-23 | 05+ | Efficient Memory System. The memory controller maps the large on-chip 256 |
| BAU | (1) | The output current limit threshold of the regulator can be programmed w | |||
| BAV | (469) | PHILIPS | new/original | 07/08+ | The Schottky Powermite employs the Schottky Barrier principle wit |
| BAW | (174) | ROHM | 08+ | These Schottky-clamped high-performance multiplexers feature TRI-STATE o | |
| BAX | (17) | PHI | SOP | The HYM71V65M801 X-Series are Small Outline Dual In-line Memory Modules su | |
| BAY | (30) | sie | sie | dc89 | b) Be careful with ground connections. Avoid ground loops. In general, co |
| BAZ | (7) | 2008 | The AT40KAL can be used as a coprocessor for high-speed (DSP/processor-ba | ||
| BB- | (11) | ITT | SOT-23 | Logic control inputs can be driven up to +5.5V regardless of the supply v | |
| BB0 | (9) | BB | N/A | Internally fixed or adjustable output modes 250mV dropout at 1.0A load | |
| BB1 | (226) | PH | 07+ | The Hynix HYM71V8M655HC(L)T6 Series are 8Mx64bits Synchronous DRAM Modules | |
| BB2 | (52) | Siemens AG | n/a | dMAX Dual Data Movement Accelerator. The dMAX is a module designed to per | |
| BB3 | (196) | BB | CDIP19 | 00+ | Synchronous operation mode. This function pre- vents occasional motor noi |
| BB4 | (55) | BB | N/A | The ADC08D1500 is a dual, low power, high performance CMOS analog-to-dig | |
| BB5 | (130) | SOP-16 | 98+ | The PI90LV14 is a low-skew 1:5 clock distribution chip which incorporate | |
| BB6 | (106) | INFINEON/BD | N/A | N/A | The MK1491-06 requires some inexpensive external components for proper |
| BB7 | (45) | BB | 模块 | When the device is in current limit, there will be spurious oscil- latio | |
| BB8 | (115) | sie | sie | dc92 | 1 hp (0.75kW) power output Industrial rating at 150% overload fo |
| BB9 | (20) | PHILIPS | 08+PBF | (2) The technical information described in this material is limited to sh | |
| BBA | (14) | TSSOP-8 | 03+ | Internal Timing C With external components as indicated on the application | |
| BBB | (9) | PCS | 2008 | RV and CJ are very difficult to measure. Consider the impedance of CJ = | |
| BBC | (6) | AEG | 03+ | 2. Application PFC circuit(current continuous mode) This | |
| BBD | (17) | LAMBDA | 05+ | INPUT FRAME OFFSET SELECTION Input frame offset selection allows t | |
| BBE | (16) | 153 | MOTOROLA | 02+ | Internal Power Dissipation JA (Exposed paddle soldered down) JA (Expose |
| BBF | (2) | Note 3: Without a heat sink, the thermal resistance of the TO-3 package i | |||
| BBG | (21) | BCM | 2007 | The programming flowchart in Figure 3 shows the fast interactive programm | |
| BBH | (2) | N/A | N/A | N/A | After the input data remains zero for 2500 or 12 500 cycles of Fs as set |
| BBI | (15) | ALCATEL | 06+ | SNR = 90 dB in 150 kHz bandwidth (to Nyquist @ 61.44 MSPS) Worst | |
| BBJ | (2) | TSSOP-10 | 04+ | Absolute Maximum Ratings are stress ratings only. Permanent damage to the | |
| BBK | (3) | When the ECU experiences a loss of ground condition, this pin switch to a | |||
| BBL | (21) | samtec | samtec | dc95 | Notes: 1. For Max. or Min. conditions, use appropriate value specified u |
| BBM | (3) | FAI | SOT-23 | BP_DIS is used to enable or disable the autoswitching function between bu | |
| BBN | (1) | Because of the consideration for minimized power consumption, the max. | |||
| BBO | (76) | AD | SOP-8 | EXPANSION IN ( XI ) This input is a dual-purpose pin. Expansion In | |
| BBP | (24) | MINI | 08+ | The COP87L88GD/RD OTP (One Time Programmable) Family microcontrollers a | |
| BBR | (24) | BB | The LPS input is considered inactive if it remains low for more than 2.6 | ||
| BBS | (25) | N/A | (VDD = +5V 5%, VL = 2.7V to 3.6V; VSS = 0V or -5V 5%; fSCLK = 2.0MHz, exte | ||
| BBT | (13) | MSOP | 05+ | NOTES 1. Data, Clock and Enable inputs are high impedance Schmitt buffer | |
| BBU | (1) | SANYO assumes no responsibility for equipment failures that result from u | |||
| BBV | (1) | Maximum terminal current is bounded by the maximum applied voltage | |||
| BBW | (1) | 256 x 256 channel non-blocking switch Automatic signal identification (ST | |||
| BBY | (163) | Pulse Width Modulator (PWM) with six PWM outputs with deadtime insertion | |||
| BBZ | (3) | Pin-for-Pin compatible with AMD® Am186ES/188ES devices All features | |||
| B-C | (1) | SAM | QFP | 2006 | Loop enable. When LOOPENx is active high, the internal loop-back path is |
| BC- | (4) | Beceem | 0647+ | Eight sectors with 512 Kb each Program Page Program (up to 256 bytes) i | |
| BC/ | (7) | CAN | 04/05+ | Senses motion of ring magnet targets Integrated filter capacitor | |
| BC0 | (31) | SMA | TRI-STATE is a registered trademark of National Semiconductor Corporation | ||
| BC1 | (218) | N/A | N/A | N/A | TI380PCIA can connect to up to four devices in a system: the PCI bus, the |
| BC2 | (256) | MOT/ST | CAN3 | All part numbers end with a place code, designating the silicon die revisi | |
| BC3 | (382) | 03+ | Maximum voltage device can withstand without damage at rated voltage. &nb | ||
| BC4 | (117) | MOT/ST | CAN3 | Except for pin-to-pin input and output parameters, the a.c. parameter del | |
| BC5 | (440) | PHI | TO-92 | 02+ | In addition to the three required external power supplies, a +3.3V suppl |
| BC6 | (122) | HIT | SOP | 03/+04+ | Gain-Bandwidth Product (G +5) Gain Peaking 0.1dB Gain Flatness Bandwi |
| BC7 | (15) | NO | 1. Added DDR333 function 2. Updated DDR333 test specification 3. Deleted | ||
| BC8 | (1369) | 06+ | In case of the spindle motor to repeat acceleration anddeceleration , the | ||
| BC9 | (5) | US | QFP- | 07+/08+ | NTSC-M, PAL-M/B/D/G/H/I Composite, S-Video & YCrCb component video ou |
| BCA | (13) | MARVELL | 04+ | Handle carefully Solder under the following conditions. 5 seconds max. | |
| BCB | (8) | NA | 4532 | The matte tin finish on Sirenzas lead-free package utilizes a post anneali | |
| BCC | (24) | MICROCHIP | QFN-8P小体 | 6+ | The AC ACT843 consists of nine D-type latches with TRI-STATE outputs The |
| BCD | (2) | LED BRIGHT | 04+ | The HY62256A is a high-speed, low power and 32,786 x 8-bits CMOS Static R | |
| BCE | (1) | The power supply of the device must start its ramp from 0.0 V. Functional | |||
| BCF | (10) | As shown in the functional block diagram on Page 1, the ADSP- 21262 uses | |||
| BCH | (3) | ATHEROS | 35 | ||
| BCI | (1) | or bidirectional data flow in bursts. An automatic power down feature, c | |||
| BCK | (5) | INFIN | . | 04+ | Built-in watch dog timer Low current consumption130µA |
| BCL | (27) | N/A | Specular Reflectance (Rf): The amount of incident light reflected by a s | ||
| BCM | (1974) | BROADCOM | TQFP48 | 07+ | ENCV Variable clock enable (TTL compatible input) - This input directly c |
| BCN | (127) | BI | 2.2K-2010-8P | To lower power dissipation in the regulator, a dropping resistor can be | |
| BCO | (10) | BLOSSM | SOP-28 | O2 | The MAX2602 includes a high-performance silicon bipolar RF power transist |
| BCP | (249) | • Antiparallel diode for high frequency switching devices | |||
| BCQ | (1) | TO- | N/A | Please be aware that an important notice concerning availability, | |
| BCR | (730) | INFINEON | SOT-23 | 05+ | In the normal mode, these devices are 18-bit universal bus transceivers t |
| BCS | (59) | TDK | new | The 1 Mbyte Flash memory array is organized into nineteen blocks called | |
| BCT | (58) | TI | SOP | This pin has an on-chip 1.0MΩ pullup resistor. An a.c. coupled si | |
| BCU | (4) | BLOSSOM | QFP | 01+ | These devices are organized as four 4-bit low-impedanceswitcheswithsepar |
| BCV | (103) | INFINEON | SOT-23 | 05+ | -15 VOUT - is a regulated -15 volt output available for exter- nal uses. |
| BCW | (299) | PHILIPS | SOT23-3 | 06+ | † Package drawings, standard packing quantities, thermal data, symb |
| BCX | (386) | ph | ph | dc0451 | Notes : 4. CX1 must be placed within 0.7 cm of the HSDL-3610 to obtain |
| BCY | (164) | MOTOROLA | CAN3 | A family of products offers 3-line, 2-line, and simple decod- ers in 8-b | |
| BCZ | (6) | DSI | n/a | For a microcontroller that has no dedicated SPI bus, a general purpose | |
| BD- | (33) | LED BRIGHT | 04+ | These Precision Optical Perform- ance AlInGaP LEDs provide superior l | |
| BD0 | (41) | SOP-8 | • Universal Asynchronous Receiver/Transmitter (UART) Module | ||
| BD1 | (203) | PHI | Ground Supply voltage for logic Input voltage for LCD H : Data signal, | ||
| BD2 | (267) | PHI | TO-3P | 06+ | The high-side driver is designed to drive low rDS(on) N-channel MOSFETs. |
| BD3 | (254) | ROHM | 2008 | Figure 2 illustrates a typical application circuit (output source | |
| BD4 | (281) | ROHM | SOT-153 | 04+ | Unless otherwise specified, these specifications apply over V12=12V, V5=5V |
| BD5 | (187) | FAIRCHILD/POWER | TO-220 | 06+ | DESCRIPTION Frequency Range Small Signal Gain Small Signal G |
| BD6 | (345) | ROHM | SOP-8 | 00+ | The signal on the current sense input pin is also connected to the input |
| BD7 | (159) | ST/SL/POWER | TO-3P | 07+ | The ISO120 and ISO121 are precision isolation ampli- fiers incorporating |
| BD8 | (95) | FAIRCHILD/POWER/ST | TO-220 | 06+ | The test pins control the various test modes of the CY7C68310. Most test |
| BD9 | (175) | ROHM | TQFP-S32P | 6+ | 1) CPD is defined as the value of the ICs internal equivalent capacitance |
| BDA | (10) | FDS | 08+ | Features • Hole-less TO-247 package for clip mounting • | |
| BDB | (9) | ROHM | The melting temperature of solder is higher than the rated temper | ||
| BDC | (16) | MINI | 08+ | I2C BUS INTERFACE Data transmission from main µP to the LNBEH21 an | |
| BDD | (1) | Reset In: Sets the Program Counter to zero and resets the Interrupt Enabl | |||
| BDE | (2) | N/A | QFP-48 | Tantalum Characteristics Tantalum capacitors with a minimum 10-V rating | |
| BDF | (4) | DIGITAL OUTPUTS(6) Logic Family Logic Coding Low Output Voltage (IOL = | |||
| BDG | (17) | LUCENT | SOJ16 | 06+ | High Current Transfer Ratio, 800 % Low Input Current Requirement, 0.5 m |
| BDH | (2) | SANXING | 05+ | The device has several operating modes dependent on the applied v | |
| BDK | (1) | The Link Fault Indicator (LFI) output is a TTL-level output that indicat | |||
| BDL | (10) | Infineon | 06+ | TO-3P | SUPPLY VOLTAGE, +VS to CVS BOOST VOLTAGE, +Vb to -Vb OUTPUT CURRENT, wit |
| BDM | (1) | The signal current at the input flows into the summing node of a high-gai | |||
| BDN | (1) | The BDN10-3CB/A01 is a P-Channel Power MOS FET with low on-state resista | |||
| BDP | (41) | (1) Signal Output PWM signals of L channel and R output from OUTL | |||
| BDS | (117) | PHI | Separate byte enables allow individual bytes to be written. BW1 controls | ||
| BDT | (144) | FAIRCHILD/POWER/ST | TO-220 | 06+ | ON Semiconductors e2 PowerEdge family of low VCE(sat) transistors |
| BDV | (60) | FAIRCHILD/POWER/ST | TO-220 | 06+ | IOSShort-circuit output currentC 15C 85mA ICCSupply currentVID = 0, No |
| BDW | (135) | FAIRCHILD/POWER/ST | TO-220 | 06+ | HOTLink II devices are ideal for a variety of applications where parallel |
| BDX | (209) | ST/ON/FAIRCHILD | TO-126 | 08+ | DTACK signalThe external input data acknowledge signal. When using the ex |
| BDY | (97) | PHIL/ST/MOT | TO-3 | 07+ | IF IT DOES NOT WORK Poor soldering (dry joints) is the most common reaso |
| BE- | (9) | TI | SMD | wiring C2MOS technology. It is ideal for low power applications mantain | |
| BE0 | (9) | N/A | DIP | 2006 | The negative output voltage of the Power Trends PT6900 Series ISRs may b |
| BE1 | (2) | 13 | INTERSIL | 03+ | EUROPE: LDC for ON Semiconductor C European Support German Phone: ( |
| BE2 | (11) | • Function, pinout, and drive compatible with FCT and F logi | |||
| BE3 | (5) | N/A | SOP-8 | 08+ | These Schottky diodes are specifi- cally designed for analog and digital |
| BE4 | (6) | AO | CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic ch | ||
| BE5 | (2) | Serializer/Deserializer Independent Channel Operation 2.5-V Power Supply | |||
| BE6 | (1) | The MAX8597/MAX8598/MAX8599 voltage-mode PWM step-down controllers are de | |||
| BE8 | (9) | BT | PLCC | 07+ | STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions |
| BE9 | (2) | PHILIPS | PLCC | 95 | * 3 In case supply voltage provided outside without using charge-pump bui |
| BEA | (7) | INTERSIL | TSSOP10 | EE cell S1 controls whether the macrocell will be combi- natorial or re | |
| BEB | (2) | infineon | O7+ | The Fairchild Switch FST3126 provides four high-speed CMOS TTL-compatibl | |
| BEC | (2) | ||||
| BEE | (3) | ||||
| BEF | (3) | (2) Those contemplating using the products covered herein for the followi | |||
| BEG | (3) | PHILIPS | 06+ | Motorola reserves the right to make changes without further notice to any | |
| BEH | (3) | s Two serial (I2S-bus/Japanese) digital audio inputs with independent clo | |||
| BEI | (11) | N/A | PLCC-44 | The IC41C8512 and IC41LV8512 is a CMOS DRAM optimized for high-speed ba | |
| BEK | (1) | The device has up to 64K bytes of reprogrammable flash EE- PROM program m | |||
| BEL | (7) | N/A | DIP | 98+ | Wide Operating VCC Range of 0.8 V to 3.6 V Optimized for 3.3-V Operation |
| BEM | (2) | 06+ | Agilent Technologies HLMP subminiature LED lamps [3]. For example, the p | ||
| BEN | (4) | BENISTOR | STK | 2004+ | The Hynix HYM71V32655AT8 Series are Dual In-line Memory Modules sui |
| BEP | (7) | All synchronous inputs pass through input registers controlled by the ris | |||
| BER | (12) | PHILIPS | 00+ | The ULx2803A, ULx2803LW, ULx2823A, and ULN2823LW have series inpu | |
| BES | (9) | 0603B | TAOperating free-air temperatureC4085C NOTE 4: All unused inputs o | ||
| BET | (8) | IR | SMD20 | The DAC device type identifier default is 0101[b]. In order to ac | |
| BEX | (1) | 05+ | DSD quantization noise in the digital domain, and the resulting multi-le | ||
| BF- | (10) | WP | N/A | N/A | Data Inputs/Outputs: Inputs array data during program operation, when CE |
| BF0 | (130) | LCC | 07+ | The MM74HC14 utilizes advanced silicon-gate CMOS technology to achieve | |
| BF1 | (167) | MOT/PHI | CAN4 | The following figure provides a graphical repre- sentation of the MTC20 | |
| BF2 | (166) | PHILIPS | CAN3 | 06+ | 1.70 (43.18mm) PCB Height 168-Pin Registered DIMM with Double Sided ECC |
| BF3 | (99) | ACX | 100% production tested at the specified temperature. 100% production te | ||
| BF4 | (125) | 飞利蒲 | 袋装 | Passivated guaranteed commutation triacs in a plastic envelope suitable | |
| BF5 | (96) | KEJIAXIN | SMD | 2008 | The PSC bytes are pre-programmed by the manufacturer with a code, which |
| BF6 | (40) | PHI | 08+PBF | Output voltage is set to a nominal value between 26V and 28V, by an inte | |
| BF7 | (82) | PHI | SOT-223 | 05+ | 45V zener diode between VBAT and ground with a 500Ω resistor in ser |
| BF8 | (81) | PHILIPS | 08+ | ||
| BF9 | (193) | SIE | 01+ | Note: These are stress ratings only. Stresses exceeding the range specifi | |
| BFA | (9) | FSC | Note Stresses greater than those listed under MAXIMUM RATINGS may cause | ||
| BFB | (11) | SIE | 01+ | CPU Core power: 0.925V to 2.0V output range 1% reference precision over | |
| BFC | (126) | TI | QFP-52 | 99 | ‧SOP package 4 Pin type in miniature design (4.44.32.0mm / .173.169 |
| BFD | (8) | PHILIPS | 04+ | The contents of this specification are subject to change without further | |
| BFE | (6) | PHILIPS | 2008 | This option provides four choices for each group in frequency which imp | |
| BFF | (1) | MICROCHIP | QFN-8P小体 | 6+ | Ultrasonically bonded leads and controlled die mount techniques are util |
| BFG | (244) | PHI | SOT-143 | 05+ | Select data in or data out on SDA or Measurement latching for transmissio |
| BFH | (1) | TEM | DIP | 1999 | MIC2594: Turn-Off Threshold. When the voltage at the OFF pin is less than |
| BFI | (1) | ||||
| BFJ | (20) | DSI | n/a | In software control mode (only when using external trigger), if the START | |
| BFL | (2) | N/A | o 12-Bit Resolution, 1/2LSB Linearity o Single +5V Supply Operation o S | ||
| BFM | (9) | BUTTERFLY | SSOP-28 | ||
| BFN | (41) | INFINEON | E6327 SOT89-DD | 06+ | The MPX12 series device is a silicon piezoresistive pressure senso |
| BFO | (1) | PHILIPS | 04+ | The analog input range is equal to a 2V spread. The voltage on VT-VB wi | |
| BFP | (216) | INFINEON | These devices are controlled through a 20MHz SPI™/QSPI™/MICRO | ||
| BFQ | (168) | PHILIPS | TO-92 | ||
| BFR | (312) | SIE | TO-92 | 04+ | The ISP2100A is designed to interface directly to the PCI bus and |
| BFS | (174) | SIEMENS | 99+ | Receiver Byte Clocks. Two 180 degrees out-of-phase 62.5 MHz clock signals | |
| BFT | (94) | PHILIPS | CAN3 | The TC554161AFT is a 4,194,304-bit static random access memory (SR | |
| BFU | (10) | PHILIPS | 06+ | SOT343 | n Fast single ended transceiver (typical driver enable and receiv |
| BFV | (25) | MOT / PH | CAN3 | 01+ | Note: Human Body Model ESD test performance for this product was demonstr |
| BFW | (65) | MOT/PHI | CAN4 | A six-byte command (Enter Single Pulse Program Mode) sequence to remove t | |
| BFX | (101) | N/A | N/A | N/A | The in-Line Micro filter has been specifically designed to implement the |
| BFY | (85) | N/A | N/A | N/A | Hynix HYMD264G726(L)4-K/H/L series incorporates SPD(serial presence detect |
| B-G | (1) | The memory portion of the device is a CMOS Serial EEPROM array with Int | |||
| BG0 | (9) | ph | ph | dc01 | Operating temperature range is C40C to +85C. Guaranteed by |
| BG1 | (33) | CNC7S101 is an AC input compatible optoisolator in which two GaAs | |||
| BG2 | (12) | eao | eao | dc93 | I2C BUS INTERFACE Data transmission from main µP to the LNBEH21 an |
| BG3 | (30) | N/A | QFP-80 | Lead Temperature (1.6mm or 1/16 from case for 10s)+260C (1) Stresses be | |
| BG4 | (7) | Extremely low 1µA supply current (typical) 2.55V on | |||
| BG5 | (8) | ST | 07+ | Features: Operates from 2.4V to 26V supply voltage with reverse v | |
| BG6 | (9) | Dropout Voltage The input/output Voltage differential at which the regu- | |||
| BG7 | (1) | DIP-4 | 07+/08+ | An excitation voltage is applied to the thermistor (RTHERM) and precisio | |
| BG8 | (1) | ||||
| BGA | (114) | Other | 07+ | n Single-cell 0.9V to 2.5V battery operation n BTL mode for mono speake | |
| BGB | (53) | PHILIPS | regulator and the load is gained up by the factor of (1+R2/ R1), or the e | ||
| BGC | (6) | INFINEON | 05+ | Input or Output Voltage (DC or Transient) (Referenced to VSS Vin, | |
| BGD | (53) | PH | 高频管 | N/A | The UCC381 provides unique short circuit protection circuitry that redu |
| BGE | (18) | PHI | Conditions Measured from input terminals to output terminals, s | ||
| BGF | (34) | PHILIPS | 0319+ | The g-cell is a mechanical structure formed from semiconductor ma | |
| BGG | (3) | PHI | QFN | 2005 | The four documents listed in Table 1 are required for a complete descripti |
| BGH | (11) | N/A | While maintaining all architectural and operational characteristics of th | ||
| BGJ | (5) | The LTC6900 operates with a single 2.7V to 5.5V power supply and provides | |||
| BGK | (1) | The TC170 brings low-power CMOS technology to the current-mode-sw | |||
| BGL | (10) | N/A | 0603B | Hynix BGL1608A330HT-H/L series is unbuffered 184-pin double data rate Sync | |
| BGM | (21) | NXP | 08+ | TRI-STATE is a registered trademark of National Semiconductor Corporation | |
| BGN | (1) | Note 2: Dropout voltage is specified over the full output current range of | |||
| BGO | (32) | NXP | N/A | 08+ | Using the first two interface options outlined above it is possible to co |
| BGP | (4) | SMA | The BGP36 16-kbit AddCOnly Memory identifies and stores relevant informat | ||
| BGR | (4) | NXP | N/A | 08+ | SIGNAL DESCRIPTIONS See Figure 1, Logic Diagram, and Table 1, Signal Na |
| BGS | (10) | N/A | |||
| BGT | (6) | MOT | PLCC52 | 05+ | The Bt8370/8375/8376 is a family of single chip transceivers for T1/E1 and |
| BGU | (3) | PHILIPS | 06+ | SOT343R | CPU_STOP# is an asynchronous input to the clock synthesizer. It is used to |
| BGV | (4) | 2008 | Select the desire reference voltage to be detected by serial data from th | ||
| BGW | (23) | NXP | SIP | 06+ | Master Clock. Master clock provides the clock for DSP. In MPI mode, it |
| BGX | (16) | With an increasing supply voltage the IC enters the start-up state; the | |||
| BGY | (281) | PHILIPS | O7+ | For additional flexibility, the MR pin is provided so the EPLD can | |
| B-H | (3) | FAIRCHILD | QFN | 05+ | The MAX4212/MAX4213 single, MAX4216 dual, MAX4218 triple, and MAX4220 qua |
| BH- | (66) | 霍尔传感器 | The TSM107 is a monolithic IC that includes three op-amp for which the | ||
| BH/ | (3) | MOT | CAN | 04/05+ | PRODUCT PREVIEW information concerns products in the formative or desig |
| BH0 | (30) | 交频管 | SOPT-14P | 05+ | 1.3.5.2 Decreasing Sensitivity In some cases the QT113 may be too sensiti |
| BH1 | (129) | ROHM | 06+ | HVSOF-5 | f=1kHz,THD=1% Volume=0dB VIN=1Vrms, f=1kHz Volume=0dB VIN=1Vrms, f=1kH |
| BH2 | (104) | OAKTECHLOGY | QFP-L160P | 6+ | Eight GLBs, 32 I/O cells, two dedicated inputs and two ORPs are connecte |
| BH3 | (202) | ROHM | 2004 | SOT-5 | The MAX5051 power-supply controller is primary as well as secondary-side |
| BH4 | (55) | ROHM | The repeatability of switching with a magnetic field is slightly affected | ||
| BH5 | (31) | VADEM | QFP | 07+ | Bt8110B offers internal ROM 24 or 32 full-duplex channel capacity (48 or |
| BH6 | (331) | Connect a resistor from this pin to the drain of the upper PWM MOSFET. | |||
| BH7 | (170) | ROHM | QFP | QFP | The MAX2680/MAX2681/MAX2682 operate from a sin- gle +2.7V to +5.5V supply |
| BH8 | (15) | ROHM | TSSOP | 05+ | The BH8100FV-E2EB/RB Family OTP (One Time program- mable) microcontrolle |
| BH9 | (118) | ROHM | QFP | 03+ | AT24C02SC, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 byt |
| BHA | (13) | DIP14 | 03+ | 2.7V to 5.5V Power Supply Low Power CMOS Active Read Current Less Than 1 | |
| BHB | (1) | ROHM | SSOP-16 | 04+ | Note 12: VREF is defined as the CCD OS voltage for the reference period f |
| BHC | (9) | BAI | 06+ | 500 | MPX200 series pressure sensors are available in absolute, differen |
| BHD | (38) | BOSHIDA | 07+ | MODULE | Users familiar with the PIC16C5X microcontroller family will realize th |
| BHE | (1) | ROHM | N/A | 00+ | The YZD and YED packages are available in tape and reel. Add a R suffix ( |
| BHF | (1) | 1.4 PHASE/FREQUENCY DETECTOR The Main and Aux phase(/frequency) detector | |||
| BHH | (2) | Beneficial comments (recommendations, additions, deletions) and any pertin | |||
| BHJ | (3) | ALPS | SOP32W | 2007+ | The MSP430x13x and the MSP430x14x series are microcontroller configuratio |
| BHK | (2) | ST | MODULE | N/A | If parallel loading is selected, both the COEF_WR pin and the LOAD_EN pin |
| BHL | (2) | A decode cycle begins immediately after the assigned re- ceive time-slot | |||
| BHM | (3) | The bandwidth of the HFA1102 may be limited by connecting a resistor (RD | |||
| BHN | (5) | Access Time: 200ns Simple Byte and Page Write Single 5V Supply | |||
| BHO | (1) | One/Two/Three/Four Independent DS3/E3 Framers on a Single Die Framing an | |||
| BHP | (17) | MINI | 08+ | The EM78M612 is a series of Universal Serial Bus 8-bit RISC Multi-Time Pro | |
| BHQ | (1) | N/A | Note 1: Absolute maximum ratings are DC values beyond which the device m | ||
| BHR | (36) | AD | 06+/07+ | PRELIMINARY INFORMATION describes products that are not in full production | |
| BHS | (24) | Jack(Available) | The UCC3588 synchronous step-down (Buck) regulator provides accurate high | ||
| BHT | (5) | SOT353 | 06+ | The RTL8308B is a 128-pin, low cost and ultra low power consumption 8-por | |
| BHU | (5) | ROHM | QFP | The L297s translator generates phase sequences for normal drive, wave d | |
| BHV | (1) | This 18-bit universal bus transceiver is built using advanced dual | |||
| BHX | (8) | When the master has received the ACKNOWLEDGE from the DS1050, the master | |||
| BHY | (1) | !Features 1) High power conversion efficiency. (BP5233-33A : 93%) 2) Lar | |||
| BHZ | (2) | Hand soldering and wave soldering should be avoided since these methods | |||
| BI- | (10) | BI | DIP8 | 05+ | 1. Due to the SCR structure inherent in the CMOS process, connecting any |
| BI/ | (2) | Stresses beyond those listed under "absolute maximum ratings" m | |||
| BI0 | (2) | BI | DIP14 | 03 | |
| BI1 | (124) | BI | 08+ | The following discussion refers to the schematic below. A FET cur | |
| BI2 | (4) | 2004 | !Features 1) Elimination of a transformer enables compact, lightweight po | ||
| BI3 | (15) | N/A | N/A | 0250+ | The voltage VIN in Figure 1 , on the left side of R1, is the signal volta |
| BI4 | (2) | BI | SMD8 | 03 | 2.7V to 3.6V SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPARATIONS FLA |
| BI5 | (1) | BI | 2008 | Note 2: Absolute Maximum Ratings indicate limits beyond which damage to t | |
| BI6 | (279) | 00+ | DIP | The active polarity of CLPDM and SHP (active high or active low) can be c | |
| BI7 | (11) | BI | SOP8L | 1991,08 | When the output is clamped, the negative input continues to source a sle |
| BI8 | (54) | BI | DIP16 | 07+ | Temperature Error Using Remote Diode of 0.13 micron Pentium 4 with typi |
| BI9 | (10) | IC | SOP | The high frequency oscillator allows the use of small inductors and outp | |
| BIA | (4) | PHILPS | SMD | 03/+04+ | Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital |
| BIB | (1) | ALCATEL | 06+ | between the two supply inputs is + 8.0 volts while the minimum voltage | |
| BIC | (40) | 01+ | dresses are stable, the address access time (tAVQV) is equal to the del | ||
| BID | (4) | 光纤 | 07+/08+ | Hynix HYMD264726B(L)8-M/K/H/L series incorporates SPD(serial presence dete | |
| BIE | (1) | MICROCHIP | 05+ | QFN-8P小体 | NOTES: 1. Pin is a NC for IDT70V658 and IDT70V657. 2. Pin is a NC for I |
| BIF | (11) | VIA | SOP | 506 | The BIFROSTMLAMAINCONTROLLERBOA is optimized for use as the primary-side |
| BIG | (8) | LIGHT | BGA | N/A | |
| BIH | (1) | ST | TO-220 | All voltage values, except differential voltage, are with respect to netw | |
| BIJ | (1) | If the open-load detection bit (OLD) is set to low, a pull-up current for | |||
| BIK | (1) | 92 | The Secure Microcontroller Family (DS5000FP, DS5001FP, DS5002FP, and ass | ||
| BIL | (2) | 4096-color STN LCD driver LCD drivers80-commons, 104RGB-segments Display | |||
| BIM | (5) | N/A | PLCC-M32P | 07+ | The SDA 9401 does a simple 100/120 Hz interlaced (50/60 Hz progressive) sc |
| BIN | (39) | N/A | Testing of the switching parameters is modeled after testing methods spec | ||
| BIO | (20) | AMIS | 06+ | The TDA8762 is a 10-bit high-speed analog-to-digital converter (ADC) fo | |
| BIP | (11) | EN (Pin 3): CMOS-BIPIC0106Kevel Digital Chip Enable Input. BIPIC0106Kogic | |||
| BIQ | (2) | BI | 03+ | 2µs Settling to 0.0015% for 10V Step 1LSB Max DNL and INL Over Indu | |
| BIR | (13) | SEC | SSMD | 98 | 1. 10 X 1000 ms, non−repetitive 2. 1 square copper pad, FR− |
| BIS | (40) | BI | The graph shows the boundary conditions which must be used for proper op | ||
| BIT | (49) | BITEK | QFP | 04+ | INPUT OFFSET VOLTAGE, initial OFFSET VOLTAGE, vs. temperature OFFSET |
| BIV | (5) | SC | QFN | 04 | INTERRUPT REQUEST: is a level triggered input which is sampled during the |
| BIX | (2) | Thermal fault. All the low-side transistors are turned on, shorting the l | |||
| BIZ | (1) | . | DIP | 1987 | For a write operation, the X24042 requires a second address field. This |
| BJ- | (6) | 220MHz Gain-Bandwidth Product 1500V/µs Slew Rate 6.5mA Supply Curr | |||
| BJ0 | (20) | ||||
| BJ1 | (19) | PHILIPS/BD | N/A | N/A | These Schottky chips are de- signed for hybrid applications at DC throug |
| BJ2 | (8) | 2B/0805 | The EBJ2BROM version of this device, the BJ2B, is available in plastic | ||
| BJ3 | (9) | The UCC5631A is used in multi-mode active termination applications, whe | |||
| BJ4 | (4) | BJ | N/A | 03+ | The TPS6102x devices keep the output voltage regulated even when the in |
| BJ5 | (2) | Operating the four memory banks in an interleave fashion allows random ac | |||
| BJ6 | (7) | N/A | Note The Absolute Maximum Ratings are those values beyond which the safet | ||
| BJ7 | (5) | FEATURES High Ripple Rejection70dB typ. (f=1kHz,Vo=3V Version) & | |||
| BJ8 | (16) | PHILIPS/BD | N/A | N/A | |
| BJ9 | (1) | The bq2014 determines battery capacity by monitoring the amount of charge | |||
| BJA | (3) | USB D+ signal. PWM2 output (10V open-drain). PWM1 output (5V open-drain) | |||
| BJB | (3) | PHILIPS/BD | N/A | N/A | This series of hermetically packaged products feature the latest advanced |
| BJC | (1) | The ISL6441 is a high-performance, triple-output controller optimized for | |||
| BJD | (1) | PHILIPS/BD | N/A | N/A | Item Power Rating Power Rating Thermal Resistance Resistance R |
| BJE | (4) | N/A | SMD | 03+ | Built-in overvoltage protection prevents the output from going above 115% |
| BJF | (1) | The DSC-544 digital-to-synchro (D/S) converter compliments DDCs low pr | |||
| BJG | (1) | PHILIPS/BD | N/A | N/A | Dual 2:1 multiplexer and 1:2 buffer 1C 4 Gbps fully differe |
| BJH | (9) | SGS | SOP-7.2mm | The DS1554 is in the read mode whenever CE (chip enable) is low and WE ( | |
| BJK | (3) | PHILIPS/BD | N/A | N/A | The spacings between the request packets are constrained by the followin |
| BJM | (3) | See Table 8 for information on other conversion rates. Gua | |||
| BJN | (1) | N3/23 | • LCD common output pins. • COM1, COM2, and COM3 are not us | ||
| BJP | (12) | N/A | Single-channel isolated signal-conditioning modules. Accepts outputs fro | ||
| BJS | (3) | SONY/SAN | N/A | N/A | BOOT BLOCK LOCKOUT DETECTION: A software method is available to determin |
| BJT | (3) | TOSHIBA | 03+ | • Auto precharge/precharge all banks by A10 flag • Possible t | |
| BJW | (2) | PHILIPS/BD | N/A | N/A | tPHZBus disable time17.5 ns tPLZSEL to A, B17.0 |
| BJX | (1) | ON | 2004 | - Wiper Movement Control. This input provides for wiper position ch | |
| BJZ | (3) | N/A | N/A | HP | LD3985G12R (*) LD3985G122R (*) LD3985G125R (*) LD3985G135R (*) |
| BK- | (15) | The MAX 7000E devicesincluding the EPM7128E, EPM7160E, EPM7192E, and EPM | |||
| BK/ | (411) | BUSSMANN | D077K18 | The 74VCXH16245 is an advanced performance, non−inverting 1 | |
| BK0 | (17) | TAIYO YUDEN | 08+ | Parameter DIFFERENTIAL INPUT PERFORMANCE DYNAMIC PERFORMANCE | |
| BK1 | (89) | TAIYO YUDEN | 08+ | The operating speed of each receiver and transmitter can be selected in | |
| BK2 | (46) | Each channel has a request bit associated with it in the 4-bit Request re | |||
| BK3 | (15) | N/A | The SY10EP89V is a differential fanout gate specifically designed | ||
| BK4 | (1) | ||||
| BK5 | (8) | BELLNIX | 07+ | A write cycle is accomplished by asserting write enable (WE) and chip ena | |
| BK6 | (22) | ASTEC | 10 years minimum data retention in the absence of external power Data is | ||
| BK7 | (3) | 1.4 ATM features Adaptation Layers: AAL5 (data), supported in h | |||
| BK9 | (9) | The PVN013 Series Photovoltaic Relay at 100 milliohms features the lowe | |||
| BKA | (28) | 2004/ | Differential termination for Stratix devices is supported for the left an | ||
| BKB | (3) | ST | N/A | 25 mV (or less) For normal line resistances data may be recovered from l | |
| BKC | (1) | † Stresses beyond those listed under absolute maximum ratings may c | |||
| BKD | (1) | 05+ | QFN-16 | The ISL6118 current sense and limiting circuitry sets the current limit t | |
| BKF | (1) | Finally, the CY7C374i features a very simple timing model. Unlike other | |||
| BKG | (51) | Stresses above these ratings may cause permanent damage. Exposure to abso | |||
| BKH | (13) | SDRAM Controller - 32-bit data bus interface - Supports two banks of SDR | |||
| BKM | (48) | NOTE: Device will meet the specifications after thermal equilibrium has b | |||
| BKO | (15) | MITSUBISHI | TOSHIBA is continually working to improve the quality and reliability of | ||
| BKP | (16) | TAIYO YUDEN | 08+ | The ADSP-21262 contains two computational processing ele- ments that ope | |
| BKR | (3) | One factor affecting the quality of the CIDCW service is the CPEs CAS spe | |||
| BKS | (4) | N/A | QFP | 07+ | TIA/EIA-644 Standard Operate With a Single 3.3-V Supply Designed for Sig |
| BKT | (2) | The BKT-03E contains 12 tap cells with 108 12-bit memory locations for ea | |||
| BKU | (2) | MOT | QFP44 | 07+ | HEAT SINKING In addition to assuring that an application does not exceed |
| BKZ | (1) | The following are trademarks of Skyworks Solutions, Inc.: Skyworks®, t | |||
| B-L | (1) | HIC | 2008 | For Schottky barrier diodes thermal run-away has to be considered, as in | |
| BL- | (102) | ‧Telecommunications (PC, Electronic notepad) ‧Measuring and T | |||
| BL0 | (41) | BL | DIP-24 | The TC6501 and TC6503 have an open-drain, active- low output, which targe | |
| BL1 | (48) | B | 2002 | n Memory mapped I/O n Software selectable I/O options (TRI-STATE ® | |
| BL2 | (22) | ACX | This is often true. With pin 8 shorted to V+, a check on the potentials | ||
| BL3 | (28) | The HEDS-65xx/HEDL-65xx are high performance two and three channel op | |||
| BL4 | (7) | 06+ | SMD | Low-power dissipation Operating: 55 mW/MHz (typical) Single power supply | |
| BL5 | (29) | 88 | detection, and an FSK voltage comparator which provides FSK demodulatio | ||
| BL6 | (4) | Being a member of the switch family provides a number of unique advantag | |||
| BL7 | (3) | ST | BGA | 07+ | • Fast Write Cycle Time - Page Program time : 300µs(Typ |
| BL8 | (30) | SCANLOGIE | 00+ | TQFP0707-48 | In addition to the power-on-reset and undervoltage-supervisor function, t |
| BL9 | (10) | 02 | FEATURES Allows Safe Board Insertion and Removal from a Live C48 | ||
| BLA | (80) | 1 For normal continuous operation. A higher Tj is allowed as an overload | |||
| BLB | (16) | There are 2 types of data which should be accessed through the serial data | |||
| BLC | (10) | toko | toko | dc04 | Please be aware that an important notice concerning availability, |
| BLD | (2) | ti | ti | dc81+ | (1) Lead Forming When forming leads, the leads should be bent at |
| BLF | (112) | N/A | N/A | N/A | Caution: The BiCMOS inherent to the design of this component increases th |
| BLH | (3) | Vcc = 2.3V~2.7V, TA = 0C to 70C, unless otherwise specified -12 | |||
| BLK | (5) | MINI | 08+ | The BLK-18 has a dynamic range of 102dB for ADC, 106dB for DAC and is well | |
| BLL | (3) | PHI | SOT-502A | 6 | With the circuit modification shown in Figure 2, the trailing black level |
| BLM | (890) | 1206 | During the pre-equalizing, vertical sync and post equalizing periods, com | ||
| BLN | (2) | This pin represents the output of the charge pump. The voltage at this pi | |||
| BLP | (47) | MINI | 08+ | Asynchronous output enable. OE must be low to read data from the 71V2546/4 | |
| BLQ | (1) | MURATA | Electrically-insulating, thermally-conductive "pads" may be in | ||
| BLS | (18) | N/A | 01+ | SOP-8 | Each flip-flop can be triggered on either the rising or falling clock ed |
| BLT | (28) | N/A | N/A | SZ | Note 1: Absolute Maximum Ratings are those values beyond which the life |
| BLU | (29) | PH | 高频管 | N/A | The HMU16 has independent clocks (CLKX, CLKY, CLKL, CLKM) associated wi |
| BLV | (95) | PH | 高频管 | N/A | Note 2: When non−modulated signal (optical all high or all low level |
| BLW | (53) | N/A | N/A | N/A | Software Data Protection (SDP) The SST39VF160Q/VF160 provide the JEDEC a |
| BLX | (53) | N/A | N/A | N/A | NOTE: Permanent device damage may occur if Absolute Maximum Ratings are e |
| BLY | (43) | The compensation capacitor is connected between pins 1 and 3 and | |||
| BLZ | (11) | AVX KYOCERA | 04+ | The HS-1135RH is a radiation hardened, high speed, low power current fe | |
| B-M | (1) | SOP | 90 | Notes: 1. For codes not listed in the figure above, please refer to the r | |
| BM- | (10) | N/A | QFP | 03+ | When VCC is between 0 and 2.1 V, the device is in the high-impedance stat |
| BM0 | (35) | JST | 07+ | 2500 | The intended application of these devices and signaling technique is bo |
| BM1 | (41) | JST | 07+ | AVDD Current (Normal Mode) AVDD Current (Reduced Power Mode) AVDD Curren | |
| BM2 | (31) | BM | 2007 | TO-263 | By means of controlling pin 24 less than 0.5 V, it can make the audio mut |
| BM3 | (18) | I-Cube,Inc | PQFP | 1999 | HIGH to LOW prior to the expiration of the watchdog time out period. Th |
| BM4 | (11) | ZOWIE | 99+ | ADC data outputs are internally connected directly to the receivers digi | |
| BM5 | (13) | ZOWIE | QFP | 99+ | The simplest approach for generating low-current logic levels from an AC |
| BM6 | (17) | OWNS STOCKOWIE | 99 | An incoming data burst (Figure 2, top) is retrans- mitted as outputs A2 | |
| BM7 | (15) | NS | DIP | 93 | ON Semiconductors e2 PowerEdge family of low VCE(sat) transistors |
| BM8 | (23) | ASTEC | This application note presents the design of a temperature display LIN sl | ||
| BM9 | (4) | TAIWAN | 07+ROHS | HY5V22G is offering fully synchronous operation referenced to a positive | |
| BMA | (32) | N/A | N/A | N/A | Test Procedure 100% production tested and QA sample tested per QA test p |
| BMB | (19) | 0603B | The last bit of the slave address defines the operation to be performed. | ||
| BMC | (27) | bi | bi | dc03 | Each macrocell also generates a foldback product term. This signal goes t |
| BMD | (5) | N/A | In the absence of confirmation by device specification sheets, SHARP take | ||
| BME | (2) | The Asynchronous mode is used for communication with asynchronous termina | |||
| BMF | (5) | N/A | Memories C 8 to 32K dual voltage High Density Flash (HD- Flash) | ||
| BMH | (1) | YEON HO | 04+ | passes through one or more preheat zones. The preheat zones increase the | |
| BMK | (10) | A/N | 1206-3P | Note 2: Operating Ratings indicate conditions for which the device is fun | |
| BML | (6) | 88 | 135-mΩ -Maximum (5-V Input) High-Side MOSFET Switch 250 mA Continu | ||
| BMM | (3) | FAI | SOT-23 | 05+ | Bild / Fig. 6 B6 - Sechpuls-Brckenschaltung / Six-pulse bridge circuit H |
| BMO | (1) | NOTES 1All limits at temperature extremes are guaranteed via correlation | |||
| BMP | (8) | MINI | 08+ | Flexible 3-Wire Serial Digital Audio Input and Output Ports Master | |
| BMR | (49) | SOT23 | 00+ | The SM561 uses a Cypress proprietary phase-locked loop (PLL) and Spread | |
| BMS | (16) | BUJEON | 05+ | The device fully supports live-insertion with its Ioff and power-up/ dow | |
| BMT | (4) | BMT | DIP-8 | DIP-8 | The L5970AD is a step down monolithic power switching regulator with a |
| BMV | (2) | UCC | 07/08+ | multiplier. This is analogous to using an elephant to carry a twig. It m | |
| BMW | (11) | MOT | 01/02+ | PLCC68 | The LT ®1933 is a current mode PWM step-down DC/DC converter with an |
| BMX | (2) | N/A | The output stages switch at half the oscillator frequency, in a push-pull | ||
| BN- | (3) | - | - | 531 | The MT8985 device provides both functions and allows existing systems base |
| BN/ | (5) | ST | Tantalum Characteristics Tantalum capacitors with a minimum 10-V rating | ||
| BN0 | (7) | N/A | N/A | N/A | DP and DM are the high-speed USB signaling pins, and they should be tied |
| BN1 | (24) | STM | DIP8 | 00+ | result of the assumptions that VOH = VCC and VTH = 0.5 VCC. In addition |
| BN2 | (12) | The main counter, Nominal Available Capacity (NAC), represents the availa | |||
| BN3 | (4) | NEC | TO-92S | Collector-to-Emitter Breakdown Voltage Continuous Collector Current Co | |
| BN4 | (3) | solitron | solitron | dc71 | † Stresses beyond those listed under absolute maximum ratings may c |
| BN5 | (10) | DIP | The high-current-output drivers consist of MOSFET output devices, which s | ||
| BN6 | (1) | DPSI | 06+ | Recommended power supply range: 2.0 to 3.4 V 16 Channels 0 dBm nomina | |
| BN7 | (1) | 3. If an external source backfeeding the regulators output is gre | |||
| BN8 | (4) | DIP | 9509 | Added section 4.15.3 - In-System-Programming (ISP) of FLASH ROM De | |
| BN9 | (1) | NS | DIP | 07+ | The internal configuration of the Xinger® balun is diagramed above, t |
| BNA | (3) | 2004/ | IV Conclusions A silicon bipolar low power LNA for 1.9GHz has been design | ||
| BNB | (1) | FAIRCHILD | 23 | Logic input. A low level input turns off the high-side half-bridge MOSF | |
| BNC | (11) | N/A | 36928 | WRITE PROTECTION (WP) If WP is connected to Vcc, PROGRAM operation onto t | |
| BND | (4) | MIT | QFP/64 | Logic Ground Isolation-TTL/TTL, TTL/CMOS, CMOS/ CMOS, CMOS/TTL EIA RS 2 | |
| BNH | (1) | Inputs contain a jitter-free 19.44 MHz or a 6.48 MHz reference clock when | |||
| BNI | (3) | AMERICAN | Resolution Integral Nonlinearity (fin = 10kHz) Differential Nonlinearity | ||
| BNP | (10) | murata | NOTES: 1. Pins listed as LVTTL inputs will accept 2.5V signals under all | ||
| BNR | (5) | ST | QFP | 00 | † Stresses beyond those listed under absolute maximum ratings may c |
| BNS | (2) | The BNS4308R-102-220 is a programmable interval timer/counter, bi | |||
| BNT | (10) | ML | PLCC44 | 99+ | |
| BNW | (1) | The A3946 is designed specifically for applications that req | |||
| BNX | (13) | MURAT | • 8 external analog input channels, two with level shift in | ||
| BO- | (1) | MOT | 2008 | CAPITAL letters are used as subscripts for the desig- nation of static | |
| BO1 | (1) | CTI | 钢面 | 08+ | Case: JEDEC TO-220AB, ITO-220AB & TO-263AB molded plastic body Term |
| BO2 | (2) | Interrupt Controller C Interrupt control module is responsible for the in | |||
| BO3 | (3) | MX | SOP44 | 03+ | |
| BO5 | (2) | N/A | QFP | The time and date may be set by writing to the RTC registers. To avoid | |
| BO6 | (1) | The DSP56800 core is based on a Harvard-style architecture consisting of | |||
| BO7 | (3) | When a product has been in production for a period of time such that no c | |||
| BO8 | (3) | COILCRAFT | 05+ | The BO8TJ has a serial interface designed for daisy-chaining in multi-d | |
| BO9 | (2) | XILINX | 9314+ | Low capacitance 7-fold bidirectional ESD protection diode arrays in small | |
| BOA | (5) | M | 04+ | (according to DIN EN 60747-5-2(VDE0884)/ DIN EN 60747-5-5 pending) see fi | |
| BOB | (2) | The device offers stereo line level inputs along with two control input p | |||
| BOE | (1) | DIP-20 | 02+ | Typical Applications • Vibration Monitoring and Recording • | |
| BOM | (1) | This document is a general product description and is subject to change wi | |||
| BON | (1) | 05+ | SOP-5 | Figure 1 is a simplified block diagram of a subscriber line protection t | |
| BOO | (2) | PLCC68 | The Intersil SLIC incorporates many of the BORSHT functions on a single | ||
| BOP | (1) | LUCENT | 99 | NEW Fully Plastic TO-220 for HIGH VOLTAGE APPLICATIONS NEW SERIES, ENH | |
| BOS | (6) | SIEMENS | 08+ | The 28F400B3, 28F800/008B3, 28F160/016B3, 38F320/032B3 may contain design | |
| BOT | (3) | BUJ | 04+ | The SR (refer to Figure 4) contains the interrupt mask (seven levels avai | |
| BOW | (2) | 38 | AMIS | Although ESD protection circuitry has been designed into the VC-710 proper | |
| BOX | (12) | Lamp Type: 1X 32W T8 Lamp Line Input: 90-140VAC/60Hz Interface DALI ( | |||
| BP- | (6) | BKM | 2005 | Address, data inputs, and all control signals are synchronized to the inpu | |
| BP0 | (23) | IT | 05/06+ | each port are independent of one another and can be asynchronous or coinc | |
| BP1 | (66) | Description: The CENTRAL SEMICONDUCTOR CMPTA13, CMPTA63 series types are | |||
| BP2 | (23) | SOP16S | 2007+ | † Stresses beyond those listed under absolute maximum ratings may c | |
| BP3 | (22) | ST | N/A | This is an analog output which can be used as a reference source and/or | |
| BP4 | (33) | ST | N/A | Information furnished by Analog Devices is believed to be accurate and re | |
| BP5 | (99) | N/A | N/A | 07+ | The equivalent circuit for the sensing element is shown in the figure bel |
| BP6 | (10) | The sealed modules offer a metal baseplate for improved thermal performan | |||
| BP7 | (4) | 1) All in one chip IC incorporating functions of volume, tone, an | |||
| BP8 | (18) | PGA | 05+ | The RESET/OE and CE pins control the tri-state buffer on the DATA output | |
| BP9 | (1) | The STTH60L06, which is using ST Turbo 2 600V technology, is specially | |||
| BPA | (21) | IT | 05/06+ | Note 1: Absolute Maximum Ratings indicate limits beyond which damage to t | |
| BPB | (3) | TOSHIBA | 03+ | 8042 Software Compatible 8 Bit Microcomputer 2k Bytes of Program ROM 25 | |
| BPC | (24) | HE | 08+ | Shift Frequency Read Cycle Time Access Time Read Recovery Time Read Pu | |
| BPD | (5) | DESCRIPTION The 74V2T241 is an advanced high-speed CMOS DUAL BUS BUFFER | |||
| BPE | (9) | Each Address ALU can update one address register from its respective addr | |||
| BPF | (10) | *Note: Stresses above those listed under Absolute Maximum Ratings may caus | |||
| BPH | (9) | N/A | 1812 | The digital data is supplied to either an AM- or FM-input pin, the outpu | |
| BPI | (3) | Notes: 1. Gate Open 2. Measurement using the gate trigger characteristic | |||
| BPJ | (2) | The FAN53168 features a high bandwidth control loop to provide optimal r | |||
| BPL | (8) | TI | DIP-20 | 07+/08+ | 1. ICC is dependent on output loading when the device output is selected. |
| BPM | (9) | DATEL | 模块 | 08+ | SW(Pin 9): This is the drain of the internal NMOS power switch. Minimize |
| BPN | (11) | ||||
| BPP | (1) | ON | SOP-14 | 04+ | Enough current should be supplied into the VCC lead to keep the internal |
| BPS | (7) | ON | SOT–223 | 05+ | Load Mux. RRE = "1" and MSE = "1": LDM is an output te |
| BPT | (2) | N/A | DIP | 1.1 GHz Toggle Frequency Supply Voltage 4.5 to 5.5 V Low Power 4.0 mA Ty | |
| BPV | (15) | VISHAY | 2006+ | • IN-SYSTEM PROGRAMMABLE 3.3V In-System Programmability Us | |
| BPW | (64) | ph | ph | dc90 | Parameter Positive Supply Voltage (VCC to GND) Negative Supply Voltage |
| BPX | (41) | 金属帽 | 9819 | • Message bit rates up to 1 Mbps • Conforms to CAN 2.0B ACT | |
| BPY | (4) | The TPS773xx features an integrated power-on reset, commonly used as a su | |||
| BQ- | (21) | LED BRIGHT | 04+ | During discharge and charge, the bq2050H monitors V SR for various thresh | |
| BQ/ | (1) | PMI | 94 | RFM's OPB-series Voltage Controlled SAW Clocks are designed for use in Pha | |
| BQ0 | (68) | AVX | 07+ | The customer¢s voice sources are recorded section by section into an | |
| BQ1 | (4) | The HT36A0 is an 8-bit high performance RISC-like microcontroller specifi | |||
| BQ2 | (1031) | TI | SOP-8P | 07+ | This product features an asymmetrically-blocked architecture providing |
| BQ3 | (74) | 02+ | Published by OSRAM Opto Semiconductors GmbH & Co. OHG Wernerwerkstras | ||
| BQ4 | (182) | TI | 07+ | The small package size makes these LEDs prime choices for all backligh | |
| BQ5 | (3) | TI | SOP-8P | 07+ | ESD (electrostatic discharge) sensitive device. Electrostatic charges as |
| BQ6 | (3) | TI | SSOP-8 | 02+ | RFMs BQ6257C amplifier-sequenced hybrid (ASH) receivers are specifically |
| BQ7 | (5) | TI | 07+ | CHIP ERASE: The entire device can be erased at one time by using the 6-b | |
| BQ8 | (19) | BENCHMARQ | SOP | 07+ | Maximum output deviation is 10% inclusive of trim. If remote sense is not |
| BQC | (1) | NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATIN | |||
| BQE | (1) | P2ROM stands for Production Programmed ROM. This exclusive Oki te | |||
| BQF | (2) | TOPLINE | QFP-132 | 06+ | - Post processing operation : After capturing the full-frame raw data, RP |
| BQK | (1) | 05+ | QFP | Schottky Barrier Diode Characteristics Stripped of its package, a Schott | |
| BQM | (1) | The MK3725 is a low cost, high-performance, two output 3.3 Volt VCXO an | |||
| BQP | (1) | JAT | SMA | 05+ | DESCRIPTION The M27C4002 is a 4 Mbit EPROM offered in the two ranges U |
| BQW | (6) | ADAPTEC | TQFP-128 | 98 | The values for the equation are found in the maximum ratings tabl |
| BQY | (1) | PHI | 99+ | These devices have a certain immunity to fast negative going transients. | |
| BR- | (9) | PRONIC | N/A | The UC385 is easy to use. The adjustable version requires two resistors t | |
| BR0 | (7) | The outputs ability to swing rail-to-rail and not increase supply curren | |||
| BR1 | (69) | PHI | SOP | 05+ | Notes a. Room = 25_C, Full = −40 to 85_C. b. The algebraic conve |
| BR2 | (263) | ROHM | CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic ch | ||
| BR3 | (32) | RECTRON/SEP/HY | 07+ | Figure 9(a) presents the 3-wire serial port protocol. As shown, the 3-wire | |
| BR4 | (5) | ST | 05/06+ | • 8/10-bit A/D converter : 15 channels • Resolution i | |
| BR5 | (6) | ST | 07+ | While COEF_ADDR (9-7) selects MB0-MB5 for writing, COEF_ADDR (6-0) select | |
| BR6 | (41) | RECTRON/SEP/HY | 07+ | 3.5.1 Certification/compliance mark. The certification mark for de | |
| BR7 | (11) | 4. In the case of CMOS Output Type: The time interval between the rising | |||
| BR8 | (15) | RECTRON/SEP/HY | 07+ | The SMJ320C67x DSPs are the floating-point DSP family in the SMJ320C6000 | |
| BR9 | (234) | ROHM | n Window comparison simplifies design of ACPI compatible temperat | ||
| BRA | (22) | Hitachi | The listed characteristics are ensured over the operating range of the in | ||
| BRB | (8) | N/A | n −40˚C to +85˚C operation n Complete CODEC and filteri | ||
| BRC | (20) | Hitachi | Swap Drives A and B Non-Burst Mode DMA Option Det | ||
| BRD | (4) | PLCC | RAYTHEON | 94+ | The HYM72V32M656T6 Series are gold plated socket type Dual In-line Memory |
| BRE | (1) | MOT | PLCC52 | 06+ | The HAL5xx family consists of different Hall switches produced in CMOS |
| BRF | (40) | SOT23 | The L-Series converters utilize a single-ended for- ward topology with | ||
| BRG | (3) | STANLEY | Power down control. When PD is LOW, the inputs are disabled and internal | ||
| BRI | (8) | Paradise | QFP | 00+ | Electrical Characteristics (Tc=25) ItemSymbol Collector to Emit |
| BRO | (1) | DIP8 | Oscillator Pin. If a single-ended reference is used (such as a TCXO), it | ||
| BRP | (21) | Internal Timing C With external components as indicated on the application | |||
| BRR | (3) | LUCENT | 2007 | Hynix HYMD116725B(L)8J-J series is unbuffered 184-pin double data rate Syn | |
| BRS | (27) | LUCENT | SOJ | 99+ | (3) Inductor Selection A 10uH inductor is recommended for most ap |
| BRT | (133) | INFINEON | The CE pin is taken LOW to enable all Playback and Record operations. The | ||
| BRU | (4) | DESCRIPTION Ground pin. Complement clock of differential SRC clock pair | |||
| BRX | (7) | ph | ph | dc00 | Note: Stresses greater than those listed under MAXIMUM RATINGS may cause |
| BRY | (27) | 金属帽 | 2R | The UVS-312A/313A/315A is 0.3 inch (7.62mm) height single digit display. | |
| BRZ | (2) | PHILIPS | • 1.25(31.75mm) PCB Height • 168-Pin Unbuffered DIMM with Dou | ||
| BS- | (70) | LED BRIGHT | 04+ | Operating temperature range is: C40C to +85C. Guaranteed b | |
| BS0 | (15) | INFINEON | SOP-8 | 04 | The speech recognition engine uses sophis- ticated Hidden Markov Models ( |
| BS1 | (63) | ON | TO-92 | 07+ | The MAX8597/MAX8598/MAX8599 voltage-mode PWM step-down controllers are de |
| BS2 | (38) | BI | • 3.3V+0.165V/-0.165V Power Supply. • I/O Supply Voltage 3.3V | ||
| BS3 | (14) | TOKIN | SSOP | Note 3: The maximum power dissipation must be derated at elevated tempera | |
| BS4 | (2) | LG | BGA | 05+ | Each PIC block encompasses two PIOs (PIO pairs) with their respective sys |
| BS5 | (12) | SHARP | 05+ | ➀ Typical at TA = +25C under nominal line voltage and balanced &qu | |
| BS6 | (727) | BSI | TSSOP | 04+ | NOTES: (1) Junction Temperature = Ambient Temperature for low temperature |
| BS7 | (3) | NS | SOP | 98+ | Receiver data output. RDO is the received data converted back to asynchrn |
| BS8 | (18) | ROHM | BGA | 01+ | DSP CORE FEATURES 6.25 ns Instruction Cycle Time (Internal), for up to |
| BS9 | (21) | NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATI | |||
| BSA | (7) | N/A | module | 2005+ | Ready/Busy (RB). Ready/Busy is an open drain output that can be used to |
| BSB | (5) | 04+ | 2. VIH (max) = 3.0V AC.The overshoot voltage duration is 3ns. 3. VIL (mi | ||
| BSC | (96) | INFINEON | QFN8 | Note: 1. A write cycle occurs during the overlap of a low CS and a low WE | |
| BSD | (19) | SAMSUNG | NA | Linearity errors of 0.5 and 1.0 LSB, and Differential Non-linearity to | |
| BSE | (6) | The Hitachi HM62V8100I Series is 8-Mbit static RAM organized 1,048,576-wo | |||
| BSF | (11) | All 5 V tolerant with high sink current Hardware enhanced UART, SMBusT | |||
| BSG | (2) | PHILIPS | BGA | 2006+ | The TC55VEM208ASTN is a 4,194,304-bit static random access memory |
| BSH | (63) | PHILIPS | 05+ | Parameter Total Gate Charge (turn-on) Gate - Emitter Charge (tu | |
| BSI | (4) | 2004PB | 2.3 Order of precedence. In the event of a conflict between the te | ||
| BSJ | (10) | ph | ph | dc90 | Unlike masked or programmable gate arrays, which induce variable delay de |
| BSK | (8) | or Powered-Down Low and Flat ON-State Resistance (ron) Characteristics O | |||
| BSL | (8) | 1.High isolation voltage between input and output (Viso=5000 Vrms). 2.Co | |||
| BSM | (631) | The M68300 family of integrated processors and controllers is built on an | |||
| BSN | (49) | PHilip | 05+ | PRODUCT IDENTIFICATION: The product identifica- tion mode identifies the | |
| BSO | (79) | INFINEON | SOP8 | 04+ | The CY7C024V/025V/026V and CY7C0241V/0251V/036V are low-power CMOS 4K, |
| BSP | (360) | Infineon | SMD8 | 3 | • Wide frequency rangeC122.0MHz to 300.0MHz • User specified |
| BSR | (111) | N/A | DIP | 07+ | (5-V Input and Output Voltages With 3.3-V VCC) Bus Hold on Data Inputs E |
| BSS | (343) | ZETEX | 06+ | - | CONNECTION MEMORY Data to be output on the serial streams may come |
| BST | (102) | NXP | 08+PBF | † These characteristics are guaranteed by either production test or | |
| BSU | (1) | mouse trak | mouse trak | dc02 | The received digital signal input. Internal 1 M pullup. A logic |
| BSV | (96) | MOT | CAN | Atmel Colorado Springs, USA Atmel Nantes, France Atmel Colorado Springs, | |
| BSW | (97) | MOTOROLA | CAN3 | • Low power consumption: STANDBY - 72 µW max at 3.6V | |
| BSX | (150) | PHILIPS | CAN3 | • Design Flexibility Common Anode or Common Cathode | |
| BSY | (83) | KRC | 金属帽 | TOGGLE BIT: In addition to DATA Polling the AT28C010-12DK provides another | |
| BSZ | (1) | The ISP1181 is ideally suited for application in many personal computer p | |||
| B-T | (6) | IGS | QFP | 97+ | UART channel A Receive Data or infrared receive data. Normal receive data |
| BT- | (56) | LED BRIGHT | 04+ | The application circuits were designed to achieve the optimum combination | |
| BT0 | (11) | NHBT | DIP | DIP | DESCRIPTION Positive power supply for the chip CMOS functions High side |
| BT1 | (810) | PHILIPS | TO-220 | NOTES: 1. For conditions shown as Max. or Min., use appropriate value sp | |
| BT2 | (129) | batron | batron | dc99 | An external capacitor C is charged and discharged by two cur- rent sourc |
| BT3 | (30) | ph | ph | dc01 | • Fault Protected 16-Channel 12-Bit A/D Converter with Sampl |
| BT4 | (420) | PLCC | PLCC | Wide Operating VIN Range: Up to 80V Rugged Architecture Tolerant of 100V | |
| BT5 | (12) | N/A | N/A | N/A | Line preamplifier input Line receiver signals are input through a capaci |
| BT6 | (60) | BT | PLCC-28 | 07+ | stream into active Message Mode; i.e., the contents of the Connection Me |
| BT7 | (6) | ST | SOP-8 | The ADP3806 is a complete Li-Ion battery-charging IC. The device combine | |
| BT8 | (378) | BT | 02+ | Excellent performance is maintained to an absolute maximum of 25mA, howe | |
| BT9 | (74) | 95 | The transmitter accepts logic level clock (TCLK), positive data (TPOS) an | ||
| BTA | (856) | ST | TO-220 | 06+ | 1.2.1 RHA designator. Device classes Q and V RHA marked devices me |
| BTB | (484) | ST | TO-220 | 06+ | 256-position End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, |
| BTC | (15) | SIEMENS | 07+ | Note: All devices contains Access.bus (ACB), Clock and Re- set, MICROWIR | |
| BTD | (4) | 全宇晰 | SOT-23 | The temperature of the case should be measured using a thermocou- ple pl | |
| BTE | (2) | The target can run disk less, it only needs an ethernet connection The r | |||
| BTF | (14) | LUCENT | SOP | 06+ | The AT8xC51SND1C provides the necessary features for human interface like |
| BTG | (1) | The Simtek STK14C88-3 is a fast static RAM with a nonvolatile element in | |||
| BTH | (4) | PH | 06+ | Output Current (each output) Power Off Leakage, VCC = 0, C10 V p | |
| BTI | (1) | Gain Bandwidth Product: 2 MHz (typ.) Supply Current: IQ = 170 µA | |||
| BTK | (12) | LUCENT | SOP | 07+ | VSENSE = VCC VCB = (VCC C VSENSE) VGATE = 0V VTIMER = 1.5V, VGATE = 3V |
| BTL | (3) | PHILIPS | 2008 | Pin driving the discharge-controlling FET (P-ch) Normally "L"; | |
| BTM | (13) | infineon | QFP | 03+/04+ | |
| BTN | (11) | 全宇晰 | SOT-89 | The ISP1521 is a stand-alone Universal Serial Bus (USB) hub controller IC | |
| BTP | (11) | BT | 06+ | Features • High sensitivity (+4dB compared with ICX086AK) • | |
| BTQ | (2) | Japan Wide 100k/200k L L H H Dont care Dont care Dont | |||
| BTR | (10) | NO | Low cost Resolution better than 1milli-g at 1Hz Dual axis accelerometer | ||
| BTS | (552) | INFINEON | SMD | 02+ | Product Description/Features: • Low skew, low jitter PLL clock dri |
| BTT | (13) | batron | batron | dc94 | In order to use the Candy boards, users must have Windows 98 Sec |
| BTU | (4) | 7701 | |||
| BTV | (17) | BTV | QFP1420-100 | 95+ | The ADE7763 provides a serial interface to read data and a pulse output |
| BTW | (61) | ST | 04+ | The Universal Serial Bus (USB) interface is a 12-Mb/s or 1.5-Mb/s, multip | |
| BTX | (5) | 9149 | Pin-for-Pin compatible with AMD® Am186ES/188ES devices All features | ||
| BTY | (2) | Jack(Available) | When using the FOD2741, power supply designers can reduce the component c | ||
| BTZ | (1) | ||||
| B-U | (1) | The DG308B/309B analog switches are highly improved versions of the ind | |||
| BU- | (9) | DDC | 04+ | 4. Designed to meet these characteristics over the stated voltage and tem | |
| BU0 | (8) | TOS\AHIT | 01+ | TO-3 | For the system/MAC interface, seamless support is provided for the Motor |
| BU1 | (211) | PHIL/ST/MOT | TO-220 | 07+ | The BG-LEDs are packed in cardboard boxes after packaging in anti-electros |
| BU2 | (788) | ROM | 2001 | SOP | Four different schemes are shown in Figures 2, 3, 4, and 5. Note that th |
| BU3 | (243) | RESET: A RESET input pin is provided to ease some sys- tem applications. | |||
| BU4 | (372) | ROHM | Notes: 1. Operation of this device in excess of any one of these | ||
| BU5 | (222) | N/A | N/A | N/A | 3.7 Certificate of conformance. A certificate of conformance as re |
| BU6 | (201) | ROHM | QFP/56 | 97+ | The IRU1075 is a low dropout three-terminal adjustable regulator with min |
| BU7 | (96) | PHIL/ST/MOT | TO-3P | 06+ | Notice: The information contained in this data sheet pertains to products |
| BU8 | (179) | TO-3P | |||
| BU9 | (261) | PHIL/ST/MOT | TO-3P | 06+ | October 10, 2001: Revised AC timing characteristics in Tables 5, 6 |
| BUB | (6) | ON | The CS8920As analog front end incorporates a Manchester encoder/decoder | ||
| BUC | (5) | QFP | 94+ | The NJU6673 is a 25-common x 100-segment bit map LCD driver to dis | |
| BUD | (45) | FOUR | N/A | TEL | Copies of documents which have an ordering number and are referenced in th |
| BUE | (1) | The customer¢s voice sources are recorded sec- tion by section into | |||
| BUF | (204) | AD | CAN8 | The data contained in the data stream can also affect lock time. If a spe | |
| BUG | (1) | The data rate is scalable and the ATM protocol is the basis of the broad | |||
| BUH | (44) | MOT | TO-220 | 04+ | A common ground is required between the input and the output voltages. Th |
| BUJ | (34) | PHILIPS | TO- | There are recommended techniques such as grooves and ribs which may be u | |
| BUK | (1251) | N/A | FEATURES Laser Trimmed to High Accuracy: 10.000 Volts 5 mV (L and | ||
| BUL | (184) | ST | TO-220 | 08+ | Notes: 1. All InGaN LEDs represented here are IEC825 Class 2. See Applic |
| BUM | (1) | MAL | During a reprogram cycle, the address locations and 64 bytes of data are | ||
| BUP | (91) | N/A | TO-220 | 04+ | Electrical & Optical Specifications Specifications hold over the rec |
| BUR | (28) | ST | TO-3 | Vishay Semiconductors offers a wide range of semi- conductor components | |
| BUS | (133) | DDC | DIP | N/A | MAX 7000A devices contain from 32 to 512 macrocells that are combined in |
| BUT | (125) | FSC/PH | TO-220 | 05+ | Unless otherwise specified, these specifications apply over V12=12V, V5=5V |
| BUV | (115) | N/A | TO-3P | 04+ | The high-current power driver consists of FET output de- vices, which c |
| BUW | (108) | READ: The AT28C010-12DK is accessed like a Static RAM. When CE and OE are | |||
| BUX | (171) | ST | TO-3 | These 8-bit latches feature 3-state outputs designed specifically for dri | |
| BUY | (116) | PHIL/ST/MOT | TO-3 | 07+ | clock cycle Interleaved auto refresh mode Programmable burst lengths and |
| BUZ | (300) | LINFINEON | 03+ | 220 | There are two limitations on the power handling ability of a tran |
| BV0 | (40) | 91 | 77 instructions C-Language friendly architecture PI | ||
| BV1 | (10) | TO-220 | 07+ | SS (Pin 13) (soft start): SS will remain at Gnd as long as the IC is dis | |
| BV2 | (7) | advantage series | ＳＯＰ | original stock | AEC-Q100† Qualified for Automotive Applications Customer-Specific |
| BV3 | (6) | ST | The device is designed to comply with all JEDEC standards set for Synchro | ||
| BV4 | (6) | HAR | TO92 | 2000 | Segment resistors are desirable to minimize power dissipa- tion and chip |
| BV6 | (4) | ROHM | 2007 | CEL certifies, to its knowledge, that semiconductor and laser products de | |
| BV9 | (2) | 3.0 to 6.0V Supply Operating Range 8 MHz Maximum Clock Frequency -40 t | |||
| BVA | (1) | MOT | SOP-20 | 00+ | |
| BVC | (1) | These enhancement-mode (normally-off) transistors utilize a vertical DMO | |||
| BVE | (2) | axing | axing | dc00 | Hynix HYMD212G726(L)S4-K/H/L series is designed for high speed of up to 13 |
| BVF | (1) | The AD8353 can also operate with a 5 V power supply, in which case no ex | |||
| BVH | (2) | NEC | TSOP | 99 | |
| BVN | (1) | The LTC1051 is available in an 8-lead standard plastic dual-in-line packa | |||
| BVP | (2) | To prevent oscillations, place the output capacitor between the ou | |||
| BVR | (1) | N/A | N/A | The HYM72V16M636T6 Series are Dual In-line Memory Modules suitable | |
| BVS | (8) | PLCC | A0, A1, A2, A3 (Pins 2, 3, 21, 22) Address Inputs. These inputs a | ||
| BVT | (2) | The SP8480 Series are complete monolithic data acquisition systems, featu | |||
| BVU | (1) | N/A | The RF3315 is a high-efficiency GaAs Heterojunction Bipolar Transistor | ||
| BVV | (11) | The non-overlap time is the time between turning off the conducting pai | |||
| BVX | (1) | 150 µA Typ at 5 V Fast Response Time . . . 200 ns Typ for TTL-Leve | |||
| BVY | (1) | Collector-to-Emitter Voltage Continuous Collector Current, each IGBT Con | |||
| BVZ | (1) | This advanced power MOSFET is designed, tested, and guaranteed to withs | |||
| B-W | (1) | An on chip resistor is provided which can be used to drop the sup | |||
| BW- | (54) | MINI | 08+ | ICCMaximum Quiescent Supply Current5.58.080µAVIN = VCC or GND | |
| BW1 | (7) | How are these devices different than the other Crystal PCI audio products | |||
| BW2 | (5) | SOP | Stresses beyond those listed under absolute maximum ratings may cause pe | ||
| BW3 | (4) | SIT | 9035 | Notes: 1. Failure criterion ; IR > 100 nA at VR = 30 V 2. Plea | |
| BW6 | (1) | N/A | 2.1 General. The documents listed in this section are specified in | ||
| BW8 | (1) | ROHM | 07+/08+ | Parameter Total Gate Charge (turn-on) Gate - Emitter Charge (tu | |
| BWA | (2) | NEC | DIP | 06+ | The NL17SZ07 is a high performance single inverter with open drai |
| BWD | (22) | IPD | SOP | V+ - Is the higher voltage H-bridge supply. The MOSFETS obtain the drive | |
| BWF | (1) | Parameter Positive Supply Voltage (VCC to GND) Negative Supply Voltage | |||
| BWH | (1) | regulator and not to the load. In fact, if R1 is connected to the load si | |||
| BWL | (2) | NEC | TO-92 | 99 | When the APC pin is asserted, the phase build-out function is triggered |
| BWR | (66) | DATEL | 00+ | 模块 | The TOSHIBA products listed in this document are intended for usage |
| BWS | (16) | MINI | SOP | 98+ | I/O READ: I/O Read is a bidirectional active low three-state line. In the |
| B-X | (2) | SEIKO | Sampling clock rates can be programmed to 16, 32 or 64K bits/second from | ||
| BX- | (26) | LED BRIGHT | 04+ | • Molded epoxy package meets UL94V-0 • Terminals: Solderabl | |
| BX0 | (4) | N/A | module | 2005+ | Notes: 1. For Max. or Min. conditions, use appropriate value specified u |
| BX1 | (16) | n/a | The transmitter converts electrical PECL compatible serial data (TD and | ||
| BX2 | (23) | BX | 06+ | 1300 | Motorolas MPXAZ4115A series sensor integrates onCchip, bipolar op |
| BX3 | (14) | high-frequency tube | ROHM | 04+ | •Program control unit (PCU) •DMA controller (w |
| BX4 | (13) | PULSE | 06+ | MODULE | Appendix B: Manual/Compatibility Mode Demodulator Write and Read Registe |
| BX5 | (2) | ? | CWDIP16宽 | 96 | Schmitt trigger inputs on Port G MICROWIRE PLUS serial I O Packages &nb |
| BX6 | (7) | PULSE | Test 2 Pin(Internal pull-down pin) Receiver Input 3 with Amp for 0.2Vpp | ||
| BX7 | (15) | ROHM | ZIP-10P电路集成版 | 6+ | The HYM71V653201 H-Series are Dual In-line Memory Modules suitable for eas |
| BX8 | (67) | high-frequency tube | ROHM | 04+ | Notes: 4. Not 100% tested, guaranteed by design. 5. IVDD c |
| BX9 | (1) | N/A | 05+ | The functionality of each circuit block is customized during configurati | |
| BXA | (159) | ARTESYN | SOP | A decoupling capacitor of 0.01µF must be connected between VDD (p | |
| BXB | (103) | N/A | The PHY-link interface can follow either the IEEE 1394a-2000 protocol or | ||
| BXC | (14) | The CXD3027R-1 supports variable playback speeds from 0.5 to 4. This sy | |||
| BXF | (8) | ARTESYN | SOP | Removed preliminary. Removed old CP44 pin names and replaced with updated | |
| BXM | (1) | ||||
| BXN | (2) | The clock input is differential and TTL/CMOS-compatible. The 10-bit digi | |||
| BXR | (1) | Low-power dissipation Operating: 15 mW/MHz (typical) Single power supply | |||
| BXT | (1) | • High performance ferrite core is used in this epoxy confor | |||
| BXV | (5) | VISHAY | LL34 | The ISSI IS41C82002 and IS41LV82002 are 2,097,152 x 8-bit high-performan | |
| BXX | (1) | PB0~PB5 constitute a 6-bit Schmitt trigger input port. Each bit on port ar | |||
| BXZ | (6) | Philips | 2008 | Main CLK(Hz)Under 3.58M14.3M Operating Voltage(min)2.2V3.6V | |
| BY0 | (4) | PHILIPS | ECOS1HA182AA ECOS1HA222AA ECOS1HA272AA ECOS1HA102BL ECOS1HA102BA ECOS | ||
| BY1 | (15) | Siemens AG | n/a | GND HD15 HD14 HD13 3.3V-VDD HD12 HD11 HD10 1.8V-VDD GND HD9 HD8 | |
| BY2 | (106) | dio | n/a | Output Voltage Options: Adjustable, 2.5 V, 3.3 V, 5.0 V, 8.0 V, 10 | |
| BY3 | (58) | PH | 06+ | Single Supply for Read and Write: 2.7 to 3.6V (BV), 3.0 to 3.6V (LV) Fast | |
| BY4 | (31) | ST | TOP220 | 04 | |
| BY5 | (34) | VISHAY | Output Buffer The SY88713Vs PECL output buffer is designed to dri | ||
| BY6 | (2) | DSI | n/a | The LM135, LM235, LM335 are precision tempera- ture sensors which can b | |
| BY7 | (6) | PHILIPS | The BY710 is a low-cost, full-speed Universal Serial Bus (USB) RISC-based | ||
| BY8 | (16) | Jack(Available) | The PCA9544A provides four interrupt inputs (one for each channel) and on | ||
| BYA | (2) | MSOP | 6 | To increase the flexibility of the device, it contains an Erase Suspend a | |
| BYB | (1) | 罗姆 | 06+ | † Pulse-testing techniques maintain junction temperature close to a | |
| BYC | (20) | NXP | 08+PBF | program or erase functions are being executed in memory plane A and vic | |
| BYD | (113) | ph | ph | dc95 | *Stresses above those listed under Absolute Maximum Ratings may cause per |
| BYE | (1) | GEN | TO-220 | 2000 | The coarse and fine mixers can be combined to span a wider range of fre |
| BYF | (6) | DSI | n/a | Note 5: Dynamic supply current is higher due to the gate charge being de | |
| BYG | (131) | VISHAY | DO214AC | 07 | (a) For a dual device surface mounted on 8 sq cm single sided 2oz copper |
| BYI | (2) | N/A | N/A | N/A | Byte write operation is performed by using Byte Write enable (BW) input |
| BYK | (1) | micropackage. The HCC/HCF4000B, HCC/HCF4001B, HCC/HCF 4002B and HCC/HCF4 | |||
| BYL | (1) | PH | 04+ | AV+,BV+,CV+ - are pins for connecting the tops of each half bridge to th | |
| BYM | (140) | gi | gi | dc95 | s Fully complies with Universal Serial Bus Specification Rev. 2.0 |
| BYP | (14) | Jack(Available) | 1. Life support devices or systems are devices or systems which, | ||
| BYQ | (72) | PH/ST | TO- | The TPS793xx family of low-dropout (LDO) low-power linear voltage regul | |
| BYR | (21) | PH/ST | TO- | The on-chip DPLL meets Telcordia GR-1244-CORE stratum 4 specifications (St | |
| BYS | (61) | sie | sie | dc0503 | These Precision Optical Perform- ance AlInGaP LEDs provide superior ligh |
| BYT | (322) | N/A | |||
| BYU | (3) | P2ROM stands for Production Programmed ROM. This exclusive Oki te | |||
| BYV | (471) | PH | 97+ | TO-220 | applied to the RESET pin while PWM inputs IN1,...IN6 are held high (off |
| BYW | (283) | ph | ph | dc02 | The CLB can thus be used as an asymmetrical dual-port RAM, with F being |
| BYX | (53) | DSI | n/a | Codec negative analog output. The DC level is Vcm, and the full-scale ac | |
| BYY | (4) | itt | n/a | 4. Setting possible during non-induction It is possible to set a | |
| BZ- | (51) | MICRO SO 03 | n/a | The two PWM controllers that regulate the system main 5V and 3.3V voltage | |
| BZ0 | (7) | AVX, | 法拉电容 | Conforms to JEDEC byte-wide standard Reliable CMOS with MNO | |
| BZ1 | (2) | PHI | SOP20 | 04/05+ | Notes: 1. Minimum Noise Figure and Associated Gain at Fmin computed from |
| BZ2 | (3) | LL34 | The FDC37M81x supports the ISA Plug-and- Play Standard (Version 1.0a) and | ||
| BZ3 | (1) | The device powers on in the read mode. Command sequences are used to pl | |||
| BZ4 | (1) | The SPT1175 operates from a single +5 V power supply. AVDD and DVDD must | |||
| BZ5 | (2) | LMD is the last measured discharge capacity of the battery. On initializa | |||
| BZ6 | (1) | These capabilities make the FM25L16 ideal for nonvolatile memory applic | |||
| BZ7 | (2) | TriState The TriState feature puts the LVPECL output driver into a high | |||
| BZ8 | (4) | MOT | SOT-23 | Because of the fast rise-time of the ESD transient, placement of PulseGu | |
| BZA | (64) | PHI | SOP-7.2-20P | 6+ | The timer function has three main components: an 8-bit basic timer |
| BZB | (39) | PHILIPS | n Supports high-efficiency PowerWise Technology Adaptive Voltage | ||
| BZC | (4) | intertec | intertec | dc99 | Thermal Data - Thermal Resistances Some thermal data (e.g., junction tem |
| BZD | (223) | ph | ph | dc02 | The treble network consists of R7, R8, R9, R10, C7, C8, C9, and C10. Res |
| BZE | (8) | These signal conditioners are designed to provide an easy and convenient | |||
| BZG | (483) | VISHAY | SMA | 04+ | The HT24LC08 is an 8K-bit serial read/write non-volatile memory device us |
| BZH | (2) | Note: These are stress ratings only. Stresses exceeding the range specifi | |||
| BZM | (140) | VISHAY/TFK | † Stresses beyond those listed under absolute maximum ratings may c | ||
| BZP | (12) | MIL-STD-750, method 3131. The maximum limit (not to exceed the group A, s | |||
| BZQ | (2) | N/A | DIP | 2006 | GENERAL FEATURES Programmable DAC Gain Control Sync Outputs in All Modes |
| BZT | (606) | PHILIPS | SOD-57 | 04+ | NOTE: EP circuits are designed to meet the DC specifications shown in the |
| BZU | (2) | N/A | The transmitter circuitry is disabled under the following conditions: pow | ||
| BZV | (919) | PHILIPS | SOT-89 | 2 | |
| BZW | (369) | FAGOR | It is not necessary to have a host and target system that are the same ar | ||
| BZX | (3192) | PHILIPS | 04+ | TRANSFER FUNCTION TEST A functional diagram of the transfer function tes | |
| BZY | (128) | FAGOR | Signal Processors (DSPs) TMS320C62x C 5-, 4-, 3.33-ns Instruction Cycle T | ||
| BZZ | (1) | The TDA8931 is a switching power stage for high efficiency class-D |
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