| Mfg | pack | D/C | Descrpion | ||
| U.1 | (1) | < Notice > 1. When power supply of S1T8825B is disconnected, CLK, | |||
| U.4 | (1) | ROW/COLUMN ADDRESS SELECT: In the A/A Mux interface, the R/C pin is used | |||
| U.F | (5) | HIROSE | 07+ | The receivers also include a (patent pending) fail-safe circuit that will | |
| U-0 | (3) | † Stresses beyond those listed under absolute maximum ratings may c | |||
| U00 | (14) | TOUCHSENSOR | QFP | 2006 | Signal interconnections within FLEX 8000 devices and between device pins |
| U01 | (2) | Sipex | SOT-23-3 | 05+ | Information furnished by Analog Devices is believed to be accurate and r |
| U02 | (8) | 37 | ST | 03+ | • 6/12 I/O pins with individual direction control: - High-c |
| U03 | (6) | ICX | 28/SOP | 07+/08+ | When the SVHS mode is selected, the DC restore on the Aux_Cout pin will |
| U04 | (12) | PROD | 07+/08+ | Designing for Very Fast Load Transients The transient response of the DC | |
| U05 | (29) | MOSPEC | TO-220A | 04+ | Notes : 1. Please do not use the soldering iron due to avoid high stress |
| U06 | (28) | PAN OVERSE | • Low power consumption (standby) mode • Sleep mode ( | ||
| U07 | (2) | ST | 大铁帽 | 08+ | Applying a LOW to the INIT input causes an immediate load of the programm |
| U08 | (62) | UK | N/A | Note 2: Operating Rating indicate conditions for which the device is func | |
| U09 | (1) | 7脚大铁帽 | 08+ | Temperature range TMIN to TMAX: C20C to +85C. TTL input val | |
| U0C | (1) | PT | 04+ | TSSOP-3.9-14P | L = 25-50 MHz, M = 50-300 MHz, U = 300-400 MHz Upper range coupling 0.75 |
| U0D | (1) | QFP92 | 2007+ | The HY29DL16x can be programmed and erased in-system with a single 2.7 | |
| U0X | (1) | The standard device offers access times of 70, 90, and 120 ns, allowing | |||
| U-1 | (5) | MX | PDIP24 | —— | Changed Boundary Scan Information and changed Figure 11, Boundary Scan Bi |
| U10 | (57) | 18000 | TO- | This pin is high if the PLL lock definition is valid. PLL lock definition | |
| U11 | (31) | Simplifies Circuit Design Reduces Board Space Reduc | |||
| U12 | (42) | N/A | 1206 | When setting S1 at a high level or S2 at a low level, the chip are | |
| U13 | (11) | F | CAN3 | 98+ | Hynix HYMD116M645A(L)6-K/H/L series is unbuffered 200-pin double data rate |
| U14 | (10) | 02+ | The U143M provides different solutions to measure Active and Apparent En | ||
| U15 | (28) | mot | mot | dc92 | Information at the data (D) inputs meeting the setup time requirements is |
| U16 | (32) | ST | SOP | Parameter Supply current Idle Traffic Input low voltage (digit | |
| U17 | (8) | SI | CAN | * On products compliant to MIL-PRF-38535, this parameter does not apply. | |
| U18 | (27) | wab | n/a | NOTES: 1. Inputs are capable of translating the following interface stan | |
| U19 | (6) | ROHM | SSOP | GENERAL FEATURES Programmable DAC Gain Control Sync Outputs in All Modes | |
| U1B | (7) | TOSHIBA | SOP-4 | 2002 | The Simultaneous Read/Write architecture provides simultaneous operation |
| U1C | (1) | ICSI reserves the right to make changes to its products at any time withou | |||
| U1D | (12) | Quiescent current does not increase significantly as the dropout | |||
| U1F | (7) | TOSHIBA | SOD-106 | time exhibits drift characteristics of the best low-drift amplifi- ers T | |
| U1G | (19) | n Drives up to 7 LEDs with up to 20mA each n LEDs controlled in 2 Disti | |||
| U1J | (10) | N/A | N/A | 00+ | The K1S1616B1A is fabricated by SAMSUNGs advanced CMOS technology |
| U1K | (1) | ∗1 Indications of substrate voltage (VSUB) reset gate clock voltag | |||
| U1P | (1) | Die nachfolgend angefhrten R/T-Kennlinien sind auf den Widerstandswert 25 | |||
| U1U | (1) | SHINDENGEN | 4-DIP | instruction begins with a start bit of the logical 1 or HIGH. Following | |
| U1Z | (66) | TOSHIBA | 03+ | Notes: 1. For conditions shown as Max. or Min., use appropriate value sp | |
| U-2 | (1) | TI&BB | QFN | 2007 | When active, the transmitter is configured to be operational, other |
| U20 | (109) | TFK | DIP-8 | 02+ | During the turn−on and turn−off delay times, gate current is |
| U21 | (77) | TEMIC | 2008 | Surface mount equivalents to the JEDEC registered 1N5221 thru 1N5281B ser | |
| U22 | (48) | SOP16 | Ground connection. For best performance, keep traces physically short an | ||
| U23 | (56) | tfk | tfk | dc97 | The WRITE instruction is followed by 16 bits of data to be written into |
| U24 | (64) | TFK | If an ADJ-bypass capacitor is use, the amplitude of the output ripple w | ||
| U25 | (70) | STANDARD DEFINITION MODE Hue Accuracy Color Saturation Acc | |||
| U26 | (41) | tfk | tfk | dc90 | The AD7818 and AD7817 are 10-bit, single- and 4-channel A/D converters w |
| U27 | (187) | tfk | tfk | dc96 | FEATURES Programmable Filtering: Any Characteristic up to 108 Tap |
| U28 | (60) | 04+ | Designers must not rely on the absence or characteristics of any features | ||
| U29 | (9) | MOT | CAN3 | 05+ | Flexibly organized as 32k x 32, 64k x 16 or 128k x 8bits 10 years min |
| U2B | (2) | TOSHIBA | SMB | 05+ | Reduced parts count and high efficiency add to the reliability of the HP |
| U2F | (6) | TOSHIBA | 1808 | The 16-Mbit Flash is organized as 1,048,576 words of 16 bits each. The x1 | |
| U2G | (3) | TOSHIBA | SMB | 05+ | The U2GC44A OptoGen interface has been designed for ease of use and fl |
| U2J | (3) | TOSHIBA | SMB | 05+ | The SOA curves combine the effect of these limits. For a given ap |
| U2T | (14) | UNI | 9929 | ||
| U2U | (1) | ST | ZIP-3/TUBE | This data sheet identifies products, their specifications, and their char | |
| U2Z | (4) | TOSHIBA | SMB-100V | 05+ | The basic method of communication for the device is generating a start |
| U3- | (2) | 05+ | Attention please! The information herein is given to describe certain com | ||
| U30 | (57) | (1) This data is based on using the JEDEC high-K board and topside traces | |||
| U31 | (13) | ||||
| U32 | (29) | ON | SOT-252 | 05+ | DC Bus VoltageVDC DC Bus Voltage (surge)VDC(Surge) DC Bus Voltage (short |
| U33 | (7) | ST | 00+ | 1200 | Resolution Integral Nonlinearity (fin = 10kHz) Differential Nonlinearity |
| U34 | (9) | HMC | QFP | 1996 | Note that neither product term sharing nor product term steering have a |
| U35 | (28) | sil | sil | dc91 | Eight Independent Channel 14-Bit DACs with Output Amplifiers Low |
| U36 | (38) | tfk | tfk | dc97 | The change in output voltage due to a specified change in load current. |
| U37 | (69) | TEMIC | SSOP40 | 00+ | The information contained in this document does not convey any license u |
| U38 | (30) | TFK | PLCC | A read cycle begins whenever WE (Write Enable bar) is inactive (HIGH) and | |
| U39 | (13) | TEMIC | 2008 | STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions | |
| U3A | (1) | EMC | Input /output clock. I/O CLOCK receives the serial input and performs the | ||
| U3F | (5) | TOSHIBA | SMD | 04+ | The scaled-down output voltage is internally monitored and a power good |
| U3G | (2) | N/A | N/A | N/A | The circuit of the TSOP11..KA1 is designed in that way that unexpected |
| U3P | (1) | ON | SOP8 | 00+ | This MOSFET is an enhancement-mode silicon-gate power field effect tran |
| U3X | (1) | AGERE | 07+ | Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS | |
| U40 | (219) | TEMIC | SOP28 | Figure 9(a) presents the 3-wire serial port protocol. As shown, the 3-wire | |
| U41 | (32) | SILICONI | CAN6 | The Am29DL640H is a 64 megabit, 3.0 volt-only flash memory device, orga | |
| U42 | (125) | N/A | N/A | N/A | Reader Response: To improve the quality of our publications, we welcome y |
| U43 | (27) | tfk | tfk | dc93 | Notes: (i) Io 1(min) current of 0.1A can be divided between both outputs |
| U44 | (46) | N/A | TO-71 | 2003 | EA VPP External Access enable EA must be strapped to VSS in order to enab |
| U45 | (13) | HAR | CAN | PARAMETER Reference Voltage VREF Voltage Fb Voltage Line Regulation UV | |
| U46 | (12) | TFK | DIP-40 | 95+ | 1.ICC is dependent on output loading when the device output is selected. |
| U47 | (31) | TFK | 04+ | NOTE:2677 tbl 04 1. Stresses greater than those listed under ABSOLUTE MA | |
| U48 | (8) | UNICHIP | QFP | 1992 | tPHZBus disable time0.56 ns tPLZSEL to A, B0.57 |
| U49 | (7) | TFK | DIP | DIP | Peripheral Features D 34 I/O Pins D Additional 32-Bit Accumulator D Thr |
| U4B | (3) | Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds260C (1) Str | |||
| U4D | (1) | taitien | taitien | dc96 | † Stresses beyond those listed under absolute maximum ratings may c |
| U4K | (1) | TO220-3 | As an example, suppose a HUF76139 is chosen as the upper MOSFET. The ga | ||
| U4R | (1) | N/A | QFP-44 | 2. Handling In order to avoid damage to beam lead devices, particular c | |
| U4S | (1) | Timer counter 4 : 8-bit 1 (prescaler, serial clock generator, time | |||
| U-5 | (5) | DOMOSYS | QFP | 03+ | between X2 and ground. Stuffing of these capacitors on the PCB is optio |
| U5- | (1) | MITSUMI | HIGH SPEED: tPD = 4 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = | ||
| U50 | (18) | atmel | atmel | dc0605 | 1) IC options for the half-bridge products include IR2101, IR2102, IR2103 |
| U51 | (7) | Vth can be expressed as voltage between gate and source when low o | |||
| U52 | (4) | zmd | zmd | dc91 | INTRODUCTION National Semiconductor (NSC) is committed to provide ap- p |
| U53 | (8) | 109 | TFK | 95+ | Interrupt controller • External interrupt input : Normal in |
| U54 | (1) | The TOSHIBA U5411D consists of an aluminum gallium arsenide infra | |||
| U55 | (7) | Bidirectional I/O lines. Software instructions determine the CMOS output | |||
| U56 | (2) | UINTRODE | 07+ | Using the latest high voltage technology based on a patented strip layo | |
| U57 | (3) | 98 | PRECAUTIONS FOR TESTING 1. Before appling any control supply voltage (VD | ||
| U58 | (10) | UTC | TO263 | 08+ | Positive edge triggered input clock signal that is set to 16 times the dat |
| U59 | (1) | ST | ZIP | Typical tSK(0) (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, M | |
| U5A | (1) | - Single supply with operation down to 2.5V - Completely implements DDC1/ | |||
| U5B | (3) | F | TO8 | A general-purpose data register file is contained in each processing ele | |
| U5C | (2) | MSC | 06+ | Output Driver Supply Voltage Output Driver Supply Voltage Output Drive | |
| U5D | (1) | TOSHIBA | SOT-263 | 05+ | Sensitivity and resolution are also a function of the size, shape, and c |
| U5F | (4) | amd | amd | dc72 | ispVHDL™ Systems VHDL/Verilog-HDL/Schematic Design Options Funct |
| U5G | (1) | TOSHIBA | TO- | The SPI compatible serial interface also features the ability, using the | |
| U5R | (1) | 4.3 Screening (JANS, JANTX, and JANTXV levels only). Screening shal | |||
| U5S | (1) | UMC | QFP208 | Hynix HYMD232646B(L)8-M/K/H/L series incorporates SPD(serial presence dete | |
| U5T | (1) | amd | amd | dc73 | With the Hold input held High - Figure 4. As frequencies are inpu |
| U5Z | (6) | TOSHIBA | 5W | Information furnished by Linear Technology Corporation is believed to be | |
| U60 | (104) | tfk | tfk | dc92 | The Discharge Count Register is used to update the Last Measured Discharg |
| U61 | (15) | DIP | The Media Access Control function, provided by the Ethernet Network Con | ||
| U62 | (133) | SOP28 | 04+ | 3. The SI-8300L series may not start up if the input voltage rises too ra | |
| U63 | (86) | PHI | 01+ | SOP-3.9-14P | These benchmarks provide single-channel extrapolations of measured dual- |
| U64 | (53) | TC | 04+ | An internal loop filter moderates the response of the VCO to the | |
| U65 | (6) | UTC | TO92S | 08+ | The information contained herein is presented only as a guide for t |
| U66 | (16) | 9905 | The EL5172 and EL5372 are single and triple high bandwidth amplifiers des | ||
| U67 | (18) | tfk | tfk | dc92 | . . . employing the Schottky Barrier principle in a large area me |
| U68 | (46) | TFK | SOP | 03+/04 | The FM local oscillator consists of a transistor in grounded collector c |
| U69 | (7) | COILCRAFT | ESD damage can range from subtle performance degradation to complete de | ||
| U6A | (16) | N/A | N/A | N/A | DESCRIPTION The 74VHC08 is an advanced high-speed CMOS QUAD 2-INPUT AN |
| U6H | (1) | The 320VC33 contains a JTAG port for CPU emulation within a chain of any | |||
| U6S | (5) | TFK | DIP | 00+ | This device also features a sector erase architecture. This allows for |
| U70 | (23) | N/A | N/A | N/A | Absolute Maximum Ratings indicate limits beyond which damage to the devic |
| U71 | (12) | Member of the Texas Instruments Widebus Family TI-OPC Ci | |||
| U72 | (3) | TI | 07+ | Efficient 16-bit 56800 family controller engine with dual Harvard archite | |
| U73 | (3) | SMD | 97 | Common-Mode Leakage DIGITAL INPUTS Input Logic High (SDA a | |
| U74 | (7) | SOP8 | Configuration Programs for Field Programmable Gate Arrays (FPGAs) 3.3V Ou | ||
| U75 | (3) | ST | 大铁帽 | 08+ | The U757, designed and fabricated with silicon gate CMOS technology, off |
| U76 | (7) | N/A | ST | 04+ | Stand Alone Switch On A Chip 8 Ethernet 10/100/1000 ports MII/GMII inter |
| U77 | (2) | N/A | ST | 04+ | SUMMARY DESCRIPTION The M28R400C is a 4 Mbit (256Kbit x 16) non-vol- at |
| U78 | (5) | ROHM | SSOP | Similar To Industry Standard LT1084 Approved To DESC Standardized Milit | |
| U7A | (1) | Two individual input channels o MIC+/MIC-: differential microphone inputs | |||
| U7B | (2) | International Rectifier does not recommend the use of this product in aero | |||
| U7N | (1) | Low-power dissipation Operating: 9.9 mW/MHz (typical) Single power suppl | |||
| U7P | (1) | 05+ | Information furnished by Linear Technology Corporation is believed to be | ||
| U80 | (15) | INTEL | DIP/64 | 06+ | The EP7311 includes two 16550-type UARTs for RS-232 serial communication |
| U81 | (22) | TFK | 2008 | Point of load power supplies Negative voltage buck-boost power supplies | |
| U82 | (16) | MOTOROLA | TO- | 1998 | |
| U83 | (29) | TFK | SOP- 8 | The SMSC 4-port hub controller supports the Session Request Protocol (SRP) | |
| U84 | (24) | Unknown | The U840 is a temperature sensor, Delta-Sigma analog-to-digital converter | ||
| U85 | (4) | N/A | N/A | N/A | For driving the N-Channel gates, it is important to keep in mind t |
| U86 | (17) | ON | TO-220 | 04+ | The SN74GTLPH1645 is a high-drive, 16-bit bus transceiver that provides L |
| U87 | (10) | Rohm | 06+ | 500 | Following a period of activity in the powered-up state the power-down s |
| U88 | (8) | 裸片 | 03+ | Digital Servo (DSSP) Block • Microcomputer software-based flexible | |
| U89 | (20) | tfk | tfk | dc98 | pulses. This will result in some low frequency ripple, although the LED c |
| U8K | (1) | The XC62K series are highly precise, low power consumption, negative vol | |||
| U-9 | (2) | LATTICE | 2007 | This document is a general product description and is subject to change wi | |
| U90 | (3) | LATTICE | 01+ | NOTES: (1) Junction temperature = ambient for 25C tested specifications. | |
| U91 | (6) | PAN | SOT-523 | 05+ | The IALUs have hardware support for circular buffers, bit reverse, and z |
| U92 | (3) | TEMIC | ATMEL | 04+ | PARAMETER Reference Voltage Fb Voltage Fb Voltage Line Regulation UVLO |
| U93 | (3) | 85+ | Luma Output / Red Output A 75 Ω termination resistor with short tra | ||
| U95 | (2) | MX | . | The devices are customized by loading configuration data into the intern | |
| U96 | (4) | MX | 06+ | 1. Optical switch 2. Light detecting portion of remote control ․AV | |
| U97 | (1) | ||||
| U98 | (5) | SSOP24 | 1. H = HIGH voltage level h = HIGH voltage level one set-up time | ||
| U99 | (2) | PHILIPS | PLCC | N/A | The TOSHIBA products listed in this document are intended for usage in ge |
| U9A | (2) | F | DIP-14P | 7212+ | Asynchronous active-low LVTTL power-down signal shuts down oscillator and |
| U9G | (2) | Actel | SOP | 97+ | Operation above maximum ratings may cause permanent damage to the device. |
| U9N | (1) | • VTT Bus Termination Output (Output Tracks the System VREF) | |||
| U9T | (2) | FSC | 85 | associated with such unintended or unauthorized use, even if such claim a | |
| UA- | (4) | WELTREND | DIP40 | 83+ | This bus includes a selective node awake capability, which allows normal |
| UA/ | (7) | 5-CH balanced transformerless (BTL) driver 1-CH (forward-reverse) contr | |||
| UA0 | (21) | 06+ | 36800 | 16-bit right justified 18-bit right justified 20-bit right justified 22 | |
| UA1 | (203) | NS | 04+ | FEATURES Pin-Compatible 12- and 14-Bit DACs Serial Input, Voltage Outpu | |
| UA2 | (198) | F | 86 | DIP陶瓷 | An external Protection Circuit Device assists in preventing damage to the |
| UA3 | (211) | CAN | CAN | (and other parameters) will be met at the specified input power level an | |
| UA4 | (77) | F | 04+ | The COP8TM feature family of microcontrollers use an 8-bit single-chip co | |
| UA5 | (83) | Maximum Ratings are those values beyond which damage to the device may oc | |||
| UA6 | (28) | 13 | AGILENT | 06+ | The ILD610 series is a dual channel optocoupler series for high density |
| UA7 | (1306) | 86 | FAI | 4 | HY57V28820HC(L)T is offering fully synchronous operation referenced to a |
| UA8 | (20) | ICS | SSOP56W | 2007+ | Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type. |
| UA9 | (196) | UA | CAN | Ideally, the relative size of measurement error should be fairly consta | |
| UAA | (320) | 7 | SMD24 | 96+ | |
| UAB | (39) | INFINEON | QFP144 | 3.3V power supply LVTTL compatible with multiplexed address Dual bank op | |
| UAC | (18) | MICRONAS | 2001 | In most applications, the chip address inputs A0, A1, and A2 are hard-w | |
| UAD | (1) | TEMIC | 200 | n/a | Operating Temperature: -55C to +150C Storage Temperature: -55C to +150C |
| UAF | (48) | BB | 2 | • NPT3 IGBT - low saturation voltage - positive temp | |
| UAI | (1) | The patented AT40KAL series architecture employs a symmetrical grid of sm | |||
| UAL | (2) | Synchronous Controller plus 3-LDO controllers Current Limit using MOSFET | |||
| UAM | (2) | ICS | SSOP-48 | 0032+ | Output, Pin 14, is suitable for controlling a power MOS- FET. During the |
| UAN | (1) | ICS | 02+ | The ZREF25 uses a bandgap circuit design to achieve a precision micropow | |
| UAO | (1) | Notes: 1. The dominant wavelength, ëd, is derived from the CIE chr | |||
| UAP | (5) | NEC | 150 | I2C BUS INTERFACE Data transmission from main µP to the LNBEH21 an | |
| UAR | (3) | The Am29LV065D is a 64 Mbit, 3.0 Volt (3.0 V to 3.6 V) single power sup | |||
| UAS | (2) | NS | SMD | 1990 | The SN65LV1023A serializer and SN65LV1224A deserializer comprise a 10-bit |
| UAT | (5) | The UAT04X152K6H46UAA center tap Schottky rectifier module has been optim | |||
| UAU | (1) | • Low-power consumption (Standby) Mode •Sleep mode (CP | |||
| UAW | (14) | RING INDICATION. It is asserted LOW by the CH1817 during the 2 second ON | |||
| UB- | (2) | The ACCU-TEST Self-Diagnostics option conducts automatic and manual tests | |||
| UB0 | (8) | ST | 8Ld-sop | 9935 | The AHC240 devices are organized as two 4-bit buffers/line drivers with |
| UB1 | (50) | Word width may be increased simply by connecting the corre- sponding inp | |||
| UB2 | (49) | PANASONIC | RELAY | 06+ | The Hynix UB2-3NE Series are Dual In-line Memory Modules suitable f |
| UB3 | (7) | BGA | FEATURES • Compliant with ATM, SONET OC-3, SDH STM-1 • Meet | ||
| UB4 | (5) | fcs | to-220 | 07+ | Assuming that an output load resistor of 75 Ω is connected between |
| UB5 | (3) | N/A | 20 | Current Word Register Each channel has a 16-bit Current Word Count regist | |
| UB6 | (5) | ENE | QFP | 01+ | |
| UB8 | (20) | SOP | 1984 | This document is a general product description and is subject to change wi | |
| UB9 | (2) | Figure 2 illustrates a typical application circuit (output source | |||
| UBA | (147) | System Characteristics The following spec table entries are guaranteed by | |||
| UBB | (1) | TX Mix In: The input to the TX Mix Amplifier. Used with external component | |||
| UBI | (3) | UBISYS | QFP | 05+ | MXIC Flash technology reliably stores memory con- tents even after 10,0 |
| UBJ | (1) | RON t 4 W Typical Less Than 0.25 ns−Max Delay Through Switch Near | |||
| UBM | (8) | UNIZON | 23-10V | 05+ | |
| UBP | (1) | Device erasure occurs by executing the erase command sequence. This initi | |||
| UBR | (3) | 7. Multifunctional PWM The family devices support both 8- and 16- | |||
| UBS | (4) | uni | n/a | The XC4000 families achieve high speed through ad- vanced semiconductor | |
| UBT | (8) | NHC | RADIAL | 5 | The HYM72V64656B(L)T8 H-series are high speed 3.3-Volt synchronous dynamic |
| UBW | (1) | The center-pin configuration reduces lead inductance when compared to the | |||
| UBX | (4) | N/A | N/A | 1614 | The amplifiers can operate on any supply voltage from 4V (2V) to 33V (1 |
| UC- | (66) | Uniden | O7+ | A 1 kΩ span resistor has been provided on chip for use as a feedba | |
| UC0 | (11) | UC | DIP | 93+ | Description: DIP and mini-DIP IPMs are intelligent power modules that |
| UC1 | (778) | TI | 07+ | The SO-8 has been modified through a customized leadframe for enhanced | |
| UC2 | (1496) | Uniden | O7+ | Hold only : When the channel is turned on externally (SPI or parallel inpu | |
| UC3 | (1650) | TI | SOP | • 1.5 Mbps data rate • On-chip 3.3V regulator • Endpoi | |
| UC4 | (43) | UC | DIP | † Stresses beyond those listed under absolute maximum ratings may c | |
| UC5 | (186) | SOSHIN | 5650 | 04+ | † For execution of these commands on cycle n: C CKE (n) mus |
| UC6 | (14) | N/A | UNITRODE | 04+ | This device contains protection circuitry to guard against damag |
| UC7 | (56) | SI | CAN | The sensor consists of a precision linear Hall IC, which is optimized to | |
| UC8 | (220) | 9213 | The 240xA generation offers an array of memory sizes and different periph | ||
| UC9 | (12) | CTIS | SOP8 | 07+ | NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATIN |
| UCA | (6) | ALLEGRO | DIP-22 | Note 3: Without a heat sink, the thermal resistance of the TO-3 package i | |
| UCB | (26) | PHI | 98+ | 3000 | The Hynix HYM71V8M635HC(L)T6 Series are Dual In-line Memory Modules |
| UCC | (3039) | 07+ | • All parameters specified for +5V single supply or 2.5V du | ||
| UCD | (19) | NICHICON | SMD | 07+ | Initial Release Updated Minimum Voltage Condition on page 5 Updated Anal |
| UCE | (2) | The crystal oscillators should be fundamental mode quartz crystals | |||
| UCF | (1) | SOP16W | 2007+ | tr, tfOutput rise and fall times (20% C 80%)Load: 120 Ω/14 pF | |
| UCG | (1) | NEC | 07+ | The UCG2107TH and UCG2107TH are general-purpose dual channel PCM CODECs wi | |
| UCH | (1) | This device contains protection circuitry to guard against damag | |||
| UCI | (3) | SEMTECH | SOD523 | 08+ | OUTPUT VOLTAGE LIMITERS Default Limiter Voltage Minimum Limiter Separa |
| UCK | (2) | PLCC | TI | 600 | The TLC77xxI is characterized for operation over a temperature range of C |
| UCL | (21) | guarantees lower guaranteed maximum supply current than competing produc | |||
| UCN | (285) | ALLEGRO | 06+ | 39000 | |
| UCO | (1) | 07+ | 15) Sweep the power supply to 5.5V. Verify that the LED module rem | ||
| UCP | (9) | 89 | Peak output current25C2.1A † Pulse-testing techniques are used to | ||
| UCQ | (22) | UCQ | PLCC44 | device while it is in the system (e.g., by a virus), the device has a S | |
| UCR | (2) | UTC | 07+ | is a registered trademark of VIA Technologies, Incorporated. Wind | |
| UCS | (19) | NEC | N/A | 91 | Over-Current & Over-Temperature Protection: To protect against short |
| UCT | (3) | TOS | DIP | APPLICATIONS lTelephone ring detector lDigital logic ground isolation | |
| UCU | (2) | ALLEGRO | SOP | 04+ | The ANADIGICS AWL9224 power amplifier is a high performance InGaP HBT IC |
| UCV | (37) | ALPS | 06+(PB) | DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. | |
| UCX | (4) | MOT | CAN | Burst mode operation Auto & self refresh capability (8 | |
| UCY | (15) | CEMI | DIP-28 | 88+ | Two package styles are available. HOA0901- 011 is primarily intended for |
| UCZ | (1) | UC | 01+ | The MAC unit comprises the main arithmetic processing unit of the DSP5630 | |
| UD- | (2) | LMI | TSSOP-20 | 01+ | NMOS open drain output structure, which by receiving the HKS and HF |
| UD0 | (19) | 210 | MHS | DATEL makes no representation that the use of its products in the circuit | |
| UD1 | (13) | N/A | MHS | 04+ | Port 3 is an 8 bit bi-directional I/O port with internal pullups. Port 3 |
| UD2 | (9) | MHS | 06+ | Notes: (1) RMA flux is recommended. Duration can be extended to 10 sec. m | |
| UD3 | (4) | 99+ | QFN | CEL certifies, to its knowledge, that semiconductor and laser products de | |
| UD4 | (6) | 06+ | 300 | Write access are initiated when the following conditions are satisfied at | |
| UD5 | (1) | The error-amplifier input common-mode voltage ranges from 0.9 V to 1.5 V. | |||
| UD6 | (14) | UNITRODE | DIP | 00+ | Maximum ratings are those values beyond which device damage can occur. M |
| UD7 | (2) | NEC | DIP-40 | 9013 | between X2 and ground. Stuffing of these capacitors on the PCB is optio |
| UD8 | (4) | OMC | 04+ | 2. Handling In order to avoid damage to beam lead devices, particular c | |
| UD9 | (1) | 隔离器 | 04+ | These are the data inputs for programmable counting. Data on thes | |
| UDA | (222) | PHI | SSOP | 00+ | The DAC8580 is a 16-bit, high-speed, low-noise, voltage-output DAC desi |
| UDB | (2) | NEC | DIP | 07+ | † All characteristics are measured under open-loop conditions with |
| UDC | (2) | UNIDEN | QFP1414-100 | 97+ | The CS61880 is a full-featured Octal E1 short-haul LIU that supports 2. |
| UDD | (1) | 90 | * Specifications will vary with foreigh standards certificati | ||
| UDE | (2) | N/A | N/A | N/A | For the IS24C08-2 and IS24C08-3 out of the next three bits, B1 and B0 a |
| UDF | (3) | PCS | 2008 | Ceramic Capacitors Above 150 kHz the performance of aluminum electrolyti | |
| UDG | (1) | SYNCHRONOUS READS: Synchronous reads (not available on the AT49SV12804) a | |||
| UDI | (3) | PHILIPS | SOP28 | 00+ | The FDC05 and FDC05-W series offer 5 watts of output power from a 2 x 1 x |
| UDK | (15) | ALLEGRA | PLCC28 | 2002 | (OSCIN) Serial Interface With Microprocessor (SPI) Programmable Gain Pr |
| UDL | (3) | ALL | SOP | 07+ | 3. Recommended LED forward current (IF) It is recommended that the LED |
| UDM | (18) | ROHM | 00+ | ACCURACY Linearity Error Linearity Match Differential Linearity Erro | |
| UDN | (348) | ALLEGRO | SOP | 96+ | This is a dual-function pin. In the CY Standard mode, the EF function is |
| UDO | (1) | CPCLARE | 97+ | 103 | Buffer Operating Frequency: 8 MHz to 200 MHz Low Jitter (Cycle-Cycle): 1 |
| UDP | (11) | NEC | 04+ | NOTES: VZ is programmable from -2V to +7V. IOL & IOH programmable fr | |
| UDQ | (41) | ALLEGRO | SOP | 07+ | Note 7: The current source is connected internally between VIN and VIOUT. |
| UDS | (17) | ALLEGRO | CLCC | 04+ | Category voltage UC: The maximum direct voltage, or the maximum r.m.s. v |
| UDT | (2) | The following discussion refers to the schematic in figure 2 belo | |||
| UDX | (3) | Parameter REFERENCE INPUTS REFIN(+) to REFIN(C) Voltage1, 9 &nbs | |||
| UDZ | (413) | ROHM | 03+ | Improved scan efficiency is accomplished through the adoption of a one bo | |
| UE0 | (7) | ST | 大铁帽 | 08+ | +TxIn input impedance -TxIn input impedance -RxIn input impedance Txout |
| UE1 | (4) | SOP | Address Latch Enable: Output pulse for latching the low byte of the addre | ||
| UE3 | (1) | N/A | ST | 04+ | q GUARANTEED SPECIFICATIONS WITH 12V AND 15V SUPPLIES q 1/2LSB M |
| UE7 | (1) | AMPHENOL | 1374 | When heavy loads require the OUT pin to sink large currents being | |
| UE9 | (1) | SOP | One clock should be held HIGH while counting with the other, otherwise | ||
| UEA | (2) | • Provides seamless integration for WAN connections • | |||
| UEH | (20) | The UEHP800NB1XT is a dual monolithic CMOS micropower precision high sle | |||
| UEI | (1) | UEI | AV-,BV-,CV- - are pins for connecting the bottoms of each half bridge to | ||
| UEL | (4) | When writing data to the memory, the device in- serts an acknowledge bi | |||
| UEM | (27) | N/A | 06+ | 500 | s Standard asynchronous error and framing bits (Start, Stop, and Parity O |
| UEN | (1) | This device contains circuitry protecting against damage that high-static | |||
| UEP | (7) | A buffered output-enable (OE) input can be used to place the eight output | |||
| UER | (2) | DESCRIPTION Dual center tap rectifier suited for Switch Mode Power Supp | |||
| UES | (69) | MSC | 03 | Screen tested 100% on each device at -55 C, +25 C and +125 C temp., subgr | |
| UET | (1) | The EUA5212 is a stereo audio power amplifier. When driving 1 W into 8- | |||
| UEW | (2) | Unless otherwise specified, the typical specification value applies over | |||
| UEY | (1) | The DEM-OPA68xU demonstration board is an unpopulated printed circuit b | |||
| U-F | (2) | AS | 3.9mm | 99 | *Stresses above those listed under Absolute Maximum Ratings may cause per |
| UF- | (2) | The internal circuit is composed of 2 stages including buffer output, w | |||
| UF0 | (4) | ST | 07+ | Motorola reserves the right to make changes without further notice to any | |
| UF1 | (98) | UF | 07/08+ | The circuit is designed to meet the DC specifications shown in the above | |
| UF2 | (35) | JIT | SMB | TypeDescription P3.3 volt input supply voltage. P5.0 volt referenc | |
| UF3 | (35) | GULF | DO-201AD | 2007 | The TC55V4000ST is a 4,194,304-bit static random access memory (SR |
| UF4 | (70) | MIC | DO-41 | 2008+ | To prevent the input signals oscillation, an RC coupling at each input is |
| UF5 | (38) | UF | 07/08+ | Output current rating may be restricted to a value determined by system | |
| UF6 | (12) | HY | BGA | 99+ | The HYM7V73AC1601B N-Series are Dual In-line Memory Modules suitable for |
| UF7 | (9) | KA/INF | TO | 3) This input current only exists when the voltage at any of the input le | |
| UF8 | (7) | UTC | TO-220F | 08+ | The ispGAL22LV10 has a product term for Asynchronous Reset (AR) and a p |
| UF9 | (1) | JINWEI | N/A | The PGA and black level auto-calibration are con- trolled through a sim | |
| UFA | (2) | Mornsun | 07+ | The MCP6275s VCM for op amp B (pins VOUTA/VINB+ and VINBC) is VSS + 100 m | |
| UFB | (6) | IR | 07+ | n Software selectable I/O options TRI-STATE ® Output | |
| UFC | (5) | PANASONI | BGA | 98+ | Each device requires only a single 3.0 volt power supply for both read a |
| UFD | (1) | The standard MBM29DL16XTE/BE offer access times 70 ns, 90 ns and 120 ns, | |||
| UFF | (5) | Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Co | |||
| UFI | (2) | GS | 03+ | DIP | • Plastic package has Underwriters Laboratory Flammability |
| UFL | (3) | HRS | 03+ | Note: Stresses greater than those listed under MAXIMUM RATINGS may cause | |
| UFM | (31) | RECRON | DO214AC | 07+ | The D 2Pak is a surface mount power package capable of accommodating di |
| UFN | (5) | N/A | N/A | N/A | Note 1: DC accuracy is tested at AVDD = +5.0V and DVDD = +3.0V. Performanc |
| UFP | (3) | 1.9GHz gain-bandwidth product 1.05nV/Hz input voltage noise 0.8pA/Hz | |||
| UFR | (3) | MSC | 04 | Notes: 5. Test conditions assume signal transition time of 3 ns or | |
| UFS | (11) | BGA-8 | 2007 | The UFS/7 is a low cost 8 pin CMOS control IC for the intelligent chargin | |
| UFT | (17) | The SRAM will not latch up due to any of the above radiation exposure co | |||
| UFX | (1) | Stresses beyond those listed under Absolute Maximum Ratings may cause p | |||
| UFZ | (19) | ZETEX | 05+ | Maximum Ratings are those values beyond which damage to the device may oc | |
| UG- | (38) | SAMSUNG | 06+ | Section 3.5.1, External Bus Selection Register (EBSR): − appended | |
| UG0 | (16) | ATMEL | SOP | 0423+ | PIN DESCRIPTION Non-inverting input to Ramp Comparator Inverting input t |
| UG1 | (92) | GS | TO-220 | 02+ | Figure 1-1 shows the basic UG10JT circuit using the device, with a conve |
| UG2 | (36) | N/A | TEMIC | 04+ | Figure above shows the topology of a protected analog subscriber line a |
| UG3 | (11) | NEC | QFP | After each 24-hour period has elapsed, the battery is connected to an inte | |
| UG4 | (12) | Vishay | DO-201AD | 08+ | |
| UG5 | (3) | Hitachi | 06+ | 2800 | Hynix HYMD132G725A(L)4M-K/H/L series is designed for high speed of up to |
| UG6 | (9) | NEC | 280 | 01+ | Notes : 1. In case of 40MHz Frequency, CL1 can be supported. 2. Samsung |
| UG7 | (2) | N/A | BGA | 00+ | The serial number is divided into three parts (see Figure 1). The 8Cbit |
| UG8 | (24) | INTEL | 06+ | QFP/256 | The MC68HC000 is an implementation of the M68000 16/-32 bit microprocesso |
| UG9 | (2) | The ceramic resonator of the stereo decoder PLL circuit is used as a sto | |||
| UGA | (3) | BT | PLCC68 | regulator and the load is gained up by the factor of (1+R2/ R1), or the e | |
| UGB | (28) | Vishay | TO-263 | 2007 | Notes: 4. VIL(min.) = C2.0V for pulse durations less than 20 ns. |
| UGD | (1) | Low Dropout with >99.5% Duty Cycle Lossless High-Side Current Limit W | |||
| UGE | (7) | CREE | (LX)high-frequency | The SCAN926260 integrates six 10-bit deserializer devices into a single | |
| UGF | (116) | CREE | (LX)high-frequency | Dead time can be controlled through proper selection of CT and can range | |
| UGG | (1) | ALPS | NEW | 05+ | It is recommended that CE be decoded and used as the primary device-selec |
| UGH | (1) | NOTES 1VIL is the Logic Control Input. 2Current tested at V IN = 0 V. Th | |||
| UGL | (2) | ALLEGRO | SOT-89 | 05+ | |
| UGM | (1) | Texas Instruments (TI) has recently identified a problem in the product m | |||
| UGN | (44) | FILIPINE | DIP | 98 | sFEATURES q PWM switching control q Operating Voltage(3.6 |
| UGO | (1) | T | PLCC | *Stresses above those listed under Absolute Maximum Ratings may cause per | |
| UGS | (14) | all | all | dc90 | CLK Pin The CLK pin is used to provide a clock used for loading |
| UGT | (4) | ALPS | LCC钢面 | 04+ | For the most efficient use of these two control lines, E should be deco |
| UGW | (1) | Features • Progressive scan allows individual readout of the image | |||
| UGX | (3) | 08+ | In addition, the P8xC557E8 has two software selectable reduced power mo | ||
| UH0 | (1) | ADVICS | 0247 | The MC34064 is an undervoltage sensing circuit specifically design | |
| UH1 | (4) | N/A | N/A | 06+ | Note 3: The linearity error is calculated by the difference between the |
| UH2 | (8) | VISHAY | • 16-Bit SPI for Control and Fault Reporting, 3.3 V/5.0 V Compatible | ||
| UH3 | (3) | ST | PowerSO-36 | 06+ | The CY22050 has a single PLL driving 6 programmable output clocks. The ou |
| UH4 | (2) | ST | Notes: 1. Test conditions assume signal transition times of 5 ns or less | ||
| UH5 | (2) | FOXCONN | 04+ | SMD | VREG. This supply voltage is used to operate the sink- side DMOS output |
| UH7 | (4) | N/A | 38503 | N/A | The 56F801 incorporates an 8 input, 12-bit Analog-to-Digital Converter (A |
| UH8 | (4) | ON | TO-220 | 04+ | The passive 2nd order RC filter protects the gyrator filter from strong |
| UHB | (5) | ASI | 2008 | The ZL10037 is a fully integrated direct conversion tuner for digital sat | |
| UHC | (5) | 2000 | Oxford | 6+ | The NJU26108 audio interface provides industry standard serial data format |
| UHD | (28) | N/A | N/A | N/A | The UHD-150-24-300 is designed to replace two single SO-8 MOSFETs and Sch |
| UHE | (19) | NICHICON | DIP | 2007+PB | IF input frequency at iFInP and iFInM: 130 MHz. IF differential input vol |
| UHF | (2) | Vishay | External Access enable: EA must be externally held low to enable the de | ||
| UHG | (2) | Serial data for this mode is entered at the shift-right data input When | |||
| UHI | (2) | Widebus+ Family DOC Circuitry Dynamically Changes Output | |||
| UHJ | (2) | The applied external reference input voltage VREF determines the full-s | |||
| UHM | (1) | NICHICON | DIP | 2007+PB | Hynix HYMD232G726B(L)8-M/K/H/L series is designed for high speed of up to |
| UHP | (12) | ALLEGRO | DIP | 07+ | This document is a general product description and is subject to change wi |
| UHV | (2) | TDK | 带金属端子 | 8+ | Current Transfer Ratio (CTR)1000 4000 Collector-emitter Saturation Volt |
| UHY | (1) | CAUTION: These devices are sensitive to electrostatic discharge; f | |||
| UI- | (1) | The UI-260-EX is a low power 3A adjustable and fixed voltage regulator th | |||
| UI0 | (8) | 2001 | Note 1: Absolute Maximum Ratings indicate limits beyond which damage to t | ||
| UI2 | (1) | Although the Motorola accelerometers contain internal 2kV ESD pro | |||
| UI9 | (2) | Function, Pinout, and Drive Compatible With FCT and F Logic Reduced VOH | |||
| UIA | (1) | ||||
| UIB | (1) | Minimum Dielectric Strength, Input-Output Minimum Insulation Resistance, | |||
| UIC | (6) | ALCATEL | PLCC-28 | 06+ | Stapleford™ is a highly integrated, single- chip Ethernet switch wi |
| UID | (2) | 98 | QFP | The analog input range is equal to a 2V spread. The voltage on VT-VB wi | |
| UIJ | (1) | The Line Build-Out function controls the amplitude in DS3 and STS-1 mode. | |||
| UIK | (1) | 南京菲尼斯克 | 00+ | *Stresses above those listed under Absolute Maximum Ratings may cause per | |
| UIM | (1) | Note 10: Skew is defined as the absolute value of the difference between | |||
| UIN | (4) | PANASONIC | SMD | The SYSIRQ pin provides a way for systems to request service from host so | |
| UIO | (1) | ARESYS | QFP | 94 | A memory cycle is initiated by bring RAS LOW and it is terminated by re |
| UIP | (5) | NEC | 99 | Collector-base breakdown voltage Collector-emitter breakdown voltage E | |
| UIS | (1) | Write Protect, active Low/Accelerate (VHH). Wr it e Pr ot ect Funct ion: | |||
| UIT | (2) | 1000 | On-chip 4-quadrant resistors allow flexible output ranges 10 MHz multipl | ||
| UIW | (1) | UIW | 1900 | DIP | The C67x CPU executes all C62x instructions. In addition to C62x fixed-po |
| UIZ | (2) | ||||
| UJ- | (1) | When the CY7C42x1V is in a Width-Expansion Configuration, the Read Enabl | |||
| UJ0 | (4) | ICS | 107 | SSOP | True remote load sensing it is not possible to provide, because the AMS2 |
| UJ1 | (6) | ICS | 08+ | This is Preliminary document release. All specifications are subject to ch | |
| UJ2 | (51) | ICS | 02+ | SOP | !Features 1) Built-in bias resistors enable the configuration of an &nbs |
| UJ3 | (11) | ICS | SSOP | A diode emulation feature is integrated in the ISL6208 to enhance convert | |
| UJ4 | (5) | This document contains detailed information for the MPC852T about power | |||
| UJ5 | (1) | Maximum rated frequency: 133 MHz Low cycle-to-cycle jitter Input to o | |||
| UJ7 | (11) | ICS | SSOP48W | 2007+ | Symmetrical TX and RX channels for auto MDI/MDIX capability Approved |
| UJ8 | (3) | 2 | SOP | Broadcom®, the pulse logo, and Connecting everything® are trademar | |
| UJ9 | (2) | IRIS-A6131 is a hybrid IC consisting of a power MOSFET and a controller I | |||
| UJA | (3) | PHI | N/A | These are the first monolithic JFET input operational ampli- fiers to i | |
| UJC | (1) | ICS | SOP | 1993 | Case: JEDEC TO-220AB, ITO-220AB & TO-263AB molded plastic body Term |
| UJD | (1) | The KS8842M offers an extensive feature set that includes tag/port-based | |||
| UJG | (1) | JRC | SOP-8 | 07+/08+ | Case: SOT-26, Molded Plastic Case material - UL Flammability Rating 94V-0 |
| UJM | (1) | ICS | SSOP | 1994 | 500Msps Conversion Rate 7.0 Effective Bits Typical at 250MHz 1.2GHz Anal |
| UJN | (5) | JRC | Preliminary product information describes products which are in productio | ||
| UJP | (1) | Prior to placing surface mount components onto a printed circuit | |||
| UJR | (1) | KS | SSOP-48 | 02+ | Isolation Test Voltage 5300 VRMS Current-limit Protection High-reliabi |
| UJU | (1) | JRC | PDIP28 | 01+ | The R1RW0408D is a 4-Mbit high speed static RAM organized 512-kword 8-bi |
| UK0 | (12) | UK | 9710+ | 74 | 1394b-2002 at S100B Signaling Rates Provides One Transceiver to Drive IEE |
| UK1 | (17) | ICS | SSOP/56 | 07+ | NOTES: 1. All VDD pins must be connected to 3.3V power supply. 2. All VD |
| UK2 | (8) | 2 | SOP | Crystal input, has internal load cap (36pF) and feedback resistor from | |
| UK3 | (10) | ICS | 0034 | Description Thermopile detector with on-chip PTC thermistor, floating th | |
| UK4 | (4) | MX | DIP42 | 98+ | The OPA675 and OPA676 are wideband monolithic operational amplifiers wit |
| UK6 | (1) | The 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O offers a multi-p | |||
| UK7 | (6) | 95 | Please read the EVM Users Guide and, specifically, the EVM Warnings and R | ||
| UK8 | (1) | The 0.625C/W assumes the use of the recommended footprint on a gla | |||
| ＵＫＡ | (3) | Notes: 1. DQ-to-I/O wiring is shown as recommended but may be cha | |||
| UKH | (2) | PHOENIX CONTACT | 08+ | Whatever crossover current that might occur in the low-power drivers is | |
| UKL | (29) | NICHICON | DIP | 2007+PB | The four switches are bilateral, equally matched for AC or bidirectional |
| UKM | (3) | SENSE PINCCCURRENT SENSE Analog Current Limit Voltage (Rising),VLIM | |||
| UKN | (8) | ICS | SSOP/56 | 07+ | MASK-ROM PIN-OUT COMPATIBLE SUPPLY VOLTAGE C VCC= 2.7 to 3.6V for Read |
| UKP | (4) | SHINDEGEN | SOT | 05+ | MP3 Decoding Functions (MPEG audio standard [ISO/IEC 11172-3] layer 3) |
| UL- | (5) | N/A | BGA | The improved architecture of the DMUX facilitates interfacing with high-s | |
| UL0 | (1) | ST | A power-up clear function is supplied that forces all registered outputs | ||
| UL1 | (13) | ML | DIP-22 | 90+ | FEATURES The SP8480 Series are complete data acquisi- tion systems, f |
| UL2 | (6) | ALLEGRO MICRO | SOIC18 | 02+ | For maximum output regulation, the HR301-2805 is provided with external |
| UL3 | (2) | ALLEGRO | SMD | 00+ | Notes a. Room = 25_C, Full = as determined by the operating temperature |
| UL4 | (1) | The carry output goes high with the leading edge of the count input at | |||
| UL6 | (13) | ZMD | SOP28-330m | 0611 | 6ns rise and fall time with 1000pF load 2A peak output source/sink curren |
| UL7 | (6) | . | . | 100 | Double Data Rate ( DDR II ) Applications Spread Spectrum Clock Compatible |
| UL8 | (2) | Fujitsu | DIP-40 | 07+/08+ | Address/Data number combination - HT12D: 8 address bits and 4 data bits |
| UL9 | (1) | Products designated as Not Recommended for New Design may become o | |||
| ULA | (148) | GPS | PLCC28 | 03/+04+ | The DS1267 Dual Digital Potentiometer Chip consists of two digitally contr |
| ULB | (12) | ASI | (LX)high-frequency | VCC to GND Digital Input Voltage to Gnd LNA Inout (Low-Gain Mode) Level | |
| ULC | (73) | TEMIC | 01+ | PLCC84 | Note 6: Output rise and fall times are measured between the 10% and 90% |
| ULD | (1) | ALLEGRO | 01+ | SOP-16 | Vishay Siliconix maintains worldwide manufacturing capability. Products ma |
| ULE | (6) | QFP44 | ALCATEL | 06+ | I Integrated DECT Baseband transceiver optimized for GAP handsets |
| ULF | (1) | These two schemes are shown in the 9310 data sheet The TC output is subj | |||
| ULH | (4) | ALLEGRO | SOT-23 | 05+ | Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Ga |
| ULI | (2) | 99+ | QFP-44P | output selectable). On-chip RAM performs buffering for EFM demodulation | |
| ULK | (1) | The ABT162244 devices are 16-bit buffers and line drivers designed spec | |||
| ULL | (2) | ALLEGRO | These circuits perform a single function: they assert a reset signal when | ||
| ULM | (10) | TI | Port 1 Port 1 is an 8-bit bidirectional I O port with internal pullups Po | ||
| ULN | (581) | 20 | MOT | DIP | In addition to the power-on-reset and undervoltage-supervisor function, t |
| ULO | (1) | ALLEGRO | . | 200 | Hynix HYMD512G726(L)8M-K/H/L series incorporates SPD(serial presence detec |
| ULP | (4) | ICS | BGA | 04+ | The SK-2910 Series of quartz crystal oscillators provide DPECL Fast Edge |
| ULQ | (69) | ST | 03+ | The ABTH18502A and ABTH182502A scan test devices with 18-bit universal bu | |
| ULR | (1) | 08+ | The input signal at pin DATA produces amplitude shift key (ASK) modulati | ||
| ULS | (50) | sprague | sprague | dc87+ | THERMAL EFFECTS Internal heating can have a significant effect on curren |
| ULT | (6) | ALLEGRO | SOT-89 | 05+ | Detection voltage Over charge detection voltage 1 Over charge release vo |
| ULV | (2) | AILL | DIP | 00+ | NOTES: 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Int |
| ULW | (1) | † Stresses beyond those listed under absolute maximum ratings may c | |||
| ULX | (1) | Eight GLBs, 16 I/O cells, two dedicated inputs and one ORP are connecte | |||
| ULY | (2) | (4) The products and product specifications described in this book are su | |||
| U-M | (3) | SSOP | 07+ | MASSACHUSETTS, Marborough MASSACHUSETTS, Woburn MICHIGAN, Detroit MINNE | |
| UM- | (6) | N/A | N/A | N/A | CONSTRUCTION Start with the two resistors followed by the small monoblo |
| UM/ | (2) | Ground the Pin14. Input a signal (C45 dBm) to the Pin16 and measure an | |||
| UM0 | (3) | 06+ | 5000 | The UM02 is available in the 10-pin MSOP package, making the entire conve | |
| UM1 | (57) | MITSUBISHI | MODULE | N/A | Signal Processor (DSP): - SM/SMJ320VC33-150 - 13-ns Instruction C |
| UM2 | (121) | DIP | The UM23C2101-7392 is a monolithic CMOS integrated circuit that includes | ||
| UM3 | (100) | UMC | † Test one output at a time, not exceeding 1-second duration. Measu | ||
| UM4 | (10) | PANASONIC | 04+ | Fully optimized differential digital gear tooth sensor Single chip sensin | |
| UM5 | (36) | 98 | These are the A3161 current levels. Typical rise and fall | ||
| UM6 | (394) | UM | SOJ28 | 96+ | • package: white P-LCC-4 package • feature of the device: mor |
| UM7 | (55) | UMC | 8912 | ||
| UM8 | (177) | UMC | DIP | 05+ | The first solution simply sacrifices the segment drive that share a catho |
| UM9 | (234) | 96 | - Übertragungsrate: 10/100 MBit/s - Protokoll: Modbus/TCP - Integr | ||
| UMA | (133) | PHI | 2007 | Cautions on using this product This product contains Gallium-Arse | |
| UMB | (54) | Offset error is the deviation of the average code from mid-code for a zer | |||
| UMC | (48) | ROHM | SOT-353 | 04+ | -12V TCK GND TDO VCC VCC INTB- INTD- PRSNT1- RSVD PRSNT2- GND |
| UMD | (58) | ROHM | 04+ | 3.3V 10% Receive Input Power Supply. Bypass with 0.1µF//0.01µF | |
| UMF | (41) | ROHM | 06+ | 15000 | PARAMETER Collector-Base Breakdown Voltage Collector-Emitter Breakdown |
| UMG | (54) | 04+ | En1 (Bump A2): Enable pin for the internal PMOS FET switch (Figure 2: P1 | ||
| UMH | (66) | ROHM | 0509+ | Note: (6) IX is measured under the following conditions with one diode s | |
| UMI | (6) | ACRIAN | 00+ | N/A | |
| UMJ | (1) | When CS1 is "H" or CS2 is "L" level, the UMJ0J101MDR1 | |||
| UMK | (480) | ＴＡＩＹＯ ＹＵＤＥＮ | 06+ | Fourth Generation HEXFETs from International Rectifier utilize advanced p | |
| UML | (24) | ROHM | SOT-353 | 04+05PB2900 | Distributes One Differential Clock Input Pair LVPECL/HSTL to 10 Different |
| UMN | (9) | ROHM | SOT-353 | The READ command selects the bank from BA0, BA1 inputs and starts a bur | |
| UMO | (4) | N/A | DIP-8 | 03+ | |
| UMP | (19) | ROHM | SOT-353 | Feedback input. When ADJ is grounded, the device enters fixed voltage mod | |
| UMR | (4) | ROHM | SOT-363 | 04+05PB6KM | 6.2 ST20196 FEATURES DMT modulation Max. number of bit per tone: 15 b |
| UMS | (24) | ROHM | SOT-353 | 05+ | 5V CMOS and TTL Compatible Fast Switching Single Ev |
| UMT | (50) | ROHM | SOT-363 | Caution: Stresses beyond those listed under Absolute Maximum Ratings may | |
| UMU | (8) | NS | 93+ | These family of 64MByte and 128MByte Rambus RIMM modules are offered in a | |
| UMV | (1) | Port 0: Port 0 is an open-drain, bi-directional I/O port. Port 0 pins tha | |||
| UMW | (27) | TDK | 98 | Stresses above those listed under Absolute Maximum Ratings may cause per | |
| UMX | (60) | ROHM | SOT-363 | The g-cell beams form two back-to-back capacitors (Figure 2). As | |
| UMY | (17) | SANYU | N/A | 1791 | The output and reset of the integrators is controlled by a 128-bit shift |
| UMZ | (66) | ROHM | SOT-363 | 05+ | Description The 3.3 V HCMS-39xx family is similar to the 5.0 V HCMS-29 |
| UN- | (2) | UNIGLORY | LL-41 | The PT6440 Excalibur™ power modules are a series of high per | |
| UN0 | (26) | This MOSFET is an enhancement-mode silicon-gate power field effect tran | |||
| UN1 | (15) | mat | mat | dc85 | Two package styles are available. HOA0901- 011 is primarily intended for |
| UN2 | (283) | PANASONIC | SOT-23 | 2004 | Notes: 1. Measurements made on a fixed tuned production test board that |
| UN3 | (7) | L - Low-Terminal Potentiometer. This is the low terminal of the potentiom | |||
| UN4 | (58) | PANASONIC | TO-92S | For a 1.25V input, and a 22µH inductor, the resulting peak current | |
| UN5 | (163) | PANASONIC | 02 | (red) lights indicate a faulty battery. This kit is shipped with a 10k | |
| UN6 | (20) | TO-92s | 00+ | LCD Segment output terminal / LCD Common output terminal SEG40 in 1/3Duty | |
| UN7 | (14) | NOTE: 1. This parameter is warranted but not production tested. The prop | |||
| UN8 | (8) | ST | SOP8S | 2007+ | Applications for these amplifiers include Portable and loop- powered ins |
| UN9 | (177) | PAN | SOT-523 | 06+PB | Clocking is accomplished through a two-input positive-NOR gate, permitt |
| UNA | (18) | MINI | 08+ | There is a small temperature drift of the comparator thresh- olds in the | |
| UNB | (1) | SANYO | 98 | Regulates voltage over a broad operating current and temperature range S | |
| UNC | (7) | ROHM | 02+ | • High speed switching (tstg: storage time/tf: fall time is short) & | |
| UND | (12) | Two individual input channels o MIC+/MIC-: differential microphone inputs | |||
| UNE | (1) | Transmit Clock. These ECL 100K outputs (+5V referenced) provide the bit r | |||
| UNF | (1) | nichicon | nichicon | dc00+ | 2. When using this product, please observe the absolute maximum ratings an |
| UNG | (2) | The FDC37M60x with IrDA v1.0 support incorporates a keyboard interface, | |||
| UNH | (37) | HITACHI | 01+ | Minimum time between read command (i.e., a write to Communication Regist | |
| UNI | (25) | 04+ | QFP | Stresses beyond those listed under Absolute Maximum Ratings may cause per | |
| UNJ | (2) | HY57V561620A is offering fully synchronous operation referenced to a posit | |||
| UNK | (3) | Shindengen | 04+ | DIP | The DRV593 and DRV594 are high-efficiency, high-current power amplifier |
| UNL | (7) | ST | DIP | 96 | CMOS Low Power Consumption Oscillation Frequency 4MHz to 125MHz 4 |
| UNM | (2) | ICS | O7+ | The DS1543 is available in two packages (28-pin DIP and 34-pin PowerCap m | |
| UNO | (2) | ZIOLG | SMD | N/A | Propagation Delay Tempco Prop Delay SkewRising Transition to Fal |
| UNR | (221) | DATEL | 模块 | In conjunction with the V103 transmitter, the V104 can transmit 10 bits p | |
| UNS | (2) | Panasonic | Maximum ratings are those values beyond which device damage can occur. Ma | ||
| UNT | (6) | ||||
| UNV | (1) | N/A | N/A | N/A | Fully operational to +1200V Tolerant to negative transient voltage dV/dt |
| UNW | (2) | The third, transient power due to internal capacitance takes exactly the | |||
| UNX | (1) | ROHM | 02+ | Organized as 4,194,304 words by 16 bits Single power supply voltage of 2. | |
| UNY | (1) | BGA | NOTES: 1. Inputs are capable of translating the following interface stan | ||
| UO2 | (1) | TOSHIBA | The CM3002 family of regulators is fully protected, offering both overl | ||
| UO5 | (1) | Technique must limit TJ C TC to 10C maximum The power-up clear resets t | |||
| UOB | (1) | Operation in -40C - 125C Environment TTL/DTL/CMOS Compatible Inputs NAND | |||
| UOF | (1) | ST | 02+ | • Nonvolatile Storage Without Battery Problems • Directly Rep | |
| UOG | (1) | When the SVHS mode is selected, the DC restore on the Aux_Cout pin will | |||
| UOL | (1) | The input load capacitors are placed on-die to reduce external component | |||
| UP- | (3) | TAIYO | 07+ | • Fully compliant to the IEEE 802.3u standard • Repeater mo | |
| UP0 | (70) | PANASONIC | 06+ | SMD | Note: 1. Commercial Product: TA=0 to 70C, otherwise specified. In |
| UP1 | (28) | COOPER | UP1B- | The SY58620L is a low jitter, high-speed transceiver with a variable swin | |
| UP2 | (36) | U-PEN | QFP-M64P | 6+ | • Stub-series terminated logic for 2.5 V VDDQ (SSTL_2) • Optim |
| UP3 | (13) | ICS | 03+ | BGA | Notes a. Surface Mounted on 1 x 1 FR4 Board. b. See Reliability Manual |
| UP4 | (20) | Five years minimum data retention in the absence of external power Data | |||
| UP5 | (4) | N/A | PLCC | 03+ | CT - This is the oscillator timing pin. The free-running frequency can b |
| UP6 | (8) | uchiya | uchiya | dc96 | Lock Time6 Frequency Pushing (Open Loop) Frequency Pu |
| UP7 | (6) | NEC | 03+ | VO = 1.4V, RS = 0Ω, 5V < VCC+ < 30V, 0V < Vic < V | |
| UP8 | (7) | NEC | 84+ | Notes: 1. See test circuit and waveforms. 2. This parameter is guarantee | |
| UP9 | (2) | NEC | DIP | and separate top and bottom output polarity control. The up-counter value | |
| UPA | (1090) | 2001 | The PVN013 Series Photovoltaic Relay at 100 milliohms features the lowe | ||
| UPB | (795) | NEC | DIP | DIP | The MGA-71543 offers an inte- grated solution of LNA with adjustable IIP |
| UPC | (3737) | NEC | SOT-23-5 | Ratio0 Output/PCI5 Output. At power up when RatioSel (pin 26) strapping = | |
| UPD | (18576) | NEC | 9416 | mum dc plus ac (tone) load current required, internal VILNB(th) toleranc | |
| UPE | (1) | Sampling of the analog input starts on the falling edge of the fourth I/O | |||
| UPF | (70) | UBE | SOJ | 07+/08+ | The ICS8308I is characterized for 3.3V core/3.3V output, 3.3V core/2.5V |
| UPG | (222) | NEC | _____________ | 03+ | Drain-to-Source Breakdown Voltage 200 Gate Threshold Voltage …2.04 |
| UPH | (3) | The CDS mode of operation supports both line and pixel-clamp modes and | |||
| UPI | (4) | 01+ | 铁帽-3P | Supply Voltage (VCC) AC ACT Input Voltage (VI) Output | |
| UPJ | (33) | NICHICON | DIP | 2007+PB | Typical represents the average reading at 25C and VDD = 5 V. &n |
| UPK | (1) | 1. Intersil Pb-free products employ special Pb-free material sets; | |||
| UPL | (108) | NICHICON | 6132 | Level Conversion Circuit The UPL1C221MPH has a built-in level conversion | |
| UPM | (42) | DATEL | . | 51 | International Rectifiers RAD-HardTM HEXFET® MOSFET technology provi |
| UPN | (4) | NEC | 0 | The CNY64/ CNY65/ CNY66 consist of a phototrans- istor optically couple | |
| UPO | (2) | This is the output terminal for the LPF input and charge pump output. Wh | |||
| UPP | (11) | SANYO | QFP/80 | 1995 | Stresses above those listed under Absolute Maximum Ratings may cause perm |
| UPR | (82) | POWERMITE | 脚大脚小 | 05+ | The UPR05/UPR05 implement local and remote temperature sensing with 12-bi |
| UPS | (165) | N/A | P&S | 04+ | Select data in or data out on SDA or Measurement latching for transmissio |
| UPT | (7) | MICRO | 脚大脚小 | 05+ | NEC's NR7800 Series are InGaAs PIN photo diode (PIN-PD) coaxial modules |
| UPU | (2) | NEC | QFP | The Effects of Non-zero Aperture Time For the analysis of aperture time | |
| UPV | (1) | 1. Rating applies when surface mounted on the minimum pad size recommende | |||
| UPW | (39) | NICHICON | DIP | 2007+PB | Intel Corporation assumes no responsibility for the use of any circuitry |
| UPX | (2) | NEC | DIP24(陶) | 8425 | All linear dimensions are in inches (millimeters). This drawing is subj |
| UPY | (18) | Reading from the device is accomplished by taking Chip Enable (CE) and Ou | |||
| UQF | (1) | YONGYUTH | TQFP-48P | 03+ | • High-speed switching (Fall time tf is short) • High collector |
| UQQ | (1) | This new series of digital transistors is designed to replace a si | |||
| UR1 | (108) | UTC | SOT-89 | 05+ | The product term array in the FLASH370i logic block includes 36 inputs fr |
| UR2 | (11) | ST | QFP-100 | 02+ | The LS160 and LS162 count modulo-10 in the BCD (8421) sequence From stat |
| UR3 | (2) | UTC | TO-252-5 | 08+ | operations and low power and low noise applications. It can be interfa |
| UR4 | (2) | Hitachi | TO-252 | (Load as specified in Figure 1, unless otherwise noted. VCC = +2.97V to +5 | |
| UR5 | (12) | UTC | TO-252-5 | 08+ | • Plastic package has Underwriters Laboratories Flammabilit |
| UR6 | (15) | UTC | SOT-89 | 08+ | |
| UR7 | (8) | C Glueless Interface to Synchronous Memories: SDRAM or SBSRAM C G | |||
| UR8 | (2) | Note 1) The specified condition Tj=25˚C means that the test should | |||
| URA | (49) | NEC | 3F | ||
| URC | (1) | 4. A transient suppressor is normally selected according to the working p | |||
| URD | (3) | The two independent ADCs (primary and auxiliary) include a temperature | |||
| URE | (3) | FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER | |||
| URG | (5) | STANLEY | MUTE Operation The MUTE input is active high. Whenever the input is low, | ||
| URM | (2) | 3U | RELAY | 06+ | Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pullups. |
| URS | (23) | TOSHIBA | SOT-89 | ❇1This value can change due to the switching frequency, environmen | |
| URT | (5) | SANYU | 01+ | Advanced 0.35µ E2CMOS process Security bit prevents unauthorized | |
| URV | (1) | A variety of frequency ranges and packaging options are available. Depe | |||
| URY | (1) | for Low XTO Start-up Times Modulation Scheme ASK/FSK with Internal FSK Sw | |||
| URZ | (15) | NICHICON | SOP | HN58X24xxI series are two-wire serial interface EEPROM (Electrically Eras | |
| US- | (7) | The bias winding provides operating power and feedback current to the CO | |||
| US0 | (14) | The CM3016-48 is fully protected, offering both overload current limitin | |||
| US1 | (220) | PHILIPS | SOD124 | 07 | Arbitrary trigger levels for receiver and transmitter FIFO interrupts an |
| US2 | (76) | melexis | The extremely high maximum data rate is achieved by three internal shift | ||
| US3 | (132) | TSC | DO214AB | 05 | An output-enable (OE) input places the eight outputs in either a normal |
| US4 | (7) | UNISEM | 8/SOP | 07+/08+ | incrementing and post-decrementing, to name just a few examples. In man |
| US5 | (43) | SOP | 03+ | The ICL7106 and ICL7107 are high performance, low power, 3½ digit A | |
| US6 | (33) | VISHAY | DO214AB | 07+ | Note 4: For the purpose of specifying deserializer PLL performance tDSR1 |
| US7 | (9) | 5 | MELEXIS | 0246+ | The reference current determines the input and output current compliance |
| US8 | (14) | 93 | Recording level calibration pin. ∗ Controlled with DC vo | ||
| US9 | (4) | 5 | SMD8 | 03/04+ | The parameters governing address generation are loaded into five 24-bit |
| USA | (58) | QFP-160 | In addition, the PCI interface can either be used as a bridge from the p | ||
| USB | (279) | QFP | 1999 | Ÿ Miniature, cost-effective switching solution. Ÿ State of the | |
| USC | (19) | NSC | PLCC44 | 03/+04+ | C Certain signals are logically true at a voltage defined as low |
| USD | (34) | UNI | NO | Data RAM with size selection of 648, 968, 1608 and 2248 bits Halt functi | |
| USE | (2) | Low skew: < 200ps Fast switching frequency >133 MHz Fast output | |||
| USF | (19) | TOSHIBA | SOT-89 | 05+ | Information furnished by MEMSIC is believed to be accurate and reliable. |
| USH | (2) | INFINEON | PLCC | 94+ | |
| USI | (8) | N/A | SOP-20 | The USI115S0010 is a 16-bit resolution successive approxima- tion A/D co | |
| USK | (1) | This 20 VGS gate drive vertical Power MOSFET is a general purpose | |||
| USL | (19) | The flags are synchronous, i.e., they change state relative to either th | |||
| USM | (18) | bourns | bourns | dc02 | Stresses above those listed under "Absolute Maximum Ratings" ma |
| USN | (3) | Functional Tests (In Freescale Test Fixture, 50 ohm system) VDD = 28 Vdc, | |||
| USO | (11) | the device has a Sector Protect function which hardware write protects | |||
| USP | (10) | LSI | The 0.625C/W assumes the use of the recommended footprint on a gla | ||
| USQ | (3) | DATEL | N/A | ||
| USR | (41) | ORIGIN | SOP | Provides various voltages for DDR-STR applications Provide a swit | |
| USS | (43) | LUCENT | QFP/100 | 9921+ | TheCD54HC00,CD74HC00,CD54HCT00,and CD74HCT00 logic gates utilize silicon |
| UST | (14) | DATEL | 07+ | The information provided herein is believed to be reliable at press time. | |
| USU | (1) | The AUP family is TIs premier solution to the industrys low-power needs i | |||
| USV | (2) | NICHICON | DIP | 2007+PB | Absolute maximum ratings indicate limits beyond which damage to the compon |
| UT- | (6) | NS | Distributed VCC and GND-Pin Configuration Minimizes High-Speed Switching | ||
| UT0 | (19) | UCHI | Continuous over-current loads will cause the parts internal temperature t | ||
| UT1 | (93) | The LVT16652 consists of sixteen bus transceiver circuits with D-type fl | |||
| UT2 | (35) | UNI | 60 | • Low power consumption: (typical with VDD = 3V) - 14 mA tr | |
| UT3 | (11) | UMEC | 04+ | Single Byte/Single Cycle Code Execution The efficiency is due to the fac | |
| UT4 | (3) | With their compact 64 pin package, low power consumption, various 32-bit | |||
| UT5 | (12) | 740 | Receive data. These outputs carry 10-bit parallel data output from the tr | ||
| UT6 | (273) | SMD | 1000 | UT | Title Data Enable Signal For VCR PB Mode Title Mix ROM Enable For Superim |
| UT7 | (8) | UTC | SOT89 | 08+ | † Stresses beyond those listed under absolute maximum ratings may c |
| UT8 | (15) | UT | 06-07+ | The contents of the offset registers can be read to the data outputs whe | |
| UT9 | (10) | UT Starcom | 06PB | -48V/-24V Input Active ORing for carrier class communication equipment Re | |
| UTB | (16) | PGND (Bump D3): Power ground pin. Connect directly to the ground plane. | |||
| UTC | (276) | UTC | DIP | 87 | The UTC1031, UTC1031B, UTC1031, and UTC1031 devices are part of the TMS3 |
| UTE | (1) | Beneficial comments (recommendations, additions, deletions) and any perti | |||
| UTF | (6) | Ladder Network Accuracy: 1/2 LSB from 0C to + 70C. Ladder Network Resist | |||
| UTG | (71) | MSC | The SPS product family is specially designed for an off-line SMPS with | ||
| UTL | (1) | The SY88713V low-power limiting post amplifier operates from a si | |||
| UTN | (2) | 1) Correct Fig.10 Sequential out cycle after read 2) Add the text to Fig. | |||
| UTO | (12) | 2008 | The Am29LV017D is a 16 Mbit, 3.0 Volt-only Flash memory organized as 2, | ||
| UTP | (10) | RV and CJ are very difficult to measure. Consider the impedance of CJ = | |||
| UTR | (8) | unitrode | unitrode | dc79+ | • Dual 14-bit, 1GSa/s Digital to Analog conversion • Excepti |
| UTS | (31) | XTAL1 and XTAL2 are input and output, respectively, of an inverting ampli | |||
| UTU | (1) | As an example lets find the total power consumption for an MM74C00 opera | |||
| UTV | (9) | where VINSTARTUP is the desired startup voltage at which the EV kit star | |||
| UTX | (6) | microwave | microwave | dc72+ | The NCV8505 is a family of precision micropower voltage regulator |
| UU1 | (6) | The output and reset of the integrators is controlled by a 128-bit shift | |||
| UU2 | (3) | UC | SOP-8 | 04+ | Polarity/ Description Bus size RiseClock Feeds internal clock c |
| UU3 | (3) | UC | SOP-8 | Although it is true that all interrupts will be buffered once a command | |
| UU4 | (1) | TFK | DIP | 1994 | With respect to the slew rate of the converter control loop error amplif |
| UU5 | (1) | The Intel 87C51 80C51BH 80C31BH is a single-chip control-oriented microco | |||
| UU8 | (1) | A wide input voltage range and integrated thermal and overcurrent | |||
| UU9 | (4) | Timer • Timer 0 : 16-bit timer/counter With 2-bit prescaler | |||
| UUA | (4) | Panasonic | SMD | 90 | A common method of measuring temperature is to exploit the negative temp |
| UUB | (3) | FAST data sheets carry several types of AC information. The AC Character | |||
| UUC | (4) | DIP8 | The LVT16373 and LVTH16373 contain sixteen non-invert- ing latches with | ||
| UUD | (139) | ＮＩＣＨＩＣＯＮ | 06+ | Please read Application Note 1 "General Operating Considerati | |
| UUE | (2) | MITSUBISHI | MODULE | 00+ | RJC Thermal Resistance (Output Switches)1.5C/W RJC Thermal Resistance (Re |
| UUG | (10) | QFP | QFP | Note 3: Absolute Maximum continuous ratings are those values beyond which | |
| UUH | (3) | PANASONIC | SOP8 | Left channel positive output in BTL mode and SE mode. Supply voltage Lef | |
| UUJ | (14) | PANASONIC | 95+ | 1.9GHz gain-bandwidth product 1.05nV/Hz input voltage noise 0.8pA/Hz | |
| UUK | (1) | NICHICON | 5M | 05+ | Room = 25C, Full = as determined by the operating suffix. Typical values |
| UUP | (6) | NICHICON | 07/08+ | • HIGH PERFORMANCE E2CMOS® TECHNOLOGY fmax = 180 MHz Ma | |
| UUR | (58) | NICHICON | 6M | 05+ | • AN80M19RSP (1.9 V type) Unless otherwise specially provided |
| UUS | (3) | Low−Power Schottky TTL Load Over the Rated Temperature Range | |||
| UUT | (26) | ELNA | 6.3V-22UF | The MAX1973/MAX1974 are constant-frequency 1.4MHz pulse-width-modulated ( | |
| UUV | (7) | NICHICON | 5M | 05+ | CASE: Void-free transfer molded thermosetting epoxy body meeting UL94V-0 |
| UUX | (43) | NIPPON | 10x10 | 05+ | The AD7877 is a 12-bit successive approximation ADC with a synchronous s |
| UUZ | (1) | The above data is derived from fixtured measurements which include 3 paral | |||
| UV0 | (2) | ST | SOP-8 | The conditional skip is activated by instruction. Once the condition is | |
| UV1 | (9) | PHI-COMP | O7+ | ||
| UV2 | (8) | ASSOCIAT | MOUDLE | N/A | After a successful ATR, the Protocol and Parameter Selection (PPS) protoc |
| UV3 | (8) | N/A | BRAKE - is a pin for commanding the output bridge into a motor BRAKE mode | ||
| UV4 | (11) | switch and a second IMP8980D for communication with the line interface c | |||
| UV6 | (1) | Note: Stresses greater than those listed under MAXIMUM RAT- INGS may c | |||
| UV9 | (2) | The MARC4 microcontroller consists of an advanced stack-based, 4-bit CPU | |||
| UVA | (1) | Note 1: All currents into the device are positive; all currents out of the | |||
| UVC | (4) | ITT | DIP-40 | 07+/08+ | Stresses beyond those listed under "absolute maximum ratings" m |
| UVE | (1) | Beneficial comments (recommendations, additions, deletions) and any pertin | |||
| UVK | (27) | TAIYO YUDEN | 2007+PB | The receivers also include a (patent pending) fail-safe circuit that will | |
| UVM | (1) | External Access enable: EA must be externally held low to enable the de | |||
| UVO | (1) | If the DS1481 determines that it is the last device on the port it ignor | |||
| UVP | (22) | For NTSC applications without the peaking capacitor the rejection at 27M | |||
| UVQ | (6) | Areas where care in design must be observed are thermal ground, RF groun | |||
| UVR | (228) | NICHICON | DIP | 2007+PB | Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceede |
| UVS | (16) | A memory cycle is initiated by bringing RAS LOW and it is terminated by | |||
| UVT | (4) | 01+ | QFN | To provide the high input sensitivity necessary to receive optical signals | |
| UVW | (2) | Hynix HYMD216646A(L)6J-J series is designed for high speed of up to 166MHz | |||
| UVX | (134) | ST | 06+ | 100 | The Read Manufacturer ID and Read Device ID operations read the JEDEC assi |
| UVY | (1) | ||||
| UVZ | (91) | NICHICON | DIP | 2007+PB | |
| UW- | (1) | The 329C/W for the SC-74 package assumes the use of the recommend | |||
| UW1 | (1) | NICHICON | 6.3X5.5 | 05+ | operating parameters. Those bits are summarized in Table 2. Dead-time co |
| UW2 | (6) | ICS | SSOP | 02+ | Stresses above those listed under Absolute Maximum Ratings may cause perm |
| UW6 | (1) | 95+96+ | DIP | Hardware data protection measures include a low V CC detector that autom | |
| UW7 | (1) | monitors the RXK and TX. When the two mirror each other there is no fau | |||
| UW9 | (1) | Depending upon the configuration, the circuit can be either extern | |||
| UWC | (1) | The TLV245x is a family of rail-to-rail input/output operational amplifie | |||
| UWD | (2) | NICHICON | SMD | 07+ | Instructions are given on the safety precautions to be used during stor |
| UWF | (22) | NICHICON | organized as 32,768 words by 16 bits. It is fabricated using ISSI's high | ||
| UWG | (1) | 0510+ | The KS8721BL/SL automatically configures itself for 100Mbps or 10Mbps a | ||
| UWM | (1) | NEC | TSSOP28 | The UC and DC control inputs are designed to support simple pushbutton inp | |
| UWP | (12) | NICHICON | SMD | 07+ | Note 1. Commercial Product : TA=0 to 70C, unless otherwise specified &nb |
| UWR | (78) | N/A | FEATURES 225 ps Propagation Delay through the Switch 4.5 Switch Connect | ||
| UWS | (3) | NICHICON | SMD | 07+ | |
| UWT | (157) | NICHICON | SMD | 07+ | This series of fixed-negative-voltage integrated-circuit voltage regulato |
| UWX | (97) | NICHICON | SMD | 07+ | The UWX1H010MCR2GB UWX1H010MCR2GB and UWX1H010MCR2GB are 10-bit succes- |
| UWY | (1) | NICHICON | 6.3X5.5 | 05+ | (5) The products and product specifications described in this material ar |
| UX- | (1) | If the auto-increment flag (AI) is set, the four low order bits of the C | |||
| UX0 | (40) | ADI | 98 | This device is fully specified for partial-power-down applications using | |
| UX1 | (3) | Although protection circuitry has been designed into this device, proper | |||
| UX2 | (1) | N/A | N/A | N/A | Internal Testing pin Buzzer Output Buzzer Output Continues BiBi Alarm, |
| UX3 | (1) | Notice that the triangle waveform linearity is sensitive to parasite coup | |||
| UX4 | (1) | N/A | 功放模块 | N/A | VH.A (Pin 4): Hysteresis Adjust. Hysteresis threshold voltage VTH2 = 2.5V |
| UX6 | (3) | HRS | SMD | 03+ | This will result in an input to the crystal of 50% of the rail to rail ou |
| UX7 | (1) | Category voltage UC: The maximum direct voltage, or the maximum r.m.s. v | |||
| UXA | (1) | The AMS2907 series of adjustable and fixed voltage regulators are designe | |||
| UXB | (28) | Logic Device C 3.0 to 3.6V Operating Range C 32 Macrocells | |||
| UXF | (1) | PHI | QFN | 2005 | Output Voltage Options: 2.6 V, 3.3 V, 5.0 V, 7.5 V 3.0% Output 3.5 V Op |
| UXM | (1) | UNIZON | SOT-23 | Note 1: See thermal regulation specification for changes in output voltage | |
| UXO | (4) | PHILIPS | (LX)high-frequency | FEATURES High Ripple Rejection75dB typ. (f=1kHz Vo=3V version) & | |
| UXP | (5) | Bright Red High Efficiency Red Yellow Super Bright Red Super Bright Gr | |||
| UXZ | (1) | The SNAP! Pulse programming algorithm uses an initial pulse of 100 micros | |||
| UY1 | (8) | N/A | 38503 | N/A | |
| UY3 | (5) | PHI | SOP24W | 06+ | * This is a stress rating only and functional operation of the device at |
| UY4 | (1) | ||||
| UY7 | (24) | UY | QFP | 07+ | The IDT5V991A is a high fanout 3.3V PLL based clock driver intende |
| UY8 | (2) | ROHM | LCC-36 | 02 | Note 1) All voltage are relative to VSS =0V reference. Note 2) The LSI m |
| UYB | (1) | I/O performance is increased to 622 Mb/s using Source Synchronous data | |||
| UYX | (1) | The Idle mode stops the CPU while allowing the other chip function to con | |||
| UZ- | (35) | UNIZON | International Rectifiers RADHard HEXFET® technol- ogy provides high | ||
| UZ1 | (74) | UTC | N/A | Note 1) The specified condition Tj=25˚C means that the test should | |
| UZ2 | (18) | DIGITAL OUTPUTS(6) Logic Family Logic Coding Low Output Voltage (IOL = | |||
| UZ3 | (16) | PYUNG CHANG | The UZ3.6BSB is a 512K-bit OTP ROM of which func- tion and pin assignment | ||
| UZ4 | (7) | Case: SOD-523, Plastic Case material - UL Flammability Rating Classifica | |||
| UZ5 | (10) | PYUNG CHANG | When only the S0 pin is at a logic one the pressure measuring cir | ||
| UZ6 | (11) | Notes: 1. For Max. or Min. conditions, use appropriate value specified u | |||
| UZ7 | (9) | Notes: 1. All byte outputs are active in read cycles regardless of the s | |||
| UZ8 | (4) | Recommended PCB Layout ∗ As indicated in the diagram AC coupling c | |||
| UZ9 | (4) | Configuration of a single-ended input has been facilitated by biasing n | |||
| UZD | (2) | This document is a general product description and is subject to change wi | |||
| UZE | (1) | nec | nec | dc01 | A common application for HyperPHY is the high-speed switch used in |
| UZF | (1) | For those systems using buses wider than a single byte, the four indepen | |||
| UZH | (3) | ZETEX | 05+ | SOT163 | The ADC works in fully differential mode from the analog input to the dig |
| UZL | (2) | Multi-purpose input / output pin (Figure 2-2). • Button input pin | |||
| UZM | (67) | UNIZON | 23 | Dropout voltage is defined as the input-to-output differential at which th | |
| UZN | (1) | The AMI signal first enters an equalizer and AGC gain stage. The equalize | |||
| UZP | (24) | NA | NA | WRITE PROTECTION (WP) If WP is connected to Vcc, PROGRAM operation onto t | |
| UZR | (6) | ZETEX | N/A | 0519+ | Bild / Fig. 7 W1C - Einphasen-Wechselwegschaltung / Single-phase inverse |
| UZS | (8) | NICHICON | SMD | 2007+PB | TURBOSWITCH 1200V drastically cuts losses in all high voltage operation |
| UZT | (7) | NICHICON | 6M | 05+ | The bq2060 works with an external EEPROM. The EEPROM stores the configur |
| UZU | (1) | (1) The minimum DC input voltage is C0.5V. During transitions, inputs may | |||
| UZV | (2) | By taking advantage of Analog Devices high-performance complementary Si | |||
| UZX | (15) | ZETEX | SOT-23 | The CMPIN pin drives data slicer DS1, which convert the analog signal fro | |
| UZZ | (6) | PHILIPS | SMD | 1999 | Device bus operations are initiated through the internal command regist |
About Seekchip- Services - Comments - Contact us - Links - Map
© 2008 China Electronics Market,License 浙ICP备10014259号